[deliverable/linux.git] / drivers / usb / host / ohci-pxa27x.c

/*
 * OHCI HCD (Host Controller Driver) for USB.
 *
 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
 * (C) Copyright 2002 Hewlett-Packard Company
 *
 * Bus Glue for pxa27x
 *
 * Written by Christopher Hoover <ch@hpl.hp.com>
 * Based on fragments of previous driver by Russell King et al.
 *
 * Modified for LH7A404 from ohci-sa1111.c
 *  by Durgesh Pattamatta <pattamattad@sharpsec.com>
 *
 * Modified for pxa27x from ohci-lh7a404.c
 *  by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
 *
 * This file is licenced under the GPL.
 */

#include <linux/device.h>
#include <linux/signal.h>
#include <linux/platform_device.h>
#include <linux/clk.h>

#include <mach/hardware.h>
#include <mach/ohci.h>

/*
 * UHC: USB Host Controller (OHCI-like) register definitions
 */
#define UHC_BASE_PHYS	(0x4C000000)
#define UHCREV		__REG(0x4C000000) /* UHC HCI Spec Revision */
#define UHCHCON		__REG(0x4C000004) /* UHC Host Control Register */
#define UHCCOMS		__REG(0x4C000008) /* UHC Command Status Register */
#define UHCINTS		__REG(0x4C00000C) /* UHC Interrupt Status Register */
#define UHCINTE		__REG(0x4C000010) /* UHC Interrupt Enable */
#define UHCINTD		__REG(0x4C000014) /* UHC Interrupt Disable */
#define UHCHCCA		__REG(0x4C000018) /* UHC Host Controller Comm. Area */
#define UHCPCED		__REG(0x4C00001C) /* UHC Period Current Endpt Descr */
#define UHCCHED		__REG(0x4C000020) /* UHC Control Head Endpt Descr */
#define UHCCCED		__REG(0x4C000024) /* UHC Control Current Endpt Descr */
#define UHCBHED		__REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
#define UHCBCED		__REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
#define UHCDHEAD	__REG(0x4C000030) /* UHC Done Head */
#define UHCFMI		__REG(0x4C000034) /* UHC Frame Interval */
#define UHCFMR		__REG(0x4C000038) /* UHC Frame Remaining */
#define UHCFMN		__REG(0x4C00003C) /* UHC Frame Number */
#define UHCPERS		__REG(0x4C000040) /* UHC Periodic Start */
#define UHCLS		__REG(0x4C000044) /* UHC Low Speed Threshold */

#define UHCRHDA		__REG(0x4C000048) /* UHC Root Hub Descriptor A */
#define UHCRHDA_NOCP	(1 << 12)	/* No over current protection */
#define UHCRHDA_OCPM	(1 << 11)	/* Over Current Protection Mode */
#define UHCRHDA_POTPGT(x) \
			(((x) & 0xff) << 24) /* Power On To Power Good Time */

#define UHCRHDB		__REG(0x4C00004C) /* UHC Root Hub Descriptor B */
#define UHCRHS		__REG(0x4C000050) /* UHC Root Hub Status */
#define UHCRHPS1	__REG(0x4C000054) /* UHC Root Hub Port 1 Status */
#define UHCRHPS2	__REG(0x4C000058) /* UHC Root Hub Port 2 Status */
#define UHCRHPS3	__REG(0x4C00005C) /* UHC Root Hub Port 3 Status */

#define UHCSTAT		__REG(0x4C000060) /* UHC Status Register */
#define UHCSTAT_UPS3	(1 << 16)	/* USB Power Sense Port3 */
#define UHCSTAT_SBMAI	(1 << 15)	/* System Bus Master Abort Interrupt*/
#define UHCSTAT_SBTAI	(1 << 14)	/* System Bus Target Abort Interrupt*/
#define UHCSTAT_UPRI	(1 << 13)	/* USB Port Resume Interrupt */
#define UHCSTAT_UPS2	(1 << 12)	/* USB Power Sense Port 2 */
#define UHCSTAT_UPS1	(1 << 11)	/* USB Power Sense Port 1 */
#define UHCSTAT_HTA	(1 << 10)	/* HCI Target Abort */
#define UHCSTAT_HBA	(1 << 8)	/* HCI Buffer Active */
#define UHCSTAT_RWUE	(1 << 7)	/* HCI Remote Wake Up Event */

#define UHCHR           __REG(0x4C000064) /* UHC Reset Register */
#define UHCHR_SSEP3	(1 << 11)	/* Sleep Standby Enable for Port3 */
#define UHCHR_SSEP2	(1 << 10)	/* Sleep Standby Enable for Port2 */
#define UHCHR_SSEP1	(1 << 9)	/* Sleep Standby Enable for Port1 */
#define UHCHR_PCPL	(1 << 7)	/* Power control polarity low */
#define UHCHR_PSPL	(1 << 6)	/* Power sense polarity low */
#define UHCHR_SSE	(1 << 5)	/* Sleep Standby Enable */
#define UHCHR_UIT	(1 << 4)	/* USB Interrupt Test */
#define UHCHR_SSDC	(1 << 3)	/* Simulation Scale Down Clock */
#define UHCHR_CGR	(1 << 2)	/* Clock Generation Reset */
#define UHCHR_FHR	(1 << 1)	/* Force Host Controller Reset */
#define UHCHR_FSBIR	(1 << 0)	/* Force System Bus Iface Reset */

#define UHCHIE          __REG(0x4C000068) /* UHC Interrupt Enable Register*/
#define UHCHIE_UPS3IE	(1 << 14)	/* Power Sense Port3 IntEn */
#define UHCHIE_UPRIE	(1 << 13)	/* Port Resume IntEn */
#define UHCHIE_UPS2IE	(1 << 12)	/* Power Sense Port2 IntEn */
#define UHCHIE_UPS1IE	(1 << 11)	/* Power Sense Port1 IntEn */
#define UHCHIE_TAIE	(1 << 10)	/* HCI Interface Transfer Abort
					   Interrupt Enable*/
#define UHCHIE_HBAIE	(1 << 8)	/* HCI Buffer Active IntEn */
#define UHCHIE_RWIE	(1 << 7)	/* Remote Wake-up IntEn */

#define UHCHIT          __REG(0x4C00006C) /* UHC Interrupt Test register */


#define PXA_UHC_MAX_PORTNUM    3

#define UHCRHPS(x)              __REG2( 0x4C000050, (x)<<2 )

static struct clk *usb_clk;

/*
  PMM_NPS_MODE -- PMM Non-power switching mode
      Ports are powered continuously.

  PMM_GLOBAL_MODE -- PMM global switching mode
      All ports are powered at the same time.

  PMM_PERPORT_MODE -- PMM per port switching mode
      Ports are powered individually.
 */
static int pxa27x_ohci_select_pmm( int mode )
{
	switch ( mode ) {
	case PMM_NPS_MODE:
		UHCRHDA |= RH_A_NPS;
		break;
	case PMM_GLOBAL_MODE:
		UHCRHDA &= ~(RH_A_NPS & RH_A_PSM);
		break;
	case PMM_PERPORT_MODE:
		UHCRHDA &= ~(RH_A_NPS);
		UHCRHDA |= RH_A_PSM;

		/* Set port power control mask bits, only 3 ports. */
		UHCRHDB |= (0x7<<17);
		break;
	default:
		printk( KERN_ERR
			"Invalid mode %d, set to non-power switch mode.\n",
			mode );

		UHCRHDA |= RH_A_NPS;
	}

	return 0;
}

extern int usb_disabled(void);

/*-------------------------------------------------------------------------*/

static inline void pxa27x_setup_hc(struct pxaohci_platform_data *inf)
{
	uint32_t uhchr = UHCHR;
	uint32_t uhcrhda = UHCRHDA;

	if (inf->flags & ENABLE_PORT1)
		uhchr &= ~UHCHR_SSEP1;

	if (inf->flags & ENABLE_PORT2)
		uhchr &= ~UHCHR_SSEP2;

	if (inf->flags & ENABLE_PORT3)
		uhchr &= ~UHCHR_SSEP3;

	if (inf->flags & POWER_CONTROL_LOW)
		uhchr |= UHCHR_PCPL;

	if (inf->flags & POWER_SENSE_LOW)
		uhchr |= UHCHR_PSPL;

	if (inf->flags & NO_OC_PROTECTION)
		uhcrhda |= UHCRHDA_NOCP;

	if (inf->flags & OC_MODE_PERPORT)
		uhcrhda |= UHCRHDA_OCPM;

	if (inf->power_on_delay) {
		uhcrhda &= ~UHCRHDA_POTPGT(0xff);
		uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
	}

	UHCHR = uhchr;
	UHCRHDA = uhcrhda;
}

#ifdef CONFIG_CPU_PXA27x
extern void pxa27x_clear_otgph(void);
#else
#define pxa27x_clear_otgph()	do {} while (0)
#endif

static int pxa27x_start_hc(struct device *dev)
{
	int retval = 0;
	struct pxaohci_platform_data *inf;

	inf = dev->platform_data;

	clk_enable(usb_clk);

	UHCHR |= UHCHR_FHR;
	udelay(11);
	UHCHR &= ~UHCHR_FHR;

	UHCHR |= UHCHR_FSBIR;
	while (UHCHR & UHCHR_FSBIR)
		cpu_relax();

	pxa27x_setup_hc(inf);

	if (inf->init)
		retval = inf->init(dev);

	if (retval < 0)
		return retval;

	UHCHR &= ~UHCHR_SSE;

	UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);

	/* Clear any OTG Pin Hold */
	pxa27x_clear_otgph();
	return 0;
}

static void pxa27x_stop_hc(struct device *dev)
{
	struct pxaohci_platform_data *inf;

	inf = dev->platform_data;

	if (inf->exit)
		inf->exit(dev);

	UHCHR |= UHCHR_FHR;
	udelay(11);
	UHCHR &= ~UHCHR_FHR;

	UHCCOMS |= 1;
	udelay(10);

	clk_disable(usb_clk);
}


/*-------------------------------------------------------------------------*/

/* configure so an HC device and id are always provided */
/* always called with process context; sleeping is OK */


/**
 * usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs
 * Context: !in_interrupt()
 *
 * Allocates basic resources for this USB host controller, and
 * then invokes the start() method for the HCD associated with it
 * through the hotplug entry's driver_data.
 *
 */
int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device *pdev)
{
	int retval, irq;
	struct usb_hcd *hcd;
	struct pxaohci_platform_data *inf;
	struct resource *r;

	inf = pdev->dev.platform_data;

	if (!inf)
		return -ENODEV;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		pr_err("no resource of IORESOURCE_IRQ");
		return -ENXIO;
	}

	usb_clk = clk_get(&pdev->dev, "USBCLK");
	if (IS_ERR(usb_clk))
		return PTR_ERR(usb_clk);

	hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
	if (!hcd)
		return -ENOMEM;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r) {
		pr_err("no resource of IORESOURCE_MEM");
		retval = -ENXIO;
		goto err1;
	}

	hcd->rsrc_start = r->start;
	hcd->rsrc_len = resource_size(r);

	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
		pr_debug("request_mem_region failed");
		retval = -EBUSY;
		goto err1;
	}

	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
	if (!hcd->regs) {
		pr_debug("ioremap failed");
		retval = -ENOMEM;
		goto err2;
	}

	if ((retval = pxa27x_start_hc(&pdev->dev)) < 0) {
		pr_debug("pxa27x_start_hc failed");
		goto err3;
	}

	/* Select Power Management Mode */
	pxa27x_ohci_select_pmm(inf->port_mode);

	if (inf->power_budget)
		hcd->power_budget = inf->power_budget;

	ohci_hcd_init(hcd_to_ohci(hcd));

	retval = usb_add_hcd(hcd, irq, IRQF_DISABLED);
	if (retval == 0)
		return retval;

	pxa27x_stop_hc(&pdev->dev);
 err3:
	iounmap(hcd->regs);
 err2:
	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
 err1:
	usb_put_hcd(hcd);
	clk_put(usb_clk);
	return retval;
}


/* may be called without controller electrically present */
/* may be called with controller, bus, and devices active */

/**
 * usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
 * @dev: USB Host Controller being removed
 * Context: !in_interrupt()
 *
 * Reverses the effect of usb_hcd_pxa27x_probe(), first invoking
 * the HCD's stop() method.  It is always called from a thread
 * context, normally "rmmod", "apmd", or something similar.
 *
 */
void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev)
{
	usb_remove_hcd(hcd);
	pxa27x_stop_hc(&pdev->dev);
	iounmap(hcd->regs);
	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
	usb_put_hcd(hcd);
	clk_put(usb_clk);
}

/*-------------------------------------------------------------------------*/

static int __devinit
ohci_pxa27x_start (struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
	int		ret;

	ohci_dbg (ohci, "ohci_pxa27x_start, ohci:%p", ohci);

	/* The value of NDP in roothub_a is incorrect on this hardware */
	ohci->num_ports = 3;

	if ((ret = ohci_init(ohci)) < 0)
		return ret;

	if ((ret = ohci_run (ohci)) < 0) {
		err ("can't start %s", hcd->self.bus_name);
		ohci_stop (hcd);
		return ret;
	}

	return 0;
}

/*-------------------------------------------------------------------------*/

static const struct hc_driver ohci_pxa27x_hc_driver = {
	.description =		hcd_name,
	.product_desc =		"PXA27x OHCI",
	.hcd_priv_size =	sizeof(struct ohci_hcd),

	/*
	 * generic hardware linkage
	 */
	.irq =			ohci_irq,
	.flags =		HCD_USB11 | HCD_MEMORY,

	/*
	 * basic lifecycle operations
	 */
	.start =		ohci_pxa27x_start,
	.stop =			ohci_stop,
	.shutdown =		ohci_shutdown,

	/*
	 * managing i/o requests and associated device resources
	 */
	.urb_enqueue =		ohci_urb_enqueue,
	.urb_dequeue =		ohci_urb_dequeue,
	.endpoint_disable =	ohci_endpoint_disable,

	/*
	 * scheduling support
	 */
	.get_frame_number =	ohci_get_frame,

	/*
	 * root hub support
	 */
	.hub_status_data =	ohci_hub_status_data,
	.hub_control =		ohci_hub_control,
#ifdef  CONFIG_PM
	.bus_suspend =		ohci_bus_suspend,
	.bus_resume =		ohci_bus_resume,
#endif
	.start_port_reset =	ohci_start_port_reset,
};

/*-------------------------------------------------------------------------*/

static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev)
{
	pr_debug ("In ohci_hcd_pxa27x_drv_probe");

	if (usb_disabled())
		return -ENODEV;

	return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev);
}

static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
{
	struct usb_hcd *hcd = platform_get_drvdata(pdev);

	usb_hcd_pxa27x_remove(hcd, pdev);
	platform_set_drvdata(pdev, NULL);
	return 0;
}

#ifdef	CONFIG_PM
static int ohci_hcd_pxa27x_drv_suspend(struct platform_device *pdev, pm_message_t state)
{
	struct usb_hcd *hcd = platform_get_drvdata(pdev);
	struct ohci_hcd *ohci = hcd_to_ohci(hcd);

	if (time_before(jiffies, ohci->next_statechange))
		msleep(5);
	ohci->next_statechange = jiffies;

	pxa27x_stop_hc(&pdev->dev);
	hcd->state = HC_STATE_SUSPENDED;

	return 0;
}

static int ohci_hcd_pxa27x_drv_resume(struct platform_device *pdev)
{
	struct usb_hcd *hcd = platform_get_drvdata(pdev);
	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
	int status;

	if (time_before(jiffies, ohci->next_statechange))
		msleep(5);
	ohci->next_statechange = jiffies;

	if ((status = pxa27x_start_hc(&pdev->dev)) < 0)
		return status;

	ohci_finish_controller_resume(hcd);
	return 0;
}
#endif

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:pxa27x-ohci");

static struct platform_driver ohci_hcd_pxa27x_driver = {
	.probe		= ohci_hcd_pxa27x_drv_probe,
	.remove		= ohci_hcd_pxa27x_drv_remove,
	.shutdown	= usb_hcd_platform_shutdown,
#ifdef CONFIG_PM
	.suspend	= ohci_hcd_pxa27x_drv_suspend,
	.resume		= ohci_hcd_pxa27x_drv_resume,
#endif
	.driver		= {
		.name	= "pxa27x-ohci",
		.owner	= THIS_MODULE,
	},
};
Commit	Line	Data
1da177e4 LT	1	/*
	2	* OHCI HCD (Host Controller Driver) for USB.
	3	*
	4	* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
	5	* (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
	6	* (C) Copyright 2002 Hewlett-Packard Company
	7	*
	8	* Bus Glue for pxa27x
	9	*
	10	* Written by Christopher Hoover <ch@hpl.hp.com>
	11	* Based on fragments of previous driver by Russell King et al.
	12	*
	13	* Modified for LH7A404 from ohci-sa1111.c
	14	* by Durgesh Pattamatta <pattamattad@sharpsec.com>
	15	*
	16	* Modified for pxa27x from ohci-lh7a404.c
	17	* by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
	18	*
	19	* This file is licenced under the GPL.
	20	*/
	21
	22	#include <linux/device.h>
4e57b681	23	#include <linux/signal.h>
d052d1be	24	#include <linux/platform_device.h>
a8bcf410	25	#include <linux/clk.h>
4fd5f826	26
a09e64fb	27	#include <mach/hardware.h>
a09e64fb	28	#include <mach/ohci.h>
1da177e4	29
596050bc EM	30	/*
	31	* UHC: USB Host Controller (OHCI-like) register definitions
	32	*/
	33	#define UHC_BASE_PHYS (0x4C000000)
	34	#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
	35	#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
	36	#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
	37	#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
	38	#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
	39	#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
	40	#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
	41	#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
	42	#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
	43	#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
	44	#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
	45	#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
	46	#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
	47	#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
	48	#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
	49	#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
	50	#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
	51	#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
	52
	53	#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
	54	#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
	55	#define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
	56	#define UHCRHDA_POTPGT(x) \
	57	(((x) & 0xff) << 24) /* Power On To Power Good Time */
	58
	59	#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
	60	#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
	61	#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
	62	#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
	63	#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
	64
	65	#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
	66	#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
	67	#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
	68	#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
	69	#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
	70	#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
	71	#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
	72	#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
	73	#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
	74	#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
	75
	76	#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
	77	#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
	78	#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
	79	#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
	80	#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
	81	#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
	82	#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
	83	#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
	84	#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
	85	#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
	86	#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
	87	#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
	88
	89	#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
	90	#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
	91	#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
	92	#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
	93	#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
94	#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
95	Interrupt Enable*/
96	#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
97	#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
98
99	#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
100
101
1da177e4 LT	102	#define PXA_UHC_MAX_PORTNUM 3
	103
	104	#define UHCRHPS(x) __REG2( 0x4C000050, (x)<<2 )
	105
a8bcf410	106	static struct clk *usb_clk;
a8bcf410	107
1da177e4 LT	108	/*
	109	PMM_NPS_MODE -- PMM Non-power switching mode
	110	Ports are powered continuously.
	111
	112	PMM_GLOBAL_MODE -- PMM global switching mode
	113	All ports are powered at the same time.
	114
	115	PMM_PERPORT_MODE -- PMM per port switching mode
	116	Ports are powered individually.
	117	*/
	118	static int pxa27x_ohci_select_pmm( int mode )
	119	{
1da177e4 LT	120	switch ( mode ) {
	121	case PMM_NPS_MODE:
	122	UHCRHDA \|= RH_A_NPS;
dd9048af	123	break;
1da177e4 LT	124	case PMM_GLOBAL_MODE:
	125	UHCRHDA &= ~(RH_A_NPS & RH_A_PSM);
	126	break;
	127	case PMM_PERPORT_MODE:
	128	UHCRHDA &= ~(RH_A_NPS);
	129	UHCRHDA \|= RH_A_PSM;
	130
	131	/* Set port power control mask bits, only 3 ports. */
	132	UHCRHDB \|= (0x7<<17);
	133	break;
	134	default:
	135	printk( KERN_ERR
dd9048af	136	"Invalid mode %d, set to non-power switch mode.\n",
1da177e4 LT	137	mode );
1da177e4 LT	138
1da177e4 LT	139	UHCRHDA \|= RH_A_NPS;
	140	}
	141
	142	return 0;
	143	}
	144
1da177e4 LT	145	extern int usb_disabled(void);
	146
	147	/-------------------------------------------------------------------------/
	148
097b5334 EM	149	static inline void pxa27x_setup_hc(struct pxaohci_platform_data *inf)
	150	{
	151	uint32_t uhchr = UHCHR;
	152	uint32_t uhcrhda = UHCRHDA;
	153
	154	if (inf->flags & ENABLE_PORT1)
	155	uhchr &= ~UHCHR_SSEP1;
	156
	157	if (inf->flags & ENABLE_PORT2)
	158	uhchr &= ~UHCHR_SSEP2;
	159
	160	if (inf->flags & ENABLE_PORT3)
	161	uhchr &= ~UHCHR_SSEP3;
	162
	163	if (inf->flags & POWER_CONTROL_LOW)
	164	uhchr \|= UHCHR_PCPL;
	165
	166	if (inf->flags & POWER_SENSE_LOW)
	167	uhchr \|= UHCHR_PSPL;
	168
	169	if (inf->flags & NO_OC_PROTECTION)
	170	uhcrhda \|= UHCRHDA_NOCP;
	171
	172	if (inf->flags & OC_MODE_PERPORT)
	173	uhcrhda \|= UHCRHDA_OCPM;
	174
	175	if (inf->power_on_delay) {
	176	uhcrhda &= ~UHCRHDA_POTPGT(0xff);
	177	uhcrhda \|= UHCRHDA_POTPGT(inf->power_on_delay / 2);
	178	}
	179
	180	UHCHR = uhchr;
	181	UHCRHDA = uhcrhda;
	182	}
	183
0cb0b0d3 EM	184	#ifdef CONFIG_CPU_PXA27x
	185	extern void pxa27x_clear_otgph(void);
	186	#else
	187	#define pxa27x_clear_otgph() do {} while (0)
	188	#endif
	189
81f280e2	190	static int pxa27x_start_hc(struct device *dev)
1da177e4	191	{
81f280e2 RP	192	int retval = 0;
	193	struct pxaohci_platform_data *inf;
	194
	195	inf = dev->platform_data;
	196
a8bcf410	197	clk_enable(usb_clk);
1da177e4 LT	198
	199	UHCHR \|= UHCHR_FHR;
	200	udelay(11);
	201	UHCHR &= ~UHCHR_FHR;
	202
	203	UHCHR \|= UHCHR_FSBIR;
	204	while (UHCHR & UHCHR_FSBIR)
	205	cpu_relax();
	206
097b5334 EM	207	pxa27x_setup_hc(inf);
097b5334 EM	208
81f280e2 RP	209	if (inf->init)
81f280e2 RP	210	retval = inf->init(dev);
155faf5e	211
81f280e2 RP	212	if (retval < 0)
81f280e2 RP	213	return retval;
1da177e4 LT	214
	215	UHCHR &= ~UHCHR_SSE;
	216
	217	UHCHIE = (UHCHIE_UPRIE \| UHCHIE_RWIE);
155faf5e DB	218
155faf5e DB	219	/* Clear any OTG Pin Hold */
0cb0b0d3	220	pxa27x_clear_otgph();
81f280e2	221	return 0;
1da177e4 LT	222	}
1da177e4 LT	223
81f280e2	224	static void pxa27x_stop_hc(struct device *dev)
1da177e4	225	{
81f280e2 RP	226	struct pxaohci_platform_data *inf;
	227
	228	inf = dev->platform_data;
	229
	230	if (inf->exit)
	231	inf->exit(dev);
	232
1da177e4 LT	233	UHCHR \|= UHCHR_FHR;
	234	udelay(11);
	235	UHCHR &= ~UHCHR_FHR;
	236
	237	UHCCOMS \|= 1;
	238	udelay(10);
	239
a8bcf410	240	clk_disable(usb_clk);
1da177e4 LT	241	}
	242
	243
	244	/-------------------------------------------------------------------------/
	245
	246	/* configure so an HC device and id are always provided */
	247	/* always called with process context; sleeping is OK */
	248
	249
	250	/**
	251	* usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs
	252	* Context: !in_interrupt()
	253	*
	254	* Allocates basic resources for this USB host controller, and
	255	* then invokes the start() method for the HCD associated with it
	256	* through the hotplug entry's driver_data.
	257	*
	258	*/
81f280e2	259	int usb_hcd_pxa27x_probe (const struct hc_driver driver, struct platform_device pdev)
1da177e4	260	{
84bab739	261	int retval, irq;
1da177e4	262	struct usb_hcd *hcd;
81f280e2	263	struct pxaohci_platform_data *inf;
84bab739	264	struct resource *r;
81f280e2 RP	265
81f280e2 RP	266	inf = pdev->dev.platform_data;
1da177e4	267
81f280e2 RP	268	if (!inf)
	269	return -ENODEV;
	270
84bab739 EM	271	irq = platform_get_irq(pdev, 0);
	272	if (irq < 0) {
	273	pr_err("no resource of IORESOURCE_IRQ");
	274	return -ENXIO;
1da177e4 LT	275	}
1da177e4 LT	276
a8bcf410	277	usb_clk = clk_get(&pdev->dev, "USBCLK");
	278	if (IS_ERR(usb_clk))
	279	return PTR_ERR(usb_clk);
	280
81f280e2	281	hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
1da177e4 LT	282	if (!hcd)
1da177e4 LT	283	return -ENOMEM;
84bab739 EM	284
	285	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	286	if (!r) {
	287	pr_err("no resource of IORESOURCE_MEM");
	288	retval = -ENXIO;
	289	goto err1;
	290	}
	291
	292	hcd->rsrc_start = r->start;
	293	hcd->rsrc_len = resource_size(r);
1da177e4 LT	294
	295	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
	296	pr_debug("request_mem_region failed");
	297	retval = -EBUSY;
	298	goto err1;
	299	}
	300
	301	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
	302	if (!hcd->regs) {
	303	pr_debug("ioremap failed");
	304	retval = -ENOMEM;
	305	goto err2;
	306	}
	307
81f280e2 RP	308	if ((retval = pxa27x_start_hc(&pdev->dev)) < 0) {
	309	pr_debug("pxa27x_start_hc failed");
	310	goto err3;
	311	}
1da177e4 LT	312
1da177e4 LT	313	/* Select Power Management Mode */
81f280e2	314	pxa27x_ohci_select_pmm(inf->port_mode);
1da177e4	315
0c27c5d5 RP	316	if (inf->power_budget)
	317	hcd->power_budget = inf->power_budget;
	318
1da177e4 LT	319	ohci_hcd_init(hcd_to_ohci(hcd));
1da177e4 LT	320
84bab739	321	retval = usb_add_hcd(hcd, irq, IRQF_DISABLED);
1da177e4 LT	322	if (retval == 0)
	323	return retval;
	324
81f280e2 RP	325	pxa27x_stop_hc(&pdev->dev);
81f280e2 RP	326	err3:
1da177e4 LT	327	iounmap(hcd->regs);
	328	err2:
	329	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
	330	err1:
	331	usb_put_hcd(hcd);
a8bcf410	332	clk_put(usb_clk);
1da177e4 LT	333	return retval;
	334	}
	335
	336
	337	/* may be called without controller electrically present */
	338	/* may be called with controller, bus, and devices active */
	339
	340	/**
	341	* usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
	342	* @dev: USB Host Controller being removed
	343	* Context: !in_interrupt()
	344	*
	345	* Reverses the effect of usb_hcd_pxa27x_probe(), first invoking
	346	* the HCD's stop() method. It is always called from a thread
	347	* context, normally "rmmod", "apmd", or something similar.
	348	*
	349	*/
81f280e2	350	void usb_hcd_pxa27x_remove (struct usb_hcd hcd, struct platform_device pdev)
1da177e4 LT	351	{
1da177e4 LT	352	usb_remove_hcd(hcd);
81f280e2	353	pxa27x_stop_hc(&pdev->dev);
1da177e4 LT	354	iounmap(hcd->regs);
	355	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
	356	usb_put_hcd(hcd);
a8bcf410	357	clk_put(usb_clk);
1da177e4 LT	358	}
	359
	360	/-------------------------------------------------------------------------/
	361
	362	static int __devinit
	363	ohci_pxa27x_start (struct usb_hcd *hcd)
	364	{
	365	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	366	int ret;
	367
	368	ohci_dbg (ohci, "ohci_pxa27x_start, ohci:%p", ohci);
	369
fdd13b36 DB	370	/* The value of NDP in roothub_a is incorrect on this hardware */
	371	ohci->num_ports = 3;
	372
1da177e4 LT	373	if ((ret = ohci_init(ohci)) < 0)
	374	return ret;
	375
	376	if ((ret = ohci_run (ohci)) < 0) {
	377	err ("can't start %s", hcd->self.bus_name);
	378	ohci_stop (hcd);
	379	return ret;
	380	}
	381
	382	return 0;
	383	}
	384
	385	/-------------------------------------------------------------------------/
	386
	387	static const struct hc_driver ohci_pxa27x_hc_driver = {
	388	.description = hcd_name,
	389	.product_desc = "PXA27x OHCI",
	390	.hcd_priv_size = sizeof(struct ohci_hcd),
	391
	392	/*
	393	* generic hardware linkage
	394	*/
	395	.irq = ohci_irq,
	396	.flags = HCD_USB11 \| HCD_MEMORY,
	397
	398	/*
	399	* basic lifecycle operations
	400	*/
	401	.start = ohci_pxa27x_start,
	402	.stop = ohci_stop,
dd9048af	403	.shutdown = ohci_shutdown,
1da177e4 LT	404
	405	/*
	406	* managing i/o requests and associated device resources
	407	*/
	408	.urb_enqueue = ohci_urb_enqueue,
	409	.urb_dequeue = ohci_urb_dequeue,
	410	.endpoint_disable = ohci_endpoint_disable,
	411
	412	/*
	413	* scheduling support
	414	*/
	415	.get_frame_number = ohci_get_frame,
	416
	417	/*
	418	* root hub support
	419	*/
	420	.hub_status_data = ohci_hub_status_data,
	421	.hub_control = ohci_hub_control,
8ad7fe16	422	#ifdef CONFIG_PM
0c0382e3 AS	423	.bus_suspend = ohci_bus_suspend,
0c0382e3 AS	424	.bus_resume = ohci_bus_resume,
1da177e4	425	#endif
9293677a	426	.start_port_reset = ohci_start_port_reset,
1da177e4 LT	427	};
	428
	429	/-------------------------------------------------------------------------/
	430
3ae5eaec	431	static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev)
1da177e4	432	{
1da177e4 LT	433	pr_debug ("In ohci_hcd_pxa27x_drv_probe");
	434
	435	if (usb_disabled())
	436	return -ENODEV;
	437
81f280e2	438	return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev);
1da177e4 LT	439	}
1da177e4 LT	440
3ae5eaec	441	static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
1da177e4	442	{
3ae5eaec	443	struct usb_hcd *hcd = platform_get_drvdata(pdev);
1da177e4 LT	444
1da177e4 LT	445	usb_hcd_pxa27x_remove(hcd, pdev);
a5e36d20	446	platform_set_drvdata(pdev, NULL);
1da177e4 LT	447	return 0;
	448	}
	449
2e1dcc16 RP	450	#ifdef CONFIG_PM
2e1dcc16 RP	451	static int ohci_hcd_pxa27x_drv_suspend(struct platform_device *pdev, pm_message_t state)
1da177e4	452	{
a5e36d20 RP	453	struct usb_hcd *hcd = platform_get_drvdata(pdev);
a5e36d20 RP	454	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
2e1dcc16 RP	455
	456	if (time_before(jiffies, ohci->next_statechange))
	457	msleep(5);
	458	ohci->next_statechange = jiffies;
	459
	460	pxa27x_stop_hc(&pdev->dev);
a5e36d20	461	hcd->state = HC_STATE_SUSPENDED;
1da177e4 LT	462
	463	return 0;
	464	}
	465
2e1dcc16	466	static int ohci_hcd_pxa27x_drv_resume(struct platform_device *pdev)
1da177e4	467	{
a5e36d20 RP	468	struct usb_hcd *hcd = platform_get_drvdata(pdev);
a5e36d20 RP	469	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
2e1dcc16 RP	470	int status;
	471
	472	if (time_before(jiffies, ohci->next_statechange))
	473	msleep(5);
	474	ohci->next_statechange = jiffies;
	475
	476	if ((status = pxa27x_start_hc(&pdev->dev)) < 0)
	477	return status;
	478
43bbb7e0	479	ohci_finish_controller_resume(hcd);
1da177e4 LT	480	return 0;
1da177e4 LT	481	}
2e1dcc16	482	#endif
1da177e4	483
f4fce61d KS	484	/* work with hotplug and coldplug */
f4fce61d KS	485	MODULE_ALIAS("platform:pxa27x-ohci");
1da177e4	486
3ae5eaec	487	static struct platform_driver ohci_hcd_pxa27x_driver = {
1da177e4 LT	488	.probe = ohci_hcd_pxa27x_drv_probe,
1da177e4 LT	489	.remove = ohci_hcd_pxa27x_drv_remove,
dd9048af	490	.shutdown = usb_hcd_platform_shutdown,
2e1dcc16	491	#ifdef CONFIG_PM
dd9048af	492	.suspend = ohci_hcd_pxa27x_drv_suspend,
3ae5eaec	493	.resume = ohci_hcd_pxa27x_drv_resume,
2e1dcc16	494	#endif
3ae5eaec RK	495	.driver = {
3ae5eaec RK	496	.name = "pxa27x-ohci",
f4fce61d	497	.owner = THIS_MODULE,
3ae5eaec	498	},
1da177e4 LT	499	};
1da177e4 LT	500