Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * OHCI HCD (Host Controller Driver) for USB. | |
dd9048af | 3 | * |
1da177e4 LT |
4 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> |
5 | * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net> | |
dd9048af | 6 | * |
1da177e4 LT |
7 | * This file is licenced under the GPL. |
8 | */ | |
9 | ||
7d12e780 | 10 | #include <linux/irq.h> |
5a0e3ad6 | 11 | #include <linux/slab.h> |
7d12e780 | 12 | |
1da177e4 LT |
13 | static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv) |
14 | { | |
15 | int last = urb_priv->length - 1; | |
16 | ||
17 | if (last >= 0) { | |
18 | int i; | |
19 | struct td *td; | |
20 | ||
21 | for (i = 0; i <= last; i++) { | |
22 | td = urb_priv->td [i]; | |
23 | if (td) | |
24 | td_free (hc, td); | |
25 | } | |
26 | } | |
27 | ||
28 | list_del (&urb_priv->pending); | |
29 | kfree (urb_priv); | |
30 | } | |
31 | ||
32 | /*-------------------------------------------------------------------------*/ | |
33 | ||
34 | /* | |
35 | * URB goes back to driver, and isn't reissued. | |
36 | * It's completely gone from HC data structures. | |
37 | * PRECONDITION: ohci lock held, irqs blocked. | |
38 | */ | |
39 | static void | |
55d84968 | 40 | finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status) |
1da177e4 LT |
41 | __releases(ohci->lock) |
42 | __acquires(ohci->lock) | |
43 | { | |
a8693424 AS |
44 | struct device *dev = ohci_to_hcd(ohci)->self.controller; |
45 | struct usb_host_endpoint *ep = urb->ep; | |
46 | struct urb_priv *urb_priv; | |
47 | ||
1da177e4 LT |
48 | // ASSERT (urb->hcpriv != 0); |
49 | ||
a8693424 | 50 | restart: |
1da177e4 | 51 | urb_free_priv (ohci, urb->hcpriv); |
ece1d77e | 52 | urb->hcpriv = NULL; |
55d84968 AS |
53 | if (likely(status == -EINPROGRESS)) |
54 | status = 0; | |
1da177e4 LT |
55 | |
56 | switch (usb_pipetype (urb->pipe)) { | |
57 | case PIPE_ISOCHRONOUS: | |
58 | ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--; | |
a1f17a87 LY |
59 | if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) { |
60 | if (quirk_amdiso(ohci)) | |
ad93562b | 61 | usb_amd_quirk_pll_enable(); |
a1f17a87 | 62 | if (quirk_amdprefetch(ohci)) |
2621d011 | 63 | sb800_prefetch(dev, 0); |
a1f17a87 | 64 | } |
1da177e4 LT |
65 | break; |
66 | case PIPE_INTERRUPT: | |
67 | ohci_to_hcd(ohci)->self.bandwidth_int_reqs--; | |
68 | break; | |
69 | } | |
70 | ||
1da177e4 | 71 | /* urb->complete() can reenter this HCD */ |
e9df41c5 | 72 | usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci), urb); |
1da177e4 | 73 | spin_unlock (&ohci->lock); |
4a00027d | 74 | usb_hcd_giveback_urb(ohci_to_hcd(ohci), urb, status); |
1da177e4 LT |
75 | spin_lock (&ohci->lock); |
76 | ||
77 | /* stop periodic dma if it's not needed */ | |
78 | if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0 | |
79 | && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) { | |
80 | ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE); | |
81 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
82 | } | |
a8693424 AS |
83 | |
84 | /* | |
85 | * An isochronous URB that is sumitted too late won't have any TDs | |
86 | * (marked by the fact that the td_cnt value is larger than the | |
87 | * actual number of TDs). If the next URB on this endpoint is like | |
88 | * that, give it back now. | |
89 | */ | |
90 | if (!list_empty(&ep->urb_list)) { | |
91 | urb = list_first_entry(&ep->urb_list, struct urb, urb_list); | |
92 | urb_priv = urb->hcpriv; | |
93 | if (urb_priv->td_cnt > urb_priv->length) { | |
94 | status = 0; | |
95 | goto restart; | |
96 | } | |
97 | } | |
1da177e4 LT |
98 | } |
99 | ||
100 | ||
101 | /*-------------------------------------------------------------------------* | |
102 | * ED handling functions | |
dd9048af | 103 | *-------------------------------------------------------------------------*/ |
1da177e4 LT |
104 | |
105 | /* search for the right schedule branch to use for a periodic ed. | |
106 | * does some load balancing; returns the branch, or negative errno. | |
107 | */ | |
108 | static int balance (struct ohci_hcd *ohci, int interval, int load) | |
109 | { | |
110 | int i, branch = -ENOSPC; | |
111 | ||
112 | /* iso periods can be huge; iso tds specify frame numbers */ | |
113 | if (interval > NUM_INTS) | |
114 | interval = NUM_INTS; | |
115 | ||
116 | /* search for the least loaded schedule branch of that period | |
117 | * that has enough bandwidth left unreserved. | |
118 | */ | |
119 | for (i = 0; i < interval ; i++) { | |
120 | if (branch < 0 || ohci->load [branch] > ohci->load [i]) { | |
1da177e4 LT |
121 | int j; |
122 | ||
123 | /* usb 1.1 says 90% of one frame */ | |
124 | for (j = i; j < NUM_INTS; j += interval) { | |
125 | if ((ohci->load [j] + load) > 900) | |
126 | break; | |
127 | } | |
128 | if (j < NUM_INTS) | |
129 | continue; | |
dd9048af | 130 | branch = i; |
1da177e4 LT |
131 | } |
132 | } | |
133 | return branch; | |
134 | } | |
135 | ||
136 | /*-------------------------------------------------------------------------*/ | |
137 | ||
138 | /* both iso and interrupt requests have periods; this routine puts them | |
139 | * into the schedule tree in the apppropriate place. most iso devices use | |
140 | * 1msec periods, but that's not required. | |
141 | */ | |
142 | static void periodic_link (struct ohci_hcd *ohci, struct ed *ed) | |
143 | { | |
144 | unsigned i; | |
145 | ||
d2c4254f | 146 | ohci_dbg(ohci, "link %sed %p branch %d [%dus.], interval %d\n", |
1da177e4 LT |
147 | (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "", |
148 | ed, ed->branch, ed->load, ed->interval); | |
149 | ||
150 | for (i = ed->branch; i < NUM_INTS; i += ed->interval) { | |
151 | struct ed **prev = &ohci->periodic [i]; | |
152 | __hc32 *prev_p = &ohci->hcca->int_table [i]; | |
153 | struct ed *here = *prev; | |
154 | ||
155 | /* sorting each branch by period (slow before fast) | |
156 | * lets us share the faster parts of the tree. | |
157 | * (plus maybe: put interrupt eds before iso) | |
158 | */ | |
159 | while (here && ed != here) { | |
160 | if (ed->interval > here->interval) | |
161 | break; | |
162 | prev = &here->ed_next; | |
163 | prev_p = &here->hwNextED; | |
164 | here = *prev; | |
165 | } | |
166 | if (ed != here) { | |
167 | ed->ed_next = here; | |
168 | if (here) | |
169 | ed->hwNextED = *prev_p; | |
170 | wmb (); | |
171 | *prev = ed; | |
172 | *prev_p = cpu_to_hc32(ohci, ed->dma); | |
173 | wmb(); | |
174 | } | |
175 | ohci->load [i] += ed->load; | |
176 | } | |
177 | ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval; | |
178 | } | |
179 | ||
180 | /* link an ed into one of the HC chains */ | |
181 | ||
182 | static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed) | |
dd9048af | 183 | { |
1da177e4 LT |
184 | int branch; |
185 | ||
1da177e4 LT |
186 | ed->state = ED_OPER; |
187 | ed->ed_prev = NULL; | |
188 | ed->ed_next = NULL; | |
189 | ed->hwNextED = 0; | |
190 | wmb (); | |
191 | ||
192 | /* we care about rm_list when setting CLE/BLE in case the HC was at | |
193 | * work on some TD when CLE/BLE was turned off, and isn't quiesced | |
194 | * yet. finish_unlinks() restarts as needed, some upcoming INTR_SF. | |
195 | * | |
196 | * control and bulk EDs are doubly linked (ed_next, ed_prev), but | |
197 | * periodic ones are singly linked (ed_next). that's because the | |
198 | * periodic schedule encodes a tree like figure 3-5 in the ohci | |
199 | * spec: each qh can have several "previous" nodes, and the tree | |
200 | * doesn't have unused/idle descriptors. | |
201 | */ | |
202 | switch (ed->type) { | |
203 | case PIPE_CONTROL: | |
204 | if (ohci->ed_controltail == NULL) { | |
205 | WARN_ON (ohci->hc_control & OHCI_CTRL_CLE); | |
206 | ohci_writel (ohci, ed->dma, | |
207 | &ohci->regs->ed_controlhead); | |
208 | } else { | |
209 | ohci->ed_controltail->ed_next = ed; | |
210 | ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci, | |
211 | ed->dma); | |
212 | } | |
213 | ed->ed_prev = ohci->ed_controltail; | |
214 | if (!ohci->ed_controltail && !ohci->ed_rm_list) { | |
215 | wmb(); | |
216 | ohci->hc_control |= OHCI_CTRL_CLE; | |
217 | ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent); | |
218 | ohci_writel (ohci, ohci->hc_control, | |
219 | &ohci->regs->control); | |
220 | } | |
221 | ohci->ed_controltail = ed; | |
222 | break; | |
223 | ||
224 | case PIPE_BULK: | |
225 | if (ohci->ed_bulktail == NULL) { | |
226 | WARN_ON (ohci->hc_control & OHCI_CTRL_BLE); | |
227 | ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead); | |
228 | } else { | |
229 | ohci->ed_bulktail->ed_next = ed; | |
230 | ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci, | |
231 | ed->dma); | |
232 | } | |
233 | ed->ed_prev = ohci->ed_bulktail; | |
234 | if (!ohci->ed_bulktail && !ohci->ed_rm_list) { | |
235 | wmb(); | |
236 | ohci->hc_control |= OHCI_CTRL_BLE; | |
237 | ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent); | |
238 | ohci_writel (ohci, ohci->hc_control, | |
239 | &ohci->regs->control); | |
240 | } | |
241 | ohci->ed_bulktail = ed; | |
242 | break; | |
243 | ||
244 | // case PIPE_INTERRUPT: | |
245 | // case PIPE_ISOCHRONOUS: | |
246 | default: | |
247 | branch = balance (ohci, ed->interval, ed->load); | |
248 | if (branch < 0) { | |
249 | ohci_dbg (ohci, | |
250 | "ERR %d, interval %d msecs, load %d\n", | |
251 | branch, ed->interval, ed->load); | |
252 | // FIXME if there are TDs queued, fail them! | |
253 | return branch; | |
254 | } | |
255 | ed->branch = branch; | |
256 | periodic_link (ohci, ed); | |
dd9048af | 257 | } |
1da177e4 LT |
258 | |
259 | /* the HC may not see the schedule updates yet, but if it does | |
260 | * then they'll be properly ordered. | |
261 | */ | |
262 | return 0; | |
263 | } | |
264 | ||
265 | /*-------------------------------------------------------------------------*/ | |
266 | ||
267 | /* scan the periodic table to find and unlink this ED */ | |
268 | static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed) | |
269 | { | |
270 | int i; | |
271 | ||
272 | for (i = ed->branch; i < NUM_INTS; i += ed->interval) { | |
273 | struct ed *temp; | |
274 | struct ed **prev = &ohci->periodic [i]; | |
275 | __hc32 *prev_p = &ohci->hcca->int_table [i]; | |
276 | ||
277 | while (*prev && (temp = *prev) != ed) { | |
278 | prev_p = &temp->hwNextED; | |
279 | prev = &temp->ed_next; | |
280 | } | |
281 | if (*prev) { | |
282 | *prev_p = ed->hwNextED; | |
283 | *prev = ed->ed_next; | |
284 | } | |
285 | ohci->load [i] -= ed->load; | |
dd9048af | 286 | } |
1da177e4 LT |
287 | ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval; |
288 | ||
d2c4254f | 289 | ohci_dbg(ohci, "unlink %sed %p branch %d [%dus.], interval %d\n", |
1da177e4 LT |
290 | (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "", |
291 | ed, ed->branch, ed->load, ed->interval); | |
292 | } | |
293 | ||
dd9048af | 294 | /* unlink an ed from one of the HC chains. |
1da177e4 LT |
295 | * just the link to the ed is unlinked. |
296 | * the link from the ed still points to another operational ed or 0 | |
297 | * so the HC can eventually finish the processing of the unlinked ed | |
298 | * (assuming it already started that, which needn't be true). | |
299 | * | |
300 | * ED_UNLINK is a transient state: the HC may still see this ED, but soon | |
301 | * it won't. ED_SKIP means the HC will finish its current transaction, | |
302 | * but won't start anything new. The TD queue may still grow; device | |
303 | * drivers don't know about this HCD-internal state. | |
304 | * | |
305 | * When the HC can't see the ED, something changes ED_UNLINK to one of: | |
306 | * | |
307 | * - ED_OPER: when there's any request queued, the ED gets rescheduled | |
308 | * immediately. HC should be working on them. | |
309 | * | |
977dcfdc | 310 | * - ED_IDLE: when there's no TD queue or the HC isn't running. |
1da177e4 LT |
311 | * |
312 | * When finish_unlinks() runs later, after SOF interrupt, it will often | |
313 | * complete one or more URB unlinks before making that state change. | |
314 | */ | |
dd9048af | 315 | static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed) |
1da177e4 LT |
316 | { |
317 | ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP); | |
318 | wmb (); | |
319 | ed->state = ED_UNLINK; | |
320 | ||
321 | /* To deschedule something from the control or bulk list, just | |
322 | * clear CLE/BLE and wait. There's no safe way to scrub out list | |
323 | * head/current registers until later, and "later" isn't very | |
324 | * tightly specified. Figure 6-5 and Section 6.4.2.2 show how | |
325 | * the HC is reading the ED queues (while we modify them). | |
326 | * | |
327 | * For now, ed_schedule() is "later". It might be good paranoia | |
328 | * to scrub those registers in finish_unlinks(), in case of bugs | |
329 | * that make the HC try to use them. | |
330 | */ | |
331 | switch (ed->type) { | |
332 | case PIPE_CONTROL: | |
333 | /* remove ED from the HC's list: */ | |
334 | if (ed->ed_prev == NULL) { | |
335 | if (!ed->hwNextED) { | |
336 | ohci->hc_control &= ~OHCI_CTRL_CLE; | |
337 | ohci_writel (ohci, ohci->hc_control, | |
338 | &ohci->regs->control); | |
339 | // a ohci_readl() later syncs CLE with the HC | |
340 | } else | |
341 | ohci_writel (ohci, | |
342 | hc32_to_cpup (ohci, &ed->hwNextED), | |
343 | &ohci->regs->ed_controlhead); | |
344 | } else { | |
345 | ed->ed_prev->ed_next = ed->ed_next; | |
346 | ed->ed_prev->hwNextED = ed->hwNextED; | |
347 | } | |
348 | /* remove ED from the HCD's list: */ | |
349 | if (ohci->ed_controltail == ed) { | |
350 | ohci->ed_controltail = ed->ed_prev; | |
351 | if (ohci->ed_controltail) | |
352 | ohci->ed_controltail->ed_next = NULL; | |
353 | } else if (ed->ed_next) { | |
354 | ed->ed_next->ed_prev = ed->ed_prev; | |
355 | } | |
356 | break; | |
357 | ||
358 | case PIPE_BULK: | |
359 | /* remove ED from the HC's list: */ | |
360 | if (ed->ed_prev == NULL) { | |
361 | if (!ed->hwNextED) { | |
362 | ohci->hc_control &= ~OHCI_CTRL_BLE; | |
363 | ohci_writel (ohci, ohci->hc_control, | |
364 | &ohci->regs->control); | |
365 | // a ohci_readl() later syncs BLE with the HC | |
366 | } else | |
367 | ohci_writel (ohci, | |
368 | hc32_to_cpup (ohci, &ed->hwNextED), | |
369 | &ohci->regs->ed_bulkhead); | |
370 | } else { | |
371 | ed->ed_prev->ed_next = ed->ed_next; | |
372 | ed->ed_prev->hwNextED = ed->hwNextED; | |
373 | } | |
374 | /* remove ED from the HCD's list: */ | |
375 | if (ohci->ed_bulktail == ed) { | |
376 | ohci->ed_bulktail = ed->ed_prev; | |
377 | if (ohci->ed_bulktail) | |
378 | ohci->ed_bulktail->ed_next = NULL; | |
379 | } else if (ed->ed_next) { | |
380 | ed->ed_next->ed_prev = ed->ed_prev; | |
381 | } | |
382 | break; | |
383 | ||
384 | // case PIPE_INTERRUPT: | |
385 | // case PIPE_ISOCHRONOUS: | |
386 | default: | |
387 | periodic_unlink (ohci, ed); | |
388 | break; | |
389 | } | |
390 | } | |
391 | ||
392 | ||
393 | /*-------------------------------------------------------------------------*/ | |
394 | ||
395 | /* get and maybe (re)init an endpoint. init _should_ be done only as part | |
396 | * of enumeration, usb_set_configuration() or usb_set_interface(). | |
397 | */ | |
398 | static struct ed *ed_get ( | |
399 | struct ohci_hcd *ohci, | |
400 | struct usb_host_endpoint *ep, | |
401 | struct usb_device *udev, | |
402 | unsigned int pipe, | |
403 | int interval | |
404 | ) { | |
dd9048af | 405 | struct ed *ed; |
1da177e4 LT |
406 | unsigned long flags; |
407 | ||
408 | spin_lock_irqsave (&ohci->lock, flags); | |
409 | ||
8af93191 GKH |
410 | ed = ep->hcpriv; |
411 | if (!ed) { | |
1da177e4 LT |
412 | struct td *td; |
413 | int is_out; | |
414 | u32 info; | |
415 | ||
416 | ed = ed_alloc (ohci, GFP_ATOMIC); | |
417 | if (!ed) { | |
418 | /* out of memory */ | |
419 | goto done; | |
420 | } | |
421 | ||
dd9048af | 422 | /* dummy td; end of td list for ed */ |
1da177e4 | 423 | td = td_alloc (ohci, GFP_ATOMIC); |
dd9048af | 424 | if (!td) { |
1da177e4 LT |
425 | /* out of memory */ |
426 | ed_free (ohci, ed); | |
427 | ed = NULL; | |
428 | goto done; | |
429 | } | |
430 | ed->dummy = td; | |
431 | ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma); | |
432 | ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */ | |
433 | ed->state = ED_IDLE; | |
434 | ||
435 | is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN); | |
436 | ||
437 | /* FIXME usbcore changes dev->devnum before SET_ADDRESS | |
4b26d50b | 438 | * succeeds ... otherwise we wouldn't need "pipe". |
1da177e4 LT |
439 | */ |
440 | info = usb_pipedevice (pipe); | |
441 | ed->type = usb_pipetype(pipe); | |
442 | ||
443 | info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7; | |
29cc8897 | 444 | info |= usb_endpoint_maxp(&ep->desc) << 16; |
1da177e4 LT |
445 | if (udev->speed == USB_SPEED_LOW) |
446 | info |= ED_LOWSPEED; | |
447 | /* only control transfers store pids in tds */ | |
448 | if (ed->type != PIPE_CONTROL) { | |
449 | info |= is_out ? ED_OUT : ED_IN; | |
450 | if (ed->type != PIPE_BULK) { | |
451 | /* periodic transfers... */ | |
452 | if (ed->type == PIPE_ISOCHRONOUS) | |
453 | info |= ED_ISO; | |
454 | else if (interval > 32) /* iso can be bigger */ | |
455 | interval = 32; | |
456 | ed->interval = interval; | |
457 | ed->load = usb_calc_bus_time ( | |
458 | udev->speed, !is_out, | |
459 | ed->type == PIPE_ISOCHRONOUS, | |
29cc8897 | 460 | usb_endpoint_maxp(&ep->desc)) |
1da177e4 LT |
461 | / 1000; |
462 | } | |
463 | } | |
464 | ed->hwINFO = cpu_to_hc32(ohci, info); | |
465 | ||
466 | ep->hcpriv = ed; | |
467 | } | |
468 | ||
469 | done: | |
470 | spin_unlock_irqrestore (&ohci->lock, flags); | |
dd9048af | 471 | return ed; |
1da177e4 LT |
472 | } |
473 | ||
474 | /*-------------------------------------------------------------------------*/ | |
475 | ||
476 | /* request unlinking of an endpoint from an operational HC. | |
477 | * put the ep on the rm_list | |
478 | * real work is done at the next start frame (SF) hardware interrupt | |
479 | * caller guarantees HCD is running, so hardware access is safe, | |
480 | * and that ed->state is ED_OPER | |
481 | */ | |
482 | static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed) | |
dd9048af | 483 | { |
1da177e4 LT |
484 | ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE); |
485 | ed_deschedule (ohci, ed); | |
486 | ||
487 | /* rm_list is just singly linked, for simplicity */ | |
488 | ed->ed_next = ohci->ed_rm_list; | |
489 | ed->ed_prev = NULL; | |
490 | ohci->ed_rm_list = ed; | |
491 | ||
492 | /* enable SOF interrupt */ | |
493 | ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus); | |
494 | ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable); | |
495 | // flush those writes, and get latest HCCA contents | |
496 | (void) ohci_readl (ohci, &ohci->regs->control); | |
497 | ||
498 | /* SF interrupt might get delayed; record the frame counter value that | |
499 | * indicates when the HC isn't looking at it, so concurrent unlinks | |
500 | * behave. frame_no wraps every 2^16 msec, and changes right before | |
501 | * SF is triggered. | |
502 | */ | |
503 | ed->tick = ohci_frame_no(ohci) + 1; | |
504 | ||
505 | } | |
506 | ||
507 | /*-------------------------------------------------------------------------* | |
508 | * TD handling functions | |
509 | *-------------------------------------------------------------------------*/ | |
510 | ||
511 | /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ | |
512 | ||
513 | static void | |
514 | td_fill (struct ohci_hcd *ohci, u32 info, | |
515 | dma_addr_t data, int len, | |
516 | struct urb *urb, int index) | |
517 | { | |
518 | struct td *td, *td_pt; | |
519 | struct urb_priv *urb_priv = urb->hcpriv; | |
520 | int is_iso = info & TD_ISO; | |
521 | int hash; | |
522 | ||
523 | // ASSERT (index < urb_priv->length); | |
524 | ||
525 | /* aim for only one interrupt per urb. mostly applies to control | |
526 | * and iso; other urbs rarely need more than one TD per urb. | |
527 | * this way, only final tds (or ones with an error) cause IRQs. | |
528 | * at least immediately; use DI=6 in case any control request is | |
529 | * tempted to die part way through. (and to force the hc to flush | |
530 | * its donelist soonish, even on unlink paths.) | |
531 | * | |
532 | * NOTE: could delay interrupts even for the last TD, and get fewer | |
533 | * interrupts ... increasing per-urb latency by sharing interrupts. | |
534 | * Drivers that queue bulk urbs may request that behavior. | |
535 | */ | |
536 | if (index != (urb_priv->length - 1) | |
537 | || (urb->transfer_flags & URB_NO_INTERRUPT)) | |
538 | info |= TD_DI_SET (6); | |
539 | ||
540 | /* use this td as the next dummy */ | |
541 | td_pt = urb_priv->td [index]; | |
542 | ||
543 | /* fill the old dummy TD */ | |
544 | td = urb_priv->td [index] = urb_priv->ed->dummy; | |
545 | urb_priv->ed->dummy = td_pt; | |
546 | ||
547 | td->ed = urb_priv->ed; | |
548 | td->next_dl_td = NULL; | |
549 | td->index = index; | |
dd9048af | 550 | td->urb = urb; |
1da177e4 LT |
551 | td->data_dma = data; |
552 | if (!len) | |
553 | data = 0; | |
554 | ||
555 | td->hwINFO = cpu_to_hc32 (ohci, info); | |
556 | if (is_iso) { | |
557 | td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000); | |
558 | *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci, | |
559 | (data & 0x0FFF) | 0xE000); | |
1da177e4 | 560 | } else { |
dd9048af DB |
561 | td->hwCBP = cpu_to_hc32 (ohci, data); |
562 | } | |
1da177e4 LT |
563 | if (data) |
564 | td->hwBE = cpu_to_hc32 (ohci, data + len - 1); | |
565 | else | |
566 | td->hwBE = 0; | |
567 | td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma); | |
568 | ||
569 | /* append to queue */ | |
570 | list_add_tail (&td->td_list, &td->ed->td_list); | |
571 | ||
572 | /* hash it for later reverse mapping */ | |
573 | hash = TD_HASH_FUNC (td->td_dma); | |
574 | td->td_hash = ohci->td_hash [hash]; | |
575 | ohci->td_hash [hash] = td; | |
576 | ||
577 | /* HC might read the TD (or cachelines) right away ... */ | |
578 | wmb (); | |
579 | td->ed->hwTailP = td->hwNextTD; | |
580 | } | |
581 | ||
582 | /*-------------------------------------------------------------------------*/ | |
583 | ||
584 | /* Prepare all TDs of a transfer, and queue them onto the ED. | |
585 | * Caller guarantees HC is active. | |
586 | * Usually the ED is already on the schedule, so TDs might be | |
587 | * processed as soon as they're queued. | |
588 | */ | |
589 | static void td_submit_urb ( | |
590 | struct ohci_hcd *ohci, | |
591 | struct urb *urb | |
592 | ) { | |
593 | struct urb_priv *urb_priv = urb->hcpriv; | |
2621d011 | 594 | struct device *dev = ohci_to_hcd(ohci)->self.controller; |
1da177e4 LT |
595 | dma_addr_t data; |
596 | int data_len = urb->transfer_buffer_length; | |
597 | int cnt = 0; | |
598 | u32 info = 0; | |
599 | int is_out = usb_pipeout (urb->pipe); | |
600 | int periodic = 0; | |
6f65126c AS |
601 | int i, this_sg_len, n; |
602 | struct scatterlist *sg; | |
1da177e4 LT |
603 | |
604 | /* OHCI handles the bulk/interrupt data toggles itself. We just | |
605 | * use the device toggle bits for resetting, and rely on the fact | |
606 | * that resetting toggle is meaningless if the endpoint is active. | |
607 | */ | |
dd9048af | 608 | if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) { |
1da177e4 LT |
609 | usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe), |
610 | is_out, 1); | |
611 | urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C); | |
612 | } | |
613 | ||
1da177e4 LT |
614 | list_add (&urb_priv->pending, &ohci->pending); |
615 | ||
6f65126c AS |
616 | i = urb->num_mapped_sgs; |
617 | if (data_len > 0 && i > 0) { | |
618 | sg = urb->sg; | |
619 | data = sg_dma_address(sg); | |
620 | ||
621 | /* | |
622 | * urb->transfer_buffer_length may be smaller than the | |
623 | * size of the scatterlist (or vice versa) | |
624 | */ | |
625 | this_sg_len = min_t(int, sg_dma_len(sg), data_len); | |
626 | } else { | |
627 | sg = NULL; | |
628 | if (data_len) | |
629 | data = urb->transfer_dma; | |
630 | else | |
631 | data = 0; | |
632 | this_sg_len = data_len; | |
633 | } | |
1da177e4 LT |
634 | |
635 | /* NOTE: TD_CC is set so we can tell which TDs the HC processed by | |
636 | * using TD_CC_GET, as well as by seeing them on the done list. | |
637 | * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.) | |
638 | */ | |
639 | switch (urb_priv->ed->type) { | |
640 | ||
641 | /* Bulk and interrupt are identical except for where in the schedule | |
642 | * their EDs live. | |
643 | */ | |
644 | case PIPE_INTERRUPT: | |
645 | /* ... and periodic urbs have extra accounting */ | |
646 | periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0 | |
647 | && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0; | |
648 | /* FALLTHROUGH */ | |
649 | case PIPE_BULK: | |
650 | info = is_out | |
651 | ? TD_T_TOGGLE | TD_CC | TD_DP_OUT | |
652 | : TD_T_TOGGLE | TD_CC | TD_DP_IN; | |
653 | /* TDs _could_ transfer up to 8K each */ | |
6f65126c AS |
654 | for (;;) { |
655 | n = min(this_sg_len, 4096); | |
656 | ||
657 | /* maybe avoid ED halt on final TD short read */ | |
658 | if (n >= data_len || (i == 1 && n >= this_sg_len)) { | |
659 | if (!(urb->transfer_flags & URB_SHORT_NOT_OK)) | |
660 | info |= TD_R; | |
661 | } | |
662 | td_fill(ohci, info, data, n, urb, cnt); | |
663 | this_sg_len -= n; | |
664 | data_len -= n; | |
665 | data += n; | |
1da177e4 | 666 | cnt++; |
6f65126c AS |
667 | |
668 | if (this_sg_len <= 0) { | |
669 | if (--i <= 0 || data_len <= 0) | |
670 | break; | |
671 | sg = sg_next(sg); | |
672 | data = sg_dma_address(sg); | |
673 | this_sg_len = min_t(int, sg_dma_len(sg), | |
674 | data_len); | |
675 | } | |
1da177e4 | 676 | } |
1da177e4 LT |
677 | if ((urb->transfer_flags & URB_ZERO_PACKET) |
678 | && cnt < urb_priv->length) { | |
679 | td_fill (ohci, info, 0, 0, urb, cnt); | |
680 | cnt++; | |
681 | } | |
682 | /* maybe kickstart bulk list */ | |
683 | if (urb_priv->ed->type == PIPE_BULK) { | |
684 | wmb (); | |
685 | ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus); | |
686 | } | |
687 | break; | |
688 | ||
689 | /* control manages DATA0/DATA1 toggle per-request; SETUP resets it, | |
690 | * any DATA phase works normally, and the STATUS ack is special. | |
691 | */ | |
692 | case PIPE_CONTROL: | |
693 | info = TD_CC | TD_DP_SETUP | TD_T_DATA0; | |
694 | td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++); | |
695 | if (data_len > 0) { | |
696 | info = TD_CC | TD_R | TD_T_DATA1; | |
697 | info |= is_out ? TD_DP_OUT : TD_DP_IN; | |
698 | /* NOTE: mishandles transfers >8K, some >4K */ | |
699 | td_fill (ohci, info, data, data_len, urb, cnt++); | |
700 | } | |
701 | info = (is_out || data_len == 0) | |
702 | ? TD_CC | TD_DP_IN | TD_T_DATA1 | |
703 | : TD_CC | TD_DP_OUT | TD_T_DATA1; | |
704 | td_fill (ohci, info, data, 0, urb, cnt++); | |
705 | /* maybe kickstart control list */ | |
706 | wmb (); | |
707 | ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus); | |
708 | break; | |
709 | ||
710 | /* ISO has no retransmit, so no toggle; and it uses special TDs. | |
711 | * Each TD could handle multiple consecutive frames (interval 1); | |
712 | * we could often reduce the number of TDs here. | |
713 | */ | |
714 | case PIPE_ISOCHRONOUS: | |
6a41b4d3 AS |
715 | for (cnt = urb_priv->td_cnt; cnt < urb->number_of_packets; |
716 | cnt++) { | |
1da177e4 LT |
717 | int frame = urb->start_frame; |
718 | ||
719 | // FIXME scheduling should handle frame counter | |
720 | // roll-around ... exotic case (and OHCI has | |
721 | // a 2^16 iso range, vs other HCs max of 2^10) | |
722 | frame += cnt * urb->interval; | |
723 | frame &= 0xffff; | |
724 | td_fill (ohci, TD_CC | TD_ISO | frame, | |
725 | data + urb->iso_frame_desc [cnt].offset, | |
726 | urb->iso_frame_desc [cnt].length, urb, cnt); | |
727 | } | |
a1f17a87 LY |
728 | if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) { |
729 | if (quirk_amdiso(ohci)) | |
ad93562b | 730 | usb_amd_quirk_pll_disable(); |
a1f17a87 | 731 | if (quirk_amdprefetch(ohci)) |
2621d011 | 732 | sb800_prefetch(dev, 1); |
a1f17a87 | 733 | } |
1da177e4 LT |
734 | periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0 |
735 | && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0; | |
736 | break; | |
737 | } | |
738 | ||
739 | /* start periodic dma if needed */ | |
740 | if (periodic) { | |
741 | wmb (); | |
742 | ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE; | |
743 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
744 | } | |
745 | ||
746 | // ASSERT (urb_priv->length == cnt); | |
747 | } | |
748 | ||
749 | /*-------------------------------------------------------------------------* | |
750 | * Done List handling functions | |
751 | *-------------------------------------------------------------------------*/ | |
752 | ||
55d84968 AS |
753 | /* calculate transfer length/status and update the urb */ |
754 | static int td_done(struct ohci_hcd *ohci, struct urb *urb, struct td *td) | |
1da177e4 LT |
755 | { |
756 | u32 tdINFO = hc32_to_cpup (ohci, &td->hwINFO); | |
757 | int cc = 0; | |
55d84968 | 758 | int status = -EINPROGRESS; |
1da177e4 LT |
759 | |
760 | list_del (&td->td_list); | |
761 | ||
762 | /* ISO ... drivers see per-TD length/status */ | |
dd9048af | 763 | if (tdINFO & TD_ISO) { |
55d84968 | 764 | u16 tdPSW = ohci_hwPSW(ohci, td, 0); |
1da177e4 LT |
765 | int dlen = 0; |
766 | ||
767 | /* NOTE: assumes FC in tdINFO == 0, and that | |
768 | * only the first of 0..MAXPSW psws is used. | |
769 | */ | |
770 | ||
dd9048af DB |
771 | cc = (tdPSW >> 12) & 0xF; |
772 | if (tdINFO & TD_CC) /* hc didn't touch? */ | |
55d84968 | 773 | return status; |
1da177e4 LT |
774 | |
775 | if (usb_pipeout (urb->pipe)) | |
776 | dlen = urb->iso_frame_desc [td->index].length; | |
777 | else { | |
778 | /* short reads are always OK for ISO */ | |
779 | if (cc == TD_DATAUNDERRUN) | |
780 | cc = TD_CC_NOERROR; | |
781 | dlen = tdPSW & 0x3ff; | |
782 | } | |
783 | urb->actual_length += dlen; | |
784 | urb->iso_frame_desc [td->index].actual_length = dlen; | |
785 | urb->iso_frame_desc [td->index].status = cc_to_error [cc]; | |
786 | ||
787 | if (cc != TD_CC_NOERROR) | |
d2c4254f | 788 | ohci_dbg(ohci, |
1da177e4 LT |
789 | "urb %p iso td %p (%d) len %d cc %d\n", |
790 | urb, td, 1 + td->index, dlen, cc); | |
791 | ||
792 | /* BULK, INT, CONTROL ... drivers see aggregate length/status, | |
793 | * except that "setup" bytes aren't counted and "short" transfers | |
794 | * might not be reported as errors. | |
795 | */ | |
796 | } else { | |
797 | int type = usb_pipetype (urb->pipe); | |
798 | u32 tdBE = hc32_to_cpup (ohci, &td->hwBE); | |
799 | ||
dd9048af | 800 | cc = TD_CC_GET (tdINFO); |
1da177e4 LT |
801 | |
802 | /* update packet status if needed (short is normally ok) */ | |
803 | if (cc == TD_DATAUNDERRUN | |
804 | && !(urb->transfer_flags & URB_SHORT_NOT_OK)) | |
805 | cc = TD_CC_NOERROR; | |
55d84968 AS |
806 | if (cc != TD_CC_NOERROR && cc < 0x0E) |
807 | status = cc_to_error[cc]; | |
1da177e4 LT |
808 | |
809 | /* count all non-empty packets except control SETUP packet */ | |
810 | if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) { | |
811 | if (td->hwCBP == 0) | |
812 | urb->actual_length += tdBE - td->data_dma + 1; | |
813 | else | |
814 | urb->actual_length += | |
815 | hc32_to_cpup (ohci, &td->hwCBP) | |
816 | - td->data_dma; | |
817 | } | |
818 | ||
819 | if (cc != TD_CC_NOERROR && cc < 0x0E) | |
d2c4254f | 820 | ohci_dbg(ohci, |
1da177e4 LT |
821 | "urb %p td %p (%d) cc %d, len=%d/%d\n", |
822 | urb, td, 1 + td->index, cc, | |
823 | urb->actual_length, | |
824 | urb->transfer_buffer_length); | |
dd9048af | 825 | } |
55d84968 | 826 | return status; |
1da177e4 LT |
827 | } |
828 | ||
829 | /*-------------------------------------------------------------------------*/ | |
830 | ||
6e8fe43b | 831 | static void ed_halted(struct ohci_hcd *ohci, struct td *td, int cc) |
1da177e4 | 832 | { |
dd9048af | 833 | struct urb *urb = td->urb; |
6e8fe43b | 834 | urb_priv_t *urb_priv = urb->hcpriv; |
1da177e4 LT |
835 | struct ed *ed = td->ed; |
836 | struct list_head *tmp = td->td_list.next; | |
837 | __hc32 toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C); | |
838 | ||
839 | /* clear ed halt; this is the td that caused it, but keep it inactive | |
840 | * until its urb->complete() has a chance to clean up. | |
841 | */ | |
842 | ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP); | |
843 | wmb (); | |
dd9048af | 844 | ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H); |
1da177e4 | 845 | |
6e8fe43b AS |
846 | /* Get rid of all later tds from this urb. We don't have |
847 | * to be careful: no errors and nothing was transferred. | |
848 | * Also patch the ed so it looks as if those tds completed normally. | |
1da177e4 LT |
849 | */ |
850 | while (tmp != &ed->td_list) { | |
851 | struct td *next; | |
1da177e4 LT |
852 | |
853 | next = list_entry (tmp, struct td, td_list); | |
854 | tmp = next->td_list.next; | |
855 | ||
856 | if (next->urb != urb) | |
857 | break; | |
858 | ||
859 | /* NOTE: if multi-td control DATA segments get supported, | |
860 | * this urb had one of them, this td wasn't the last td | |
861 | * in that segment (TD_R clear), this ed halted because | |
862 | * of a short read, _and_ URB_SHORT_NOT_OK is clear ... | |
863 | * then we need to leave the control STATUS packet queued | |
864 | * and clear ED_SKIP. | |
865 | */ | |
1da177e4 | 866 | |
6e8fe43b AS |
867 | list_del(&next->td_list); |
868 | urb_priv->td_cnt++; | |
1da177e4 LT |
869 | ed->hwHeadP = next->hwNextTD | toggle; |
870 | } | |
871 | ||
872 | /* help for troubleshooting: report anything that | |
873 | * looks odd ... that doesn't include protocol stalls | |
874 | * (or maybe some other things) | |
875 | */ | |
876 | switch (cc) { | |
877 | case TD_DATAUNDERRUN: | |
878 | if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0) | |
879 | break; | |
880 | /* fallthrough */ | |
881 | case TD_CC_STALL: | |
882 | if (usb_pipecontrol (urb->pipe)) | |
883 | break; | |
884 | /* fallthrough */ | |
885 | default: | |
886 | ohci_dbg (ohci, | |
887 | "urb %p path %s ep%d%s %08x cc %d --> status %d\n", | |
888 | urb, urb->dev->devpath, | |
889 | usb_pipeendpoint (urb->pipe), | |
890 | usb_pipein (urb->pipe) ? "in" : "out", | |
891 | hc32_to_cpu (ohci, td->hwINFO), | |
892 | cc, cc_to_error [cc]); | |
893 | } | |
1da177e4 LT |
894 | } |
895 | ||
c6fcb85e AS |
896 | /* Add a TD to the done list */ |
897 | static void add_to_done_list(struct ohci_hcd *ohci, struct td *td) | |
898 | { | |
899 | struct td *td2, *td_prev; | |
900 | struct ed *ed; | |
901 | ||
902 | if (td->next_dl_td) | |
903 | return; /* Already on the list */ | |
904 | ||
905 | /* Add all the TDs going back until we reach one that's on the list */ | |
906 | ed = td->ed; | |
907 | td2 = td_prev = td; | |
908 | list_for_each_entry_continue_reverse(td2, &ed->td_list, td_list) { | |
909 | if (td2->next_dl_td) | |
910 | break; | |
911 | td2->next_dl_td = td_prev; | |
912 | td_prev = td2; | |
913 | } | |
914 | ||
915 | if (ohci->dl_end) | |
916 | ohci->dl_end->next_dl_td = td_prev; | |
917 | else | |
918 | ohci->dl_start = td_prev; | |
919 | ||
920 | /* | |
921 | * Make td->next_dl_td point to td itself, to mark the fact | |
922 | * that td is on the done list. | |
923 | */ | |
924 | ohci->dl_end = td->next_dl_td = td; | |
81e38333 AS |
925 | |
926 | /* Did we just add the latest pending TD? */ | |
927 | td2 = ed->pending_td; | |
928 | if (td2 && td2->next_dl_td) | |
929 | ed->pending_td = NULL; | |
c6fcb85e AS |
930 | } |
931 | ||
932 | /* Get the entries on the hardware done queue and put them on our list */ | |
933 | static void update_done_list(struct ohci_hcd *ohci) | |
1da177e4 LT |
934 | { |
935 | u32 td_dma; | |
1da177e4 LT |
936 | struct td *td = NULL; |
937 | ||
938 | td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head); | |
939 | ohci->hcca->done_head = 0; | |
940 | wmb(); | |
941 | ||
942 | /* get TD from hc's singly linked list, and | |
c6fcb85e | 943 | * add to ours. ed->td_list changes later. |
1da177e4 | 944 | */ |
dd9048af DB |
945 | while (td_dma) { |
946 | int cc; | |
1da177e4 LT |
947 | |
948 | td = dma_to_td (ohci, td_dma); | |
949 | if (!td) { | |
950 | ohci_err (ohci, "bad entry %8x\n", td_dma); | |
951 | break; | |
952 | } | |
953 | ||
954 | td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE); | |
955 | cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO)); | |
956 | ||
957 | /* Non-iso endpoints can halt on error; un-halt, | |
958 | * and dequeue any other TDs from this urb. | |
959 | * No other TD could have caused the halt. | |
960 | */ | |
961 | if (cc != TD_CC_NOERROR | |
962 | && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H))) | |
6e8fe43b | 963 | ed_halted(ohci, td, cc); |
1da177e4 | 964 | |
1da177e4 | 965 | td_dma = hc32_to_cpup (ohci, &td->hwNextTD); |
c6fcb85e | 966 | add_to_done_list(ohci, td); |
dd9048af | 967 | } |
1da177e4 LT |
968 | } |
969 | ||
970 | /*-------------------------------------------------------------------------*/ | |
971 | ||
972 | /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */ | |
cdb4dd15 | 973 | static void finish_unlinks(struct ohci_hcd *ohci) |
1da177e4 | 974 | { |
cdb4dd15 | 975 | unsigned tick = ohci_frame_no(ohci); |
1da177e4 LT |
976 | struct ed *ed, **last; |
977 | ||
978 | rescan_all: | |
979 | for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) { | |
980 | struct list_head *entry, *tmp; | |
981 | int completed, modified; | |
982 | __hc32 *prev; | |
983 | ||
984 | /* only take off EDs that the HC isn't using, accounting for | |
985 | * frame counter wraps and EDs with partially retired TDs | |
986 | */ | |
c6fcb85e AS |
987 | if (likely(ohci->rh_state == OHCI_RH_RUNNING) && |
988 | tick_before(tick, ed->tick)) { | |
1da177e4 | 989 | skip_ed: |
c6fcb85e AS |
990 | last = &ed->ed_next; |
991 | continue; | |
992 | } | |
993 | if (!list_empty(&ed->td_list)) { | |
994 | struct td *td; | |
995 | u32 head; | |
1da177e4 | 996 | |
c6fcb85e | 997 | td = list_first_entry(&ed->td_list, struct td, td_list); |
1da177e4 | 998 | |
c6fcb85e AS |
999 | /* INTR_WDH may need to clean up first */ |
1000 | head = hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK; | |
1001 | if (td->td_dma != head && | |
1002 | ohci->rh_state == OHCI_RH_RUNNING) | |
1003 | goto skip_ed; | |
1da177e4 | 1004 | |
c6fcb85e AS |
1005 | /* Don't mess up anything already on the done list */ |
1006 | if (td->next_dl_td) | |
1007 | goto skip_ed; | |
1da177e4 LT |
1008 | } |
1009 | ||
977dcfdc | 1010 | /* ED's now officially unlinked, hc doesn't see */ |
977dcfdc AS |
1011 | ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H); |
1012 | ed->hwNextED = 0; | |
1013 | wmb(); | |
1014 | ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE); | |
977dcfdc | 1015 | |
1da177e4 LT |
1016 | /* reentrancy: if we drop the schedule lock, someone might |
1017 | * have modified this list. normally it's just prepending | |
1018 | * entries (which we'd ignore), but paranoia won't hurt. | |
1019 | */ | |
1da177e4 LT |
1020 | modified = 0; |
1021 | ||
1022 | /* unlink urbs as requested, but rescan the list after | |
1023 | * we call a completion since it might have unlinked | |
1024 | * another (earlier) urb | |
1025 | * | |
1026 | * When we get here, the HC doesn't see this ed. But it | |
1027 | * must not be rescheduled until all completed URBs have | |
1028 | * been given back to the driver. | |
1029 | */ | |
1030 | rescan_this: | |
1031 | completed = 0; | |
1032 | prev = &ed->hwHeadP; | |
1033 | list_for_each_safe (entry, tmp, &ed->td_list) { | |
1034 | struct td *td; | |
1035 | struct urb *urb; | |
1036 | urb_priv_t *urb_priv; | |
1037 | __hc32 savebits; | |
29c8f6a7 | 1038 | u32 tdINFO; |
1da177e4 LT |
1039 | |
1040 | td = list_entry (entry, struct td, td_list); | |
1041 | urb = td->urb; | |
1042 | urb_priv = td->urb->hcpriv; | |
1043 | ||
eb231054 | 1044 | if (!urb->unlinked) { |
1da177e4 LT |
1045 | prev = &td->hwNextTD; |
1046 | continue; | |
1047 | } | |
1048 | ||
1049 | /* patch pointer hc uses */ | |
1050 | savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK); | |
1051 | *prev = td->hwNextTD | savebits; | |
1052 | ||
29c8f6a7 DB |
1053 | /* If this was unlinked, the TD may not have been |
1054 | * retired ... so manually save the data toggle. | |
1055 | * The controller ignores the value we save for | |
1056 | * control and ISO endpoints. | |
1057 | */ | |
1058 | tdINFO = hc32_to_cpup(ohci, &td->hwINFO); | |
1059 | if ((tdINFO & TD_T) == TD_T_DATA0) | |
1060 | ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_C); | |
1061 | else if ((tdINFO & TD_T) == TD_T_DATA1) | |
1062 | ed->hwHeadP |= cpu_to_hc32(ohci, ED_C); | |
1063 | ||
1da177e4 LT |
1064 | /* HC may have partly processed this TD */ |
1065 | td_done (ohci, urb, td); | |
1066 | urb_priv->td_cnt++; | |
1067 | ||
1068 | /* if URB is done, clean up */ | |
a8693424 | 1069 | if (urb_priv->td_cnt >= urb_priv->length) { |
1da177e4 | 1070 | modified = completed = 1; |
55d84968 | 1071 | finish_urb(ohci, urb, 0); |
1da177e4 LT |
1072 | } |
1073 | } | |
1074 | if (completed && !list_empty (&ed->td_list)) | |
1075 | goto rescan_this; | |
1076 | ||
977dcfdc AS |
1077 | /* |
1078 | * If no TDs are queued, take ED off the ed_rm_list. | |
1079 | * Otherwise, if the HC is running, reschedule. | |
1080 | * If not, leave it on the list for further dequeues. | |
1081 | */ | |
1082 | if (list_empty(&ed->td_list)) { | |
1083 | *last = ed->ed_next; | |
1084 | ed->ed_next = NULL; | |
7d8021c9 | 1085 | ed->state = ED_IDLE; |
81e38333 | 1086 | list_del(&ed->in_use_list); |
977dcfdc AS |
1087 | } else if (ohci->rh_state == OHCI_RH_RUNNING) { |
1088 | *last = ed->ed_next; | |
1089 | ed->ed_next = NULL; | |
1090 | ed_schedule(ohci, ed); | |
1091 | } else { | |
1092 | last = &ed->ed_next; | |
1da177e4 LT |
1093 | } |
1094 | ||
1095 | if (modified) | |
1096 | goto rescan_all; | |
dd9048af | 1097 | } |
1da177e4 | 1098 | |
dd9048af | 1099 | /* maybe reenable control and bulk lists */ |
b7463c71 | 1100 | if (ohci->rh_state == OHCI_RH_RUNNING && !ohci->ed_rm_list) { |
1da177e4 LT |
1101 | u32 command = 0, control = 0; |
1102 | ||
1103 | if (ohci->ed_controltail) { | |
1104 | command |= OHCI_CLF; | |
89a0fd18 | 1105 | if (quirk_zfmicro(ohci)) |
0e498763 | 1106 | mdelay(1); |
1da177e4 LT |
1107 | if (!(ohci->hc_control & OHCI_CTRL_CLE)) { |
1108 | control |= OHCI_CTRL_CLE; | |
1109 | ohci_writel (ohci, 0, | |
1110 | &ohci->regs->ed_controlcurrent); | |
1111 | } | |
1112 | } | |
1113 | if (ohci->ed_bulktail) { | |
1114 | command |= OHCI_BLF; | |
89a0fd18 | 1115 | if (quirk_zfmicro(ohci)) |
0e498763 | 1116 | mdelay(1); |
1da177e4 LT |
1117 | if (!(ohci->hc_control & OHCI_CTRL_BLE)) { |
1118 | control |= OHCI_CTRL_BLE; | |
1119 | ohci_writel (ohci, 0, | |
1120 | &ohci->regs->ed_bulkcurrent); | |
1121 | } | |
1122 | } | |
dd9048af | 1123 | |
1da177e4 LT |
1124 | /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */ |
1125 | if (control) { | |
1126 | ohci->hc_control |= control; | |
89a0fd18 | 1127 | if (quirk_zfmicro(ohci)) |
0e498763 | 1128 | mdelay(1); |
dd9048af DB |
1129 | ohci_writel (ohci, ohci->hc_control, |
1130 | &ohci->regs->control); | |
1131 | } | |
0e498763 | 1132 | if (command) { |
89a0fd18 | 1133 | if (quirk_zfmicro(ohci)) |
0e498763 | 1134 | mdelay(1); |
dd9048af DB |
1135 | ohci_writel (ohci, command, &ohci->regs->cmdstatus); |
1136 | } | |
0e498763 | 1137 | } |
1da177e4 LT |
1138 | } |
1139 | ||
1140 | ||
1141 | ||
1142 | /*-------------------------------------------------------------------------*/ | |
1143 | ||
95d9a01d | 1144 | /* Take back a TD from the host controller */ |
89a0fd18 MN |
1145 | static void takeback_td(struct ohci_hcd *ohci, struct td *td) |
1146 | { | |
1147 | struct urb *urb = td->urb; | |
1148 | urb_priv_t *urb_priv = urb->hcpriv; | |
1149 | struct ed *ed = td->ed; | |
55d84968 | 1150 | int status; |
89a0fd18 MN |
1151 | |
1152 | /* update URB's length and status from TD */ | |
55d84968 | 1153 | status = td_done(ohci, urb, td); |
89a0fd18 MN |
1154 | urb_priv->td_cnt++; |
1155 | ||
1156 | /* If all this urb's TDs are done, call complete() */ | |
a8693424 | 1157 | if (urb_priv->td_cnt >= urb_priv->length) |
55d84968 | 1158 | finish_urb(ohci, urb, status); |
89a0fd18 MN |
1159 | |
1160 | /* clean schedule: unlink EDs that are no longer busy */ | |
1161 | if (list_empty(&ed->td_list)) { | |
1162 | if (ed->state == ED_OPER) | |
1163 | start_ed_unlink(ohci, ed); | |
1164 | ||
1165 | /* ... reenabling halted EDs only after fault cleanup */ | |
1166 | } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE)) | |
1167 | == cpu_to_hc32(ohci, ED_SKIP)) { | |
1168 | td = list_entry(ed->td_list.next, struct td, td_list); | |
1169 | if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) { | |
1170 | ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP); | |
1171 | /* ... hc may need waking-up */ | |
1172 | switch (ed->type) { | |
1173 | case PIPE_CONTROL: | |
1174 | ohci_writel(ohci, OHCI_CLF, | |
1175 | &ohci->regs->cmdstatus); | |
1176 | break; | |
1177 | case PIPE_BULK: | |
1178 | ohci_writel(ohci, OHCI_BLF, | |
1179 | &ohci->regs->cmdstatus); | |
1180 | break; | |
1181 | } | |
1182 | } | |
1183 | } | |
1184 | } | |
1185 | ||
1da177e4 LT |
1186 | /* |
1187 | * Process normal completions (error or success) and clean the schedules. | |
1188 | * | |
1189 | * This is the main path for handing urbs back to drivers. The only other | |
89a0fd18 | 1190 | * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list, |
95d9a01d | 1191 | * instead of scanning the (re-reversed) donelist as this does. |
1da177e4 | 1192 | */ |
c6fcb85e | 1193 | static void process_done_list(struct ohci_hcd *ohci) |
1da177e4 | 1194 | { |
c6fcb85e | 1195 | struct td *td; |
50ce5c06 | 1196 | |
c6fcb85e AS |
1197 | while (ohci->dl_start) { |
1198 | td = ohci->dl_start; | |
1199 | if (td == ohci->dl_end) | |
1200 | ohci->dl_start = ohci->dl_end = NULL; | |
1201 | else | |
1202 | ohci->dl_start = td->next_dl_td; | |
50ce5c06 | 1203 | |
89a0fd18 | 1204 | takeback_td(ohci, td); |
dd9048af | 1205 | } |
1da177e4 | 1206 | } |
cdb4dd15 AS |
1207 | |
1208 | /* | |
1209 | * TD takeback and URB giveback must be single-threaded. | |
1210 | * This routine takes care of it all. | |
1211 | */ | |
1212 | static void ohci_work(struct ohci_hcd *ohci) | |
1213 | { | |
1214 | if (ohci->working) { | |
1215 | ohci->restart_work = 1; | |
1216 | return; | |
1217 | } | |
1218 | ohci->working = 1; | |
1219 | ||
1220 | restart: | |
1221 | process_done_list(ohci); | |
1222 | if (ohci->ed_rm_list) | |
1223 | finish_unlinks(ohci); | |
1224 | ||
1225 | if (ohci->restart_work) { | |
1226 | ohci->restart_work = 0; | |
1227 | goto restart; | |
1228 | } | |
1229 | ohci->working = 0; | |
1230 | } |