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Merge branch 'for-next' of master.kernel.org:/pub/scm/linux/kernel/git/balbi/usb...
[deliverable/linux.git] / drivers / usb / host / pci-quirks.c
CommitLineData
7586269c
DB		 1/*
2 * This file contains code to reset and initialize USB host controllers.
3 * Some of it includes work-arounds for PCI hardware and BIOS quirks.
4 * It may need to run early during booting -- before USB would normally
5 * initialize -- to ensure that Linux doesn't use any legacy modes.
6 *
7 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
8 * (and others)
9 */
10
7586269c
DB		 11#include <linux/types.h>
12#include <linux/kernel.h>
13#include <linux/pci.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/acpi.h>
3610ea53 17#include <linux/dmi.h>
75e2df60 18#include "pci-quirks.h"
66d4eadd 19#include "xhci-ext-caps.h"
7586269c
DB		 20
21
7586269c
DB		 22#define UHCI_USBLEGSUP 0xc0 /* legacy support */
23#define UHCI_USBCMD 0 /* command register */
7586269c 24#define UHCI_USBINTR 4 /* interrupt register */
bb200f6e
AS		 25#define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
26#define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
27#define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */
28#define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */
29#define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */
30#define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */
31#define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */
7586269c
DB		 32
33#define OHCI_CONTROL 0x04
34#define OHCI_CMDSTATUS 0x08
35#define OHCI_INTRSTATUS 0x0c
36#define OHCI_INTRENABLE 0x10
37#define OHCI_INTRDISABLE 0x14
38#define OHCI_OCR (1 << 3) /* ownership change request */
f2cb36c1 39#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
7586269c
DB		 40#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
41#define OHCI_INTR_OC (1 << 30) /* ownership change */
42
43#define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
44#define EHCI_USBCMD 0 /* command register */
45#define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
46#define EHCI_USBSTS 4 /* status register */
47#define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
48#define EHCI_USBINTR 8 /* interrupt register */
4fe5354f 49#define EHCI_CONFIGFLAG 0x40 /* configured flag register */
7586269c
DB		 50#define EHCI_USBLEGSUP 0 /* legacy support register */
51#define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
52#define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
53#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
54#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
55
ad93562b
AX		 56/* AMD quirk use */
57#define AB_REG_BAR_LOW 0xe0
58#define AB_REG_BAR_HIGH 0xe1
59#define AB_REG_BAR_SB700 0xf0
60#define AB_INDX(addr) ((addr) + 0x00)
61#define AB_DATA(addr) ((addr) + 0x04)
62#define AX_INDXC 0x30
63#define AX_DATAC 0x34
64
65#define NB_PCIE_INDX_ADDR 0xe0
66#define NB_PCIE_INDX_DATA 0xe4
67#define PCIE_P_CNTL 0x10040
68#define BIF_NB 0x10002
69#define NB_PIF0_PWRDOWN_0 0x01100012
70#define NB_PIF0_PWRDOWN_1 0x01100013
71
69e848c2
SS		 72#define USB_INTEL_XUSB2PR 0xD0
73#define USB_INTEL_USB3_PSSEN 0xD8
74
ad93562b
AX		 75static struct amd_chipset_info {
76 struct pci_dev *nb_dev;
77 struct pci_dev *smbus_dev;
78 int nb_type;
79 int sb_type;
80 int isoc_reqs;
81 int probe_count;
82 int probe_result;
83} amd_chipset;
84
85static DEFINE_SPINLOCK(amd_lock);
86
87int usb_amd_find_chipset_info(void)
88{
89 u8 rev = 0;
90 unsigned long flags;
9ab7927b
JR		 91 struct amd_chipset_info info;
92 int ret;
ad93562b
AX		 93
94 spin_lock_irqsave(&amd_lock, flags);
95
ad93562b 96 /* probe only once */
9ab7927b
JR		 97 if (amd_chipset.probe_count > 0) {
98 amd_chipset.probe_count++;
ad93562b
AX		 99 spin_unlock_irqrestore(&amd_lock, flags);
100 return amd_chipset.probe_result;
101 }
9ab7927b
JR		 102 memset(&info, 0, sizeof(info));
103 spin_unlock_irqrestore(&amd_lock, flags);
ad93562b 104
9ab7927b
JR		 105 info.smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL);
106 if (info.smbus_dev) {
107 rev = info.smbus_dev->revision;
ad93562b 108 if (rev >= 0x40)
9ab7927b 109 info.sb_type = 1;
ad93562b 110 else if (rev >= 0x30 && rev <= 0x3b)
9ab7927b 111 info.sb_type = 3;
ad93562b 112 } else {
9ab7927b
JR		 113 info.smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
114 0x780b, NULL);
115 if (!info.smbus_dev) {
116 ret = 0;
117 goto commit;
ad93562b 118 }
9ab7927b
JR		 119
120 rev = info.smbus_dev->revision;
ad93562b 121 if (rev >= 0x11 && rev <= 0x18)
9ab7927b 122 info.sb_type = 2;
ad93562b
AX		 123 }
124
9ab7927b
JR		 125 if (info.sb_type == 0) {
126 if (info.smbus_dev) {
127 pci_dev_put(info.smbus_dev);
128 info.smbus_dev = NULL;
ad93562b 129 }
9ab7927b
JR		 130 ret = 0;
131 goto commit;
ad93562b
AX		 132 }
133
9ab7927b
JR		 134 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);
135 if (info.nb_dev) {
136 info.nb_type = 1;
ad93562b 137 } else {
9ab7927b
JR		 138 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
139 if (info.nb_dev) {
140 info.nb_type = 2;
141 } else {
142 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
143 0x9600, NULL);
144 if (info.nb_dev)
145 info.nb_type = 3;
ad93562b
AX		 146 }
147 }
148
9ab7927b 149 ret = info.probe_result = 1;
ad93562b
AX		 150 printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
151
9ab7927b
JR		 152commit:
153
154 spin_lock_irqsave(&amd_lock, flags);
155 if (amd_chipset.probe_count > 0) {
156 /* race - someone else was faster - drop devices */
157
158 /* Mark that we where here */
159 amd_chipset.probe_count++;
160 ret = amd_chipset.probe_result;
161
162 spin_unlock_irqrestore(&amd_lock, flags);
163
164 if (info.nb_dev)
165 pci_dev_put(info.nb_dev);
166 if (info.smbus_dev)
167 pci_dev_put(info.smbus_dev);
168
169 } else {
170 /* no race - commit the result */
171 info.probe_count++;
172 amd_chipset = info;
173 spin_unlock_irqrestore(&amd_lock, flags);
174 }
175
176 return ret;
ad93562b
AX		 177}
178EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info);
179
180/*
181 * The hardware normally enables the A-link power management feature, which
182 * lets the system lower the power consumption in idle states.
183 *
184 * This USB quirk prevents the link going into that lower power state
185 * during isochronous transfers.
186 *
187 * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
188 * some AMD platforms may stutter or have breaks occasionally.
189 */
190static void usb_amd_quirk_pll(int disable)
191{
192 u32 addr, addr_low, addr_high, val;
193 u32 bit = disable ? 0 : 1;
194 unsigned long flags;
195
196 spin_lock_irqsave(&amd_lock, flags);
197
198 if (disable) {
199 amd_chipset.isoc_reqs++;
200 if (amd_chipset.isoc_reqs > 1) {
201 spin_unlock_irqrestore(&amd_lock, flags);
202 return;
203 }
204 } else {
205 amd_chipset.isoc_reqs--;
206 if (amd_chipset.isoc_reqs > 0) {
207 spin_unlock_irqrestore(&amd_lock, flags);
208 return;
209 }
210 }
211
212 if (amd_chipset.sb_type == 1 || amd_chipset.sb_type == 2) {
213 outb_p(AB_REG_BAR_LOW, 0xcd6);
214 addr_low = inb_p(0xcd7);
215 outb_p(AB_REG_BAR_HIGH, 0xcd6);
216 addr_high = inb_p(0xcd7);
217 addr = addr_high << 8 | addr_low;
218
219 outl_p(0x30, AB_INDX(addr));
220 outl_p(0x40, AB_DATA(addr));
221 outl_p(0x34, AB_INDX(addr));
222 val = inl_p(AB_DATA(addr));
223 } else if (amd_chipset.sb_type == 3) {
224 pci_read_config_dword(amd_chipset.smbus_dev,
225 AB_REG_BAR_SB700, &addr);
226 outl(AX_INDXC, AB_INDX(addr));
227 outl(0x40, AB_DATA(addr));
228 outl(AX_DATAC, AB_INDX(addr));
229 val = inl(AB_DATA(addr));
230 } else {
231 spin_unlock_irqrestore(&amd_lock, flags);
232 return;
233 }
234
235 if (disable) {
236 val &= ~0x08;
237 val |= (1 << 4) | (1 << 9);
238 } else {
239 val |= 0x08;
240 val &= ~((1 << 4) | (1 << 9));
241 }
242 outl_p(val, AB_DATA(addr));
243
244 if (!amd_chipset.nb_dev) {
245 spin_unlock_irqrestore(&amd_lock, flags);
246 return;
247 }
248
249 if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) {
250 addr = PCIE_P_CNTL;
251 pci_write_config_dword(amd_chipset.nb_dev,
252 NB_PCIE_INDX_ADDR, addr);
253 pci_read_config_dword(amd_chipset.nb_dev,
254 NB_PCIE_INDX_DATA, &val);
255
256 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
257 val |= bit | (bit << 3) | (bit << 12);
258 val |= ((!bit) << 4) | ((!bit) << 9);
259 pci_write_config_dword(amd_chipset.nb_dev,
260 NB_PCIE_INDX_DATA, val);
261
262 addr = BIF_NB;
263 pci_write_config_dword(amd_chipset.nb_dev,
264 NB_PCIE_INDX_ADDR, addr);
265 pci_read_config_dword(amd_chipset.nb_dev,
266 NB_PCIE_INDX_DATA, &val);
267 val &= ~(1 << 8);
268 val |= bit << 8;
269
270 pci_write_config_dword(amd_chipset.nb_dev,
271 NB_PCIE_INDX_DATA, val);
272 } else if (amd_chipset.nb_type == 2) {
273 addr = NB_PIF0_PWRDOWN_0;
274 pci_write_config_dword(amd_chipset.nb_dev,
275 NB_PCIE_INDX_ADDR, addr);
276 pci_read_config_dword(amd_chipset.nb_dev,
277 NB_PCIE_INDX_DATA, &val);
278 if (disable)
279 val &= ~(0x3f << 7);
280 else
281 val |= 0x3f << 7;
282
283 pci_write_config_dword(amd_chipset.nb_dev,
284 NB_PCIE_INDX_DATA, val);
285
286 addr = NB_PIF0_PWRDOWN_1;
287 pci_write_config_dword(amd_chipset.nb_dev,
288 NB_PCIE_INDX_ADDR, addr);
289 pci_read_config_dword(amd_chipset.nb_dev,
290 NB_PCIE_INDX_DATA, &val);
291 if (disable)
292 val &= ~(0x3f << 7);
293 else
294 val |= 0x3f << 7;
295
296 pci_write_config_dword(amd_chipset.nb_dev,
297 NB_PCIE_INDX_DATA, val);
298 }
299
300 spin_unlock_irqrestore(&amd_lock, flags);
301 return;
302}
303
304void usb_amd_quirk_pll_disable(void)
305{
306 usb_amd_quirk_pll(1);
307}
308EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
309
310void usb_amd_quirk_pll_enable(void)
311{
312 usb_amd_quirk_pll(0);
313}
314EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable);
315
316void usb_amd_dev_put(void)
317{
9ab7927b 318 struct pci_dev *nb, *smbus;
ad93562b
AX		 319 unsigned long flags;
320
321 spin_lock_irqsave(&amd_lock, flags);
322
323 amd_chipset.probe_count--;
324 if (amd_chipset.probe_count > 0) {
325 spin_unlock_irqrestore(&amd_lock, flags);
326 return;
327 }
328
9ab7927b
JR		 329 /* save them to pci_dev_put outside of spinlock */
330 nb = amd_chipset.nb_dev;
331 smbus = amd_chipset.smbus_dev;
332
333 amd_chipset.nb_dev = NULL;
334 amd_chipset.smbus_dev = NULL;
ad93562b
AX		 335 amd_chipset.nb_type = 0;
336 amd_chipset.sb_type = 0;
337 amd_chipset.isoc_reqs = 0;
338 amd_chipset.probe_result = 0;
339
340 spin_unlock_irqrestore(&amd_lock, flags);
9ab7927b
JR		 341
342 if (nb)
343 pci_dev_put(nb);
344 if (smbus)
345 pci_dev_put(smbus);
ad93562b
AX		 346}
347EXPORT_SYMBOL_GPL(usb_amd_dev_put);
7586269c 348
bb200f6e
AS		 349/*
350 * Make sure the controller is completely inactive, unable to
351 * generate interrupts or do DMA.
352 */
353void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
354{
355 /* Turn off PIRQ enable and SMI enable. (This also turns off the
356 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
357 */
358 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
359
360 /* Reset the HC - this will force us to get a
361 * new notification of any already connected
362 * ports due to the virtual disconnect that it
363 * implies.
364 */
365 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
366 mb();
367 udelay(5);
368 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
369 dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
370
371 /* Just to be safe, disable interrupt requests and
372 * make sure the controller is stopped.
373 */
374 outw(0, base + UHCI_USBINTR);
375 outw(0, base + UHCI_USBCMD);
376}
377EXPORT_SYMBOL_GPL(uhci_reset_hc);
378
379/*
380 * Initialize a controller that was newly discovered or has just been
381 * resumed. In either case we can't be sure of its previous state.
382 *
383 * Returns: 1 if the controller was reset, 0 otherwise.
384 */
385int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
386{
387 u16 legsup;
388 unsigned int cmd, intr;
389
390 /*
391 * When restarting a suspended controller, we expect all the
392 * settings to be the same as we left them:
393 *
394 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
395 * Controller is stopped and configured with EGSM set;
396 * No interrupts enabled except possibly Resume Detect.
397 *
398 * If any of these conditions are violated we do a complete reset.
399 */
400 pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
401 if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
402 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
441b62c1 403 __func__, legsup);
bb200f6e
AS		 404 goto reset_needed;
405 }
406
407 cmd = inw(base + UHCI_USBCMD);
408 if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
409 !(cmd & UHCI_USBCMD_EGSM)) {
410 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
441b62c1 411 __func__, cmd);
bb200f6e
AS		 412 goto reset_needed;
413 }
414
415 intr = inw(base + UHCI_USBINTR);
416 if (intr & (~UHCI_USBINTR_RESUME)) {
417 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
441b62c1 418 __func__, intr);
bb200f6e
AS		 419 goto reset_needed;
420 }
421 return 0;
422
423reset_needed:
424 dev_dbg(&pdev->dev, "Performing full reset\n");
425 uhci_reset_hc(pdev, base);
426 return 1;
427}
428EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
429
541ab4af
LT		 430static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
431{
432 u16 cmd;
433 return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
434}
435
436#define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
437#define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
438
7586269c
DB		 439static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
440{
441 unsigned long base = 0;
7586269c
DB		 442 int i;
443
541ab4af
LT		 444 if (!pio_enabled(pdev))
445 return;
446
7586269c
DB		 447 for (i = 0; i < PCI_ROM_RESOURCE; i++)
448 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
449 base = pci_resource_start(pdev, i);
450 break;
451 }
452
bb200f6e
AS		 453 if (base)
454 uhci_check_and_reset_hc(pdev, base);
7586269c
DB		 455}
456
541ab4af
LT		 457static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx)
458{
459 return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
460}
461
7586269c
DB		 462static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
463{
464 void __iomem *base;
3df7169e 465 u32 control;
7586269c 466
541ab4af
LT		 467 if (!mmio_resource_enabled(pdev, 0))
468 return;
469
8e8ce4b6
AV		 470 base = pci_ioremap_bar(pdev, 0);
471 if (base == NULL)
472 return;
7586269c 473
3df7169e
AS		 474 control = readl(base + OHCI_CONTROL);
475
f2cb36c1 476/* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
3df7169e
AS		 477#ifdef __hppa__
478#define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR)
479#else
480#define OHCI_CTRL_MASK OHCI_CTRL_RWC
481
f2cb36c1 482 if (control & OHCI_CTRL_IR) {
c1b45f24 483 int wait_time = 500; /* arbitrary; 5 seconds */
7586269c
DB		 484 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
485 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
486 while (wait_time > 0 &&
487 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
488 wait_time -= 10;
489 msleep(10);
490 }
f2cb36c1 491 if (wait_time <= 0)
f0fda801 492 dev_warn(&pdev->dev, "OHCI: BIOS handoff failed"
493 " (BIOS bug?) %08x\n",
a38408cd 494 readl(base + OHCI_CONTROL));
7586269c 495 }
f2cb36c1 496#endif
7586269c 497
3df7169e
AS		 498 /* reset controller, preserving RWC (and possibly IR) */
499 writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
500
7586269c
DB		 501 /*
502 * disable interrupts
503 */
504 writel(~(u32)0, base + OHCI_INTRDISABLE);
505 writel(~(u32)0, base + OHCI_INTRSTATUS);
506
507 iounmap(base);
508}
509
03c75362
AA		 510static const struct dmi_system_id __initconst ehci_dmi_nohandoff_table[] = {
511 {
512 /* Pegatron Lucid (ExoPC) */
513 .matches = {
514 DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"),
515 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"),
516 },
517 },
0c42a4e8
AA		 518 {
519 /* Pegatron Lucid (Ordissimo AIRIS) */
520 .matches = {
521 DMI_MATCH(DMI_BOARD_NAME, "M11JB"),
522 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-GE-133"),
523 },
524 },
03c75362
AA		 525 { }
526};
527
5c853013
AR		 528static void __devinit ehci_bios_handoff(struct pci_dev *pdev,
529 void __iomem *op_reg_base,
530 u32 cap, u8 offset)
531{
3610ea53
AR		 532 int try_handoff = 1, tried_handoff = 0;
533
03c75362
AA		 534 /* The Pegatron Lucid tablet sporadically waits for 98 seconds trying
535 * the handoff on its unused controller. Skip it. */
3610ea53 536 if (pdev->vendor == 0x8086 && pdev->device == 0x283a) {
03c75362 537 if (dmi_check_system(ehci_dmi_nohandoff_table))
3610ea53
AR		 538 try_handoff = 0;
539 }
5c853013 540
3610ea53 541 if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) {
5c853013
AR		 542 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
543
544#if 0
545/* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
546 * but that seems dubious in general (the BIOS left it off intentionally)
547 * and is known to prevent some systems from booting. so we won't do this
548 * unless maybe we can determine when we're on a system that needs SMI forced.
549 */
550 /* BIOS workaround (?): be sure the pre-Linux code
551 * receives the SMI
552 */
553 pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val);
554 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS,
555 val | EHCI_USBLEGCTLSTS_SOOE);
556#endif
557
558 /* some systems get upset if this semaphore is
559 * set for any other reason than forcing a BIOS
560 * handoff..
561 */
562 pci_write_config_byte(pdev, offset + 3, 1);
563 }
564
565 /* if boot firmware now owns EHCI, spin till it hands it over. */
3610ea53
AR		 566 if (try_handoff) {
567 int msec = 1000;
568 while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
569 tried_handoff = 1;
570 msleep(10);
571 msec -= 10;
572 pci_read_config_dword(pdev, offset, &cap);
573 }
5c853013
AR		 574 }
575
576 if (cap & EHCI_USBLEGSUP_BIOS) {
577 /* well, possibly buggy BIOS... try to shut it down,
578 * and hope nothing goes too wrong
579 */
3610ea53
AR		 580 if (try_handoff)
581 dev_warn(&pdev->dev, "EHCI: BIOS handoff failed"
582 " (BIOS bug?) %08x\n", cap);
5c853013
AR		 583 pci_write_config_byte(pdev, offset + 2, 0);
584 }
585
586 /* just in case, always disable EHCI SMIs */
587 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0);
588
589 /* If the BIOS ever owned the controller then we can't expect
590 * any power sessions to remain intact.
591 */
592 if (tried_handoff)
593 writel(0, op_reg_base + EHCI_CONFIGFLAG);
594}
595
7586269c
DB		 596static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
597{
7586269c 598 void __iomem *base, *op_reg_base;
5c853013 599 u32 hcc_params, cap, val;
401feafa 600 u8 offset, cap_length;
5c853013 601 int wait_time, delta, count = 256/4;
7586269c 602
541ab4af
LT		 603 if (!mmio_resource_enabled(pdev, 0))
604 return;
605
8e8ce4b6
AV		 606 base = pci_ioremap_bar(pdev, 0);
607 if (base == NULL)
608 return;
7586269c
DB		 609
610 cap_length = readb(base);
611 op_reg_base = base + cap_length;
401feafa
DB		 612
613 /* EHCI 0.96 and later may have "extended capabilities"
614 * spec section 5.1 explains the bios handoff, e.g. for
615 * booting from USB disk or using a usb keyboard
616 */
7586269c 617 hcc_params = readl(base + EHCI_HCC_PARAMS);
401feafa 618 offset = (hcc_params >> 8) & 0xff;
6e14bda1 619 while (offset && --count) {
401feafa 620 pci_read_config_dword(pdev, offset, &cap);
401feafa 621
5c853013
AR		 622 switch (cap & 0xff) {
623 case 1:
624 ehci_bios_handoff(pdev, op_reg_base, cap, offset);
401feafa 625 break;
5c853013
AR		 626 case 0: /* Illegal reserved cap, set cap=0 so we exit */
627 cap = 0; /* then fallthrough... */
401feafa 628 default:
f0fda801 629 dev_warn(&pdev->dev, "EHCI: unrecognized capability "
5c853013 630 "%02x\n", cap & 0xff);
7586269c 631 }
401feafa 632 offset = (cap >> 8) & 0xff;
7586269c 633 }
401feafa 634 if (!count)
f0fda801 635 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
7586269c
DB		 636
637 /*
638 * halt EHCI & disable its interrupts in any case
639 */
640 val = readl(op_reg_base + EHCI_USBSTS);
641 if ((val & EHCI_USBSTS_HALTED) == 0) {
642 val = readl(op_reg_base + EHCI_USBCMD);
643 val &= ~EHCI_USBCMD_RUN;
644 writel(val, op_reg_base + EHCI_USBCMD);
645
646 wait_time = 2000;
647 delta = 100;
648 do {
649 writel(0x3f, op_reg_base + EHCI_USBSTS);
650 udelay(delta);
651 wait_time -= delta;
652 val = readl(op_reg_base + EHCI_USBSTS);
653 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
654 break;
655 }
656 } while (wait_time > 0);
657 }
658 writel(0, op_reg_base + EHCI_USBINTR);
659 writel(0x3f, op_reg_base + EHCI_USBSTS);
660
661 iounmap(base);
7586269c
DB		 662}
663
66d4eadd
SS		 664/*
665 * handshake - spin reading a register until handshake completes
666 * @ptr: address of hc register to be read
667 * @mask: bits to look at in result of read
668 * @done: value of those bits when handshake succeeds
669 * @wait_usec: timeout in microseconds
670 * @delay_usec: delay in microseconds to wait between polling
671 *
672 * Polls a register every delay_usec microseconds.
673 * Returns 0 when the mask bits have the value done.
674 * Returns -ETIMEDOUT if this condition is not true after
675 * wait_usec microseconds have passed.
676 */
677static int handshake(void __iomem *ptr, u32 mask, u32 done,
678 int wait_usec, int delay_usec)
679{
680 u32 result;
681
682 do {
683 result = readl(ptr);
684 result &= mask;
685 if (result == done)
686 return 0;
687 udelay(delay_usec);
688 wait_usec -= delay_usec;
689 } while (wait_usec > 0);
690 return -ETIMEDOUT;
691}
692
69e848c2
SS		 693bool usb_is_intel_switchable_xhci(struct pci_dev *pdev)
694{
695 return pdev->class == PCI_CLASS_SERIAL_USB_XHCI &&
696 pdev->vendor == PCI_VENDOR_ID_INTEL &&
697 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI;
698}
699EXPORT_SYMBOL_GPL(usb_is_intel_switchable_xhci);
700
701/*
702 * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that
703 * share some number of ports. These ports can be switched between either
704 * controller. Not all of the ports under the EHCI host controller may be
705 * switchable.
706 *
707 * The ports should be switched over to xHCI before PCI probes for any device
708 * start. This avoids active devices under EHCI being disconnected during the
709 * port switchover, which could cause loss of data on USB storage devices, or
710 * failed boot when the root file system is on a USB mass storage device and is
711 * enumerated under EHCI first.
712 *
713 * We write into the xHC's PCI configuration space in some Intel-specific
714 * registers to switch the ports over. The USB 3.0 terminations and the USB
715 * 2.0 data wires are switched separately. We want to enable the SuperSpeed
716 * terminations before switching the USB 2.0 wires over, so that USB 3.0
717 * devices connect at SuperSpeed, rather than at USB 2.0 speeds.
718 */
719void usb_enable_xhci_ports(struct pci_dev *xhci_pdev)
720{
721 u32 ports_available;
722
723 ports_available = 0xffffffff;
724 /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable
725 * Register, to turn on SuperSpeed terminations for all
726 * available ports.
727 */
728 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
729 cpu_to_le32(ports_available));
730
731 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
732 &ports_available);
733 dev_dbg(&xhci_pdev->dev, "USB 3.0 ports that are now enabled "
734 "under xHCI: 0x%x\n", ports_available);
735
736 ports_available = 0xffffffff;
737 /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to
738 * switch the USB 2.0 power and data lines over to the xHCI
739 * host.
740 */
741 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
742 cpu_to_le32(ports_available));
743
744 pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
745 &ports_available);
746 dev_dbg(&xhci_pdev->dev, "USB 2.0 ports that are now switched over "
747 "to xHCI: 0x%x\n", ports_available);
748}
749EXPORT_SYMBOL_GPL(usb_enable_xhci_ports);
750
66d4eadd
SS		 751/**
752 * PCI Quirks for xHCI.
753 *
754 * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
755 * It signals to the BIOS that the OS wants control of the host controller,
756 * and then waits 5 seconds for the BIOS to hand over control.
757 * If we timeout, assume the BIOS is broken and take control anyway.
758 */
759static void __devinit quirk_usb_handoff_xhci(struct pci_dev *pdev)
760{
761 void __iomem *base;
762 int ext_cap_offset;
763 void __iomem *op_reg_base;
764 u32 val;
765 int timeout;
766
767 if (!mmio_resource_enabled(pdev, 0))
768 return;
769
770 base = ioremap_nocache(pci_resource_start(pdev, 0),
771 pci_resource_len(pdev, 0));
772 if (base == NULL)
773 return;
7586269c 774
66d4eadd
SS		 775 /*
776 * Find the Legacy Support Capability register -
777 * this is optional for xHCI host controllers.
778 */
779 ext_cap_offset = xhci_find_next_cap_offset(base, XHCI_HCC_PARAMS_OFFSET);
780 do {
781 if (!ext_cap_offset)
782 /* We've reached the end of the extended capabilities */
783 goto hc_init;
784 val = readl(base + ext_cap_offset);
785 if (XHCI_EXT_CAPS_ID(val) == XHCI_EXT_CAPS_LEGACY)
786 break;
787 ext_cap_offset = xhci_find_next_cap_offset(base, ext_cap_offset);
788 } while (1);
789
790 /* If the BIOS owns the HC, signal that the OS wants it, and wait */
791 if (val & XHCI_HC_BIOS_OWNED) {
792 writel(val & XHCI_HC_OS_OWNED, base + ext_cap_offset);
793
794 /* Wait for 5 seconds with 10 microsecond polling interval */
795 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
796 0, 5000, 10);
797
798 /* Assume a buggy BIOS and take HC ownership anyway */
799 if (timeout) {
800 dev_warn(&pdev->dev, "xHCI BIOS handoff failed"
801 " (BIOS bug ?) %08x\n", val);
802 writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
803 }
804 }
805
806 /* Disable any BIOS SMIs */
807 writel(XHCI_LEGACY_DISABLE_SMI,
808 base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
809
69e848c2
SS		 810 if (usb_is_intel_switchable_xhci(pdev))
811 usb_enable_xhci_ports(pdev);
66d4eadd
SS		 812hc_init:
813 op_reg_base = base + XHCI_HC_LENGTH(readl(base));
814
815 /* Wait for the host controller to be ready before writing any
816 * operational or runtime registers. Wait 5 seconds and no more.
817 */
818 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
819 5000, 10);
820 /* Assume a buggy HC and start HC initialization anyway */
821 if (timeout) {
822 val = readl(op_reg_base + XHCI_STS_OFFSET);
823 dev_warn(&pdev->dev,
824 "xHCI HW not ready after 5 sec (HC bug?) "
825 "status = 0x%x\n", val);
826 }
827
828 /* Send the halt and disable interrupts command */
829 val = readl(op_reg_base + XHCI_CMD_OFFSET);
830 val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
831 writel(val, op_reg_base + XHCI_CMD_OFFSET);
832
833 /* Wait for the HC to halt - poll every 125 usec (one microframe). */
834 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
835 XHCI_MAX_HALT_USEC, 125);
836 if (timeout) {
837 val = readl(op_reg_base + XHCI_STS_OFFSET);
838 dev_warn(&pdev->dev,
839 "xHCI HW did not halt within %d usec "
840 "status = 0x%x\n", XHCI_MAX_HALT_USEC, val);
841 }
842
843 iounmap(base);
844}
7586269c
DB		 845
846static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
847{
478a3bab 848 if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
7586269c 849 quirk_usb_handoff_uhci(pdev);
478a3bab 850 else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
7586269c 851 quirk_usb_handoff_ohci(pdev);
478a3bab 852 else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
7586269c 853 quirk_usb_disable_ehci(pdev);
66d4eadd
SS		 854 else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
855 quirk_usb_handoff_xhci(pdev);
7586269c 856}
d93a8f82 857DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);
Linux kernel - Deliverables
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