projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
usb: ehci: use amd_chipset_type to filter for usb subsystem hang bug
[deliverable/linux.git] / drivers / usb / host / pci-quirks.c
CommitLineData
7586269c
DB		 1/*
2 * This file contains code to reset and initialize USB host controllers.
3 * Some of it includes work-arounds for PCI hardware and BIOS quirks.
4 * It may need to run early during booting -- before USB would normally
5 * initialize -- to ensure that Linux doesn't use any legacy modes.
6 *
7 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
8 * (and others)
9 */
10
7586269c 11#include <linux/types.h>
51c9e6c7 12#include <linux/kconfig.h>
7586269c
DB		 13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <linux/init.h>
16#include <linux/delay.h>
f940fcd8 17#include <linux/export.h>
7586269c 18#include <linux/acpi.h>
3610ea53 19#include <linux/dmi.h>
75e2df60 20#include "pci-quirks.h"
66d4eadd 21#include "xhci-ext-caps.h"
7586269c
DB		 22
23
7586269c
DB		 24#define UHCI_USBLEGSUP 0xc0 /* legacy support */
25#define UHCI_USBCMD 0 /* command register */
7586269c 26#define UHCI_USBINTR 4 /* interrupt register */
bb200f6e
AS		 27#define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
28#define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
29#define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */
30#define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */
31#define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */
32#define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */
33#define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */
7586269c
DB		 34
35#define OHCI_CONTROL 0x04
36#define OHCI_CMDSTATUS 0x08
37#define OHCI_INTRSTATUS 0x0c
38#define OHCI_INTRENABLE 0x10
39#define OHCI_INTRDISABLE 0x14
6ea12a04 40#define OHCI_FMINTERVAL 0x34
c6187597 41#define OHCI_HCFS (3 << 6) /* hc functional state */
6ea12a04 42#define OHCI_HCR (1 << 0) /* host controller reset */
7586269c 43#define OHCI_OCR (1 << 3) /* ownership change request */
f2cb36c1 44#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
7586269c
DB		 45#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
46#define OHCI_INTR_OC (1 << 30) /* ownership change */
47
48#define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
49#define EHCI_USBCMD 0 /* command register */
50#define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
51#define EHCI_USBSTS 4 /* status register */
52#define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
53#define EHCI_USBINTR 8 /* interrupt register */
4fe5354f 54#define EHCI_CONFIGFLAG 0x40 /* configured flag register */
7586269c
DB		 55#define EHCI_USBLEGSUP 0 /* legacy support register */
56#define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
57#define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
58#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
59#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
60
ad93562b
AX		 61/* AMD quirk use */
62#define AB_REG_BAR_LOW 0xe0
63#define AB_REG_BAR_HIGH 0xe1
64#define AB_REG_BAR_SB700 0xf0
65#define AB_INDX(addr) ((addr) + 0x00)
66#define AB_DATA(addr) ((addr) + 0x04)
67#define AX_INDXC 0x30
68#define AX_DATAC 0x34
69
70#define NB_PCIE_INDX_ADDR 0xe0
71#define NB_PCIE_INDX_DATA 0xe4
72#define PCIE_P_CNTL 0x10040
73#define BIF_NB 0x10002
74#define NB_PIF0_PWRDOWN_0 0x01100012
75#define NB_PIF0_PWRDOWN_1 0x01100013
76
69e848c2 77#define USB_INTEL_XUSB2PR 0xD0
a96874a2 78#define USB_INTEL_USB2PRM 0xD4
69e848c2 79#define USB_INTEL_USB3_PSSEN 0xD8
a96874a2 80#define USB_INTEL_USB3PRM 0xDC
69e848c2 81
22b4f0cd
HR		 82/*
83 * amd_chipset_gen values represent AMD different chipset generations
84 */
85enum amd_chipset_gen {
86 NOT_AMD_CHIPSET = 0,
87 AMD_CHIPSET_SB600,
88 AMD_CHIPSET_SB700,
89 AMD_CHIPSET_SB800,
90 AMD_CHIPSET_HUDSON2,
91 AMD_CHIPSET_BOLTON,
92 AMD_CHIPSET_YANGTZE,
93 AMD_CHIPSET_UNKNOWN,
94};
95
96struct amd_chipset_type {
97 enum amd_chipset_gen gen;
98 u8 rev;
99};
100
ad93562b
AX		 101static struct amd_chipset_info {
102 struct pci_dev *nb_dev;
103 struct pci_dev *smbus_dev;
104 int nb_type;
22b4f0cd 105 struct amd_chipset_type sb_type;
ad93562b
AX		 106 int isoc_reqs;
107 int probe_count;
108 int probe_result;
109} amd_chipset;
110
111static DEFINE_SPINLOCK(amd_lock);
112
22b4f0cd
HR		 113/*
114 * amd_chipset_sb_type_init - initialize amd chipset southbridge type
115 *
116 * AMD FCH/SB generation and revision is identified by SMBus controller
117 * vendor, device and revision IDs.
118 *
119 * Returns: 1 if it is an AMD chipset, 0 otherwise.
120 */
40b3dc6d 121static int amd_chipset_sb_type_init(struct amd_chipset_info *pinfo)
22b4f0cd
HR		 122{
123 u8 rev = 0;
124 pinfo->sb_type.gen = AMD_CHIPSET_UNKNOWN;
125
126 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI,
127 PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL);
128 if (pinfo->smbus_dev) {
129 rev = pinfo->smbus_dev->revision;
130 if (rev >= 0x10 && rev <= 0x1f)
131 pinfo->sb_type.gen = AMD_CHIPSET_SB600;
132 else if (rev >= 0x30 && rev <= 0x3f)
133 pinfo->sb_type.gen = AMD_CHIPSET_SB700;
134 else if (rev >= 0x40 && rev <= 0x4f)
135 pinfo->sb_type.gen = AMD_CHIPSET_SB800;
136 } else {
137 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
138 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
139
140 if (!pinfo->smbus_dev) {
141 pinfo->sb_type.gen = NOT_AMD_CHIPSET;
142 return 0;
143 }
144
145 rev = pinfo->smbus_dev->revision;
146 if (rev >= 0x11 && rev <= 0x14)
147 pinfo->sb_type.gen = AMD_CHIPSET_HUDSON2;
148 else if (rev >= 0x15 && rev <= 0x18)
149 pinfo->sb_type.gen = AMD_CHIPSET_BOLTON;
150 else if (rev >= 0x39 && rev <= 0x3a)
151 pinfo->sb_type.gen = AMD_CHIPSET_YANGTZE;
152 }
153
154 pinfo->sb_type.rev = rev;
155 return 1;
156}
157
2621d011
MG		 158void sb800_prefetch(struct device *dev, int on)
159{
160 u16 misc;
161 struct pci_dev *pdev = to_pci_dev(dev);
162
163 pci_read_config_word(pdev, 0x50, &misc);
164 if (on == 0)
165 pci_write_config_word(pdev, 0x50, misc & 0xfcff);
166 else
167 pci_write_config_word(pdev, 0x50, misc | 0x0300);
168}
169EXPORT_SYMBOL_GPL(sb800_prefetch);
170
ad93562b
AX		 171int usb_amd_find_chipset_info(void)
172{
ad93562b 173 unsigned long flags;
9ab7927b
JR		 174 struct amd_chipset_info info;
175 int ret;
ad93562b
AX		 176
177 spin_lock_irqsave(&amd_lock, flags);
178
ad93562b 179 /* probe only once */
9ab7927b
JR		 180 if (amd_chipset.probe_count > 0) {
181 amd_chipset.probe_count++;
ad93562b
AX		 182 spin_unlock_irqrestore(&amd_lock, flags);
183 return amd_chipset.probe_result;
184 }
9ab7927b
JR		 185 memset(&info, 0, sizeof(info));
186 spin_unlock_irqrestore(&amd_lock, flags);
ad93562b 187
22b4f0cd
HR		 188 if (!amd_chipset_sb_type_init(&info)) {
189 ret = 0;
190 goto commit;
ad93562b
AX		 191 }
192
22b4f0cd
HR		 193 /* Below chipset generations needn't enable AMD PLL quirk */
194 if (info.sb_type.gen == AMD_CHIPSET_UNKNOWN ||
195 info.sb_type.gen == AMD_CHIPSET_SB600 ||
196 info.sb_type.gen == AMD_CHIPSET_YANGTZE ||
197 (info.sb_type.gen == AMD_CHIPSET_SB700 &&
198 info.sb_type.rev > 0x3b)) {
9ab7927b
JR		 199 if (info.smbus_dev) {
200 pci_dev_put(info.smbus_dev);
201 info.smbus_dev = NULL;
ad93562b 202 }
9ab7927b
JR		 203 ret = 0;
204 goto commit;
ad93562b
AX		 205 }
206
9ab7927b
JR		 207 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);
208 if (info.nb_dev) {
209 info.nb_type = 1;
ad93562b 210 } else {
9ab7927b
JR		 211 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
212 if (info.nb_dev) {
213 info.nb_type = 2;
214 } else {
215 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
216 0x9600, NULL);
217 if (info.nb_dev)
218 info.nb_type = 3;
ad93562b
AX		 219 }
220 }
221
9ab7927b 222 ret = info.probe_result = 1;
ad93562b
AX		 223 printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
224
9ab7927b
JR		 225commit:
226
227 spin_lock_irqsave(&amd_lock, flags);
228 if (amd_chipset.probe_count > 0) {
229 /* race - someone else was faster - drop devices */
230
231 /* Mark that we where here */
232 amd_chipset.probe_count++;
233 ret = amd_chipset.probe_result;
234
235 spin_unlock_irqrestore(&amd_lock, flags);
236
237 if (info.nb_dev)
238 pci_dev_put(info.nb_dev);
239 if (info.smbus_dev)
240 pci_dev_put(info.smbus_dev);
241
242 } else {
243 /* no race - commit the result */
244 info.probe_count++;
245 amd_chipset = info;
246 spin_unlock_irqrestore(&amd_lock, flags);
247 }
248
249 return ret;
ad93562b
AX		 250}
251EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info);
252
7868943d
HR		 253int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev)
254{
255 /* Make sure amd chipset type has already been initialized */
256 usb_amd_find_chipset_info();
257 if (amd_chipset.sb_type.gen != AMD_CHIPSET_YANGTZE)
258 return 0;
259
260 dev_dbg(&pdev->dev, "QUIRK: Enable AMD remote wakeup fix\n");
261 return 1;
262}
263EXPORT_SYMBOL_GPL(usb_hcd_amd_remote_wakeup_quirk);
264
3ad145b6
HR		 265bool usb_amd_hang_symptom_quirk(void)
266{
267 u8 rev;
268
269 usb_amd_find_chipset_info();
270 rev = amd_chipset.sb_type.rev;
271 /* SB600 and old version of SB700 have hang symptom bug */
272 return amd_chipset.sb_type.gen == AMD_CHIPSET_SB600 ||
273 (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 &&
274 rev >= 0x3a && rev <= 0x3b);
275}
276EXPORT_SYMBOL_GPL(usb_amd_hang_symptom_quirk);
277
ad93562b
AX		 278/*
279 * The hardware normally enables the A-link power management feature, which
280 * lets the system lower the power consumption in idle states.
281 *
282 * This USB quirk prevents the link going into that lower power state
283 * during isochronous transfers.
284 *
285 * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
286 * some AMD platforms may stutter or have breaks occasionally.
287 */
288static void usb_amd_quirk_pll(int disable)
289{
290 u32 addr, addr_low, addr_high, val;
291 u32 bit = disable ? 0 : 1;
292 unsigned long flags;
293
294 spin_lock_irqsave(&amd_lock, flags);
295
296 if (disable) {
297 amd_chipset.isoc_reqs++;
298 if (amd_chipset.isoc_reqs > 1) {
299 spin_unlock_irqrestore(&amd_lock, flags);
300 return;
301 }
302 } else {
303 amd_chipset.isoc_reqs--;
304 if (amd_chipset.isoc_reqs > 0) {
305 spin_unlock_irqrestore(&amd_lock, flags);
306 return;
307 }
308 }
309
22b4f0cd
HR		 310 if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB800 ||
311 amd_chipset.sb_type.gen == AMD_CHIPSET_HUDSON2 ||
312 amd_chipset.sb_type.gen == AMD_CHIPSET_BOLTON) {
ad93562b
AX		 313 outb_p(AB_REG_BAR_LOW, 0xcd6);
314 addr_low = inb_p(0xcd7);
315 outb_p(AB_REG_BAR_HIGH, 0xcd6);
316 addr_high = inb_p(0xcd7);
317 addr = addr_high << 8 | addr_low;
318
319 outl_p(0x30, AB_INDX(addr));
320 outl_p(0x40, AB_DATA(addr));
321 outl_p(0x34, AB_INDX(addr));
322 val = inl_p(AB_DATA(addr));
22b4f0cd
HR		 323 } else if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 &&
324 amd_chipset.sb_type.rev <= 0x3b) {
ad93562b
AX		 325 pci_read_config_dword(amd_chipset.smbus_dev,
326 AB_REG_BAR_SB700, &addr);
327 outl(AX_INDXC, AB_INDX(addr));
328 outl(0x40, AB_DATA(addr));
329 outl(AX_DATAC, AB_INDX(addr));
330 val = inl(AB_DATA(addr));
331 } else {
332 spin_unlock_irqrestore(&amd_lock, flags);
333 return;
334 }
335
336 if (disable) {
337 val &= ~0x08;
338 val |= (1 << 4) | (1 << 9);
339 } else {
340 val |= 0x08;
341 val &= ~((1 << 4) | (1 << 9));
342 }
343 outl_p(val, AB_DATA(addr));
344
345 if (!amd_chipset.nb_dev) {
346 spin_unlock_irqrestore(&amd_lock, flags);
347 return;
348 }
349
350 if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) {
351 addr = PCIE_P_CNTL;
352 pci_write_config_dword(amd_chipset.nb_dev,
353 NB_PCIE_INDX_ADDR, addr);
354 pci_read_config_dword(amd_chipset.nb_dev,
355 NB_PCIE_INDX_DATA, &val);
356
357 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
358 val |= bit | (bit << 3) | (bit << 12);
359 val |= ((!bit) << 4) | ((!bit) << 9);
360 pci_write_config_dword(amd_chipset.nb_dev,
361 NB_PCIE_INDX_DATA, val);
362
363 addr = BIF_NB;
364 pci_write_config_dword(amd_chipset.nb_dev,
365 NB_PCIE_INDX_ADDR, addr);
366 pci_read_config_dword(amd_chipset.nb_dev,
367 NB_PCIE_INDX_DATA, &val);
368 val &= ~(1 << 8);
369 val |= bit << 8;
370
371 pci_write_config_dword(amd_chipset.nb_dev,
372 NB_PCIE_INDX_DATA, val);
373 } else if (amd_chipset.nb_type == 2) {
374 addr = NB_PIF0_PWRDOWN_0;
375 pci_write_config_dword(amd_chipset.nb_dev,
376 NB_PCIE_INDX_ADDR, addr);
377 pci_read_config_dword(amd_chipset.nb_dev,
378 NB_PCIE_INDX_DATA, &val);
379 if (disable)
380 val &= ~(0x3f << 7);
381 else
382 val |= 0x3f << 7;
383
384 pci_write_config_dword(amd_chipset.nb_dev,
385 NB_PCIE_INDX_DATA, val);
386
387 addr = NB_PIF0_PWRDOWN_1;
388 pci_write_config_dword(amd_chipset.nb_dev,
389 NB_PCIE_INDX_ADDR, addr);
390 pci_read_config_dword(amd_chipset.nb_dev,
391 NB_PCIE_INDX_DATA, &val);
392 if (disable)
393 val &= ~(0x3f << 7);
394 else
395 val |= 0x3f << 7;
396
397 pci_write_config_dword(amd_chipset.nb_dev,
398 NB_PCIE_INDX_DATA, val);
399 }
400
401 spin_unlock_irqrestore(&amd_lock, flags);
402 return;
403}
404
405void usb_amd_quirk_pll_disable(void)
406{
407 usb_amd_quirk_pll(1);
408}
409EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
410
411void usb_amd_quirk_pll_enable(void)
412{
413 usb_amd_quirk_pll(0);
414}
415EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable);
416
417void usb_amd_dev_put(void)
418{
9ab7927b 419 struct pci_dev *nb, *smbus;
ad93562b
AX		 420 unsigned long flags;
421
422 spin_lock_irqsave(&amd_lock, flags);
423
424 amd_chipset.probe_count--;
425 if (amd_chipset.probe_count > 0) {
426 spin_unlock_irqrestore(&amd_lock, flags);
427 return;
428 }
429
9ab7927b
JR		 430 /* save them to pci_dev_put outside of spinlock */
431 nb = amd_chipset.nb_dev;
432 smbus = amd_chipset.smbus_dev;
433
434 amd_chipset.nb_dev = NULL;
435 amd_chipset.smbus_dev = NULL;
ad93562b 436 amd_chipset.nb_type = 0;
22b4f0cd 437 memset(&amd_chipset.sb_type, 0, sizeof(amd_chipset.sb_type));
ad93562b
AX		 438 amd_chipset.isoc_reqs = 0;
439 amd_chipset.probe_result = 0;
440
441 spin_unlock_irqrestore(&amd_lock, flags);
9ab7927b
JR		 442
443 if (nb)
444 pci_dev_put(nb);
445 if (smbus)
446 pci_dev_put(smbus);
ad93562b
AX		 447}
448EXPORT_SYMBOL_GPL(usb_amd_dev_put);
7586269c 449
bb200f6e
AS		 450/*
451 * Make sure the controller is completely inactive, unable to
452 * generate interrupts or do DMA.
453 */
454void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
455{
456 /* Turn off PIRQ enable and SMI enable. (This also turns off the
457 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
458 */
459 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
460
461 /* Reset the HC - this will force us to get a
462 * new notification of any already connected
463 * ports due to the virtual disconnect that it
464 * implies.
465 */
466 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
467 mb();
468 udelay(5);
469 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
470 dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
471
472 /* Just to be safe, disable interrupt requests and
473 * make sure the controller is stopped.
474 */
475 outw(0, base + UHCI_USBINTR);
476 outw(0, base + UHCI_USBCMD);
477}
478EXPORT_SYMBOL_GPL(uhci_reset_hc);
479
480/*
481 * Initialize a controller that was newly discovered or has just been
482 * resumed. In either case we can't be sure of its previous state.
483 *
484 * Returns: 1 if the controller was reset, 0 otherwise.
485 */
486int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
487{
488 u16 legsup;
489 unsigned int cmd, intr;
490
491 /*
492 * When restarting a suspended controller, we expect all the
493 * settings to be the same as we left them:
494 *
495 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
496 * Controller is stopped and configured with EGSM set;
497 * No interrupts enabled except possibly Resume Detect.
498 *
499 * If any of these conditions are violated we do a complete reset.
500 */
501 pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
502 if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
503 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
441b62c1 504 __func__, legsup);
bb200f6e
AS		 505 goto reset_needed;
506 }
507
508 cmd = inw(base + UHCI_USBCMD);
509 if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
510 !(cmd & UHCI_USBCMD_EGSM)) {
511 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
441b62c1 512 __func__, cmd);
bb200f6e
AS		 513 goto reset_needed;
514 }
515
516 intr = inw(base + UHCI_USBINTR);
517 if (intr & (~UHCI_USBINTR_RESUME)) {
518 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
441b62c1 519 __func__, intr);
bb200f6e
AS		 520 goto reset_needed;
521 }
522 return 0;
523
524reset_needed:
525 dev_dbg(&pdev->dev, "Performing full reset\n");
526 uhci_reset_hc(pdev, base);
527 return 1;
528}
529EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
530
541ab4af
LT		 531static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
532{
533 u16 cmd;
534 return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
535}
536
537#define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
538#define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
539
41ac7b3a 540static void quirk_usb_handoff_uhci(struct pci_dev *pdev)
7586269c
DB		 541{
542 unsigned long base = 0;
7586269c
DB		 543 int i;
544
541ab4af
LT		 545 if (!pio_enabled(pdev))
546 return;
547
7586269c
DB		 548 for (i = 0; i < PCI_ROM_RESOURCE; i++)
549 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
550 base = pci_resource_start(pdev, i);
551 break;
552 }
553
bb200f6e
AS		 554 if (base)
555 uhci_check_and_reset_hc(pdev, base);
7586269c
DB		 556}
557
41ac7b3a 558static int mmio_resource_enabled(struct pci_dev *pdev, int idx)
541ab4af
LT		 559{
560 return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
561}
562
41ac7b3a 563static void quirk_usb_handoff_ohci(struct pci_dev *pdev)
7586269c
DB		 564{
565 void __iomem *base;
3df7169e 566 u32 control;
c6187597
AS		 567 u32 fminterval;
568 int cnt;
7586269c 569
541ab4af
LT		 570 if (!mmio_resource_enabled(pdev, 0))
571 return;
572
8e8ce4b6
AV		 573 base = pci_ioremap_bar(pdev, 0);
574 if (base == NULL)
575 return;
7586269c 576
3df7169e
AS		 577 control = readl(base + OHCI_CONTROL);
578
f2cb36c1 579/* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
3df7169e
AS		 580#ifdef __hppa__
581#define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR)
582#else
583#define OHCI_CTRL_MASK OHCI_CTRL_RWC
584
f2cb36c1 585 if (control & OHCI_CTRL_IR) {
c1b45f24 586 int wait_time = 500; /* arbitrary; 5 seconds */
7586269c
DB		 587 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
588 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
589 while (wait_time > 0 &&
590 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
591 wait_time -= 10;
592 msleep(10);
593 }
f2cb36c1 594 if (wait_time <= 0)
f0fda801 595 dev_warn(&pdev->dev, "OHCI: BIOS handoff failed"
596 " (BIOS bug?) %08x\n",
a38408cd 597 readl(base + OHCI_CONTROL));
7586269c 598 }
f2cb36c1 599#endif
7586269c 600
c6187597
AS		 601 /* disable interrupts */
602 writel((u32) ~0, base + OHCI_INTRDISABLE);
6ea12a04 603
c6187597
AS		 604 /* Reset the USB bus, if the controller isn't already in RESET */
605 if (control & OHCI_HCFS) {
606 /* Go into RESET, preserving RWC (and possibly IR) */
607 writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
608 readl(base + OHCI_CONTROL);
6ea12a04 609
c6187597 610 /* drive bus reset for at least 50 ms (7.1.7.5) */
6ea12a04 611 msleep(50);
c6187597 612 }
6ea12a04 613
c6187597
AS		 614 /* software reset of the controller, preserving HcFmInterval */
615 fminterval = readl(base + OHCI_FMINTERVAL);
616 writel(OHCI_HCR, base + OHCI_CMDSTATUS);
6ea12a04 617
c6187597
AS		 618 /* reset requires max 10 us delay */
619 for (cnt = 30; cnt > 0; --cnt) { /* ... allow extra time */
620 if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0)
621 break;
622 udelay(1);
6ea12a04 623 }
c6187597 624 writel(fminterval, base + OHCI_FMINTERVAL);
3df7169e 625
c6187597 626 /* Now the controller is safely in SUSPEND and nothing can wake it up */
7586269c
DB		 627 iounmap(base);
628}
629
2f82686e 630static const struct dmi_system_id ehci_dmi_nohandoff_table[] = {
03c75362
AA		 631 {
632 /* Pegatron Lucid (ExoPC) */
633 .matches = {
634 DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"),
635 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"),
636 },
637 },
0c42a4e8
AA		 638 {
639 /* Pegatron Lucid (Ordissimo AIRIS) */
640 .matches = {
641 DMI_MATCH(DMI_BOARD_NAME, "M11JB"),
c323dc02 642 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"),
0c42a4e8
AA		 643 },
644 },
8daf8b60
AA		 645 {
646 /* Pegatron Lucid (Ordissimo) */
647 .matches = {
648 DMI_MATCH(DMI_BOARD_NAME, "Ordissimo"),
649 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"),
650 },
651 },
03c75362
AA		 652 { }
653};
654
41ac7b3a 655static void ehci_bios_handoff(struct pci_dev *pdev,
5c853013
AR		 656 void __iomem *op_reg_base,
657 u32 cap, u8 offset)
658{
3610ea53
AR		 659 int try_handoff = 1, tried_handoff = 0;
660
03c75362
AA		 661 /* The Pegatron Lucid tablet sporadically waits for 98 seconds trying
662 * the handoff on its unused controller. Skip it. */
3610ea53 663 if (pdev->vendor == 0x8086 && pdev->device == 0x283a) {
03c75362 664 if (dmi_check_system(ehci_dmi_nohandoff_table))
3610ea53
AR		 665 try_handoff = 0;
666 }
5c853013 667
3610ea53 668 if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) {
5c853013
AR		 669 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
670
671#if 0
672/* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
673 * but that seems dubious in general (the BIOS left it off intentionally)
674 * and is known to prevent some systems from booting. so we won't do this
675 * unless maybe we can determine when we're on a system that needs SMI forced.
676 */
677 /* BIOS workaround (?): be sure the pre-Linux code
678 * receives the SMI
679 */
680 pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val);
681 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS,
682 val | EHCI_USBLEGCTLSTS_SOOE);
683#endif
684
685 /* some systems get upset if this semaphore is
686 * set for any other reason than forcing a BIOS
687 * handoff..
688 */
689 pci_write_config_byte(pdev, offset + 3, 1);
690 }
691
692 /* if boot firmware now owns EHCI, spin till it hands it over. */
3610ea53
AR		 693 if (try_handoff) {
694 int msec = 1000;
695 while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
696 tried_handoff = 1;
697 msleep(10);
698 msec -= 10;
699 pci_read_config_dword(pdev, offset, &cap);
700 }
5c853013
AR		 701 }
702
703 if (cap & EHCI_USBLEGSUP_BIOS) {
704 /* well, possibly buggy BIOS... try to shut it down,
705 * and hope nothing goes too wrong
706 */
3610ea53
AR		 707 if (try_handoff)
708 dev_warn(&pdev->dev, "EHCI: BIOS handoff failed"
709 " (BIOS bug?) %08x\n", cap);
5c853013
AR		 710 pci_write_config_byte(pdev, offset + 2, 0);
711 }
712
713 /* just in case, always disable EHCI SMIs */
714 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0);
715
716 /* If the BIOS ever owned the controller then we can't expect
717 * any power sessions to remain intact.
718 */
719 if (tried_handoff)
720 writel(0, op_reg_base + EHCI_CONFIGFLAG);
721}
722
41ac7b3a 723static void quirk_usb_disable_ehci(struct pci_dev *pdev)
7586269c 724{
7586269c 725 void __iomem *base, *op_reg_base;
5c853013 726 u32 hcc_params, cap, val;
401feafa 727 u8 offset, cap_length;
97ff22ee 728 int wait_time, count = 256/4;
7586269c 729
541ab4af
LT		 730 if (!mmio_resource_enabled(pdev, 0))
731 return;
732
8e8ce4b6
AV		 733 base = pci_ioremap_bar(pdev, 0);
734 if (base == NULL)
735 return;
7586269c
DB		 736
737 cap_length = readb(base);
738 op_reg_base = base + cap_length;
401feafa
DB		 739
740 /* EHCI 0.96 and later may have "extended capabilities"
741 * spec section 5.1 explains the bios handoff, e.g. for
742 * booting from USB disk or using a usb keyboard
743 */
7586269c 744 hcc_params = readl(base + EHCI_HCC_PARAMS);
401feafa 745 offset = (hcc_params >> 8) & 0xff;
6e14bda1 746 while (offset && --count) {
401feafa 747 pci_read_config_dword(pdev, offset, &cap);
401feafa 748
5c853013
AR		 749 switch (cap & 0xff) {
750 case 1:
751 ehci_bios_handoff(pdev, op_reg_base, cap, offset);
401feafa 752 break;
5c853013
AR		 753 case 0: /* Illegal reserved cap, set cap=0 so we exit */
754 cap = 0; /* then fallthrough... */
401feafa 755 default:
f0fda801 756 dev_warn(&pdev->dev, "EHCI: unrecognized capability "
5c853013 757 "%02x\n", cap & 0xff);
7586269c 758 }
401feafa 759 offset = (cap >> 8) & 0xff;
7586269c 760 }
401feafa 761 if (!count)
f0fda801 762 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
7586269c
DB		 763
764 /*
765 * halt EHCI & disable its interrupts in any case
766 */
767 val = readl(op_reg_base + EHCI_USBSTS);
768 if ((val & EHCI_USBSTS_HALTED) == 0) {
769 val = readl(op_reg_base + EHCI_USBCMD);
770 val &= ~EHCI_USBCMD_RUN;
771 writel(val, op_reg_base + EHCI_USBCMD);
772
773 wait_time = 2000;
7586269c
DB		 774 do {
775 writel(0x3f, op_reg_base + EHCI_USBSTS);
97ff22ee
AS		 776 udelay(100);
777 wait_time -= 100;
7586269c
DB		 778 val = readl(op_reg_base + EHCI_USBSTS);
779 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
780 break;
781 }
782 } while (wait_time > 0);
783 }
784 writel(0, op_reg_base + EHCI_USBINTR);
785 writel(0x3f, op_reg_base + EHCI_USBSTS);
786
787 iounmap(base);
7586269c
DB		 788}
789
66d4eadd
SS		 790/*
791 * handshake - spin reading a register until handshake completes
792 * @ptr: address of hc register to be read
793 * @mask: bits to look at in result of read
794 * @done: value of those bits when handshake succeeds
795 * @wait_usec: timeout in microseconds
796 * @delay_usec: delay in microseconds to wait between polling
797 *
798 * Polls a register every delay_usec microseconds.
799 * Returns 0 when the mask bits have the value done.
800 * Returns -ETIMEDOUT if this condition is not true after
801 * wait_usec microseconds have passed.
802 */
803static int handshake(void __iomem *ptr, u32 mask, u32 done,
804 int wait_usec, int delay_usec)
805{
806 u32 result;
807
808 do {
809 result = readl(ptr);
810 result &= mask;
811 if (result == done)
812 return 0;
813 udelay(delay_usec);
814 wait_usec -= delay_usec;
815 } while (wait_usec > 0);
816 return -ETIMEDOUT;
817}
818
69e848c2
SS		 819/*
820 * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that
821 * share some number of ports. These ports can be switched between either
822 * controller. Not all of the ports under the EHCI host controller may be
823 * switchable.
824 *
825 * The ports should be switched over to xHCI before PCI probes for any device
826 * start. This avoids active devices under EHCI being disconnected during the
827 * port switchover, which could cause loss of data on USB storage devices, or
828 * failed boot when the root file system is on a USB mass storage device and is
829 * enumerated under EHCI first.
830 *
831 * We write into the xHC's PCI configuration space in some Intel-specific
832 * registers to switch the ports over. The USB 3.0 terminations and the USB
833 * 2.0 data wires are switched separately. We want to enable the SuperSpeed
834 * terminations before switching the USB 2.0 wires over, so that USB 3.0
835 * devices connect at SuperSpeed, rather than at USB 2.0 speeds.
836 */
26b76798 837void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev)
69e848c2
SS		 838{
839 u32 ports_available;
26b76798
MN		 840 bool ehci_found = false;
841 struct pci_dev *companion = NULL;
842
843 /* make sure an intel EHCI controller exists */
844 for_each_pci_dev(companion) {
845 if (companion->class == PCI_CLASS_SERIAL_USB_EHCI &&
846 companion->vendor == PCI_VENDOR_ID_INTEL) {
847 ehci_found = true;
848 break;
849 }
850 }
851
852 if (!ehci_found)
853 return;
69e848c2 854
51c9e6c7
SS		 855 /* Don't switchover the ports if the user hasn't compiled the xHCI
856 * driver. Otherwise they will see "dead" USB ports that don't power
857 * the devices.
858 */
859 if (!IS_ENABLED(CONFIG_USB_XHCI_HCD)) {
860 dev_warn(&xhci_pdev->dev,
861 "CONFIG_USB_XHCI_HCD is turned off, "
862 "defaulting to EHCI.\n");
863 dev_warn(&xhci_pdev->dev,
864 "USB 3.0 devices will work at USB 2.0 speeds.\n");
58b2939b 865 usb_disable_xhci_ports(xhci_pdev);
51c9e6c7
SS		 866 return;
867 }
868
a96874a2
KYL		 869 /* Read USB3PRM, the USB 3.0 Port Routing Mask Register
870 * Indicate the ports that can be changed from OS.
871 */
872 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3PRM,
873 &ports_available);
874
875 dev_dbg(&xhci_pdev->dev, "Configurable ports to enable SuperSpeed: 0x%x\n",
876 ports_available);
877
69e848c2 878 /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable
a96874a2
KYL		 879 * Register, to turn on SuperSpeed terminations for the
880 * switchable ports.
69e848c2
SS		 881 */
882 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
883 cpu_to_le32(ports_available));
884
885 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
886 &ports_available);
887 dev_dbg(&xhci_pdev->dev, "USB 3.0 ports that are now enabled "
888 "under xHCI: 0x%x\n", ports_available);
889
a96874a2
KYL		 890 /* Read XUSB2PRM, xHCI USB 2.0 Port Routing Mask Register
891 * Indicate the USB 2.0 ports to be controlled by the xHCI host.
892 */
893
894 pci_read_config_dword(xhci_pdev, USB_INTEL_USB2PRM,
895 &ports_available);
896
897 dev_dbg(&xhci_pdev->dev, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n",
898 ports_available);
899
69e848c2
SS		 900 /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to
901 * switch the USB 2.0 power and data lines over to the xHCI
902 * host.
903 */
904 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
905 cpu_to_le32(ports_available));
906
907 pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
908 &ports_available);
909 dev_dbg(&xhci_pdev->dev, "USB 2.0 ports that are now switched over "
910 "to xHCI: 0x%x\n", ports_available);
911}
26b76798 912EXPORT_SYMBOL_GPL(usb_enable_intel_xhci_ports);
69e848c2 913
e95829f4
SS		 914void usb_disable_xhci_ports(struct pci_dev *xhci_pdev)
915{
916 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 0x0);
917 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 0x0);
918}
919EXPORT_SYMBOL_GPL(usb_disable_xhci_ports);
920
66d4eadd
SS		 921/**
922 * PCI Quirks for xHCI.
923 *
924 * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
925 * It signals to the BIOS that the OS wants control of the host controller,
926 * and then waits 5 seconds for the BIOS to hand over control.
927 * If we timeout, assume the BIOS is broken and take control anyway.
928 */
41ac7b3a 929static void quirk_usb_handoff_xhci(struct pci_dev *pdev)
66d4eadd
SS		 930{
931 void __iomem *base;
932 int ext_cap_offset;
933 void __iomem *op_reg_base;
934 u32 val;
935 int timeout;
e955a1cd 936 int len = pci_resource_len(pdev, 0);
66d4eadd
SS		 937
938 if (!mmio_resource_enabled(pdev, 0))
939 return;
940
e955a1cd 941 base = ioremap_nocache(pci_resource_start(pdev, 0), len);
66d4eadd
SS		 942 if (base == NULL)
943 return;
7586269c 944
66d4eadd
SS		 945 /*
946 * Find the Legacy Support Capability register -
947 * this is optional for xHCI host controllers.
948 */
949 ext_cap_offset = xhci_find_next_cap_offset(base, XHCI_HCC_PARAMS_OFFSET);
950 do {
e955a1cd
MG		 951 if ((ext_cap_offset + sizeof(val)) > len) {
952 /* We're reading garbage from the controller */
953 dev_warn(&pdev->dev,
954 "xHCI controller failing to respond");
955 return;
956 }
957
66d4eadd
SS		 958 if (!ext_cap_offset)
959 /* We've reached the end of the extended capabilities */
960 goto hc_init;
e955a1cd 961
66d4eadd
SS		 962 val = readl(base + ext_cap_offset);
963 if (XHCI_EXT_CAPS_ID(val) == XHCI_EXT_CAPS_LEGACY)
964 break;
965 ext_cap_offset = xhci_find_next_cap_offset(base, ext_cap_offset);
966 } while (1);
967
968 /* If the BIOS owns the HC, signal that the OS wants it, and wait */
969 if (val & XHCI_HC_BIOS_OWNED) {
6768458b 970 writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset);
66d4eadd
SS		 971
972 /* Wait for 5 seconds with 10 microsecond polling interval */
973 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
974 0, 5000, 10);
975
976 /* Assume a buggy BIOS and take HC ownership anyway */
977 if (timeout) {
978 dev_warn(&pdev->dev, "xHCI BIOS handoff failed"
979 " (BIOS bug ?) %08x\n", val);
980 writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
981 }
982 }
983
95018a53
AH		 984 val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
985 /* Mask off (turn off) any enabled SMIs */
986 val &= XHCI_LEGACY_DISABLE_SMI;
987 /* Mask all SMI events bits, RW1C */
988 val |= XHCI_LEGACY_SMI_EVENTS;
989 /* Disable any BIOS SMIs and clear all SMI events*/
990 writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
66d4eadd 991
29d21457 992hc_init:
26b76798
MN		 993 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
994 usb_enable_intel_xhci_ports(pdev);
29d21457 995
66d4eadd
SS		 996 op_reg_base = base + XHCI_HC_LENGTH(readl(base));
997
998 /* Wait for the host controller to be ready before writing any
999 * operational or runtime registers. Wait 5 seconds and no more.
1000 */
1001 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
1002 5000, 10);
1003 /* Assume a buggy HC and start HC initialization anyway */
1004 if (timeout) {
1005 val = readl(op_reg_base + XHCI_STS_OFFSET);
1006 dev_warn(&pdev->dev,
1007 "xHCI HW not ready after 5 sec (HC bug?) "
1008 "status = 0x%x\n", val);
1009 }
1010
1011 /* Send the halt and disable interrupts command */
1012 val = readl(op_reg_base + XHCI_CMD_OFFSET);
1013 val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
1014 writel(val, op_reg_base + XHCI_CMD_OFFSET);
1015
1016 /* Wait for the HC to halt - poll every 125 usec (one microframe). */
1017 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
1018 XHCI_MAX_HALT_USEC, 125);
1019 if (timeout) {
1020 val = readl(op_reg_base + XHCI_STS_OFFSET);
1021 dev_warn(&pdev->dev,
1022 "xHCI HW did not halt within %d usec "
1023 "status = 0x%x\n", XHCI_MAX_HALT_USEC, val);
1024 }
1025
1026 iounmap(base);
1027}
7586269c 1028
41ac7b3a 1029static void quirk_usb_early_handoff(struct pci_dev *pdev)
7586269c 1030{
e4436a7c
J		 1031 /* Skip Netlogic mips SoC's internal PCI USB controller.
1032 * This device does not need/support EHCI/OHCI handoff
1033 */
1034 if (pdev->vendor == 0x184e) /* vendor Netlogic */
1035 return;
cab928ee
SS		 1036 if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI &&
1037 pdev->class != PCI_CLASS_SERIAL_USB_OHCI &&
1038 pdev->class != PCI_CLASS_SERIAL_USB_EHCI &&
1039 pdev->class != PCI_CLASS_SERIAL_USB_XHCI)
1040 return;
e4436a7c 1041
cab928ee
SS		 1042 if (pci_enable_device(pdev) < 0) {
1043 dev_warn(&pdev->dev, "Can't enable PCI device, "
1044 "BIOS handoff failed.\n");
1045 return;
1046 }
478a3bab 1047 if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
7586269c 1048 quirk_usb_handoff_uhci(pdev);
478a3bab 1049 else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
7586269c 1050 quirk_usb_handoff_ohci(pdev);
478a3bab 1051 else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
7586269c 1052 quirk_usb_disable_ehci(pdev);
66d4eadd
SS		 1053 else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
1054 quirk_usb_handoff_xhci(pdev);
cab928ee 1055 pci_disable_device(pdev);
7586269c 1056}
8474ecd9
YL		 1057DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1058 PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff);
Linux kernel - Deliverables
This page took 0.764786 seconds and 5 git commands to generate.