Commit | Line | Data |
---|---|---|
7586269c DB |
1 | /* |
2 | * This file contains code to reset and initialize USB host controllers. | |
3 | * Some of it includes work-arounds for PCI hardware and BIOS quirks. | |
4 | * It may need to run early during booting -- before USB would normally | |
5 | * initialize -- to ensure that Linux doesn't use any legacy modes. | |
6 | * | |
7 | * Copyright (c) 1999 Martin Mares <mj@ucw.cz> | |
8 | * (and others) | |
9 | */ | |
10 | ||
7586269c | 11 | #include <linux/types.h> |
51c9e6c7 | 12 | #include <linux/kconfig.h> |
7586269c DB |
13 | #include <linux/kernel.h> |
14 | #include <linux/pci.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/delay.h> | |
f940fcd8 | 17 | #include <linux/export.h> |
7586269c | 18 | #include <linux/acpi.h> |
3610ea53 | 19 | #include <linux/dmi.h> |
75e2df60 | 20 | #include "pci-quirks.h" |
66d4eadd | 21 | #include "xhci-ext-caps.h" |
7586269c DB |
22 | |
23 | ||
7586269c DB |
24 | #define UHCI_USBLEGSUP 0xc0 /* legacy support */ |
25 | #define UHCI_USBCMD 0 /* command register */ | |
7586269c | 26 | #define UHCI_USBINTR 4 /* interrupt register */ |
bb200f6e AS |
27 | #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ |
28 | #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ | |
29 | #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */ | |
30 | #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */ | |
31 | #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */ | |
32 | #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */ | |
33 | #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */ | |
7586269c DB |
34 | |
35 | #define OHCI_CONTROL 0x04 | |
36 | #define OHCI_CMDSTATUS 0x08 | |
37 | #define OHCI_INTRSTATUS 0x0c | |
38 | #define OHCI_INTRENABLE 0x10 | |
39 | #define OHCI_INTRDISABLE 0x14 | |
6ea12a04 | 40 | #define OHCI_FMINTERVAL 0x34 |
c6187597 | 41 | #define OHCI_HCFS (3 << 6) /* hc functional state */ |
6ea12a04 | 42 | #define OHCI_HCR (1 << 0) /* host controller reset */ |
7586269c | 43 | #define OHCI_OCR (1 << 3) /* ownership change request */ |
f2cb36c1 | 44 | #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ |
7586269c DB |
45 | #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ |
46 | #define OHCI_INTR_OC (1 << 30) /* ownership change */ | |
47 | ||
48 | #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */ | |
49 | #define EHCI_USBCMD 0 /* command register */ | |
50 | #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */ | |
51 | #define EHCI_USBSTS 4 /* status register */ | |
52 | #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */ | |
53 | #define EHCI_USBINTR 8 /* interrupt register */ | |
4fe5354f | 54 | #define EHCI_CONFIGFLAG 0x40 /* configured flag register */ |
7586269c DB |
55 | #define EHCI_USBLEGSUP 0 /* legacy support register */ |
56 | #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */ | |
57 | #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */ | |
58 | #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */ | |
59 | #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */ | |
60 | ||
ad93562b AX |
61 | /* AMD quirk use */ |
62 | #define AB_REG_BAR_LOW 0xe0 | |
63 | #define AB_REG_BAR_HIGH 0xe1 | |
64 | #define AB_REG_BAR_SB700 0xf0 | |
65 | #define AB_INDX(addr) ((addr) + 0x00) | |
66 | #define AB_DATA(addr) ((addr) + 0x04) | |
67 | #define AX_INDXC 0x30 | |
68 | #define AX_DATAC 0x34 | |
69 | ||
70 | #define NB_PCIE_INDX_ADDR 0xe0 | |
71 | #define NB_PCIE_INDX_DATA 0xe4 | |
72 | #define PCIE_P_CNTL 0x10040 | |
73 | #define BIF_NB 0x10002 | |
74 | #define NB_PIF0_PWRDOWN_0 0x01100012 | |
75 | #define NB_PIF0_PWRDOWN_1 0x01100013 | |
76 | ||
69e848c2 | 77 | #define USB_INTEL_XUSB2PR 0xD0 |
a96874a2 | 78 | #define USB_INTEL_USB2PRM 0xD4 |
69e848c2 | 79 | #define USB_INTEL_USB3_PSSEN 0xD8 |
a96874a2 | 80 | #define USB_INTEL_USB3PRM 0xDC |
69e848c2 | 81 | |
22b4f0cd HR |
82 | /* |
83 | * amd_chipset_gen values represent AMD different chipset generations | |
84 | */ | |
85 | enum amd_chipset_gen { | |
86 | NOT_AMD_CHIPSET = 0, | |
87 | AMD_CHIPSET_SB600, | |
88 | AMD_CHIPSET_SB700, | |
89 | AMD_CHIPSET_SB800, | |
90 | AMD_CHIPSET_HUDSON2, | |
91 | AMD_CHIPSET_BOLTON, | |
92 | AMD_CHIPSET_YANGTZE, | |
93 | AMD_CHIPSET_UNKNOWN, | |
94 | }; | |
95 | ||
96 | struct amd_chipset_type { | |
97 | enum amd_chipset_gen gen; | |
98 | u8 rev; | |
99 | }; | |
100 | ||
ad93562b AX |
101 | static struct amd_chipset_info { |
102 | struct pci_dev *nb_dev; | |
103 | struct pci_dev *smbus_dev; | |
104 | int nb_type; | |
22b4f0cd | 105 | struct amd_chipset_type sb_type; |
ad93562b AX |
106 | int isoc_reqs; |
107 | int probe_count; | |
108 | int probe_result; | |
109 | } amd_chipset; | |
110 | ||
111 | static DEFINE_SPINLOCK(amd_lock); | |
112 | ||
22b4f0cd HR |
113 | /* |
114 | * amd_chipset_sb_type_init - initialize amd chipset southbridge type | |
115 | * | |
116 | * AMD FCH/SB generation and revision is identified by SMBus controller | |
117 | * vendor, device and revision IDs. | |
118 | * | |
119 | * Returns: 1 if it is an AMD chipset, 0 otherwise. | |
120 | */ | |
40b3dc6d | 121 | static int amd_chipset_sb_type_init(struct amd_chipset_info *pinfo) |
22b4f0cd HR |
122 | { |
123 | u8 rev = 0; | |
124 | pinfo->sb_type.gen = AMD_CHIPSET_UNKNOWN; | |
125 | ||
126 | pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, | |
127 | PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL); | |
128 | if (pinfo->smbus_dev) { | |
129 | rev = pinfo->smbus_dev->revision; | |
130 | if (rev >= 0x10 && rev <= 0x1f) | |
131 | pinfo->sb_type.gen = AMD_CHIPSET_SB600; | |
132 | else if (rev >= 0x30 && rev <= 0x3f) | |
133 | pinfo->sb_type.gen = AMD_CHIPSET_SB700; | |
134 | else if (rev >= 0x40 && rev <= 0x4f) | |
135 | pinfo->sb_type.gen = AMD_CHIPSET_SB800; | |
136 | } else { | |
137 | pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, | |
138 | PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); | |
139 | ||
140 | if (!pinfo->smbus_dev) { | |
141 | pinfo->sb_type.gen = NOT_AMD_CHIPSET; | |
142 | return 0; | |
143 | } | |
144 | ||
145 | rev = pinfo->smbus_dev->revision; | |
146 | if (rev >= 0x11 && rev <= 0x14) | |
147 | pinfo->sb_type.gen = AMD_CHIPSET_HUDSON2; | |
148 | else if (rev >= 0x15 && rev <= 0x18) | |
149 | pinfo->sb_type.gen = AMD_CHIPSET_BOLTON; | |
150 | else if (rev >= 0x39 && rev <= 0x3a) | |
151 | pinfo->sb_type.gen = AMD_CHIPSET_YANGTZE; | |
152 | } | |
153 | ||
154 | pinfo->sb_type.rev = rev; | |
155 | return 1; | |
156 | } | |
157 | ||
2621d011 MG |
158 | void sb800_prefetch(struct device *dev, int on) |
159 | { | |
160 | u16 misc; | |
161 | struct pci_dev *pdev = to_pci_dev(dev); | |
162 | ||
163 | pci_read_config_word(pdev, 0x50, &misc); | |
164 | if (on == 0) | |
165 | pci_write_config_word(pdev, 0x50, misc & 0xfcff); | |
166 | else | |
167 | pci_write_config_word(pdev, 0x50, misc | 0x0300); | |
168 | } | |
169 | EXPORT_SYMBOL_GPL(sb800_prefetch); | |
170 | ||
ad93562b AX |
171 | int usb_amd_find_chipset_info(void) |
172 | { | |
ad93562b | 173 | unsigned long flags; |
9ab7927b JR |
174 | struct amd_chipset_info info; |
175 | int ret; | |
ad93562b AX |
176 | |
177 | spin_lock_irqsave(&amd_lock, flags); | |
178 | ||
ad93562b | 179 | /* probe only once */ |
9ab7927b JR |
180 | if (amd_chipset.probe_count > 0) { |
181 | amd_chipset.probe_count++; | |
ad93562b AX |
182 | spin_unlock_irqrestore(&amd_lock, flags); |
183 | return amd_chipset.probe_result; | |
184 | } | |
9ab7927b JR |
185 | memset(&info, 0, sizeof(info)); |
186 | spin_unlock_irqrestore(&amd_lock, flags); | |
ad93562b | 187 | |
22b4f0cd HR |
188 | if (!amd_chipset_sb_type_init(&info)) { |
189 | ret = 0; | |
190 | goto commit; | |
ad93562b AX |
191 | } |
192 | ||
22b4f0cd HR |
193 | /* Below chipset generations needn't enable AMD PLL quirk */ |
194 | if (info.sb_type.gen == AMD_CHIPSET_UNKNOWN || | |
195 | info.sb_type.gen == AMD_CHIPSET_SB600 || | |
196 | info.sb_type.gen == AMD_CHIPSET_YANGTZE || | |
197 | (info.sb_type.gen == AMD_CHIPSET_SB700 && | |
198 | info.sb_type.rev > 0x3b)) { | |
9ab7927b JR |
199 | if (info.smbus_dev) { |
200 | pci_dev_put(info.smbus_dev); | |
201 | info.smbus_dev = NULL; | |
ad93562b | 202 | } |
9ab7927b JR |
203 | ret = 0; |
204 | goto commit; | |
ad93562b AX |
205 | } |
206 | ||
9ab7927b JR |
207 | info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL); |
208 | if (info.nb_dev) { | |
209 | info.nb_type = 1; | |
ad93562b | 210 | } else { |
9ab7927b JR |
211 | info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL); |
212 | if (info.nb_dev) { | |
213 | info.nb_type = 2; | |
214 | } else { | |
215 | info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, | |
216 | 0x9600, NULL); | |
217 | if (info.nb_dev) | |
218 | info.nb_type = 3; | |
ad93562b AX |
219 | } |
220 | } | |
221 | ||
9ab7927b | 222 | ret = info.probe_result = 1; |
ad93562b AX |
223 | printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n"); |
224 | ||
9ab7927b JR |
225 | commit: |
226 | ||
227 | spin_lock_irqsave(&amd_lock, flags); | |
228 | if (amd_chipset.probe_count > 0) { | |
229 | /* race - someone else was faster - drop devices */ | |
230 | ||
231 | /* Mark that we where here */ | |
232 | amd_chipset.probe_count++; | |
233 | ret = amd_chipset.probe_result; | |
234 | ||
235 | spin_unlock_irqrestore(&amd_lock, flags); | |
236 | ||
237 | if (info.nb_dev) | |
238 | pci_dev_put(info.nb_dev); | |
239 | if (info.smbus_dev) | |
240 | pci_dev_put(info.smbus_dev); | |
241 | ||
242 | } else { | |
243 | /* no race - commit the result */ | |
244 | info.probe_count++; | |
245 | amd_chipset = info; | |
246 | spin_unlock_irqrestore(&amd_lock, flags); | |
247 | } | |
248 | ||
249 | return ret; | |
ad93562b AX |
250 | } |
251 | EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info); | |
252 | ||
7868943d HR |
253 | int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev) |
254 | { | |
255 | /* Make sure amd chipset type has already been initialized */ | |
256 | usb_amd_find_chipset_info(); | |
257 | if (amd_chipset.sb_type.gen != AMD_CHIPSET_YANGTZE) | |
258 | return 0; | |
259 | ||
260 | dev_dbg(&pdev->dev, "QUIRK: Enable AMD remote wakeup fix\n"); | |
261 | return 1; | |
262 | } | |
263 | EXPORT_SYMBOL_GPL(usb_hcd_amd_remote_wakeup_quirk); | |
264 | ||
ad93562b AX |
265 | /* |
266 | * The hardware normally enables the A-link power management feature, which | |
267 | * lets the system lower the power consumption in idle states. | |
268 | * | |
269 | * This USB quirk prevents the link going into that lower power state | |
270 | * during isochronous transfers. | |
271 | * | |
272 | * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of | |
273 | * some AMD platforms may stutter or have breaks occasionally. | |
274 | */ | |
275 | static void usb_amd_quirk_pll(int disable) | |
276 | { | |
277 | u32 addr, addr_low, addr_high, val; | |
278 | u32 bit = disable ? 0 : 1; | |
279 | unsigned long flags; | |
280 | ||
281 | spin_lock_irqsave(&amd_lock, flags); | |
282 | ||
283 | if (disable) { | |
284 | amd_chipset.isoc_reqs++; | |
285 | if (amd_chipset.isoc_reqs > 1) { | |
286 | spin_unlock_irqrestore(&amd_lock, flags); | |
287 | return; | |
288 | } | |
289 | } else { | |
290 | amd_chipset.isoc_reqs--; | |
291 | if (amd_chipset.isoc_reqs > 0) { | |
292 | spin_unlock_irqrestore(&amd_lock, flags); | |
293 | return; | |
294 | } | |
295 | } | |
296 | ||
22b4f0cd HR |
297 | if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB800 || |
298 | amd_chipset.sb_type.gen == AMD_CHIPSET_HUDSON2 || | |
299 | amd_chipset.sb_type.gen == AMD_CHIPSET_BOLTON) { | |
ad93562b AX |
300 | outb_p(AB_REG_BAR_LOW, 0xcd6); |
301 | addr_low = inb_p(0xcd7); | |
302 | outb_p(AB_REG_BAR_HIGH, 0xcd6); | |
303 | addr_high = inb_p(0xcd7); | |
304 | addr = addr_high << 8 | addr_low; | |
305 | ||
306 | outl_p(0x30, AB_INDX(addr)); | |
307 | outl_p(0x40, AB_DATA(addr)); | |
308 | outl_p(0x34, AB_INDX(addr)); | |
309 | val = inl_p(AB_DATA(addr)); | |
22b4f0cd HR |
310 | } else if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 && |
311 | amd_chipset.sb_type.rev <= 0x3b) { | |
ad93562b AX |
312 | pci_read_config_dword(amd_chipset.smbus_dev, |
313 | AB_REG_BAR_SB700, &addr); | |
314 | outl(AX_INDXC, AB_INDX(addr)); | |
315 | outl(0x40, AB_DATA(addr)); | |
316 | outl(AX_DATAC, AB_INDX(addr)); | |
317 | val = inl(AB_DATA(addr)); | |
318 | } else { | |
319 | spin_unlock_irqrestore(&amd_lock, flags); | |
320 | return; | |
321 | } | |
322 | ||
323 | if (disable) { | |
324 | val &= ~0x08; | |
325 | val |= (1 << 4) | (1 << 9); | |
326 | } else { | |
327 | val |= 0x08; | |
328 | val &= ~((1 << 4) | (1 << 9)); | |
329 | } | |
330 | outl_p(val, AB_DATA(addr)); | |
331 | ||
332 | if (!amd_chipset.nb_dev) { | |
333 | spin_unlock_irqrestore(&amd_lock, flags); | |
334 | return; | |
335 | } | |
336 | ||
337 | if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) { | |
338 | addr = PCIE_P_CNTL; | |
339 | pci_write_config_dword(amd_chipset.nb_dev, | |
340 | NB_PCIE_INDX_ADDR, addr); | |
341 | pci_read_config_dword(amd_chipset.nb_dev, | |
342 | NB_PCIE_INDX_DATA, &val); | |
343 | ||
344 | val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12)); | |
345 | val |= bit | (bit << 3) | (bit << 12); | |
346 | val |= ((!bit) << 4) | ((!bit) << 9); | |
347 | pci_write_config_dword(amd_chipset.nb_dev, | |
348 | NB_PCIE_INDX_DATA, val); | |
349 | ||
350 | addr = BIF_NB; | |
351 | pci_write_config_dword(amd_chipset.nb_dev, | |
352 | NB_PCIE_INDX_ADDR, addr); | |
353 | pci_read_config_dword(amd_chipset.nb_dev, | |
354 | NB_PCIE_INDX_DATA, &val); | |
355 | val &= ~(1 << 8); | |
356 | val |= bit << 8; | |
357 | ||
358 | pci_write_config_dword(amd_chipset.nb_dev, | |
359 | NB_PCIE_INDX_DATA, val); | |
360 | } else if (amd_chipset.nb_type == 2) { | |
361 | addr = NB_PIF0_PWRDOWN_0; | |
362 | pci_write_config_dword(amd_chipset.nb_dev, | |
363 | NB_PCIE_INDX_ADDR, addr); | |
364 | pci_read_config_dword(amd_chipset.nb_dev, | |
365 | NB_PCIE_INDX_DATA, &val); | |
366 | if (disable) | |
367 | val &= ~(0x3f << 7); | |
368 | else | |
369 | val |= 0x3f << 7; | |
370 | ||
371 | pci_write_config_dword(amd_chipset.nb_dev, | |
372 | NB_PCIE_INDX_DATA, val); | |
373 | ||
374 | addr = NB_PIF0_PWRDOWN_1; | |
375 | pci_write_config_dword(amd_chipset.nb_dev, | |
376 | NB_PCIE_INDX_ADDR, addr); | |
377 | pci_read_config_dword(amd_chipset.nb_dev, | |
378 | NB_PCIE_INDX_DATA, &val); | |
379 | if (disable) | |
380 | val &= ~(0x3f << 7); | |
381 | else | |
382 | val |= 0x3f << 7; | |
383 | ||
384 | pci_write_config_dword(amd_chipset.nb_dev, | |
385 | NB_PCIE_INDX_DATA, val); | |
386 | } | |
387 | ||
388 | spin_unlock_irqrestore(&amd_lock, flags); | |
389 | return; | |
390 | } | |
391 | ||
392 | void usb_amd_quirk_pll_disable(void) | |
393 | { | |
394 | usb_amd_quirk_pll(1); | |
395 | } | |
396 | EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable); | |
397 | ||
398 | void usb_amd_quirk_pll_enable(void) | |
399 | { | |
400 | usb_amd_quirk_pll(0); | |
401 | } | |
402 | EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable); | |
403 | ||
404 | void usb_amd_dev_put(void) | |
405 | { | |
9ab7927b | 406 | struct pci_dev *nb, *smbus; |
ad93562b AX |
407 | unsigned long flags; |
408 | ||
409 | spin_lock_irqsave(&amd_lock, flags); | |
410 | ||
411 | amd_chipset.probe_count--; | |
412 | if (amd_chipset.probe_count > 0) { | |
413 | spin_unlock_irqrestore(&amd_lock, flags); | |
414 | return; | |
415 | } | |
416 | ||
9ab7927b JR |
417 | /* save them to pci_dev_put outside of spinlock */ |
418 | nb = amd_chipset.nb_dev; | |
419 | smbus = amd_chipset.smbus_dev; | |
420 | ||
421 | amd_chipset.nb_dev = NULL; | |
422 | amd_chipset.smbus_dev = NULL; | |
ad93562b | 423 | amd_chipset.nb_type = 0; |
22b4f0cd | 424 | memset(&amd_chipset.sb_type, 0, sizeof(amd_chipset.sb_type)); |
ad93562b AX |
425 | amd_chipset.isoc_reqs = 0; |
426 | amd_chipset.probe_result = 0; | |
427 | ||
428 | spin_unlock_irqrestore(&amd_lock, flags); | |
9ab7927b JR |
429 | |
430 | if (nb) | |
431 | pci_dev_put(nb); | |
432 | if (smbus) | |
433 | pci_dev_put(smbus); | |
ad93562b AX |
434 | } |
435 | EXPORT_SYMBOL_GPL(usb_amd_dev_put); | |
7586269c | 436 | |
bb200f6e AS |
437 | /* |
438 | * Make sure the controller is completely inactive, unable to | |
439 | * generate interrupts or do DMA. | |
440 | */ | |
441 | void uhci_reset_hc(struct pci_dev *pdev, unsigned long base) | |
442 | { | |
443 | /* Turn off PIRQ enable and SMI enable. (This also turns off the | |
444 | * BIOS's USB Legacy Support.) Turn off all the R/WC bits too. | |
445 | */ | |
446 | pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC); | |
447 | ||
448 | /* Reset the HC - this will force us to get a | |
449 | * new notification of any already connected | |
450 | * ports due to the virtual disconnect that it | |
451 | * implies. | |
452 | */ | |
453 | outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD); | |
454 | mb(); | |
455 | udelay(5); | |
456 | if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET) | |
457 | dev_warn(&pdev->dev, "HCRESET not completed yet!\n"); | |
458 | ||
459 | /* Just to be safe, disable interrupt requests and | |
460 | * make sure the controller is stopped. | |
461 | */ | |
462 | outw(0, base + UHCI_USBINTR); | |
463 | outw(0, base + UHCI_USBCMD); | |
464 | } | |
465 | EXPORT_SYMBOL_GPL(uhci_reset_hc); | |
466 | ||
467 | /* | |
468 | * Initialize a controller that was newly discovered or has just been | |
469 | * resumed. In either case we can't be sure of its previous state. | |
470 | * | |
471 | * Returns: 1 if the controller was reset, 0 otherwise. | |
472 | */ | |
473 | int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) | |
474 | { | |
475 | u16 legsup; | |
476 | unsigned int cmd, intr; | |
477 | ||
478 | /* | |
479 | * When restarting a suspended controller, we expect all the | |
480 | * settings to be the same as we left them: | |
481 | * | |
482 | * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP; | |
483 | * Controller is stopped and configured with EGSM set; | |
484 | * No interrupts enabled except possibly Resume Detect. | |
485 | * | |
486 | * If any of these conditions are violated we do a complete reset. | |
487 | */ | |
488 | pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup); | |
489 | if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) { | |
490 | dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n", | |
441b62c1 | 491 | __func__, legsup); |
bb200f6e AS |
492 | goto reset_needed; |
493 | } | |
494 | ||
495 | cmd = inw(base + UHCI_USBCMD); | |
496 | if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) || | |
497 | !(cmd & UHCI_USBCMD_EGSM)) { | |
498 | dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n", | |
441b62c1 | 499 | __func__, cmd); |
bb200f6e AS |
500 | goto reset_needed; |
501 | } | |
502 | ||
503 | intr = inw(base + UHCI_USBINTR); | |
504 | if (intr & (~UHCI_USBINTR_RESUME)) { | |
505 | dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n", | |
441b62c1 | 506 | __func__, intr); |
bb200f6e AS |
507 | goto reset_needed; |
508 | } | |
509 | return 0; | |
510 | ||
511 | reset_needed: | |
512 | dev_dbg(&pdev->dev, "Performing full reset\n"); | |
513 | uhci_reset_hc(pdev, base); | |
514 | return 1; | |
515 | } | |
516 | EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc); | |
517 | ||
541ab4af LT |
518 | static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) |
519 | { | |
520 | u16 cmd; | |
521 | return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask); | |
522 | } | |
523 | ||
524 | #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO) | |
525 | #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY) | |
526 | ||
41ac7b3a | 527 | static void quirk_usb_handoff_uhci(struct pci_dev *pdev) |
7586269c DB |
528 | { |
529 | unsigned long base = 0; | |
7586269c DB |
530 | int i; |
531 | ||
541ab4af LT |
532 | if (!pio_enabled(pdev)) |
533 | return; | |
534 | ||
7586269c DB |
535 | for (i = 0; i < PCI_ROM_RESOURCE; i++) |
536 | if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) { | |
537 | base = pci_resource_start(pdev, i); | |
538 | break; | |
539 | } | |
540 | ||
bb200f6e AS |
541 | if (base) |
542 | uhci_check_and_reset_hc(pdev, base); | |
7586269c DB |
543 | } |
544 | ||
41ac7b3a | 545 | static int mmio_resource_enabled(struct pci_dev *pdev, int idx) |
541ab4af LT |
546 | { |
547 | return pci_resource_start(pdev, idx) && mmio_enabled(pdev); | |
548 | } | |
549 | ||
41ac7b3a | 550 | static void quirk_usb_handoff_ohci(struct pci_dev *pdev) |
7586269c DB |
551 | { |
552 | void __iomem *base; | |
3df7169e | 553 | u32 control; |
c6187597 AS |
554 | u32 fminterval; |
555 | int cnt; | |
7586269c | 556 | |
541ab4af LT |
557 | if (!mmio_resource_enabled(pdev, 0)) |
558 | return; | |
559 | ||
8e8ce4b6 AV |
560 | base = pci_ioremap_bar(pdev, 0); |
561 | if (base == NULL) | |
562 | return; | |
7586269c | 563 | |
3df7169e AS |
564 | control = readl(base + OHCI_CONTROL); |
565 | ||
f2cb36c1 | 566 | /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ |
3df7169e AS |
567 | #ifdef __hppa__ |
568 | #define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR) | |
569 | #else | |
570 | #define OHCI_CTRL_MASK OHCI_CTRL_RWC | |
571 | ||
f2cb36c1 | 572 | if (control & OHCI_CTRL_IR) { |
c1b45f24 | 573 | int wait_time = 500; /* arbitrary; 5 seconds */ |
7586269c DB |
574 | writel(OHCI_INTR_OC, base + OHCI_INTRENABLE); |
575 | writel(OHCI_OCR, base + OHCI_CMDSTATUS); | |
576 | while (wait_time > 0 && | |
577 | readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) { | |
578 | wait_time -= 10; | |
579 | msleep(10); | |
580 | } | |
f2cb36c1 | 581 | if (wait_time <= 0) |
f0fda801 | 582 | dev_warn(&pdev->dev, "OHCI: BIOS handoff failed" |
583 | " (BIOS bug?) %08x\n", | |
a38408cd | 584 | readl(base + OHCI_CONTROL)); |
7586269c | 585 | } |
f2cb36c1 | 586 | #endif |
7586269c | 587 | |
c6187597 AS |
588 | /* disable interrupts */ |
589 | writel((u32) ~0, base + OHCI_INTRDISABLE); | |
6ea12a04 | 590 | |
c6187597 AS |
591 | /* Reset the USB bus, if the controller isn't already in RESET */ |
592 | if (control & OHCI_HCFS) { | |
593 | /* Go into RESET, preserving RWC (and possibly IR) */ | |
594 | writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL); | |
595 | readl(base + OHCI_CONTROL); | |
6ea12a04 | 596 | |
c6187597 | 597 | /* drive bus reset for at least 50 ms (7.1.7.5) */ |
6ea12a04 | 598 | msleep(50); |
c6187597 | 599 | } |
6ea12a04 | 600 | |
c6187597 AS |
601 | /* software reset of the controller, preserving HcFmInterval */ |
602 | fminterval = readl(base + OHCI_FMINTERVAL); | |
603 | writel(OHCI_HCR, base + OHCI_CMDSTATUS); | |
6ea12a04 | 604 | |
c6187597 AS |
605 | /* reset requires max 10 us delay */ |
606 | for (cnt = 30; cnt > 0; --cnt) { /* ... allow extra time */ | |
607 | if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0) | |
608 | break; | |
609 | udelay(1); | |
6ea12a04 | 610 | } |
c6187597 | 611 | writel(fminterval, base + OHCI_FMINTERVAL); |
3df7169e | 612 | |
c6187597 | 613 | /* Now the controller is safely in SUSPEND and nothing can wake it up */ |
7586269c DB |
614 | iounmap(base); |
615 | } | |
616 | ||
2f82686e | 617 | static const struct dmi_system_id ehci_dmi_nohandoff_table[] = { |
03c75362 AA |
618 | { |
619 | /* Pegatron Lucid (ExoPC) */ | |
620 | .matches = { | |
621 | DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"), | |
622 | DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"), | |
623 | }, | |
624 | }, | |
0c42a4e8 AA |
625 | { |
626 | /* Pegatron Lucid (Ordissimo AIRIS) */ | |
627 | .matches = { | |
628 | DMI_MATCH(DMI_BOARD_NAME, "M11JB"), | |
c323dc02 | 629 | DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"), |
0c42a4e8 AA |
630 | }, |
631 | }, | |
8daf8b60 AA |
632 | { |
633 | /* Pegatron Lucid (Ordissimo) */ | |
634 | .matches = { | |
635 | DMI_MATCH(DMI_BOARD_NAME, "Ordissimo"), | |
636 | DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"), | |
637 | }, | |
638 | }, | |
03c75362 AA |
639 | { } |
640 | }; | |
641 | ||
41ac7b3a | 642 | static void ehci_bios_handoff(struct pci_dev *pdev, |
5c853013 AR |
643 | void __iomem *op_reg_base, |
644 | u32 cap, u8 offset) | |
645 | { | |
3610ea53 AR |
646 | int try_handoff = 1, tried_handoff = 0; |
647 | ||
03c75362 AA |
648 | /* The Pegatron Lucid tablet sporadically waits for 98 seconds trying |
649 | * the handoff on its unused controller. Skip it. */ | |
3610ea53 | 650 | if (pdev->vendor == 0x8086 && pdev->device == 0x283a) { |
03c75362 | 651 | if (dmi_check_system(ehci_dmi_nohandoff_table)) |
3610ea53 AR |
652 | try_handoff = 0; |
653 | } | |
5c853013 | 654 | |
3610ea53 | 655 | if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) { |
5c853013 AR |
656 | dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n"); |
657 | ||
658 | #if 0 | |
659 | /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on, | |
660 | * but that seems dubious in general (the BIOS left it off intentionally) | |
661 | * and is known to prevent some systems from booting. so we won't do this | |
662 | * unless maybe we can determine when we're on a system that needs SMI forced. | |
663 | */ | |
664 | /* BIOS workaround (?): be sure the pre-Linux code | |
665 | * receives the SMI | |
666 | */ | |
667 | pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val); | |
668 | pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, | |
669 | val | EHCI_USBLEGCTLSTS_SOOE); | |
670 | #endif | |
671 | ||
672 | /* some systems get upset if this semaphore is | |
673 | * set for any other reason than forcing a BIOS | |
674 | * handoff.. | |
675 | */ | |
676 | pci_write_config_byte(pdev, offset + 3, 1); | |
677 | } | |
678 | ||
679 | /* if boot firmware now owns EHCI, spin till it hands it over. */ | |
3610ea53 AR |
680 | if (try_handoff) { |
681 | int msec = 1000; | |
682 | while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) { | |
683 | tried_handoff = 1; | |
684 | msleep(10); | |
685 | msec -= 10; | |
686 | pci_read_config_dword(pdev, offset, &cap); | |
687 | } | |
5c853013 AR |
688 | } |
689 | ||
690 | if (cap & EHCI_USBLEGSUP_BIOS) { | |
691 | /* well, possibly buggy BIOS... try to shut it down, | |
692 | * and hope nothing goes too wrong | |
693 | */ | |
3610ea53 AR |
694 | if (try_handoff) |
695 | dev_warn(&pdev->dev, "EHCI: BIOS handoff failed" | |
696 | " (BIOS bug?) %08x\n", cap); | |
5c853013 AR |
697 | pci_write_config_byte(pdev, offset + 2, 0); |
698 | } | |
699 | ||
700 | /* just in case, always disable EHCI SMIs */ | |
701 | pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0); | |
702 | ||
703 | /* If the BIOS ever owned the controller then we can't expect | |
704 | * any power sessions to remain intact. | |
705 | */ | |
706 | if (tried_handoff) | |
707 | writel(0, op_reg_base + EHCI_CONFIGFLAG); | |
708 | } | |
709 | ||
41ac7b3a | 710 | static void quirk_usb_disable_ehci(struct pci_dev *pdev) |
7586269c | 711 | { |
7586269c | 712 | void __iomem *base, *op_reg_base; |
5c853013 | 713 | u32 hcc_params, cap, val; |
401feafa | 714 | u8 offset, cap_length; |
97ff22ee | 715 | int wait_time, count = 256/4; |
7586269c | 716 | |
541ab4af LT |
717 | if (!mmio_resource_enabled(pdev, 0)) |
718 | return; | |
719 | ||
8e8ce4b6 AV |
720 | base = pci_ioremap_bar(pdev, 0); |
721 | if (base == NULL) | |
722 | return; | |
7586269c DB |
723 | |
724 | cap_length = readb(base); | |
725 | op_reg_base = base + cap_length; | |
401feafa DB |
726 | |
727 | /* EHCI 0.96 and later may have "extended capabilities" | |
728 | * spec section 5.1 explains the bios handoff, e.g. for | |
729 | * booting from USB disk or using a usb keyboard | |
730 | */ | |
7586269c | 731 | hcc_params = readl(base + EHCI_HCC_PARAMS); |
401feafa | 732 | offset = (hcc_params >> 8) & 0xff; |
6e14bda1 | 733 | while (offset && --count) { |
401feafa | 734 | pci_read_config_dword(pdev, offset, &cap); |
401feafa | 735 | |
5c853013 AR |
736 | switch (cap & 0xff) { |
737 | case 1: | |
738 | ehci_bios_handoff(pdev, op_reg_base, cap, offset); | |
401feafa | 739 | break; |
5c853013 AR |
740 | case 0: /* Illegal reserved cap, set cap=0 so we exit */ |
741 | cap = 0; /* then fallthrough... */ | |
401feafa | 742 | default: |
f0fda801 | 743 | dev_warn(&pdev->dev, "EHCI: unrecognized capability " |
5c853013 | 744 | "%02x\n", cap & 0xff); |
7586269c | 745 | } |
401feafa | 746 | offset = (cap >> 8) & 0xff; |
7586269c | 747 | } |
401feafa | 748 | if (!count) |
f0fda801 | 749 | dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n"); |
7586269c DB |
750 | |
751 | /* | |
752 | * halt EHCI & disable its interrupts in any case | |
753 | */ | |
754 | val = readl(op_reg_base + EHCI_USBSTS); | |
755 | if ((val & EHCI_USBSTS_HALTED) == 0) { | |
756 | val = readl(op_reg_base + EHCI_USBCMD); | |
757 | val &= ~EHCI_USBCMD_RUN; | |
758 | writel(val, op_reg_base + EHCI_USBCMD); | |
759 | ||
760 | wait_time = 2000; | |
7586269c DB |
761 | do { |
762 | writel(0x3f, op_reg_base + EHCI_USBSTS); | |
97ff22ee AS |
763 | udelay(100); |
764 | wait_time -= 100; | |
7586269c DB |
765 | val = readl(op_reg_base + EHCI_USBSTS); |
766 | if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) { | |
767 | break; | |
768 | } | |
769 | } while (wait_time > 0); | |
770 | } | |
771 | writel(0, op_reg_base + EHCI_USBINTR); | |
772 | writel(0x3f, op_reg_base + EHCI_USBSTS); | |
773 | ||
774 | iounmap(base); | |
7586269c DB |
775 | } |
776 | ||
66d4eadd SS |
777 | /* |
778 | * handshake - spin reading a register until handshake completes | |
779 | * @ptr: address of hc register to be read | |
780 | * @mask: bits to look at in result of read | |
781 | * @done: value of those bits when handshake succeeds | |
782 | * @wait_usec: timeout in microseconds | |
783 | * @delay_usec: delay in microseconds to wait between polling | |
784 | * | |
785 | * Polls a register every delay_usec microseconds. | |
786 | * Returns 0 when the mask bits have the value done. | |
787 | * Returns -ETIMEDOUT if this condition is not true after | |
788 | * wait_usec microseconds have passed. | |
789 | */ | |
790 | static int handshake(void __iomem *ptr, u32 mask, u32 done, | |
791 | int wait_usec, int delay_usec) | |
792 | { | |
793 | u32 result; | |
794 | ||
795 | do { | |
796 | result = readl(ptr); | |
797 | result &= mask; | |
798 | if (result == done) | |
799 | return 0; | |
800 | udelay(delay_usec); | |
801 | wait_usec -= delay_usec; | |
802 | } while (wait_usec > 0); | |
803 | return -ETIMEDOUT; | |
804 | } | |
805 | ||
69e848c2 SS |
806 | /* |
807 | * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that | |
808 | * share some number of ports. These ports can be switched between either | |
809 | * controller. Not all of the ports under the EHCI host controller may be | |
810 | * switchable. | |
811 | * | |
812 | * The ports should be switched over to xHCI before PCI probes for any device | |
813 | * start. This avoids active devices under EHCI being disconnected during the | |
814 | * port switchover, which could cause loss of data on USB storage devices, or | |
815 | * failed boot when the root file system is on a USB mass storage device and is | |
816 | * enumerated under EHCI first. | |
817 | * | |
818 | * We write into the xHC's PCI configuration space in some Intel-specific | |
819 | * registers to switch the ports over. The USB 3.0 terminations and the USB | |
820 | * 2.0 data wires are switched separately. We want to enable the SuperSpeed | |
821 | * terminations before switching the USB 2.0 wires over, so that USB 3.0 | |
822 | * devices connect at SuperSpeed, rather than at USB 2.0 speeds. | |
823 | */ | |
26b76798 | 824 | void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev) |
69e848c2 SS |
825 | { |
826 | u32 ports_available; | |
26b76798 MN |
827 | bool ehci_found = false; |
828 | struct pci_dev *companion = NULL; | |
829 | ||
830 | /* make sure an intel EHCI controller exists */ | |
831 | for_each_pci_dev(companion) { | |
832 | if (companion->class == PCI_CLASS_SERIAL_USB_EHCI && | |
833 | companion->vendor == PCI_VENDOR_ID_INTEL) { | |
834 | ehci_found = true; | |
835 | break; | |
836 | } | |
837 | } | |
838 | ||
839 | if (!ehci_found) | |
840 | return; | |
69e848c2 | 841 | |
51c9e6c7 SS |
842 | /* Don't switchover the ports if the user hasn't compiled the xHCI |
843 | * driver. Otherwise they will see "dead" USB ports that don't power | |
844 | * the devices. | |
845 | */ | |
846 | if (!IS_ENABLED(CONFIG_USB_XHCI_HCD)) { | |
847 | dev_warn(&xhci_pdev->dev, | |
848 | "CONFIG_USB_XHCI_HCD is turned off, " | |
849 | "defaulting to EHCI.\n"); | |
850 | dev_warn(&xhci_pdev->dev, | |
851 | "USB 3.0 devices will work at USB 2.0 speeds.\n"); | |
58b2939b | 852 | usb_disable_xhci_ports(xhci_pdev); |
51c9e6c7 SS |
853 | return; |
854 | } | |
855 | ||
a96874a2 KYL |
856 | /* Read USB3PRM, the USB 3.0 Port Routing Mask Register |
857 | * Indicate the ports that can be changed from OS. | |
858 | */ | |
859 | pci_read_config_dword(xhci_pdev, USB_INTEL_USB3PRM, | |
860 | &ports_available); | |
861 | ||
862 | dev_dbg(&xhci_pdev->dev, "Configurable ports to enable SuperSpeed: 0x%x\n", | |
863 | ports_available); | |
864 | ||
69e848c2 | 865 | /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable |
a96874a2 KYL |
866 | * Register, to turn on SuperSpeed terminations for the |
867 | * switchable ports. | |
69e848c2 SS |
868 | */ |
869 | pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, | |
870 | cpu_to_le32(ports_available)); | |
871 | ||
872 | pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, | |
873 | &ports_available); | |
874 | dev_dbg(&xhci_pdev->dev, "USB 3.0 ports that are now enabled " | |
875 | "under xHCI: 0x%x\n", ports_available); | |
876 | ||
a96874a2 KYL |
877 | /* Read XUSB2PRM, xHCI USB 2.0 Port Routing Mask Register |
878 | * Indicate the USB 2.0 ports to be controlled by the xHCI host. | |
879 | */ | |
880 | ||
881 | pci_read_config_dword(xhci_pdev, USB_INTEL_USB2PRM, | |
882 | &ports_available); | |
883 | ||
884 | dev_dbg(&xhci_pdev->dev, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n", | |
885 | ports_available); | |
886 | ||
69e848c2 SS |
887 | /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to |
888 | * switch the USB 2.0 power and data lines over to the xHCI | |
889 | * host. | |
890 | */ | |
891 | pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, | |
892 | cpu_to_le32(ports_available)); | |
893 | ||
894 | pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, | |
895 | &ports_available); | |
896 | dev_dbg(&xhci_pdev->dev, "USB 2.0 ports that are now switched over " | |
897 | "to xHCI: 0x%x\n", ports_available); | |
898 | } | |
26b76798 | 899 | EXPORT_SYMBOL_GPL(usb_enable_intel_xhci_ports); |
69e848c2 | 900 | |
e95829f4 SS |
901 | void usb_disable_xhci_ports(struct pci_dev *xhci_pdev) |
902 | { | |
903 | pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 0x0); | |
904 | pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 0x0); | |
905 | } | |
906 | EXPORT_SYMBOL_GPL(usb_disable_xhci_ports); | |
907 | ||
66d4eadd SS |
908 | /** |
909 | * PCI Quirks for xHCI. | |
910 | * | |
911 | * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS. | |
912 | * It signals to the BIOS that the OS wants control of the host controller, | |
913 | * and then waits 5 seconds for the BIOS to hand over control. | |
914 | * If we timeout, assume the BIOS is broken and take control anyway. | |
915 | */ | |
41ac7b3a | 916 | static void quirk_usb_handoff_xhci(struct pci_dev *pdev) |
66d4eadd SS |
917 | { |
918 | void __iomem *base; | |
919 | int ext_cap_offset; | |
920 | void __iomem *op_reg_base; | |
921 | u32 val; | |
922 | int timeout; | |
e955a1cd | 923 | int len = pci_resource_len(pdev, 0); |
66d4eadd SS |
924 | |
925 | if (!mmio_resource_enabled(pdev, 0)) | |
926 | return; | |
927 | ||
e955a1cd | 928 | base = ioremap_nocache(pci_resource_start(pdev, 0), len); |
66d4eadd SS |
929 | if (base == NULL) |
930 | return; | |
7586269c | 931 | |
66d4eadd SS |
932 | /* |
933 | * Find the Legacy Support Capability register - | |
934 | * this is optional for xHCI host controllers. | |
935 | */ | |
936 | ext_cap_offset = xhci_find_next_cap_offset(base, XHCI_HCC_PARAMS_OFFSET); | |
937 | do { | |
e955a1cd MG |
938 | if ((ext_cap_offset + sizeof(val)) > len) { |
939 | /* We're reading garbage from the controller */ | |
940 | dev_warn(&pdev->dev, | |
941 | "xHCI controller failing to respond"); | |
942 | return; | |
943 | } | |
944 | ||
66d4eadd SS |
945 | if (!ext_cap_offset) |
946 | /* We've reached the end of the extended capabilities */ | |
947 | goto hc_init; | |
e955a1cd | 948 | |
66d4eadd SS |
949 | val = readl(base + ext_cap_offset); |
950 | if (XHCI_EXT_CAPS_ID(val) == XHCI_EXT_CAPS_LEGACY) | |
951 | break; | |
952 | ext_cap_offset = xhci_find_next_cap_offset(base, ext_cap_offset); | |
953 | } while (1); | |
954 | ||
955 | /* If the BIOS owns the HC, signal that the OS wants it, and wait */ | |
956 | if (val & XHCI_HC_BIOS_OWNED) { | |
6768458b | 957 | writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset); |
66d4eadd SS |
958 | |
959 | /* Wait for 5 seconds with 10 microsecond polling interval */ | |
960 | timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED, | |
961 | 0, 5000, 10); | |
962 | ||
963 | /* Assume a buggy BIOS and take HC ownership anyway */ | |
964 | if (timeout) { | |
965 | dev_warn(&pdev->dev, "xHCI BIOS handoff failed" | |
966 | " (BIOS bug ?) %08x\n", val); | |
967 | writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset); | |
968 | } | |
969 | } | |
970 | ||
95018a53 AH |
971 | val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); |
972 | /* Mask off (turn off) any enabled SMIs */ | |
973 | val &= XHCI_LEGACY_DISABLE_SMI; | |
974 | /* Mask all SMI events bits, RW1C */ | |
975 | val |= XHCI_LEGACY_SMI_EVENTS; | |
976 | /* Disable any BIOS SMIs and clear all SMI events*/ | |
977 | writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); | |
66d4eadd | 978 | |
29d21457 | 979 | hc_init: |
26b76798 MN |
980 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) |
981 | usb_enable_intel_xhci_ports(pdev); | |
29d21457 | 982 | |
66d4eadd SS |
983 | op_reg_base = base + XHCI_HC_LENGTH(readl(base)); |
984 | ||
985 | /* Wait for the host controller to be ready before writing any | |
986 | * operational or runtime registers. Wait 5 seconds and no more. | |
987 | */ | |
988 | timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0, | |
989 | 5000, 10); | |
990 | /* Assume a buggy HC and start HC initialization anyway */ | |
991 | if (timeout) { | |
992 | val = readl(op_reg_base + XHCI_STS_OFFSET); | |
993 | dev_warn(&pdev->dev, | |
994 | "xHCI HW not ready after 5 sec (HC bug?) " | |
995 | "status = 0x%x\n", val); | |
996 | } | |
997 | ||
998 | /* Send the halt and disable interrupts command */ | |
999 | val = readl(op_reg_base + XHCI_CMD_OFFSET); | |
1000 | val &= ~(XHCI_CMD_RUN | XHCI_IRQS); | |
1001 | writel(val, op_reg_base + XHCI_CMD_OFFSET); | |
1002 | ||
1003 | /* Wait for the HC to halt - poll every 125 usec (one microframe). */ | |
1004 | timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1, | |
1005 | XHCI_MAX_HALT_USEC, 125); | |
1006 | if (timeout) { | |
1007 | val = readl(op_reg_base + XHCI_STS_OFFSET); | |
1008 | dev_warn(&pdev->dev, | |
1009 | "xHCI HW did not halt within %d usec " | |
1010 | "status = 0x%x\n", XHCI_MAX_HALT_USEC, val); | |
1011 | } | |
1012 | ||
1013 | iounmap(base); | |
1014 | } | |
7586269c | 1015 | |
41ac7b3a | 1016 | static void quirk_usb_early_handoff(struct pci_dev *pdev) |
7586269c | 1017 | { |
e4436a7c J |
1018 | /* Skip Netlogic mips SoC's internal PCI USB controller. |
1019 | * This device does not need/support EHCI/OHCI handoff | |
1020 | */ | |
1021 | if (pdev->vendor == 0x184e) /* vendor Netlogic */ | |
1022 | return; | |
cab928ee SS |
1023 | if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI && |
1024 | pdev->class != PCI_CLASS_SERIAL_USB_OHCI && | |
1025 | pdev->class != PCI_CLASS_SERIAL_USB_EHCI && | |
1026 | pdev->class != PCI_CLASS_SERIAL_USB_XHCI) | |
1027 | return; | |
e4436a7c | 1028 | |
cab928ee SS |
1029 | if (pci_enable_device(pdev) < 0) { |
1030 | dev_warn(&pdev->dev, "Can't enable PCI device, " | |
1031 | "BIOS handoff failed.\n"); | |
1032 | return; | |
1033 | } | |
478a3bab | 1034 | if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI) |
7586269c | 1035 | quirk_usb_handoff_uhci(pdev); |
478a3bab | 1036 | else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI) |
7586269c | 1037 | quirk_usb_handoff_ohci(pdev); |
478a3bab | 1038 | else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI) |
7586269c | 1039 | quirk_usb_disable_ehci(pdev); |
66d4eadd SS |
1040 | else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI) |
1041 | quirk_usb_handoff_xhci(pdev); | |
cab928ee | 1042 | pci_disable_device(pdev); |
7586269c | 1043 | } |
8474ecd9 YL |
1044 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, |
1045 | PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff); |