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1da177e4 LT |
1 | /* |
2 | * Universal Host Controller Interface driver for USB. | |
3 | * | |
4 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | |
5 | * | |
6 | * (C) Copyright 1999 Linus Torvalds | |
7 | * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com | |
8 | * (C) Copyright 1999 Randy Dunlap | |
9 | * (C) Copyright 1999 Georg Acher, acher@in.tum.de | |
10 | * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de | |
11 | * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch | |
12 | * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at | |
13 | * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface | |
14 | * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com). | |
15 | * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c) | |
17230acd | 16 | * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu |
1da177e4 LT |
17 | * |
18 | * Intel documents this fairly well, and as far as I know there | |
19 | * are no royalties or anything like that, but even so there are | |
20 | * people who decided that they want to do the same thing in a | |
21 | * completely different way. | |
22 | * | |
1da177e4 LT |
23 | */ |
24 | ||
1da177e4 LT |
25 | #include <linux/module.h> |
26 | #include <linux/pci.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/ioport.h> | |
1da177e4 | 31 | #include <linux/slab.h> |
1da177e4 LT |
32 | #include <linux/errno.h> |
33 | #include <linux/unistd.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/spinlock.h> | |
36 | #include <linux/debugfs.h> | |
37 | #include <linux/pm.h> | |
38 | #include <linux/dmapool.h> | |
39 | #include <linux/dma-mapping.h> | |
40 | #include <linux/usb.h> | |
27729aad | 41 | #include <linux/usb/hcd.h> |
1da177e4 | 42 | #include <linux/bitops.h> |
b62df451 | 43 | #include <linux/dmi.h> |
1da177e4 LT |
44 | |
45 | #include <asm/uaccess.h> | |
46 | #include <asm/io.h> | |
47 | #include <asm/irq.h> | |
48 | #include <asm/system.h> | |
49 | ||
1da177e4 | 50 | #include "uhci-hcd.h" |
75e2df60 | 51 | #include "pci-quirks.h" |
1da177e4 LT |
52 | |
53 | /* | |
54 | * Version Information | |
55 | */ | |
1da177e4 LT |
56 | #define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \ |
57 | Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \ | |
58 | Alan Stern" | |
59 | #define DRIVER_DESC "USB Universal Host Controller Interface driver" | |
60 | ||
5f8364b7 AS |
61 | /* for flakey hardware, ignore overcurrent indicators */ |
62 | static int ignore_oc; | |
63 | module_param(ignore_oc, bool, S_IRUGO); | |
64 | MODULE_PARM_DESC(ignore_oc, "ignore hardware overcurrent indications"); | |
65 | ||
1da177e4 LT |
66 | /* |
67 | * debug = 0, no debugging messages | |
687f5f34 AS |
68 | * debug = 1, dump failed URBs except for stalls |
69 | * debug = 2, dump all failed URBs (including stalls) | |
837cbb07 | 70 | * show all queues in /sys/kernel/debug/uhci/[pci_addr] |
687f5f34 | 71 | * debug = 3, show all TDs in URBs when dumping |
1da177e4 LT |
72 | */ |
73 | #ifdef DEBUG | |
8d402e1a | 74 | #define DEBUG_CONFIGURED 1 |
1da177e4 | 75 | static int debug = 1; |
1da177e4 LT |
76 | module_param(debug, int, S_IRUGO | S_IWUSR); |
77 | MODULE_PARM_DESC(debug, "Debug level"); | |
8d402e1a AS |
78 | |
79 | #else | |
80 | #define DEBUG_CONFIGURED 0 | |
81 | #define debug 0 | |
82 | #endif | |
83 | ||
1da177e4 LT |
84 | static char *errbuf; |
85 | #define ERRBUF_LEN (32 * 1024) | |
86 | ||
e18b890b | 87 | static struct kmem_cache *uhci_up_cachep; /* urb_priv */ |
1da177e4 | 88 | |
6c1b445c AS |
89 | static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state); |
90 | static void wakeup_rh(struct uhci_hcd *uhci); | |
1da177e4 | 91 | static void uhci_get_current_frame_number(struct uhci_hcd *uhci); |
1da177e4 | 92 | |
f3fe239b AS |
93 | /* |
94 | * Calculate the link pointer DMA value for the first Skeleton QH in a frame. | |
95 | */ | |
96 | static __le32 uhci_frame_skel_link(struct uhci_hcd *uhci, int frame) | |
97 | { | |
98 | int skelnum; | |
99 | ||
100 | /* | |
101 | * The interrupt queues will be interleaved as evenly as possible. | |
102 | * There's not much to be done about period-1 interrupts; they have | |
103 | * to occur in every frame. But we can schedule period-2 interrupts | |
104 | * in odd-numbered frames, period-4 interrupts in frames congruent | |
105 | * to 2 (mod 4), and so on. This way each frame only has two | |
106 | * interrupt QHs, which will help spread out bandwidth utilization. | |
107 | * | |
108 | * ffs (Find First bit Set) does exactly what we need: | |
17230acd AS |
109 | * 1,3,5,... => ffs = 0 => use period-2 QH = skelqh[8], |
110 | * 2,6,10,... => ffs = 1 => use period-4 QH = skelqh[7], etc. | |
f3fe239b | 111 | * ffs >= 7 => not on any high-period queue, so use |
17230acd | 112 | * period-1 QH = skelqh[9]. |
f3fe239b AS |
113 | * Add in UHCI_NUMFRAMES to insure at least one bit is set. |
114 | */ | |
115 | skelnum = 8 - (int) __ffs(frame | UHCI_NUMFRAMES); | |
116 | if (skelnum <= 1) | |
117 | skelnum = 9; | |
28b9325e | 118 | return LINK_TO_QH(uhci->skelqh[skelnum]); |
f3fe239b AS |
119 | } |
120 | ||
1da177e4 LT |
121 | #include "uhci-debug.c" |
122 | #include "uhci-q.c" | |
1f09df8b | 123 | #include "uhci-hub.c" |
1da177e4 | 124 | |
a8bed8b6 | 125 | /* |
bb200f6e | 126 | * Finish up a host controller reset and update the recorded state. |
a8bed8b6 | 127 | */ |
bb200f6e | 128 | static void finish_reset(struct uhci_hcd *uhci) |
1da177e4 | 129 | { |
c074b416 AS |
130 | int port; |
131 | ||
c074b416 AS |
132 | /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect |
133 | * bits in the port status and control registers. | |
134 | * We have to clear them by hand. | |
135 | */ | |
136 | for (port = 0; port < uhci->rh_numports; ++port) | |
137 | outw(0, uhci->io_addr + USBPORTSC1 + (port * 2)); | |
138 | ||
8e326406 | 139 | uhci->port_c_suspend = uhci->resuming_ports = 0; |
c8f4fe43 | 140 | uhci->rh_state = UHCI_RH_RESET; |
a8bed8b6 AS |
141 | uhci->is_stopped = UHCI_IS_STOPPED; |
142 | uhci_to_hcd(uhci)->state = HC_STATE_HALT; | |
541c7d43 | 143 | clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); |
e323de46 AS |
144 | |
145 | uhci->dead = 0; /* Full reset resurrects the controller */ | |
1da177e4 LT |
146 | } |
147 | ||
4daaa87c AS |
148 | /* |
149 | * Last rites for a defunct/nonfunctional controller | |
02597d2d | 150 | * or one we don't want to use any more. |
4daaa87c | 151 | */ |
e323de46 | 152 | static void uhci_hc_died(struct uhci_hcd *uhci) |
4daaa87c | 153 | { |
e323de46 | 154 | uhci_get_current_frame_number(uhci); |
bb200f6e AS |
155 | uhci_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr); |
156 | finish_reset(uhci); | |
e323de46 AS |
157 | uhci->dead = 1; |
158 | ||
159 | /* The current frame may already be partway finished */ | |
160 | ++uhci->frame_number; | |
4daaa87c AS |
161 | } |
162 | ||
a8bed8b6 | 163 | /* |
be3cbc5f DB |
164 | * Initialize a controller that was newly discovered or has lost power |
165 | * or otherwise been reset while it was suspended. In none of these cases | |
166 | * can we be sure of its previous state. | |
a8bed8b6 AS |
167 | */ |
168 | static void check_and_reset_hc(struct uhci_hcd *uhci) | |
169 | { | |
bb200f6e AS |
170 | if (uhci_check_and_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr)) |
171 | finish_reset(uhci); | |
a8bed8b6 AS |
172 | } |
173 | ||
174 | /* | |
175 | * Store the basic register settings needed by the controller. | |
176 | */ | |
177 | static void configure_hc(struct uhci_hcd *uhci) | |
178 | { | |
0d436b42 AS |
179 | struct pci_dev *pdev = to_pci_dev(uhci_dev(uhci)); |
180 | ||
a8bed8b6 AS |
181 | /* Set the frame length to the default: 1 ms exactly */ |
182 | outb(USBSOF_DEFAULT, uhci->io_addr + USBSOF); | |
183 | ||
184 | /* Store the frame list base address */ | |
a1d59ce8 | 185 | outl(uhci->frame_dma_handle, uhci->io_addr + USBFLBASEADD); |
a8bed8b6 AS |
186 | |
187 | /* Set the current frame number */ | |
c4334726 AS |
188 | outw(uhci->frame_number & UHCI_MAX_SOF_NUMBER, |
189 | uhci->io_addr + USBFRNUM); | |
a8bed8b6 | 190 | |
f37be9b9 AS |
191 | /* Mark controller as not halted before we enable interrupts */ |
192 | uhci_to_hcd(uhci)->state = HC_STATE_SUSPENDED; | |
a8bed8b6 AS |
193 | mb(); |
194 | ||
195 | /* Enable PIRQ */ | |
0d436b42 AS |
196 | pci_write_config_word(pdev, USBLEGSUP, USBLEGSUP_DEFAULT); |
197 | ||
198 | /* Disable platform-specific non-PME# wakeup */ | |
199 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) | |
200 | pci_write_config_byte(pdev, USBRES_INTEL, 0); | |
a8bed8b6 AS |
201 | } |
202 | ||
203 | ||
c8f4fe43 | 204 | static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci) |
1da177e4 | 205 | { |
c8f4fe43 | 206 | int port; |
1da177e4 | 207 | |
5f8364b7 AS |
208 | /* If we have to ignore overcurrent events then almost by definition |
209 | * we can't depend on resume-detect interrupts. */ | |
210 | if (ignore_oc) | |
211 | return 1; | |
212 | ||
c8f4fe43 AS |
213 | switch (to_pci_dev(uhci_dev(uhci))->vendor) { |
214 | default: | |
215 | break; | |
216 | ||
217 | case PCI_VENDOR_ID_GENESYS: | |
218 | /* Genesys Logic's GL880S controllers don't generate | |
219 | * resume-detect interrupts. | |
220 | */ | |
221 | return 1; | |
222 | ||
223 | case PCI_VENDOR_ID_INTEL: | |
224 | /* Some of Intel's USB controllers have a bug that causes | |
225 | * resume-detect interrupts if any port has an over-current | |
226 | * condition. To make matters worse, some motherboards | |
227 | * hardwire unused USB ports' over-current inputs active! | |
228 | * To prevent problems, we will not enable resume-detect | |
229 | * interrupts if any ports are OC. | |
230 | */ | |
231 | for (port = 0; port < uhci->rh_numports; ++port) { | |
232 | if (inw(uhci->io_addr + USBPORTSC1 + port * 2) & | |
233 | USBPORTSC_OC) | |
234 | return 1; | |
235 | } | |
236 | break; | |
237 | } | |
238 | return 0; | |
239 | } | |
240 | ||
d8f12ab5 | 241 | static int global_suspend_mode_is_broken(struct uhci_hcd *uhci) |
b62df451 | 242 | { |
b62df451 | 243 | int port; |
1855256c | 244 | const char *sys_info; |
c80a70d5 | 245 | static char bad_Asus_board[] = "A7V8X"; |
b62df451 AS |
246 | |
247 | /* One of Asus's motherboards has a bug which causes it to | |
248 | * wake up immediately from suspend-to-RAM if any of the ports | |
249 | * are connected. In such cases we will not set EGSM. | |
250 | */ | |
c80a70d5 AS |
251 | sys_info = dmi_get_system_info(DMI_BOARD_NAME); |
252 | if (sys_info && !strcmp(sys_info, bad_Asus_board)) { | |
b62df451 AS |
253 | for (port = 0; port < uhci->rh_numports; ++port) { |
254 | if (inw(uhci->io_addr + USBPORTSC1 + port * 2) & | |
255 | USBPORTSC_CCS) | |
256 | return 1; | |
257 | } | |
258 | } | |
259 | ||
260 | return 0; | |
261 | } | |
262 | ||
a8bed8b6 | 263 | static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state) |
c8f4fe43 AS |
264 | __releases(uhci->lock) |
265 | __acquires(uhci->lock) | |
266 | { | |
267 | int auto_stop; | |
d8f12ab5 | 268 | int int_enable, egsm_enable, wakeup_enable; |
58a97ffe | 269 | struct usb_device *rhdev = uhci_to_hcd(uhci)->self.root_hub; |
c8f4fe43 AS |
270 | |
271 | auto_stop = (new_state == UHCI_RH_AUTO_STOPPED); | |
58a97ffe | 272 | dev_dbg(&rhdev->dev, "%s%s\n", __func__, |
c8f4fe43 AS |
273 | (auto_stop ? " (auto-stop)" : "")); |
274 | ||
d8f12ab5 AS |
275 | /* Start off by assuming Resume-Detect interrupts and EGSM work |
276 | * and that remote wakeups should be enabled. | |
c8f4fe43 | 277 | */ |
b62df451 | 278 | egsm_enable = USBCMD_EGSM; |
d8f12ab5 | 279 | uhci->RD_enable = 1; |
1f09df8b | 280 | int_enable = USBINTR_RESUME; |
d8f12ab5 AS |
281 | wakeup_enable = 1; |
282 | ||
283 | /* In auto-stop mode wakeups must always be detected, but | |
284 | * Resume-Detect interrupts may be prohibited. (In the absence | |
285 | * of CONFIG_PM, they are always disallowed.) | |
286 | */ | |
287 | if (auto_stop) { | |
288 | if (!device_may_wakeup(&rhdev->dev)) | |
289 | int_enable = 0; | |
290 | ||
291 | /* In bus-suspend mode wakeups may be disabled, but if they are | |
292 | * allowed then so are Resume-Detect interrupts. | |
293 | */ | |
294 | } else { | |
58a97ffe | 295 | #ifdef CONFIG_PM |
d8f12ab5 AS |
296 | if (!rhdev->do_remote_wakeup) |
297 | wakeup_enable = 0; | |
58a97ffe | 298 | #endif |
d8f12ab5 AS |
299 | } |
300 | ||
301 | /* EGSM causes the root hub to echo a 'K' signal (resume) out any | |
302 | * port which requests a remote wakeup. According to the USB spec, | |
303 | * every hub is supposed to do this. But if we are ignoring | |
304 | * remote-wakeup requests anyway then there's no point to it. | |
305 | * We also shouldn't enable EGSM if it's broken. | |
306 | */ | |
307 | if (!wakeup_enable || global_suspend_mode_is_broken(uhci)) | |
308 | egsm_enable = 0; | |
309 | ||
310 | /* If we're ignoring wakeup events then there's no reason to | |
311 | * enable Resume-Detect interrupts. We also shouldn't enable | |
312 | * them if they are broken or disallowed. | |
313 | * | |
314 | * This logic may lead us to enabling RD but not EGSM. The UHCI | |
315 | * spec foolishly says that RD works only when EGSM is on, but | |
316 | * there's no harm in enabling it anyway -- perhaps some chips | |
317 | * will implement it! | |
318 | */ | |
319 | if (!wakeup_enable || resume_detect_interrupts_are_broken(uhci) || | |
320 | !int_enable) | |
321 | uhci->RD_enable = int_enable = 0; | |
b62df451 | 322 | |
c8f4fe43 | 323 | outw(int_enable, uhci->io_addr + USBINTR); |
b62df451 | 324 | outw(egsm_enable | USBCMD_CF, uhci->io_addr + USBCMD); |
a8bed8b6 | 325 | mb(); |
c8f4fe43 AS |
326 | udelay(5); |
327 | ||
328 | /* If we're auto-stopping then no devices have been attached | |
329 | * for a while, so there shouldn't be any active URBs and the | |
330 | * controller should stop after a few microseconds. Otherwise | |
331 | * we will give the controller one frame to stop. | |
332 | */ | |
333 | if (!auto_stop && !(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) { | |
334 | uhci->rh_state = UHCI_RH_SUSPENDING; | |
335 | spin_unlock_irq(&uhci->lock); | |
336 | msleep(1); | |
337 | spin_lock_irq(&uhci->lock); | |
e323de46 | 338 | if (uhci->dead) |
4daaa87c | 339 | return; |
c8f4fe43 AS |
340 | } |
341 | if (!(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) | |
58a97ffe | 342 | dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n"); |
1da177e4 | 343 | |
1da177e4 | 344 | uhci_get_current_frame_number(uhci); |
c8f4fe43 AS |
345 | |
346 | uhci->rh_state = new_state; | |
1da177e4 | 347 | uhci->is_stopped = UHCI_IS_STOPPED; |
d8f12ab5 AS |
348 | |
349 | /* If interrupts don't work and remote wakeup is enabled then | |
350 | * the suspended root hub needs to be polled. | |
351 | */ | |
541c7d43 AS |
352 | if (!int_enable && wakeup_enable) |
353 | set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); | |
354 | else | |
355 | clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); | |
1da177e4 | 356 | |
7d12e780 | 357 | uhci_scan_schedule(uhci); |
84afddd7 | 358 | uhci_fsbr_off(uhci); |
1da177e4 LT |
359 | } |
360 | ||
a8bed8b6 AS |
361 | static void start_rh(struct uhci_hcd *uhci) |
362 | { | |
f37be9b9 | 363 | uhci_to_hcd(uhci)->state = HC_STATE_RUNNING; |
a8bed8b6 | 364 | uhci->is_stopped = 0; |
a8bed8b6 AS |
365 | |
366 | /* Mark it configured and running with a 64-byte max packet. | |
367 | * All interrupts are enabled, even though RESUME won't do anything. | |
368 | */ | |
369 | outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, uhci->io_addr + USBCMD); | |
370 | outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP, | |
371 | uhci->io_addr + USBINTR); | |
372 | mb(); | |
6c1b445c | 373 | uhci->rh_state = UHCI_RH_RUNNING; |
541c7d43 | 374 | set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); |
a8bed8b6 AS |
375 | } |
376 | ||
377 | static void wakeup_rh(struct uhci_hcd *uhci) | |
c8f4fe43 AS |
378 | __releases(uhci->lock) |
379 | __acquires(uhci->lock) | |
1da177e4 | 380 | { |
be3cbc5f | 381 | dev_dbg(&uhci_to_hcd(uhci)->self.root_hub->dev, |
441b62c1 | 382 | "%s%s\n", __func__, |
c8f4fe43 AS |
383 | uhci->rh_state == UHCI_RH_AUTO_STOPPED ? |
384 | " (auto-start)" : ""); | |
1da177e4 | 385 | |
c8f4fe43 AS |
386 | /* If we are auto-stopped then no devices are attached so there's |
387 | * no need for wakeup signals. Otherwise we send Global Resume | |
388 | * for 20 ms. | |
389 | */ | |
390 | if (uhci->rh_state == UHCI_RH_SUSPENDED) { | |
d8f12ab5 AS |
391 | unsigned egsm; |
392 | ||
393 | /* Keep EGSM on if it was set before */ | |
394 | egsm = inw(uhci->io_addr + USBCMD) & USBCMD_EGSM; | |
c8f4fe43 | 395 | uhci->rh_state = UHCI_RH_RESUMING; |
d8f12ab5 | 396 | outw(USBCMD_FGR | USBCMD_CF | egsm, uhci->io_addr + USBCMD); |
c8f4fe43 AS |
397 | spin_unlock_irq(&uhci->lock); |
398 | msleep(20); | |
399 | spin_lock_irq(&uhci->lock); | |
e323de46 | 400 | if (uhci->dead) |
4daaa87c | 401 | return; |
1da177e4 | 402 | |
c8f4fe43 AS |
403 | /* End Global Resume and wait for EOP to be sent */ |
404 | outw(USBCMD_CF, uhci->io_addr + USBCMD); | |
a8bed8b6 | 405 | mb(); |
c8f4fe43 AS |
406 | udelay(4); |
407 | if (inw(uhci->io_addr + USBCMD) & USBCMD_FGR) | |
408 | dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n"); | |
409 | } | |
1da177e4 | 410 | |
a8bed8b6 | 411 | start_rh(uhci); |
c8f4fe43 | 412 | |
6c1b445c AS |
413 | /* Restart root hub polling */ |
414 | mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies); | |
1da177e4 LT |
415 | } |
416 | ||
7d12e780 | 417 | static irqreturn_t uhci_irq(struct usb_hcd *hcd) |
014e73c9 AS |
418 | { |
419 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
014e73c9 | 420 | unsigned short status; |
1da177e4 LT |
421 | |
422 | /* | |
014e73c9 AS |
423 | * Read the interrupt status, and write it back to clear the |
424 | * interrupt cause. Contrary to the UHCI specification, the | |
425 | * "HC Halted" status bit is persistent: it is RO, not R/WC. | |
1da177e4 | 426 | */ |
a8bed8b6 | 427 | status = inw(uhci->io_addr + USBSTS); |
014e73c9 AS |
428 | if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */ |
429 | return IRQ_NONE; | |
a8bed8b6 | 430 | outw(status, uhci->io_addr + USBSTS); /* Clear it */ |
014e73c9 AS |
431 | |
432 | if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) { | |
433 | if (status & USBSTS_HSE) | |
434 | dev_err(uhci_dev(uhci), "host system error, " | |
435 | "PCI problems?\n"); | |
436 | if (status & USBSTS_HCPE) | |
437 | dev_err(uhci_dev(uhci), "host controller process " | |
438 | "error, something bad happened!\n"); | |
4daaa87c | 439 | if (status & USBSTS_HCH) { |
442258e2 | 440 | spin_lock(&uhci->lock); |
4daaa87c AS |
441 | if (uhci->rh_state >= UHCI_RH_RUNNING) { |
442 | dev_err(uhci_dev(uhci), | |
443 | "host controller halted, " | |
014e73c9 | 444 | "very bad!\n"); |
8d402e1a AS |
445 | if (debug > 1 && errbuf) { |
446 | /* Print the schedule for debugging */ | |
447 | uhci_sprint_schedule(uhci, | |
448 | errbuf, ERRBUF_LEN); | |
449 | lprintk(errbuf); | |
450 | } | |
e323de46 | 451 | uhci_hc_died(uhci); |
1f09df8b AS |
452 | |
453 | /* Force a callback in case there are | |
454 | * pending unlinks */ | |
455 | mod_timer(&hcd->rh_timer, jiffies); | |
4daaa87c | 456 | } |
442258e2 | 457 | spin_unlock(&uhci->lock); |
1da177e4 | 458 | } |
1da177e4 LT |
459 | } |
460 | ||
014e73c9 | 461 | if (status & USBSTS_RD) |
6c1b445c | 462 | usb_hcd_poll_rh_status(hcd); |
1f09df8b | 463 | else { |
442258e2 | 464 | spin_lock(&uhci->lock); |
7d12e780 | 465 | uhci_scan_schedule(uhci); |
442258e2 | 466 | spin_unlock(&uhci->lock); |
1f09df8b | 467 | } |
1da177e4 | 468 | |
014e73c9 AS |
469 | return IRQ_HANDLED; |
470 | } | |
1da177e4 | 471 | |
014e73c9 AS |
472 | /* |
473 | * Store the current frame number in uhci->frame_number if the controller | |
ae0e47f0 | 474 | * is running. Expand from 11 bits (of which we use only 10) to a |
c4334726 AS |
475 | * full-sized integer. |
476 | * | |
477 | * Like many other parts of the driver, this code relies on being polled | |
478 | * more than once per second as long as the controller is running. | |
014e73c9 AS |
479 | */ |
480 | static void uhci_get_current_frame_number(struct uhci_hcd *uhci) | |
481 | { | |
c4334726 AS |
482 | if (!uhci->is_stopped) { |
483 | unsigned delta; | |
484 | ||
485 | delta = (inw(uhci->io_addr + USBFRNUM) - uhci->frame_number) & | |
486 | (UHCI_NUMFRAMES - 1); | |
487 | uhci->frame_number += delta; | |
488 | } | |
1da177e4 LT |
489 | } |
490 | ||
491 | /* | |
492 | * De-allocate all resources | |
493 | */ | |
494 | static void release_uhci(struct uhci_hcd *uhci) | |
495 | { | |
496 | int i; | |
497 | ||
8d402e1a AS |
498 | if (DEBUG_CONFIGURED) { |
499 | spin_lock_irq(&uhci->lock); | |
500 | uhci->is_initialized = 0; | |
501 | spin_unlock_irq(&uhci->lock); | |
502 | ||
503 | debugfs_remove(uhci->dentry); | |
504 | } | |
505 | ||
1da177e4 | 506 | for (i = 0; i < UHCI_NUM_SKELQH; i++) |
8b4cd421 | 507 | uhci_free_qh(uhci, uhci->skelqh[i]); |
1da177e4 | 508 | |
8b4cd421 | 509 | uhci_free_td(uhci, uhci->term_td); |
1da177e4 | 510 | |
8b4cd421 | 511 | dma_pool_destroy(uhci->qh_pool); |
1da177e4 | 512 | |
8b4cd421 | 513 | dma_pool_destroy(uhci->td_pool); |
1da177e4 | 514 | |
a1d59ce8 AS |
515 | kfree(uhci->frame_cpu); |
516 | ||
517 | dma_free_coherent(uhci_dev(uhci), | |
518 | UHCI_NUMFRAMES * sizeof(*uhci->frame), | |
519 | uhci->frame, uhci->frame_dma_handle); | |
1da177e4 LT |
520 | } |
521 | ||
be3cbc5f | 522 | static int uhci_init(struct usb_hcd *hcd) |
1da177e4 LT |
523 | { |
524 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
c074b416 AS |
525 | unsigned io_size = (unsigned) hcd->rsrc_len; |
526 | int port; | |
1da177e4 LT |
527 | |
528 | uhci->io_addr = (unsigned long) hcd->rsrc_start; | |
529 | ||
c074b416 AS |
530 | /* The UHCI spec says devices must have 2 ports, and goes on to say |
531 | * they may have more but gives no way to determine how many there | |
e07fefa6 | 532 | * are. However according to the UHCI spec, Bit 7 of the port |
c074b416 | 533 | * status and control register is always set to 1. So we try to |
e07fefa6 AS |
534 | * use this to our advantage. Another common failure mode when |
535 | * a nonexistent register is addressed is to return all ones, so | |
536 | * we test for that also. | |
c074b416 AS |
537 | */ |
538 | for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) { | |
539 | unsigned int portstatus; | |
540 | ||
541 | portstatus = inw(uhci->io_addr + USBPORTSC1 + (port * 2)); | |
e07fefa6 | 542 | if (!(portstatus & 0x0080) || portstatus == 0xffff) |
c074b416 AS |
543 | break; |
544 | } | |
545 | if (debug) | |
546 | dev_info(uhci_dev(uhci), "detected %d ports\n", port); | |
547 | ||
e07fefa6 AS |
548 | /* Anything greater than 7 is weird so we'll ignore it. */ |
549 | if (port > UHCI_RH_MAXCHILD) { | |
c074b416 AS |
550 | dev_info(uhci_dev(uhci), "port count misdetected? " |
551 | "forcing to 2 ports\n"); | |
552 | port = 2; | |
553 | } | |
554 | uhci->rh_numports = port; | |
555 | ||
a8bed8b6 AS |
556 | /* Kick BIOS off this hardware and reset if the controller |
557 | * isn't already safely quiescent. | |
1da177e4 | 558 | */ |
a8bed8b6 | 559 | check_and_reset_hc(uhci); |
1da177e4 LT |
560 | return 0; |
561 | } | |
562 | ||
02597d2d AS |
563 | /* Make sure the controller is quiescent and that we're not using it |
564 | * any more. This is mainly for the benefit of programs which, like kexec, | |
565 | * expect the hardware to be idle: not doing DMA or generating IRQs. | |
566 | * | |
567 | * This routine may be called in a damaged or failing kernel. Hence we | |
568 | * do not acquire the spinlock before shutting down the controller. | |
569 | */ | |
570 | static void uhci_shutdown(struct pci_dev *pdev) | |
571 | { | |
ce7eb32f | 572 | struct usb_hcd *hcd = pci_get_drvdata(pdev); |
02597d2d | 573 | |
e323de46 | 574 | uhci_hc_died(hcd_to_uhci(hcd)); |
02597d2d AS |
575 | } |
576 | ||
1da177e4 LT |
577 | /* |
578 | * Allocate a frame list, and then setup the skeleton | |
579 | * | |
580 | * The hardware doesn't really know any difference | |
581 | * in the queues, but the order does matter for the | |
17230acd AS |
582 | * protocols higher up. The order in which the queues |
583 | * are encountered by the hardware is: | |
1da177e4 | 584 | * |
17230acd | 585 | * - All isochronous events are handled before any |
1da177e4 LT |
586 | * of the queues. We don't do that here, because |
587 | * we'll create the actual TD entries on demand. | |
17230acd AS |
588 | * - The first queue is the high-period interrupt queue. |
589 | * - The second queue is the period-1 interrupt and async | |
590 | * (low-speed control, full-speed control, then bulk) queue. | |
591 | * - The third queue is the terminating bandwidth reclamation queue, | |
592 | * which contains no members, loops back to itself, and is present | |
593 | * only when FSBR is on and there are no full-speed control or bulk QHs. | |
1da177e4 LT |
594 | */ |
595 | static int uhci_start(struct usb_hcd *hcd) | |
596 | { | |
597 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
598 | int retval = -EBUSY; | |
c074b416 | 599 | int i; |
b409214c | 600 | struct dentry __maybe_unused *dentry; |
1da177e4 | 601 | |
6c1b445c | 602 | hcd->uses_new_polling = 1; |
1da177e4 | 603 | |
1da177e4 | 604 | spin_lock_init(&uhci->lock); |
c5e3b741 AS |
605 | setup_timer(&uhci->fsbr_timer, uhci_fsbr_timeout, |
606 | (unsigned long) uhci); | |
dccf4a48 | 607 | INIT_LIST_HEAD(&uhci->idle_qh_list); |
1da177e4 LT |
608 | init_waitqueue_head(&uhci->waitqh); |
609 | ||
b409214c AS |
610 | #ifdef UHCI_DEBUG_OPS |
611 | dentry = debugfs_create_file(hcd->self.bus_name, | |
612 | S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root, | |
613 | uhci, &uhci_debug_operations); | |
614 | if (!dentry) { | |
615 | dev_err(uhci_dev(uhci), "couldn't create uhci debugfs entry\n"); | |
616 | return -ENOMEM; | |
8d402e1a | 617 | } |
b409214c AS |
618 | uhci->dentry = dentry; |
619 | #endif | |
8d402e1a | 620 | |
a1d59ce8 AS |
621 | uhci->frame = dma_alloc_coherent(uhci_dev(uhci), |
622 | UHCI_NUMFRAMES * sizeof(*uhci->frame), | |
623 | &uhci->frame_dma_handle, 0); | |
624 | if (!uhci->frame) { | |
1da177e4 LT |
625 | dev_err(uhci_dev(uhci), "unable to allocate " |
626 | "consistent memory for frame list\n"); | |
a1d59ce8 | 627 | goto err_alloc_frame; |
1da177e4 | 628 | } |
a1d59ce8 | 629 | memset(uhci->frame, 0, UHCI_NUMFRAMES * sizeof(*uhci->frame)); |
1da177e4 | 630 | |
a1d59ce8 AS |
631 | uhci->frame_cpu = kcalloc(UHCI_NUMFRAMES, sizeof(*uhci->frame_cpu), |
632 | GFP_KERNEL); | |
633 | if (!uhci->frame_cpu) { | |
634 | dev_err(uhci_dev(uhci), "unable to allocate " | |
635 | "memory for frame pointers\n"); | |
636 | goto err_alloc_frame_cpu; | |
637 | } | |
1da177e4 LT |
638 | |
639 | uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci), | |
640 | sizeof(struct uhci_td), 16, 0); | |
641 | if (!uhci->td_pool) { | |
642 | dev_err(uhci_dev(uhci), "unable to create td dma_pool\n"); | |
643 | goto err_create_td_pool; | |
644 | } | |
645 | ||
646 | uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci), | |
647 | sizeof(struct uhci_qh), 16, 0); | |
648 | if (!uhci->qh_pool) { | |
649 | dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n"); | |
650 | goto err_create_qh_pool; | |
651 | } | |
652 | ||
2532178a | 653 | uhci->term_td = uhci_alloc_td(uhci); |
1da177e4 LT |
654 | if (!uhci->term_td) { |
655 | dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n"); | |
656 | goto err_alloc_term_td; | |
657 | } | |
658 | ||
659 | for (i = 0; i < UHCI_NUM_SKELQH; i++) { | |
dccf4a48 | 660 | uhci->skelqh[i] = uhci_alloc_qh(uhci, NULL, NULL); |
1da177e4 LT |
661 | if (!uhci->skelqh[i]) { |
662 | dev_err(uhci_dev(uhci), "unable to allocate QH\n"); | |
663 | goto err_alloc_skelqh; | |
664 | } | |
665 | } | |
666 | ||
667 | /* | |
17230acd | 668 | * 8 Interrupt queues; link all higher int queues to int1 = async |
1da177e4 | 669 | */ |
17230acd AS |
670 | for (i = SKEL_ISO + 1; i < SKEL_ASYNC; ++i) |
671 | uhci->skelqh[i]->link = LINK_TO_QH(uhci->skel_async_qh); | |
e009f1b2 AS |
672 | uhci->skel_async_qh->link = UHCI_PTR_TERM; |
673 | uhci->skel_term_qh->link = LINK_TO_QH(uhci->skel_term_qh); | |
1da177e4 LT |
674 | |
675 | /* This dummy TD is to work around a bug in Intel PIIX controllers */ | |
fa346568 | 676 | uhci_fill_td(uhci->term_td, 0, uhci_explen(0) | |
17230acd AS |
677 | (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0); |
678 | uhci->term_td->link = UHCI_PTR_TERM; | |
679 | uhci->skel_async_qh->element = uhci->skel_term_qh->element = | |
680 | LINK_TO_TD(uhci->term_td); | |
1da177e4 LT |
681 | |
682 | /* | |
683 | * Fill the frame list: make all entries point to the proper | |
684 | * interrupt queue. | |
1da177e4 LT |
685 | */ |
686 | for (i = 0; i < UHCI_NUMFRAMES; i++) { | |
1da177e4 LT |
687 | |
688 | /* Only place we don't use the frame list routines */ | |
f3fe239b | 689 | uhci->frame[i] = uhci_frame_skel_link(uhci, i); |
1da177e4 LT |
690 | } |
691 | ||
692 | /* | |
693 | * Some architectures require a full mb() to enforce completion of | |
a8bed8b6 | 694 | * the memory writes above before the I/O transfers in configure_hc(). |
1da177e4 LT |
695 | */ |
696 | mb(); | |
a8bed8b6 AS |
697 | |
698 | configure_hc(uhci); | |
8d402e1a | 699 | uhci->is_initialized = 1; |
ba297edd | 700 | spin_lock_irq(&uhci->lock); |
a8bed8b6 | 701 | start_rh(uhci); |
ba297edd | 702 | spin_unlock_irq(&uhci->lock); |
1da177e4 LT |
703 | return 0; |
704 | ||
705 | /* | |
706 | * error exits: | |
707 | */ | |
1da177e4 | 708 | err_alloc_skelqh: |
8b4cd421 AS |
709 | for (i = 0; i < UHCI_NUM_SKELQH; i++) { |
710 | if (uhci->skelqh[i]) | |
1da177e4 | 711 | uhci_free_qh(uhci, uhci->skelqh[i]); |
8b4cd421 | 712 | } |
1da177e4 LT |
713 | |
714 | uhci_free_td(uhci, uhci->term_td); | |
1da177e4 LT |
715 | |
716 | err_alloc_term_td: | |
1da177e4 | 717 | dma_pool_destroy(uhci->qh_pool); |
1da177e4 LT |
718 | |
719 | err_create_qh_pool: | |
720 | dma_pool_destroy(uhci->td_pool); | |
1da177e4 LT |
721 | |
722 | err_create_td_pool: | |
a1d59ce8 AS |
723 | kfree(uhci->frame_cpu); |
724 | ||
725 | err_alloc_frame_cpu: | |
726 | dma_free_coherent(uhci_dev(uhci), | |
727 | UHCI_NUMFRAMES * sizeof(*uhci->frame), | |
728 | uhci->frame, uhci->frame_dma_handle); | |
1da177e4 | 729 | |
a1d59ce8 | 730 | err_alloc_frame: |
1da177e4 | 731 | debugfs_remove(uhci->dentry); |
1da177e4 | 732 | |
1da177e4 LT |
733 | return retval; |
734 | } | |
735 | ||
736 | static void uhci_stop(struct usb_hcd *hcd) | |
737 | { | |
738 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
739 | ||
1da177e4 | 740 | spin_lock_irq(&uhci->lock); |
541c7d43 | 741 | if (HCD_HW_ACCESSIBLE(hcd) && !uhci->dead) |
e323de46 | 742 | uhci_hc_died(uhci); |
7d12e780 | 743 | uhci_scan_schedule(uhci); |
1da177e4 | 744 | spin_unlock_irq(&uhci->lock); |
d23356da | 745 | synchronize_irq(hcd->irq); |
6c1b445c | 746 | |
c5e3b741 | 747 | del_timer_sync(&uhci->fsbr_timer); |
1da177e4 LT |
748 | release_uhci(uhci); |
749 | } | |
750 | ||
751 | #ifdef CONFIG_PM | |
a8bed8b6 AS |
752 | static int uhci_rh_suspend(struct usb_hcd *hcd) |
753 | { | |
754 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
be3cbc5f | 755 | int rc = 0; |
a8bed8b6 AS |
756 | |
757 | spin_lock_irq(&uhci->lock); | |
541c7d43 | 758 | if (!HCD_HW_ACCESSIBLE(hcd)) |
be3cbc5f | 759 | rc = -ESHUTDOWN; |
cec3a53c AS |
760 | else if (uhci->dead) |
761 | ; /* Dead controllers tell no tales */ | |
762 | ||
763 | /* Once the controller is stopped, port resumes that are already | |
764 | * in progress won't complete. Hence if remote wakeup is enabled | |
765 | * for the root hub and any ports are in the middle of a resume or | |
766 | * remote wakeup, we must fail the suspend. | |
767 | */ | |
768 | else if (hcd->self.root_hub->do_remote_wakeup && | |
769 | uhci->resuming_ports) { | |
770 | dev_dbg(uhci_dev(uhci), "suspend failed because a port " | |
771 | "is resuming\n"); | |
772 | rc = -EBUSY; | |
773 | } else | |
4daaa87c | 774 | suspend_rh(uhci, UHCI_RH_SUSPENDED); |
a8bed8b6 | 775 | spin_unlock_irq(&uhci->lock); |
be3cbc5f | 776 | return rc; |
a8bed8b6 AS |
777 | } |
778 | ||
779 | static int uhci_rh_resume(struct usb_hcd *hcd) | |
780 | { | |
781 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
4daaa87c | 782 | int rc = 0; |
a8bed8b6 AS |
783 | |
784 | spin_lock_irq(&uhci->lock); | |
541c7d43 | 785 | if (!HCD_HW_ACCESSIBLE(hcd)) |
be3cbc5f | 786 | rc = -ESHUTDOWN; |
cfa59dab | 787 | else if (!uhci->dead) |
4daaa87c | 788 | wakeup_rh(uhci); |
a8bed8b6 | 789 | spin_unlock_irq(&uhci->lock); |
4daaa87c | 790 | return rc; |
a8bed8b6 AS |
791 | } |
792 | ||
4147200d | 793 | static int uhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) |
1da177e4 LT |
794 | { |
795 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
0d436b42 | 796 | struct pci_dev *pdev = to_pci_dev(uhci_dev(uhci)); |
4daaa87c | 797 | int rc = 0; |
1da177e4 | 798 | |
441b62c1 | 799 | dev_dbg(uhci_dev(uhci), "%s\n", __func__); |
a8bed8b6 | 800 | |
1da177e4 | 801 | spin_lock_irq(&uhci->lock); |
541c7d43 | 802 | if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead) |
e323de46 | 803 | goto done_okay; /* Already suspended or dead */ |
a8bed8b6 | 804 | |
4daaa87c AS |
805 | if (uhci->rh_state > UHCI_RH_SUSPENDED) { |
806 | dev_warn(uhci_dev(uhci), "Root hub isn't suspended!\n"); | |
4daaa87c AS |
807 | rc = -EBUSY; |
808 | goto done; | |
809 | }; | |
810 | ||
a8bed8b6 AS |
811 | /* All PCI host controllers are required to disable IRQ generation |
812 | * at the source, so we must turn off PIRQ. | |
813 | */ | |
0d436b42 | 814 | pci_write_config_word(pdev, USBLEGSUP, 0); |
541c7d43 | 815 | clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
a8bed8b6 | 816 | |
0d436b42 AS |
817 | /* Enable platform-specific non-PME# wakeup */ |
818 | if (do_wakeup) { | |
819 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) | |
820 | pci_write_config_byte(pdev, USBRES_INTEL, | |
821 | USBPORT1EN | USBPORT2EN); | |
822 | } | |
a8bed8b6 | 823 | |
e323de46 AS |
824 | done_okay: |
825 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
4daaa87c | 826 | done: |
1da177e4 | 827 | spin_unlock_irq(&uhci->lock); |
4daaa87c | 828 | return rc; |
1da177e4 LT |
829 | } |
830 | ||
6ec4beb5 | 831 | static int uhci_pci_resume(struct usb_hcd *hcd, bool hibernated) |
1da177e4 LT |
832 | { |
833 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
1da177e4 | 834 | |
441b62c1 | 835 | dev_dbg(uhci_dev(uhci), "%s\n", __func__); |
a8bed8b6 | 836 | |
687f5f34 | 837 | /* Since we aren't in D3 any more, it's safe to set this flag |
e323de46 | 838 | * even if the controller was dead. |
8de98402 BH |
839 | */ |
840 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
841 | ||
1da177e4 | 842 | spin_lock_irq(&uhci->lock); |
1da177e4 | 843 | |
6ec4beb5 AS |
844 | /* Make sure resume from hibernation re-enumerates everything */ |
845 | if (hibernated) | |
846 | uhci_hc_died(uhci); | |
847 | ||
e323de46 AS |
848 | /* The firmware or a boot kernel may have changed the controller |
849 | * settings during a system wakeup. Check it and reconfigure | |
850 | * to avoid problems. | |
a8bed8b6 AS |
851 | */ |
852 | check_and_reset_hc(uhci); | |
e323de46 AS |
853 | |
854 | /* If the controller was dead before, it's back alive now */ | |
a8bed8b6 AS |
855 | configure_hc(uhci); |
856 | ||
0d436b42 AS |
857 | /* Tell the core if the controller had to be reset */ |
858 | if (uhci->rh_state == UHCI_RH_RESET) | |
1c50c317 | 859 | usb_root_hub_lost_power(hcd->self.root_hub); |
c8f4fe43 | 860 | |
a8bed8b6 | 861 | spin_unlock_irq(&uhci->lock); |
6c1b445c | 862 | |
d8f12ab5 AS |
863 | /* If interrupts don't work and remote wakeup is enabled then |
864 | * the suspended root hub needs to be polled. | |
865 | */ | |
ee0b9be8 | 866 | if (!uhci->RD_enable && hcd->self.root_hub->do_remote_wakeup) |
541c7d43 | 867 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
ee0b9be8 AS |
868 | |
869 | /* Does the root hub have a port wakeup pending? */ | |
870 | usb_hcd_poll_rh_status(hcd); | |
1da177e4 LT |
871 | return 0; |
872 | } | |
873 | #endif | |
874 | ||
dccf4a48 | 875 | /* Wait until a particular device/endpoint's QH is idle, and free it */ |
1da177e4 | 876 | static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd, |
dccf4a48 | 877 | struct usb_host_endpoint *hep) |
1da177e4 LT |
878 | { |
879 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
dccf4a48 AS |
880 | struct uhci_qh *qh; |
881 | ||
882 | spin_lock_irq(&uhci->lock); | |
883 | qh = (struct uhci_qh *) hep->hcpriv; | |
884 | if (qh == NULL) | |
885 | goto done; | |
1da177e4 | 886 | |
dccf4a48 AS |
887 | while (qh->state != QH_STATE_IDLE) { |
888 | ++uhci->num_waiting; | |
889 | spin_unlock_irq(&uhci->lock); | |
890 | wait_event_interruptible(uhci->waitqh, | |
891 | qh->state == QH_STATE_IDLE); | |
892 | spin_lock_irq(&uhci->lock); | |
893 | --uhci->num_waiting; | |
894 | } | |
895 | ||
896 | uhci_free_qh(uhci, qh); | |
897 | done: | |
898 | spin_unlock_irq(&uhci->lock); | |
1da177e4 LT |
899 | } |
900 | ||
901 | static int uhci_hcd_get_frame_number(struct usb_hcd *hcd) | |
902 | { | |
903 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
c4334726 AS |
904 | unsigned frame_number; |
905 | unsigned delta; | |
1da177e4 LT |
906 | |
907 | /* Minimize latency by avoiding the spinlock */ | |
c4334726 AS |
908 | frame_number = uhci->frame_number; |
909 | barrier(); | |
910 | delta = (inw(uhci->io_addr + USBFRNUM) - frame_number) & | |
911 | (UHCI_NUMFRAMES - 1); | |
912 | return frame_number + delta; | |
1da177e4 LT |
913 | } |
914 | ||
915 | static const char hcd_name[] = "uhci_hcd"; | |
916 | ||
917 | static const struct hc_driver uhci_driver = { | |
918 | .description = hcd_name, | |
919 | .product_desc = "UHCI Host Controller", | |
920 | .hcd_priv_size = sizeof(struct uhci_hcd), | |
921 | ||
922 | /* Generic hardware linkage */ | |
923 | .irq = uhci_irq, | |
924 | .flags = HCD_USB11, | |
925 | ||
926 | /* Basic lifecycle operations */ | |
be3cbc5f | 927 | .reset = uhci_init, |
1da177e4 LT |
928 | .start = uhci_start, |
929 | #ifdef CONFIG_PM | |
7be7d741 AS |
930 | .pci_suspend = uhci_pci_suspend, |
931 | .pci_resume = uhci_pci_resume, | |
0c0382e3 AS |
932 | .bus_suspend = uhci_rh_suspend, |
933 | .bus_resume = uhci_rh_resume, | |
1da177e4 LT |
934 | #endif |
935 | .stop = uhci_stop, | |
936 | ||
937 | .urb_enqueue = uhci_urb_enqueue, | |
938 | .urb_dequeue = uhci_urb_dequeue, | |
939 | ||
940 | .endpoint_disable = uhci_hcd_endpoint_disable, | |
941 | .get_frame_number = uhci_hcd_get_frame_number, | |
942 | ||
943 | .hub_status_data = uhci_hub_status_data, | |
944 | .hub_control = uhci_hub_control, | |
945 | }; | |
946 | ||
947 | static const struct pci_device_id uhci_pci_ids[] = { { | |
948 | /* handle any USB UHCI controller */ | |
c67808ee | 949 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_UHCI, ~0), |
1da177e4 LT |
950 | .driver_data = (unsigned long) &uhci_driver, |
951 | }, { /* end: all zeroes */ } | |
952 | }; | |
953 | ||
954 | MODULE_DEVICE_TABLE(pci, uhci_pci_ids); | |
955 | ||
956 | static struct pci_driver uhci_pci_driver = { | |
957 | .name = (char *)hcd_name, | |
958 | .id_table = uhci_pci_ids, | |
959 | ||
960 | .probe = usb_hcd_pci_probe, | |
961 | .remove = usb_hcd_pci_remove, | |
02597d2d | 962 | .shutdown = uhci_shutdown, |
1da177e4 | 963 | |
abb30641 AS |
964 | #ifdef CONFIG_PM_SLEEP |
965 | .driver = { | |
966 | .pm = &usb_hcd_pci_pm_ops | |
967 | }, | |
968 | #endif | |
1da177e4 LT |
969 | }; |
970 | ||
971 | static int __init uhci_hcd_init(void) | |
972 | { | |
973 | int retval = -ENOMEM; | |
974 | ||
1da177e4 LT |
975 | if (usb_disabled()) |
976 | return -ENODEV; | |
977 | ||
2b70f073 AS |
978 | printk(KERN_INFO "uhci_hcd: " DRIVER_DESC "%s\n", |
979 | ignore_oc ? ", overcurrent ignored" : ""); | |
9beeee65 | 980 | set_bit(USB_UHCI_LOADED, &usb_hcds_loaded); |
2b70f073 | 981 | |
8d402e1a | 982 | if (DEBUG_CONFIGURED) { |
1da177e4 LT |
983 | errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL); |
984 | if (!errbuf) | |
985 | goto errbuf_failed; | |
ec20df2e | 986 | uhci_debugfs_root = debugfs_create_dir("uhci", usb_debug_root); |
8d402e1a AS |
987 | if (!uhci_debugfs_root) |
988 | goto debug_failed; | |
1da177e4 LT |
989 | } |
990 | ||
1da177e4 | 991 | uhci_up_cachep = kmem_cache_create("uhci_urb_priv", |
20c2df83 | 992 | sizeof(struct urb_priv), 0, 0, NULL); |
1da177e4 LT |
993 | if (!uhci_up_cachep) |
994 | goto up_failed; | |
995 | ||
996 | retval = pci_register_driver(&uhci_pci_driver); | |
997 | if (retval) | |
998 | goto init_failed; | |
999 | ||
1000 | return 0; | |
1001 | ||
1002 | init_failed: | |
1a1d92c1 | 1003 | kmem_cache_destroy(uhci_up_cachep); |
1da177e4 LT |
1004 | |
1005 | up_failed: | |
1006 | debugfs_remove(uhci_debugfs_root); | |
1007 | ||
1008 | debug_failed: | |
1bc3c9e1 | 1009 | kfree(errbuf); |
1da177e4 LT |
1010 | |
1011 | errbuf_failed: | |
1012 | ||
9beeee65 | 1013 | clear_bit(USB_UHCI_LOADED, &usb_hcds_loaded); |
1da177e4 LT |
1014 | return retval; |
1015 | } | |
1016 | ||
1017 | static void __exit uhci_hcd_cleanup(void) | |
1018 | { | |
1019 | pci_unregister_driver(&uhci_pci_driver); | |
1a1d92c1 | 1020 | kmem_cache_destroy(uhci_up_cachep); |
1da177e4 | 1021 | debugfs_remove(uhci_debugfs_root); |
1bc3c9e1 | 1022 | kfree(errbuf); |
9beeee65 | 1023 | clear_bit(USB_UHCI_LOADED, &usb_hcds_loaded); |
1da177e4 LT |
1024 | } |
1025 | ||
1026 | module_init(uhci_hcd_init); | |
1027 | module_exit(uhci_hcd_cleanup); | |
1028 | ||
1029 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
1030 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1031 | MODULE_LICENSE("GPL"); |