[PATCH] Additional device ID for Conexant AccessRunner USB driver
[deliverable/linux.git] / drivers / usb / host / uhci-hcd.c
CommitLineData
1da177e4
LT
1/*
2 * Universal Host Controller Interface driver for USB.
3 *
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
5 *
6 * (C) Copyright 1999 Linus Torvalds
7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
8 * (C) Copyright 1999 Randy Dunlap
9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
12 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
13 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
14 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
15 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
4daaa87c 16 * (C) Copyright 2004-2005 Alan Stern, stern@rowland.harvard.edu
1da177e4
LT
17 *
18 * Intel documents this fairly well, and as far as I know there
19 * are no royalties or anything like that, but even so there are
20 * people who decided that they want to do the same thing in a
21 * completely different way.
22 *
1da177e4
LT
23 */
24
25#include <linux/config.h>
26#ifdef CONFIG_USB_DEBUG
27#define DEBUG
28#else
29#undef DEBUG
30#endif
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/kernel.h>
34#include <linux/init.h>
35#include <linux/delay.h>
36#include <linux/ioport.h>
37#include <linux/sched.h>
38#include <linux/slab.h>
39#include <linux/smp_lock.h>
40#include <linux/errno.h>
41#include <linux/unistd.h>
42#include <linux/interrupt.h>
43#include <linux/spinlock.h>
44#include <linux/debugfs.h>
45#include <linux/pm.h>
46#include <linux/dmapool.h>
47#include <linux/dma-mapping.h>
48#include <linux/usb.h>
49#include <linux/bitops.h>
50
51#include <asm/uaccess.h>
52#include <asm/io.h>
53#include <asm/irq.h>
54#include <asm/system.h>
55
56#include "../core/hcd.h"
57#include "uhci-hcd.h"
58
59/*
60 * Version Information
61 */
c8f4fe43 62#define DRIVER_VERSION "v2.3"
1da177e4
LT
63#define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \
64Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \
65Alan Stern"
66#define DRIVER_DESC "USB Universal Host Controller Interface driver"
67
68/*
69 * debug = 0, no debugging messages
70 * debug = 1, dump failed URB's except for stalls
71 * debug = 2, dump all failed URB's (including stalls)
72 * show all queues in /debug/uhci/[pci_addr]
73 * debug = 3, show all TD's in URB's when dumping
74 */
75#ifdef DEBUG
76static int debug = 1;
77#else
78static int debug = 0;
79#endif
80module_param(debug, int, S_IRUGO | S_IWUSR);
81MODULE_PARM_DESC(debug, "Debug level");
82static char *errbuf;
83#define ERRBUF_LEN (32 * 1024)
84
85static kmem_cache_t *uhci_up_cachep; /* urb_priv */
86
6c1b445c
AS
87static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state);
88static void wakeup_rh(struct uhci_hcd *uhci);
1da177e4 89static void uhci_get_current_frame_number(struct uhci_hcd *uhci);
1da177e4
LT
90
91/* If a transfer is still active after this much time, turn off FSBR */
92#define IDLE_TIMEOUT msecs_to_jiffies(50)
93#define FSBR_DELAY msecs_to_jiffies(50)
94
95/* When we timeout an idle transfer for FSBR, we'll switch it over to */
96/* depth first traversal. We'll do it in groups of this number of TD's */
97/* to make sure it doesn't hog all of the bandwidth */
98#define DEPTH_INTERVAL 5
99
1da177e4
LT
100#include "uhci-debug.c"
101#include "uhci-q.c"
1f09df8b 102#include "uhci-hub.c"
1da177e4 103
bb200f6e
AS
104extern void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);
105extern int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);
106
a8bed8b6 107/*
bb200f6e 108 * Finish up a host controller reset and update the recorded state.
a8bed8b6 109 */
bb200f6e 110static void finish_reset(struct uhci_hcd *uhci)
1da177e4 111{
c074b416
AS
112 int port;
113
c074b416
AS
114 /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect
115 * bits in the port status and control registers.
116 * We have to clear them by hand.
117 */
118 for (port = 0; port < uhci->rh_numports; ++port)
119 outw(0, uhci->io_addr + USBPORTSC1 + (port * 2));
120
a8bed8b6
AS
121 uhci->port_c_suspend = uhci->suspended_ports =
122 uhci->resuming_ports = 0;
c8f4fe43 123 uhci->rh_state = UHCI_RH_RESET;
a8bed8b6
AS
124 uhci->is_stopped = UHCI_IS_STOPPED;
125 uhci_to_hcd(uhci)->state = HC_STATE_HALT;
6c1b445c 126 uhci_to_hcd(uhci)->poll_rh = 0;
1da177e4
LT
127}
128
4daaa87c
AS
129/*
130 * Last rites for a defunct/nonfunctional controller
02597d2d 131 * or one we don't want to use any more.
4daaa87c
AS
132 */
133static void hc_died(struct uhci_hcd *uhci)
134{
bb200f6e
AS
135 uhci_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr);
136 finish_reset(uhci);
4daaa87c
AS
137 uhci->hc_inaccessible = 1;
138}
139
a8bed8b6
AS
140/*
141 * Initialize a controller that was newly discovered or has just been
142 * resumed. In either case we can't be sure of its previous state.
143 */
144static void check_and_reset_hc(struct uhci_hcd *uhci)
145{
bb200f6e
AS
146 if (uhci_check_and_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr))
147 finish_reset(uhci);
a8bed8b6
AS
148}
149
150/*
151 * Store the basic register settings needed by the controller.
152 */
153static void configure_hc(struct uhci_hcd *uhci)
154{
155 /* Set the frame length to the default: 1 ms exactly */
156 outb(USBSOF_DEFAULT, uhci->io_addr + USBSOF);
157
158 /* Store the frame list base address */
a1d59ce8 159 outl(uhci->frame_dma_handle, uhci->io_addr + USBFLBASEADD);
a8bed8b6
AS
160
161 /* Set the current frame number */
162 outw(uhci->frame_number, uhci->io_addr + USBFRNUM);
163
f37be9b9
AS
164 /* Mark controller as not halted before we enable interrupts */
165 uhci_to_hcd(uhci)->state = HC_STATE_SUSPENDED;
a8bed8b6
AS
166 mb();
167
168 /* Enable PIRQ */
169 pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP,
170 USBLEGSUP_DEFAULT);
171}
172
173
c8f4fe43 174static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci)
1da177e4 175{
c8f4fe43 176 int port;
1da177e4 177
c8f4fe43
AS
178 switch (to_pci_dev(uhci_dev(uhci))->vendor) {
179 default:
180 break;
181
182 case PCI_VENDOR_ID_GENESYS:
183 /* Genesys Logic's GL880S controllers don't generate
184 * resume-detect interrupts.
185 */
186 return 1;
187
188 case PCI_VENDOR_ID_INTEL:
189 /* Some of Intel's USB controllers have a bug that causes
190 * resume-detect interrupts if any port has an over-current
191 * condition. To make matters worse, some motherboards
192 * hardwire unused USB ports' over-current inputs active!
193 * To prevent problems, we will not enable resume-detect
194 * interrupts if any ports are OC.
195 */
196 for (port = 0; port < uhci->rh_numports; ++port) {
197 if (inw(uhci->io_addr + USBPORTSC1 + port * 2) &
198 USBPORTSC_OC)
199 return 1;
200 }
201 break;
202 }
203 return 0;
204}
205
a8bed8b6 206static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state)
c8f4fe43
AS
207__releases(uhci->lock)
208__acquires(uhci->lock)
209{
210 int auto_stop;
211 int int_enable;
212
213 auto_stop = (new_state == UHCI_RH_AUTO_STOPPED);
214 dev_dbg(uhci_dev(uhci), "%s%s\n", __FUNCTION__,
215 (auto_stop ? " (auto-stop)" : ""));
216
217 /* If we get a suspend request when we're already auto-stopped
218 * then there's nothing to do.
219 */
220 if (uhci->rh_state == UHCI_RH_AUTO_STOPPED) {
221 uhci->rh_state = new_state;
222 return;
223 }
224
225 /* Enable resume-detect interrupts if they work.
226 * Then enter Global Suspend mode, still configured.
227 */
1f09df8b
AS
228 uhci->working_RD = 1;
229 int_enable = USBINTR_RESUME;
230 if (resume_detect_interrupts_are_broken(uhci)) {
231 uhci->working_RD = int_enable = 0;
232 }
c8f4fe43
AS
233 outw(int_enable, uhci->io_addr + USBINTR);
234 outw(USBCMD_EGSM | USBCMD_CF, uhci->io_addr + USBCMD);
a8bed8b6 235 mb();
c8f4fe43
AS
236 udelay(5);
237
238 /* If we're auto-stopping then no devices have been attached
239 * for a while, so there shouldn't be any active URBs and the
240 * controller should stop after a few microseconds. Otherwise
241 * we will give the controller one frame to stop.
242 */
243 if (!auto_stop && !(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) {
244 uhci->rh_state = UHCI_RH_SUSPENDING;
245 spin_unlock_irq(&uhci->lock);
246 msleep(1);
247 spin_lock_irq(&uhci->lock);
4daaa87c
AS
248 if (uhci->hc_inaccessible) /* Died */
249 return;
c8f4fe43
AS
250 }
251 if (!(inw(uhci->io_addr + USBSTS) & USBSTS_HCH))
252 dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n");
1da177e4 253
1da177e4 254 uhci_get_current_frame_number(uhci);
c8f4fe43
AS
255 smp_wmb();
256
257 uhci->rh_state = new_state;
1da177e4 258 uhci->is_stopped = UHCI_IS_STOPPED;
6c1b445c 259 uhci_to_hcd(uhci)->poll_rh = !int_enable;
1da177e4
LT
260
261 uhci_scan_schedule(uhci, NULL);
262}
263
a8bed8b6
AS
264static void start_rh(struct uhci_hcd *uhci)
265{
f37be9b9 266 uhci_to_hcd(uhci)->state = HC_STATE_RUNNING;
a8bed8b6
AS
267 uhci->is_stopped = 0;
268 smp_wmb();
269
270 /* Mark it configured and running with a 64-byte max packet.
271 * All interrupts are enabled, even though RESUME won't do anything.
272 */
273 outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, uhci->io_addr + USBCMD);
274 outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP,
275 uhci->io_addr + USBINTR);
276 mb();
6c1b445c
AS
277 uhci->rh_state = UHCI_RH_RUNNING;
278 uhci_to_hcd(uhci)->poll_rh = 1;
a8bed8b6
AS
279}
280
281static void wakeup_rh(struct uhci_hcd *uhci)
c8f4fe43
AS
282__releases(uhci->lock)
283__acquires(uhci->lock)
1da177e4 284{
c8f4fe43
AS
285 dev_dbg(uhci_dev(uhci), "%s%s\n", __FUNCTION__,
286 uhci->rh_state == UHCI_RH_AUTO_STOPPED ?
287 " (auto-start)" : "");
1da177e4 288
c8f4fe43
AS
289 /* If we are auto-stopped then no devices are attached so there's
290 * no need for wakeup signals. Otherwise we send Global Resume
291 * for 20 ms.
292 */
293 if (uhci->rh_state == UHCI_RH_SUSPENDED) {
294 uhci->rh_state = UHCI_RH_RESUMING;
295 outw(USBCMD_FGR | USBCMD_EGSM | USBCMD_CF,
296 uhci->io_addr + USBCMD);
297 spin_unlock_irq(&uhci->lock);
298 msleep(20);
299 spin_lock_irq(&uhci->lock);
4daaa87c
AS
300 if (uhci->hc_inaccessible) /* Died */
301 return;
1da177e4 302
c8f4fe43
AS
303 /* End Global Resume and wait for EOP to be sent */
304 outw(USBCMD_CF, uhci->io_addr + USBCMD);
a8bed8b6 305 mb();
c8f4fe43
AS
306 udelay(4);
307 if (inw(uhci->io_addr + USBCMD) & USBCMD_FGR)
308 dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n");
309 }
1da177e4 310
a8bed8b6 311 start_rh(uhci);
c8f4fe43 312
6c1b445c
AS
313 /* Restart root hub polling */
314 mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
1da177e4
LT
315}
316
014e73c9
AS
317static irqreturn_t uhci_irq(struct usb_hcd *hcd, struct pt_regs *regs)
318{
319 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
014e73c9 320 unsigned short status;
4daaa87c 321 unsigned long flags;
1da177e4
LT
322
323 /*
014e73c9
AS
324 * Read the interrupt status, and write it back to clear the
325 * interrupt cause. Contrary to the UHCI specification, the
326 * "HC Halted" status bit is persistent: it is RO, not R/WC.
1da177e4 327 */
a8bed8b6 328 status = inw(uhci->io_addr + USBSTS);
014e73c9
AS
329 if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */
330 return IRQ_NONE;
a8bed8b6 331 outw(status, uhci->io_addr + USBSTS); /* Clear it */
014e73c9
AS
332
333 if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) {
334 if (status & USBSTS_HSE)
335 dev_err(uhci_dev(uhci), "host system error, "
336 "PCI problems?\n");
337 if (status & USBSTS_HCPE)
338 dev_err(uhci_dev(uhci), "host controller process "
339 "error, something bad happened!\n");
4daaa87c
AS
340 if (status & USBSTS_HCH) {
341 spin_lock_irqsave(&uhci->lock, flags);
342 if (uhci->rh_state >= UHCI_RH_RUNNING) {
343 dev_err(uhci_dev(uhci),
344 "host controller halted, "
014e73c9 345 "very bad!\n");
4daaa87c 346 hc_died(uhci);
1f09df8b
AS
347
348 /* Force a callback in case there are
349 * pending unlinks */
350 mod_timer(&hcd->rh_timer, jiffies);
4daaa87c
AS
351 }
352 spin_unlock_irqrestore(&uhci->lock, flags);
1da177e4 353 }
1da177e4
LT
354 }
355
014e73c9 356 if (status & USBSTS_RD)
6c1b445c 357 usb_hcd_poll_rh_status(hcd);
1f09df8b
AS
358 else {
359 spin_lock_irqsave(&uhci->lock, flags);
360 uhci_scan_schedule(uhci, regs);
361 spin_unlock_irqrestore(&uhci->lock, flags);
362 }
1da177e4 363
014e73c9
AS
364 return IRQ_HANDLED;
365}
1da177e4 366
014e73c9
AS
367/*
368 * Store the current frame number in uhci->frame_number if the controller
369 * is runnning
370 */
371static void uhci_get_current_frame_number(struct uhci_hcd *uhci)
372{
373 if (!uhci->is_stopped)
374 uhci->frame_number = inw(uhci->io_addr + USBFRNUM);
1da177e4
LT
375}
376
377/*
378 * De-allocate all resources
379 */
380static void release_uhci(struct uhci_hcd *uhci)
381{
382 int i;
383
384 for (i = 0; i < UHCI_NUM_SKELQH; i++)
8b4cd421 385 uhci_free_qh(uhci, uhci->skelqh[i]);
1da177e4 386
8b4cd421 387 uhci_free_td(uhci, uhci->term_td);
1da177e4 388
8b4cd421 389 dma_pool_destroy(uhci->qh_pool);
1da177e4 390
8b4cd421 391 dma_pool_destroy(uhci->td_pool);
1da177e4 392
a1d59ce8
AS
393 kfree(uhci->frame_cpu);
394
395 dma_free_coherent(uhci_dev(uhci),
396 UHCI_NUMFRAMES * sizeof(*uhci->frame),
397 uhci->frame, uhci->frame_dma_handle);
1da177e4 398
8b4cd421 399 debugfs_remove(uhci->dentry);
1da177e4
LT
400}
401
402static int uhci_reset(struct usb_hcd *hcd)
403{
404 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
c074b416
AS
405 unsigned io_size = (unsigned) hcd->rsrc_len;
406 int port;
1da177e4
LT
407
408 uhci->io_addr = (unsigned long) hcd->rsrc_start;
409
c074b416
AS
410 /* The UHCI spec says devices must have 2 ports, and goes on to say
411 * they may have more but gives no way to determine how many there
e07fefa6 412 * are. However according to the UHCI spec, Bit 7 of the port
c074b416 413 * status and control register is always set to 1. So we try to
e07fefa6
AS
414 * use this to our advantage. Another common failure mode when
415 * a nonexistent register is addressed is to return all ones, so
416 * we test for that also.
c074b416
AS
417 */
418 for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) {
419 unsigned int portstatus;
420
421 portstatus = inw(uhci->io_addr + USBPORTSC1 + (port * 2));
e07fefa6 422 if (!(portstatus & 0x0080) || portstatus == 0xffff)
c074b416
AS
423 break;
424 }
425 if (debug)
426 dev_info(uhci_dev(uhci), "detected %d ports\n", port);
427
e07fefa6
AS
428 /* Anything greater than 7 is weird so we'll ignore it. */
429 if (port > UHCI_RH_MAXCHILD) {
c074b416
AS
430 dev_info(uhci_dev(uhci), "port count misdetected? "
431 "forcing to 2 ports\n");
432 port = 2;
433 }
434 uhci->rh_numports = port;
435
a8bed8b6
AS
436 /* Kick BIOS off this hardware and reset if the controller
437 * isn't already safely quiescent.
1da177e4 438 */
a8bed8b6 439 check_and_reset_hc(uhci);
1da177e4
LT
440 return 0;
441}
442
02597d2d
AS
443/* Make sure the controller is quiescent and that we're not using it
444 * any more. This is mainly for the benefit of programs which, like kexec,
445 * expect the hardware to be idle: not doing DMA or generating IRQs.
446 *
447 * This routine may be called in a damaged or failing kernel. Hence we
448 * do not acquire the spinlock before shutting down the controller.
449 */
450static void uhci_shutdown(struct pci_dev *pdev)
451{
452 struct usb_hcd *hcd = (struct usb_hcd *) pci_get_drvdata(pdev);
453
454 hc_died(hcd_to_uhci(hcd));
455}
456
1da177e4
LT
457/*
458 * Allocate a frame list, and then setup the skeleton
459 *
460 * The hardware doesn't really know any difference
461 * in the queues, but the order does matter for the
462 * protocols higher up. The order is:
463 *
464 * - any isochronous events handled before any
465 * of the queues. We don't do that here, because
466 * we'll create the actual TD entries on demand.
467 * - The first queue is the interrupt queue.
468 * - The second queue is the control queue, split into low- and full-speed
469 * - The third queue is bulk queue.
470 * - The fourth queue is the bandwidth reclamation queue, which loops back
471 * to the full-speed control queue.
472 */
473static int uhci_start(struct usb_hcd *hcd)
474{
475 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
476 int retval = -EBUSY;
c074b416 477 int i;
1da177e4
LT
478 struct dentry *dentry;
479
6c1b445c 480 hcd->uses_new_polling = 1;
4daaa87c
AS
481 if (pci_find_capability(to_pci_dev(uhci_dev(uhci)), PCI_CAP_ID_PM))
482 hcd->can_wakeup = 1; /* Assume it supports PME# */
1da177e4 483
4daaa87c
AS
484 dentry = debugfs_create_file(hcd->self.bus_name,
485 S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root, uhci,
486 &uhci_debug_operations);
1da177e4 487 if (!dentry) {
4daaa87c
AS
488 dev_err(uhci_dev(uhci),
489 "couldn't create uhci debugfs entry\n");
1da177e4
LT
490 retval = -ENOMEM;
491 goto err_create_debug_entry;
492 }
493 uhci->dentry = dentry;
494
495 uhci->fsbr = 0;
496 uhci->fsbrtimeout = 0;
497
498 spin_lock_init(&uhci->lock);
499 INIT_LIST_HEAD(&uhci->qh_remove_list);
500
501 INIT_LIST_HEAD(&uhci->td_remove_list);
502
503 INIT_LIST_HEAD(&uhci->urb_remove_list);
504
505 INIT_LIST_HEAD(&uhci->urb_list);
506
507 INIT_LIST_HEAD(&uhci->complete_list);
508
509 init_waitqueue_head(&uhci->waitqh);
510
a1d59ce8
AS
511 uhci->frame = dma_alloc_coherent(uhci_dev(uhci),
512 UHCI_NUMFRAMES * sizeof(*uhci->frame),
513 &uhci->frame_dma_handle, 0);
514 if (!uhci->frame) {
1da177e4
LT
515 dev_err(uhci_dev(uhci), "unable to allocate "
516 "consistent memory for frame list\n");
a1d59ce8 517 goto err_alloc_frame;
1da177e4 518 }
a1d59ce8 519 memset(uhci->frame, 0, UHCI_NUMFRAMES * sizeof(*uhci->frame));
1da177e4 520
a1d59ce8
AS
521 uhci->frame_cpu = kcalloc(UHCI_NUMFRAMES, sizeof(*uhci->frame_cpu),
522 GFP_KERNEL);
523 if (!uhci->frame_cpu) {
524 dev_err(uhci_dev(uhci), "unable to allocate "
525 "memory for frame pointers\n");
526 goto err_alloc_frame_cpu;
527 }
1da177e4
LT
528
529 uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci),
530 sizeof(struct uhci_td), 16, 0);
531 if (!uhci->td_pool) {
532 dev_err(uhci_dev(uhci), "unable to create td dma_pool\n");
533 goto err_create_td_pool;
534 }
535
536 uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci),
537 sizeof(struct uhci_qh), 16, 0);
538 if (!uhci->qh_pool) {
539 dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n");
540 goto err_create_qh_pool;
541 }
542
2532178a 543 uhci->term_td = uhci_alloc_td(uhci);
1da177e4
LT
544 if (!uhci->term_td) {
545 dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n");
546 goto err_alloc_term_td;
547 }
548
549 for (i = 0; i < UHCI_NUM_SKELQH; i++) {
2532178a 550 uhci->skelqh[i] = uhci_alloc_qh(uhci);
1da177e4
LT
551 if (!uhci->skelqh[i]) {
552 dev_err(uhci_dev(uhci), "unable to allocate QH\n");
553 goto err_alloc_skelqh;
554 }
555 }
556
557 /*
558 * 8 Interrupt queues; link all higher int queues to int1,
559 * then link int1 to control and control to bulk
560 */
561 uhci->skel_int128_qh->link =
562 uhci->skel_int64_qh->link =
563 uhci->skel_int32_qh->link =
564 uhci->skel_int16_qh->link =
565 uhci->skel_int8_qh->link =
566 uhci->skel_int4_qh->link =
567 uhci->skel_int2_qh->link =
568 cpu_to_le32(uhci->skel_int1_qh->dma_handle) | UHCI_PTR_QH;
569 uhci->skel_int1_qh->link = cpu_to_le32(uhci->skel_ls_control_qh->dma_handle) | UHCI_PTR_QH;
570
571 uhci->skel_ls_control_qh->link = cpu_to_le32(uhci->skel_fs_control_qh->dma_handle) | UHCI_PTR_QH;
572 uhci->skel_fs_control_qh->link = cpu_to_le32(uhci->skel_bulk_qh->dma_handle) | UHCI_PTR_QH;
573 uhci->skel_bulk_qh->link = cpu_to_le32(uhci->skel_term_qh->dma_handle) | UHCI_PTR_QH;
574
575 /* This dummy TD is to work around a bug in Intel PIIX controllers */
576 uhci_fill_td(uhci->term_td, 0, (UHCI_NULL_DATA_SIZE << 21) |
577 (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0);
578 uhci->term_td->link = cpu_to_le32(uhci->term_td->dma_handle);
579
580 uhci->skel_term_qh->link = UHCI_PTR_TERM;
581 uhci->skel_term_qh->element = cpu_to_le32(uhci->term_td->dma_handle);
582
583 /*
584 * Fill the frame list: make all entries point to the proper
585 * interrupt queue.
586 *
587 * The interrupt queues will be interleaved as evenly as possible.
588 * There's not much to be done about period-1 interrupts; they have
589 * to occur in every frame. But we can schedule period-2 interrupts
590 * in odd-numbered frames, period-4 interrupts in frames congruent
591 * to 2 (mod 4), and so on. This way each frame only has two
592 * interrupt QHs, which will help spread out bandwidth utilization.
593 */
594 for (i = 0; i < UHCI_NUMFRAMES; i++) {
595 int irq;
596
597 /*
598 * ffs (Find First bit Set) does exactly what we need:
599 * 1,3,5,... => ffs = 0 => use skel_int2_qh = skelqh[6],
600 * 2,6,10,... => ffs = 1 => use skel_int4_qh = skelqh[5], etc.
601 * ffs > 6 => not on any high-period queue, so use
602 * skel_int1_qh = skelqh[7].
603 * Add UHCI_NUMFRAMES to insure at least one bit is set.
604 */
605 irq = 6 - (int) __ffs(i + UHCI_NUMFRAMES);
606 if (irq < 0)
607 irq = 7;
608
609 /* Only place we don't use the frame list routines */
a1d59ce8 610 uhci->frame[i] = UHCI_PTR_QH |
1da177e4
LT
611 cpu_to_le32(uhci->skelqh[irq]->dma_handle);
612 }
613
614 /*
615 * Some architectures require a full mb() to enforce completion of
a8bed8b6 616 * the memory writes above before the I/O transfers in configure_hc().
1da177e4
LT
617 */
618 mb();
a8bed8b6
AS
619
620 configure_hc(uhci);
621 start_rh(uhci);
1da177e4
LT
622 return 0;
623
624/*
625 * error exits:
626 */
1da177e4 627err_alloc_skelqh:
8b4cd421
AS
628 for (i = 0; i < UHCI_NUM_SKELQH; i++) {
629 if (uhci->skelqh[i])
1da177e4 630 uhci_free_qh(uhci, uhci->skelqh[i]);
8b4cd421 631 }
1da177e4
LT
632
633 uhci_free_td(uhci, uhci->term_td);
1da177e4
LT
634
635err_alloc_term_td:
1da177e4 636 dma_pool_destroy(uhci->qh_pool);
1da177e4
LT
637
638err_create_qh_pool:
639 dma_pool_destroy(uhci->td_pool);
1da177e4
LT
640
641err_create_td_pool:
a1d59ce8
AS
642 kfree(uhci->frame_cpu);
643
644err_alloc_frame_cpu:
645 dma_free_coherent(uhci_dev(uhci),
646 UHCI_NUMFRAMES * sizeof(*uhci->frame),
647 uhci->frame, uhci->frame_dma_handle);
1da177e4 648
a1d59ce8 649err_alloc_frame:
1da177e4 650 debugfs_remove(uhci->dentry);
1da177e4
LT
651
652err_create_debug_entry:
653 return retval;
654}
655
656static void uhci_stop(struct usb_hcd *hcd)
657{
658 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
659
1da177e4 660 spin_lock_irq(&uhci->lock);
1f09df8b 661 if (!uhci->hc_inaccessible)
bb200f6e 662 hc_died(uhci);
1da177e4
LT
663 uhci_scan_schedule(uhci, NULL);
664 spin_unlock_irq(&uhci->lock);
6c1b445c 665
1da177e4
LT
666 release_uhci(uhci);
667}
668
669#ifdef CONFIG_PM
a8bed8b6
AS
670static int uhci_rh_suspend(struct usb_hcd *hcd)
671{
672 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
673
674 spin_lock_irq(&uhci->lock);
4daaa87c
AS
675 if (!uhci->hc_inaccessible) /* Not dead */
676 suspend_rh(uhci, UHCI_RH_SUSPENDED);
a8bed8b6
AS
677 spin_unlock_irq(&uhci->lock);
678 return 0;
679}
680
681static int uhci_rh_resume(struct usb_hcd *hcd)
682{
683 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
4daaa87c 684 int rc = 0;
a8bed8b6
AS
685
686 spin_lock_irq(&uhci->lock);
4daaa87c
AS
687 if (uhci->hc_inaccessible) {
688 if (uhci->rh_state == UHCI_RH_SUSPENDED) {
689 dev_warn(uhci_dev(uhci), "HC isn't running!\n");
690 rc = -ENODEV;
691 }
692 /* Otherwise the HC is dead */
693 } else
694 wakeup_rh(uhci);
a8bed8b6 695 spin_unlock_irq(&uhci->lock);
4daaa87c 696 return rc;
a8bed8b6
AS
697}
698
9a5d3e98 699static int uhci_suspend(struct usb_hcd *hcd, pm_message_t message)
1da177e4
LT
700{
701 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
4daaa87c 702 int rc = 0;
1da177e4 703
a8bed8b6
AS
704 dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__);
705
1da177e4 706 spin_lock_irq(&uhci->lock);
4daaa87c
AS
707 if (uhci->hc_inaccessible) /* Dead or already suspended */
708 goto done;
a8bed8b6 709
4daaa87c
AS
710 if (uhci->rh_state > UHCI_RH_SUSPENDED) {
711 dev_warn(uhci_dev(uhci), "Root hub isn't suspended!\n");
4daaa87c
AS
712 rc = -EBUSY;
713 goto done;
714 };
715
a8bed8b6
AS
716 /* All PCI host controllers are required to disable IRQ generation
717 * at the source, so we must turn off PIRQ.
718 */
719 pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 0);
720 uhci->hc_inaccessible = 1;
1f09df8b 721 hcd->poll_rh = 0;
a8bed8b6
AS
722
723 /* FIXME: Enable non-PME# remote wakeup? */
724
4daaa87c 725done:
1da177e4 726 spin_unlock_irq(&uhci->lock);
4daaa87c 727 return rc;
1da177e4
LT
728}
729
730static int uhci_resume(struct usb_hcd *hcd)
731{
732 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
1da177e4 733
a8bed8b6
AS
734 dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__);
735
4daaa87c
AS
736 if (uhci->rh_state == UHCI_RH_RESET) /* Dead */
737 return 0;
1da177e4 738 spin_lock_irq(&uhci->lock);
1da177e4 739
a8bed8b6
AS
740 /* FIXME: Disable non-PME# remote wakeup? */
741
742 uhci->hc_inaccessible = 0;
743
744 /* The BIOS may have changed the controller settings during a
745 * system wakeup. Check it and reconfigure to avoid problems.
746 */
747 check_and_reset_hc(uhci);
748 configure_hc(uhci);
749
a8bed8b6
AS
750 if (uhci->rh_state == UHCI_RH_RESET)
751 suspend_rh(uhci, UHCI_RH_SUSPENDED);
c8f4fe43 752
a8bed8b6 753 spin_unlock_irq(&uhci->lock);
6c1b445c 754
1f09df8b
AS
755 if (!uhci->working_RD) {
756 /* Suspended root hub needs to be polled */
757 hcd->poll_rh = 1;
6c1b445c 758 usb_hcd_poll_rh_status(hcd);
1f09df8b 759 }
1da177e4
LT
760 return 0;
761}
762#endif
763
764/* Wait until all the URBs for a particular device/endpoint are gone */
765static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd,
766 struct usb_host_endpoint *ep)
767{
768 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
769
770 wait_event_interruptible(uhci->waitqh, list_empty(&ep->urb_list));
771}
772
773static int uhci_hcd_get_frame_number(struct usb_hcd *hcd)
774{
775 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
1da177e4 776 unsigned long flags;
c8f4fe43
AS
777 int is_stopped;
778 int frame_number;
1da177e4
LT
779
780 /* Minimize latency by avoiding the spinlock */
781 local_irq_save(flags);
c8f4fe43
AS
782 is_stopped = uhci->is_stopped;
783 smp_rmb();
784 frame_number = (is_stopped ? uhci->frame_number :
1da177e4
LT
785 inw(uhci->io_addr + USBFRNUM));
786 local_irq_restore(flags);
787 return frame_number;
788}
789
790static const char hcd_name[] = "uhci_hcd";
791
792static const struct hc_driver uhci_driver = {
793 .description = hcd_name,
794 .product_desc = "UHCI Host Controller",
795 .hcd_priv_size = sizeof(struct uhci_hcd),
796
797 /* Generic hardware linkage */
798 .irq = uhci_irq,
799 .flags = HCD_USB11,
800
801 /* Basic lifecycle operations */
802 .reset = uhci_reset,
803 .start = uhci_start,
804#ifdef CONFIG_PM
805 .suspend = uhci_suspend,
806 .resume = uhci_resume,
0c0382e3
AS
807 .bus_suspend = uhci_rh_suspend,
808 .bus_resume = uhci_rh_resume,
1da177e4
LT
809#endif
810 .stop = uhci_stop,
811
812 .urb_enqueue = uhci_urb_enqueue,
813 .urb_dequeue = uhci_urb_dequeue,
814
815 .endpoint_disable = uhci_hcd_endpoint_disable,
816 .get_frame_number = uhci_hcd_get_frame_number,
817
818 .hub_status_data = uhci_hub_status_data,
819 .hub_control = uhci_hub_control,
820};
821
822static const struct pci_device_id uhci_pci_ids[] = { {
823 /* handle any USB UHCI controller */
824 PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x00), ~0),
825 .driver_data = (unsigned long) &uhci_driver,
826 }, { /* end: all zeroes */ }
827};
828
829MODULE_DEVICE_TABLE(pci, uhci_pci_ids);
830
831static struct pci_driver uhci_pci_driver = {
832 .name = (char *)hcd_name,
833 .id_table = uhci_pci_ids,
834
835 .probe = usb_hcd_pci_probe,
836 .remove = usb_hcd_pci_remove,
02597d2d 837 .shutdown = uhci_shutdown,
1da177e4
LT
838
839#ifdef CONFIG_PM
840 .suspend = usb_hcd_pci_suspend,
841 .resume = usb_hcd_pci_resume,
842#endif /* PM */
843};
844
845static int __init uhci_hcd_init(void)
846{
847 int retval = -ENOMEM;
848
849 printk(KERN_INFO DRIVER_DESC " " DRIVER_VERSION "\n");
850
851 if (usb_disabled())
852 return -ENODEV;
853
854 if (debug) {
855 errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL);
856 if (!errbuf)
857 goto errbuf_failed;
858 }
859
860 uhci_debugfs_root = debugfs_create_dir("uhci", NULL);
861 if (!uhci_debugfs_root)
862 goto debug_failed;
863
864 uhci_up_cachep = kmem_cache_create("uhci_urb_priv",
865 sizeof(struct urb_priv), 0, 0, NULL, NULL);
866 if (!uhci_up_cachep)
867 goto up_failed;
868
869 retval = pci_register_driver(&uhci_pci_driver);
870 if (retval)
871 goto init_failed;
872
873 return 0;
874
875init_failed:
876 if (kmem_cache_destroy(uhci_up_cachep))
877 warn("not all urb_priv's were freed!");
878
879up_failed:
880 debugfs_remove(uhci_debugfs_root);
881
882debug_failed:
1bc3c9e1 883 kfree(errbuf);
1da177e4
LT
884
885errbuf_failed:
886
887 return retval;
888}
889
890static void __exit uhci_hcd_cleanup(void)
891{
892 pci_unregister_driver(&uhci_pci_driver);
893
894 if (kmem_cache_destroy(uhci_up_cachep))
895 warn("not all urb_priv's were freed!");
896
897 debugfs_remove(uhci_debugfs_root);
1bc3c9e1 898 kfree(errbuf);
1da177e4
LT
899}
900
901module_init(uhci_hcd_init);
902module_exit(uhci_hcd_cleanup);
903
904MODULE_AUTHOR(DRIVER_AUTHOR);
905MODULE_DESCRIPTION(DRIVER_DESC);
906MODULE_LICENSE("GPL");
This page took 0.124762 seconds and 5 git commands to generate.