Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Universal Host Controller Interface driver for USB. | |
3 | * | |
4 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | |
5 | * | |
6 | * (C) Copyright 1999 Linus Torvalds | |
7 | * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com | |
8 | * (C) Copyright 1999 Randy Dunlap | |
9 | * (C) Copyright 1999 Georg Acher, acher@in.tum.de | |
10 | * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de | |
11 | * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch | |
12 | * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at | |
13 | * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface | |
14 | * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com). | |
15 | * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c) | |
16 | * (C) Copyright 2004 Alan Stern, stern@rowland.harvard.edu | |
17 | * | |
18 | * Intel documents this fairly well, and as far as I know there | |
19 | * are no royalties or anything like that, but even so there are | |
20 | * people who decided that they want to do the same thing in a | |
21 | * completely different way. | |
22 | * | |
23 | * WARNING! The USB documentation is downright evil. Most of it | |
24 | * is just crap, written by a committee. You're better off ignoring | |
25 | * most of it, the important stuff is: | |
26 | * - the low-level protocol (fairly simple but lots of small details) | |
27 | * - working around the horridness of the rest | |
28 | */ | |
29 | ||
30 | #include <linux/config.h> | |
31 | #ifdef CONFIG_USB_DEBUG | |
32 | #define DEBUG | |
33 | #else | |
34 | #undef DEBUG | |
35 | #endif | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/kernel.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/ioport.h> | |
42 | #include <linux/sched.h> | |
43 | #include <linux/slab.h> | |
44 | #include <linux/smp_lock.h> | |
45 | #include <linux/errno.h> | |
46 | #include <linux/unistd.h> | |
47 | #include <linux/interrupt.h> | |
48 | #include <linux/spinlock.h> | |
49 | #include <linux/debugfs.h> | |
50 | #include <linux/pm.h> | |
51 | #include <linux/dmapool.h> | |
52 | #include <linux/dma-mapping.h> | |
53 | #include <linux/usb.h> | |
54 | #include <linux/bitops.h> | |
55 | ||
56 | #include <asm/uaccess.h> | |
57 | #include <asm/io.h> | |
58 | #include <asm/irq.h> | |
59 | #include <asm/system.h> | |
60 | ||
61 | #include "../core/hcd.h" | |
62 | #include "uhci-hcd.h" | |
63 | ||
64 | /* | |
65 | * Version Information | |
66 | */ | |
67 | #define DRIVER_VERSION "v2.2" | |
68 | #define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \ | |
69 | Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \ | |
70 | Alan Stern" | |
71 | #define DRIVER_DESC "USB Universal Host Controller Interface driver" | |
72 | ||
73 | /* | |
74 | * debug = 0, no debugging messages | |
75 | * debug = 1, dump failed URB's except for stalls | |
76 | * debug = 2, dump all failed URB's (including stalls) | |
77 | * show all queues in /debug/uhci/[pci_addr] | |
78 | * debug = 3, show all TD's in URB's when dumping | |
79 | */ | |
80 | #ifdef DEBUG | |
81 | static int debug = 1; | |
82 | #else | |
83 | static int debug = 0; | |
84 | #endif | |
85 | module_param(debug, int, S_IRUGO | S_IWUSR); | |
86 | MODULE_PARM_DESC(debug, "Debug level"); | |
87 | static char *errbuf; | |
88 | #define ERRBUF_LEN (32 * 1024) | |
89 | ||
90 | static kmem_cache_t *uhci_up_cachep; /* urb_priv */ | |
91 | ||
92 | static void uhci_get_current_frame_number(struct uhci_hcd *uhci); | |
1da177e4 LT |
93 | |
94 | /* If a transfer is still active after this much time, turn off FSBR */ | |
95 | #define IDLE_TIMEOUT msecs_to_jiffies(50) | |
96 | #define FSBR_DELAY msecs_to_jiffies(50) | |
97 | ||
98 | /* When we timeout an idle transfer for FSBR, we'll switch it over to */ | |
99 | /* depth first traversal. We'll do it in groups of this number of TD's */ | |
100 | /* to make sure it doesn't hog all of the bandwidth */ | |
101 | #define DEPTH_INTERVAL 5 | |
102 | ||
f5946f82 AS |
103 | static inline void restart_timer(struct uhci_hcd *uhci) |
104 | { | |
105 | mod_timer(&uhci->stall_timer, jiffies + msecs_to_jiffies(100)); | |
106 | } | |
107 | ||
1da177e4 LT |
108 | #include "uhci-hub.c" |
109 | #include "uhci-debug.c" | |
110 | #include "uhci-q.c" | |
111 | ||
014e73c9 | 112 | static int suspend_allowed(struct uhci_hcd *uhci) |
1da177e4 | 113 | { |
1da177e4 | 114 | unsigned long io_addr = uhci->io_addr; |
014e73c9 | 115 | int i; |
1da177e4 | 116 | |
014e73c9 AS |
117 | if (to_pci_dev(uhci_dev(uhci))->vendor != PCI_VENDOR_ID_INTEL) |
118 | return 1; | |
119 | ||
120 | /* Some of Intel's USB controllers have a bug that causes false | |
121 | * resume indications if any port has an over current condition. | |
122 | * To prevent problems, we will not allow a global suspend if | |
123 | * any ports are OC. | |
124 | * | |
125 | * Some motherboards using Intel's chipsets (but not using all | |
126 | * the USB ports) appear to hardwire the over current inputs active | |
127 | * to disable the USB ports. | |
1da177e4 | 128 | */ |
1da177e4 | 129 | |
014e73c9 AS |
130 | /* check for over current condition on any port */ |
131 | for (i = 0; i < uhci->rh_numports; i++) { | |
132 | if (inw(io_addr + USBPORTSC1 + i * 2) & USBPORTSC_OC) | |
133 | return 0; | |
1da177e4 LT |
134 | } |
135 | ||
014e73c9 | 136 | return 1; |
1da177e4 LT |
137 | } |
138 | ||
139 | static void reset_hc(struct uhci_hcd *uhci) | |
140 | { | |
141 | unsigned long io_addr = uhci->io_addr; | |
142 | ||
143 | /* Turn off PIRQ, SMI, and all interrupts. This also turns off | |
144 | * the BIOS's USB Legacy Support. | |
145 | */ | |
146 | pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 0); | |
147 | outw(0, uhci->io_addr + USBINTR); | |
148 | ||
149 | /* Global reset for 50ms */ | |
150 | uhci->state = UHCI_RESET; | |
151 | outw(USBCMD_GRESET, io_addr + USBCMD); | |
152 | msleep(50); | |
153 | outw(0, io_addr + USBCMD); | |
154 | ||
155 | /* Another 10ms delay */ | |
156 | msleep(10); | |
157 | uhci->resume_detect = 0; | |
158 | uhci->is_stopped = UHCI_IS_STOPPED; | |
159 | } | |
160 | ||
161 | static void suspend_hc(struct uhci_hcd *uhci) | |
162 | { | |
163 | unsigned long io_addr = uhci->io_addr; | |
164 | ||
165 | dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__); | |
166 | uhci->state = UHCI_SUSPENDED; | |
167 | uhci->resume_detect = 0; | |
168 | outw(USBCMD_EGSM, io_addr + USBCMD); | |
169 | ||
170 | /* FIXME: Wait for the controller to actually stop */ | |
171 | uhci_get_current_frame_number(uhci); | |
172 | uhci->is_stopped = UHCI_IS_STOPPED; | |
173 | ||
174 | uhci_scan_schedule(uhci, NULL); | |
175 | } | |
176 | ||
177 | static void wakeup_hc(struct uhci_hcd *uhci) | |
178 | { | |
179 | unsigned long io_addr = uhci->io_addr; | |
180 | ||
181 | switch (uhci->state) { | |
182 | case UHCI_SUSPENDED: /* Start the resume */ | |
183 | dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__); | |
184 | ||
185 | /* Global resume for >= 20ms */ | |
186 | outw(USBCMD_FGR | USBCMD_EGSM, io_addr + USBCMD); | |
187 | uhci->state = UHCI_RESUMING_1; | |
188 | uhci->state_end = jiffies + msecs_to_jiffies(20); | |
189 | uhci->is_stopped = 0; | |
190 | break; | |
191 | ||
192 | case UHCI_RESUMING_1: /* End global resume */ | |
193 | uhci->state = UHCI_RESUMING_2; | |
194 | outw(0, io_addr + USBCMD); | |
195 | /* Falls through */ | |
196 | ||
197 | case UHCI_RESUMING_2: /* Wait for EOP to be sent */ | |
198 | if (inw(io_addr + USBCMD) & USBCMD_FGR) | |
199 | break; | |
200 | ||
201 | /* Run for at least 1 second, and | |
202 | * mark it configured with a 64-byte max packet */ | |
203 | uhci->state = UHCI_RUNNING_GRACE; | |
204 | uhci->state_end = jiffies + HZ; | |
205 | outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, | |
206 | io_addr + USBCMD); | |
207 | break; | |
208 | ||
209 | case UHCI_RUNNING_GRACE: /* Now allowed to suspend */ | |
210 | uhci->state = UHCI_RUNNING; | |
211 | break; | |
212 | ||
213 | default: | |
214 | break; | |
215 | } | |
216 | } | |
217 | ||
014e73c9 | 218 | static int start_hc(struct uhci_hcd *uhci) |
1da177e4 LT |
219 | { |
220 | unsigned long io_addr = uhci->io_addr; | |
014e73c9 | 221 | int timeout = 10; |
1da177e4 | 222 | |
014e73c9 AS |
223 | /* |
224 | * Reset the HC - this will force us to get a | |
225 | * new notification of any already connected | |
226 | * ports due to the virtual disconnect that it | |
227 | * implies. | |
228 | */ | |
229 | outw(USBCMD_HCRESET, io_addr + USBCMD); | |
230 | while (inw(io_addr + USBCMD) & USBCMD_HCRESET) { | |
231 | if (--timeout < 0) { | |
232 | dev_err(uhci_dev(uhci), "USBCMD_HCRESET timed out!\n"); | |
233 | return -ETIMEDOUT; | |
234 | } | |
235 | msleep(1); | |
236 | } | |
1da177e4 | 237 | |
014e73c9 AS |
238 | /* Mark controller as running before we enable interrupts */ |
239 | uhci_to_hcd(uhci)->state = HC_STATE_RUNNING; | |
1da177e4 | 240 | |
014e73c9 AS |
241 | /* Turn on PIRQ and all interrupts */ |
242 | pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, | |
243 | USBLEGSUP_DEFAULT); | |
244 | outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP, | |
245 | io_addr + USBINTR); | |
1da177e4 | 246 | |
014e73c9 AS |
247 | /* Start at frame 0 */ |
248 | outw(0, io_addr + USBFRNUM); | |
249 | outl(uhci->fl->dma_handle, io_addr + USBFLBASEADD); | |
1da177e4 | 250 | |
014e73c9 AS |
251 | /* Run and mark it configured with a 64-byte max packet */ |
252 | uhci->state = UHCI_RUNNING_GRACE; | |
253 | uhci->state_end = jiffies + HZ; | |
254 | outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, io_addr + USBCMD); | |
255 | uhci->is_stopped = 0; | |
1da177e4 | 256 | |
014e73c9 | 257 | return 0; |
1da177e4 LT |
258 | } |
259 | ||
260 | static void hc_state_transitions(struct uhci_hcd *uhci) | |
261 | { | |
262 | switch (uhci->state) { | |
263 | case UHCI_RUNNING: | |
264 | ||
265 | /* global suspend if nothing connected for 1 second */ | |
f5946f82 | 266 | if (!any_ports_active(uhci) && suspend_allowed(uhci)) { |
1da177e4 LT |
267 | uhci->state = UHCI_SUSPENDING_GRACE; |
268 | uhci->state_end = jiffies + HZ; | |
269 | } | |
270 | break; | |
271 | ||
272 | case UHCI_SUSPENDING_GRACE: | |
f5946f82 | 273 | if (any_ports_active(uhci)) |
1da177e4 LT |
274 | uhci->state = UHCI_RUNNING; |
275 | else if (time_after_eq(jiffies, uhci->state_end)) | |
276 | suspend_hc(uhci); | |
277 | break; | |
278 | ||
279 | case UHCI_SUSPENDED: | |
280 | ||
281 | /* wakeup if requested by a device */ | |
282 | if (uhci->resume_detect) | |
283 | wakeup_hc(uhci); | |
284 | break; | |
285 | ||
286 | case UHCI_RESUMING_1: | |
287 | case UHCI_RESUMING_2: | |
288 | case UHCI_RUNNING_GRACE: | |
289 | if (time_after_eq(jiffies, uhci->state_end)) | |
290 | wakeup_hc(uhci); | |
291 | break; | |
292 | ||
293 | default: | |
294 | break; | |
295 | } | |
296 | } | |
297 | ||
f5946f82 | 298 | static void stall_callback(unsigned long _uhci) |
1da177e4 | 299 | { |
f5946f82 | 300 | struct uhci_hcd *uhci = (struct uhci_hcd *) _uhci; |
014e73c9 AS |
301 | unsigned long flags; |
302 | ||
303 | spin_lock_irqsave(&uhci->lock, flags); | |
304 | uhci_scan_schedule(uhci, NULL); | |
f5946f82 | 305 | check_fsbr(uhci); |
014e73c9 AS |
306 | |
307 | /* Poll for and perform state transitions */ | |
308 | hc_state_transitions(uhci); | |
309 | if (unlikely(uhci->suspended_ports && uhci->state != UHCI_SUSPENDED)) | |
310 | uhci_check_ports(uhci); | |
311 | ||
f5946f82 | 312 | restart_timer(uhci); |
014e73c9 | 313 | spin_unlock_irqrestore(&uhci->lock, flags); |
1da177e4 LT |
314 | } |
315 | ||
014e73c9 AS |
316 | static irqreturn_t uhci_irq(struct usb_hcd *hcd, struct pt_regs *regs) |
317 | { | |
318 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
1da177e4 | 319 | unsigned long io_addr = uhci->io_addr; |
014e73c9 | 320 | unsigned short status; |
1da177e4 LT |
321 | |
322 | /* | |
014e73c9 AS |
323 | * Read the interrupt status, and write it back to clear the |
324 | * interrupt cause. Contrary to the UHCI specification, the | |
325 | * "HC Halted" status bit is persistent: it is RO, not R/WC. | |
1da177e4 | 326 | */ |
014e73c9 AS |
327 | status = inw(io_addr + USBSTS); |
328 | if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */ | |
329 | return IRQ_NONE; | |
330 | outw(status, io_addr + USBSTS); /* Clear it */ | |
331 | ||
332 | if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) { | |
333 | if (status & USBSTS_HSE) | |
334 | dev_err(uhci_dev(uhci), "host system error, " | |
335 | "PCI problems?\n"); | |
336 | if (status & USBSTS_HCPE) | |
337 | dev_err(uhci_dev(uhci), "host controller process " | |
338 | "error, something bad happened!\n"); | |
339 | if ((status & USBSTS_HCH) && uhci->state > 0) { | |
340 | dev_err(uhci_dev(uhci), "host controller halted, " | |
341 | "very bad!\n"); | |
342 | /* FIXME: Reset the controller, fix the offending TD */ | |
1da177e4 | 343 | } |
1da177e4 LT |
344 | } |
345 | ||
014e73c9 AS |
346 | if (status & USBSTS_RD) |
347 | uhci->resume_detect = 1; | |
1da177e4 | 348 | |
014e73c9 AS |
349 | spin_lock(&uhci->lock); |
350 | uhci_scan_schedule(uhci, regs); | |
351 | spin_unlock(&uhci->lock); | |
1da177e4 | 352 | |
014e73c9 AS |
353 | return IRQ_HANDLED; |
354 | } | |
1da177e4 | 355 | |
014e73c9 AS |
356 | /* |
357 | * Store the current frame number in uhci->frame_number if the controller | |
358 | * is runnning | |
359 | */ | |
360 | static void uhci_get_current_frame_number(struct uhci_hcd *uhci) | |
361 | { | |
362 | if (!uhci->is_stopped) | |
363 | uhci->frame_number = inw(uhci->io_addr + USBFRNUM); | |
1da177e4 LT |
364 | } |
365 | ||
366 | /* | |
367 | * De-allocate all resources | |
368 | */ | |
369 | static void release_uhci(struct uhci_hcd *uhci) | |
370 | { | |
371 | int i; | |
372 | ||
373 | for (i = 0; i < UHCI_NUM_SKELQH; i++) | |
374 | if (uhci->skelqh[i]) { | |
375 | uhci_free_qh(uhci, uhci->skelqh[i]); | |
376 | uhci->skelqh[i] = NULL; | |
377 | } | |
378 | ||
379 | if (uhci->term_td) { | |
380 | uhci_free_td(uhci, uhci->term_td); | |
381 | uhci->term_td = NULL; | |
382 | } | |
383 | ||
384 | if (uhci->qh_pool) { | |
385 | dma_pool_destroy(uhci->qh_pool); | |
386 | uhci->qh_pool = NULL; | |
387 | } | |
388 | ||
389 | if (uhci->td_pool) { | |
390 | dma_pool_destroy(uhci->td_pool); | |
391 | uhci->td_pool = NULL; | |
392 | } | |
393 | ||
394 | if (uhci->fl) { | |
395 | dma_free_coherent(uhci_dev(uhci), sizeof(*uhci->fl), | |
396 | uhci->fl, uhci->fl->dma_handle); | |
397 | uhci->fl = NULL; | |
398 | } | |
399 | ||
400 | if (uhci->dentry) { | |
401 | debugfs_remove(uhci->dentry); | |
402 | uhci->dentry = NULL; | |
403 | } | |
404 | } | |
405 | ||
406 | static int uhci_reset(struct usb_hcd *hcd) | |
407 | { | |
408 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
409 | ||
410 | uhci->io_addr = (unsigned long) hcd->rsrc_start; | |
411 | ||
412 | /* Kick BIOS off this hardware and reset, so we won't get | |
413 | * interrupts from any previous setup. | |
414 | */ | |
415 | reset_hc(uhci); | |
416 | return 0; | |
417 | } | |
418 | ||
419 | /* | |
420 | * Allocate a frame list, and then setup the skeleton | |
421 | * | |
422 | * The hardware doesn't really know any difference | |
423 | * in the queues, but the order does matter for the | |
424 | * protocols higher up. The order is: | |
425 | * | |
426 | * - any isochronous events handled before any | |
427 | * of the queues. We don't do that here, because | |
428 | * we'll create the actual TD entries on demand. | |
429 | * - The first queue is the interrupt queue. | |
430 | * - The second queue is the control queue, split into low- and full-speed | |
431 | * - The third queue is bulk queue. | |
432 | * - The fourth queue is the bandwidth reclamation queue, which loops back | |
433 | * to the full-speed control queue. | |
434 | */ | |
435 | static int uhci_start(struct usb_hcd *hcd) | |
436 | { | |
437 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
438 | int retval = -EBUSY; | |
439 | int i, port; | |
440 | unsigned io_size; | |
441 | dma_addr_t dma_handle; | |
442 | struct usb_device *udev; | |
443 | struct dentry *dentry; | |
444 | ||
445 | io_size = (unsigned) hcd->rsrc_len; | |
446 | ||
447 | dentry = debugfs_create_file(hcd->self.bus_name, S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root, uhci, &uhci_debug_operations); | |
448 | if (!dentry) { | |
449 | dev_err(uhci_dev(uhci), "couldn't create uhci debugfs entry\n"); | |
450 | retval = -ENOMEM; | |
451 | goto err_create_debug_entry; | |
452 | } | |
453 | uhci->dentry = dentry; | |
454 | ||
455 | uhci->fsbr = 0; | |
456 | uhci->fsbrtimeout = 0; | |
457 | ||
458 | spin_lock_init(&uhci->lock); | |
459 | INIT_LIST_HEAD(&uhci->qh_remove_list); | |
460 | ||
461 | INIT_LIST_HEAD(&uhci->td_remove_list); | |
462 | ||
463 | INIT_LIST_HEAD(&uhci->urb_remove_list); | |
464 | ||
465 | INIT_LIST_HEAD(&uhci->urb_list); | |
466 | ||
467 | INIT_LIST_HEAD(&uhci->complete_list); | |
468 | ||
469 | init_waitqueue_head(&uhci->waitqh); | |
470 | ||
f5946f82 AS |
471 | init_timer(&uhci->stall_timer); |
472 | uhci->stall_timer.function = stall_callback; | |
473 | uhci->stall_timer.data = (unsigned long) uhci; | |
474 | ||
1da177e4 LT |
475 | uhci->fl = dma_alloc_coherent(uhci_dev(uhci), sizeof(*uhci->fl), |
476 | &dma_handle, 0); | |
477 | if (!uhci->fl) { | |
478 | dev_err(uhci_dev(uhci), "unable to allocate " | |
479 | "consistent memory for frame list\n"); | |
480 | goto err_alloc_fl; | |
481 | } | |
482 | ||
483 | memset((void *)uhci->fl, 0, sizeof(*uhci->fl)); | |
484 | ||
485 | uhci->fl->dma_handle = dma_handle; | |
486 | ||
487 | uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci), | |
488 | sizeof(struct uhci_td), 16, 0); | |
489 | if (!uhci->td_pool) { | |
490 | dev_err(uhci_dev(uhci), "unable to create td dma_pool\n"); | |
491 | goto err_create_td_pool; | |
492 | } | |
493 | ||
494 | uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci), | |
495 | sizeof(struct uhci_qh), 16, 0); | |
496 | if (!uhci->qh_pool) { | |
497 | dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n"); | |
498 | goto err_create_qh_pool; | |
499 | } | |
500 | ||
501 | /* Initialize the root hub */ | |
502 | ||
503 | /* UHCI specs says devices must have 2 ports, but goes on to say */ | |
504 | /* they may have more but give no way to determine how many they */ | |
505 | /* have. However, according to the UHCI spec, Bit 7 is always set */ | |
506 | /* to 1. So we try to use this to our advantage */ | |
507 | for (port = 0; port < (io_size - 0x10) / 2; port++) { | |
508 | unsigned int portstatus; | |
509 | ||
510 | portstatus = inw(uhci->io_addr + 0x10 + (port * 2)); | |
511 | if (!(portstatus & 0x0080)) | |
512 | break; | |
513 | } | |
514 | if (debug) | |
515 | dev_info(uhci_dev(uhci), "detected %d ports\n", port); | |
516 | ||
517 | /* This is experimental so anything less than 2 or greater than 8 is */ | |
518 | /* something weird and we'll ignore it */ | |
519 | if (port < 2 || port > UHCI_RH_MAXCHILD) { | |
520 | dev_info(uhci_dev(uhci), "port count misdetected? " | |
521 | "forcing to 2 ports\n"); | |
522 | port = 2; | |
523 | } | |
524 | ||
525 | uhci->rh_numports = port; | |
526 | ||
527 | udev = usb_alloc_dev(NULL, &hcd->self, 0); | |
528 | if (!udev) { | |
529 | dev_err(uhci_dev(uhci), "unable to allocate root hub\n"); | |
530 | goto err_alloc_root_hub; | |
531 | } | |
532 | ||
533 | uhci->term_td = uhci_alloc_td(uhci, udev); | |
534 | if (!uhci->term_td) { | |
535 | dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n"); | |
536 | goto err_alloc_term_td; | |
537 | } | |
538 | ||
539 | for (i = 0; i < UHCI_NUM_SKELQH; i++) { | |
540 | uhci->skelqh[i] = uhci_alloc_qh(uhci, udev); | |
541 | if (!uhci->skelqh[i]) { | |
542 | dev_err(uhci_dev(uhci), "unable to allocate QH\n"); | |
543 | goto err_alloc_skelqh; | |
544 | } | |
545 | } | |
546 | ||
547 | /* | |
548 | * 8 Interrupt queues; link all higher int queues to int1, | |
549 | * then link int1 to control and control to bulk | |
550 | */ | |
551 | uhci->skel_int128_qh->link = | |
552 | uhci->skel_int64_qh->link = | |
553 | uhci->skel_int32_qh->link = | |
554 | uhci->skel_int16_qh->link = | |
555 | uhci->skel_int8_qh->link = | |
556 | uhci->skel_int4_qh->link = | |
557 | uhci->skel_int2_qh->link = | |
558 | cpu_to_le32(uhci->skel_int1_qh->dma_handle) | UHCI_PTR_QH; | |
559 | uhci->skel_int1_qh->link = cpu_to_le32(uhci->skel_ls_control_qh->dma_handle) | UHCI_PTR_QH; | |
560 | ||
561 | uhci->skel_ls_control_qh->link = cpu_to_le32(uhci->skel_fs_control_qh->dma_handle) | UHCI_PTR_QH; | |
562 | uhci->skel_fs_control_qh->link = cpu_to_le32(uhci->skel_bulk_qh->dma_handle) | UHCI_PTR_QH; | |
563 | uhci->skel_bulk_qh->link = cpu_to_le32(uhci->skel_term_qh->dma_handle) | UHCI_PTR_QH; | |
564 | ||
565 | /* This dummy TD is to work around a bug in Intel PIIX controllers */ | |
566 | uhci_fill_td(uhci->term_td, 0, (UHCI_NULL_DATA_SIZE << 21) | | |
567 | (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0); | |
568 | uhci->term_td->link = cpu_to_le32(uhci->term_td->dma_handle); | |
569 | ||
570 | uhci->skel_term_qh->link = UHCI_PTR_TERM; | |
571 | uhci->skel_term_qh->element = cpu_to_le32(uhci->term_td->dma_handle); | |
572 | ||
573 | /* | |
574 | * Fill the frame list: make all entries point to the proper | |
575 | * interrupt queue. | |
576 | * | |
577 | * The interrupt queues will be interleaved as evenly as possible. | |
578 | * There's not much to be done about period-1 interrupts; they have | |
579 | * to occur in every frame. But we can schedule period-2 interrupts | |
580 | * in odd-numbered frames, period-4 interrupts in frames congruent | |
581 | * to 2 (mod 4), and so on. This way each frame only has two | |
582 | * interrupt QHs, which will help spread out bandwidth utilization. | |
583 | */ | |
584 | for (i = 0; i < UHCI_NUMFRAMES; i++) { | |
585 | int irq; | |
586 | ||
587 | /* | |
588 | * ffs (Find First bit Set) does exactly what we need: | |
589 | * 1,3,5,... => ffs = 0 => use skel_int2_qh = skelqh[6], | |
590 | * 2,6,10,... => ffs = 1 => use skel_int4_qh = skelqh[5], etc. | |
591 | * ffs > 6 => not on any high-period queue, so use | |
592 | * skel_int1_qh = skelqh[7]. | |
593 | * Add UHCI_NUMFRAMES to insure at least one bit is set. | |
594 | */ | |
595 | irq = 6 - (int) __ffs(i + UHCI_NUMFRAMES); | |
596 | if (irq < 0) | |
597 | irq = 7; | |
598 | ||
599 | /* Only place we don't use the frame list routines */ | |
600 | uhci->fl->frame[i] = UHCI_PTR_QH | | |
601 | cpu_to_le32(uhci->skelqh[irq]->dma_handle); | |
602 | } | |
603 | ||
604 | /* | |
605 | * Some architectures require a full mb() to enforce completion of | |
606 | * the memory writes above before the I/O transfers in start_hc(). | |
607 | */ | |
608 | mb(); | |
609 | if ((retval = start_hc(uhci)) != 0) | |
610 | goto err_alloc_skelqh; | |
611 | ||
f5946f82 | 612 | restart_timer(uhci); |
1da177e4 LT |
613 | |
614 | udev->speed = USB_SPEED_FULL; | |
615 | ||
616 | if (usb_hcd_register_root_hub(udev, hcd) != 0) { | |
617 | dev_err(uhci_dev(uhci), "unable to start root hub\n"); | |
618 | retval = -ENOMEM; | |
619 | goto err_start_root_hub; | |
620 | } | |
621 | ||
622 | return 0; | |
623 | ||
624 | /* | |
625 | * error exits: | |
626 | */ | |
627 | err_start_root_hub: | |
628 | reset_hc(uhci); | |
629 | ||
630 | del_timer_sync(&uhci->stall_timer); | |
631 | ||
632 | err_alloc_skelqh: | |
633 | for (i = 0; i < UHCI_NUM_SKELQH; i++) | |
634 | if (uhci->skelqh[i]) { | |
635 | uhci_free_qh(uhci, uhci->skelqh[i]); | |
636 | uhci->skelqh[i] = NULL; | |
637 | } | |
638 | ||
639 | uhci_free_td(uhci, uhci->term_td); | |
640 | uhci->term_td = NULL; | |
641 | ||
642 | err_alloc_term_td: | |
643 | usb_put_dev(udev); | |
644 | ||
645 | err_alloc_root_hub: | |
646 | dma_pool_destroy(uhci->qh_pool); | |
647 | uhci->qh_pool = NULL; | |
648 | ||
649 | err_create_qh_pool: | |
650 | dma_pool_destroy(uhci->td_pool); | |
651 | uhci->td_pool = NULL; | |
652 | ||
653 | err_create_td_pool: | |
654 | dma_free_coherent(uhci_dev(uhci), sizeof(*uhci->fl), | |
655 | uhci->fl, uhci->fl->dma_handle); | |
656 | uhci->fl = NULL; | |
657 | ||
658 | err_alloc_fl: | |
659 | debugfs_remove(uhci->dentry); | |
660 | uhci->dentry = NULL; | |
661 | ||
662 | err_create_debug_entry: | |
663 | return retval; | |
664 | } | |
665 | ||
666 | static void uhci_stop(struct usb_hcd *hcd) | |
667 | { | |
668 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
669 | ||
670 | del_timer_sync(&uhci->stall_timer); | |
671 | reset_hc(uhci); | |
672 | ||
673 | spin_lock_irq(&uhci->lock); | |
674 | uhci_scan_schedule(uhci, NULL); | |
675 | spin_unlock_irq(&uhci->lock); | |
676 | ||
677 | release_uhci(uhci); | |
678 | } | |
679 | ||
680 | #ifdef CONFIG_PM | |
9a5d3e98 | 681 | static int uhci_suspend(struct usb_hcd *hcd, pm_message_t message) |
1da177e4 LT |
682 | { |
683 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
684 | ||
685 | spin_lock_irq(&uhci->lock); | |
686 | ||
687 | /* Don't try to suspend broken motherboards, reset instead */ | |
688 | if (suspend_allowed(uhci)) | |
689 | suspend_hc(uhci); | |
690 | else { | |
691 | spin_unlock_irq(&uhci->lock); | |
692 | reset_hc(uhci); | |
693 | spin_lock_irq(&uhci->lock); | |
694 | uhci_scan_schedule(uhci, NULL); | |
695 | } | |
696 | ||
697 | spin_unlock_irq(&uhci->lock); | |
698 | return 0; | |
699 | } | |
700 | ||
701 | static int uhci_resume(struct usb_hcd *hcd) | |
702 | { | |
703 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
704 | int rc; | |
705 | ||
706 | pci_set_master(to_pci_dev(uhci_dev(uhci))); | |
707 | ||
708 | spin_lock_irq(&uhci->lock); | |
709 | ||
710 | if (uhci->state == UHCI_SUSPENDED) { | |
711 | ||
712 | /* | |
713 | * Some systems don't maintain the UHCI register values | |
714 | * during a PM suspend/resume cycle, so reinitialize | |
715 | * the Frame Number, Framelist Base Address, Interrupt | |
716 | * Enable, and Legacy Support registers. | |
717 | */ | |
718 | pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, | |
719 | 0); | |
720 | outw(uhci->frame_number, uhci->io_addr + USBFRNUM); | |
721 | outl(uhci->fl->dma_handle, uhci->io_addr + USBFLBASEADD); | |
722 | outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | | |
723 | USBINTR_SP, uhci->io_addr + USBINTR); | |
724 | uhci->resume_detect = 1; | |
725 | pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, | |
726 | USBLEGSUP_DEFAULT); | |
727 | } else { | |
728 | spin_unlock_irq(&uhci->lock); | |
729 | reset_hc(uhci); | |
730 | if ((rc = start_hc(uhci)) != 0) | |
731 | return rc; | |
732 | spin_lock_irq(&uhci->lock); | |
733 | } | |
734 | hcd->state = HC_STATE_RUNNING; | |
735 | ||
736 | spin_unlock_irq(&uhci->lock); | |
737 | return 0; | |
738 | } | |
739 | #endif | |
740 | ||
741 | /* Wait until all the URBs for a particular device/endpoint are gone */ | |
742 | static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd, | |
743 | struct usb_host_endpoint *ep) | |
744 | { | |
745 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
746 | ||
747 | wait_event_interruptible(uhci->waitqh, list_empty(&ep->urb_list)); | |
748 | } | |
749 | ||
750 | static int uhci_hcd_get_frame_number(struct usb_hcd *hcd) | |
751 | { | |
752 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
753 | int frame_number; | |
754 | unsigned long flags; | |
755 | ||
756 | /* Minimize latency by avoiding the spinlock */ | |
757 | local_irq_save(flags); | |
758 | rmb(); | |
759 | frame_number = (uhci->is_stopped ? uhci->frame_number : | |
760 | inw(uhci->io_addr + USBFRNUM)); | |
761 | local_irq_restore(flags); | |
762 | return frame_number; | |
763 | } | |
764 | ||
765 | static const char hcd_name[] = "uhci_hcd"; | |
766 | ||
767 | static const struct hc_driver uhci_driver = { | |
768 | .description = hcd_name, | |
769 | .product_desc = "UHCI Host Controller", | |
770 | .hcd_priv_size = sizeof(struct uhci_hcd), | |
771 | ||
772 | /* Generic hardware linkage */ | |
773 | .irq = uhci_irq, | |
774 | .flags = HCD_USB11, | |
775 | ||
776 | /* Basic lifecycle operations */ | |
777 | .reset = uhci_reset, | |
778 | .start = uhci_start, | |
779 | #ifdef CONFIG_PM | |
780 | .suspend = uhci_suspend, | |
781 | .resume = uhci_resume, | |
782 | #endif | |
783 | .stop = uhci_stop, | |
784 | ||
785 | .urb_enqueue = uhci_urb_enqueue, | |
786 | .urb_dequeue = uhci_urb_dequeue, | |
787 | ||
788 | .endpoint_disable = uhci_hcd_endpoint_disable, | |
789 | .get_frame_number = uhci_hcd_get_frame_number, | |
790 | ||
791 | .hub_status_data = uhci_hub_status_data, | |
792 | .hub_control = uhci_hub_control, | |
793 | }; | |
794 | ||
795 | static const struct pci_device_id uhci_pci_ids[] = { { | |
796 | /* handle any USB UHCI controller */ | |
797 | PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x00), ~0), | |
798 | .driver_data = (unsigned long) &uhci_driver, | |
799 | }, { /* end: all zeroes */ } | |
800 | }; | |
801 | ||
802 | MODULE_DEVICE_TABLE(pci, uhci_pci_ids); | |
803 | ||
804 | static struct pci_driver uhci_pci_driver = { | |
805 | .name = (char *)hcd_name, | |
806 | .id_table = uhci_pci_ids, | |
807 | ||
808 | .probe = usb_hcd_pci_probe, | |
809 | .remove = usb_hcd_pci_remove, | |
810 | ||
811 | #ifdef CONFIG_PM | |
812 | .suspend = usb_hcd_pci_suspend, | |
813 | .resume = usb_hcd_pci_resume, | |
814 | #endif /* PM */ | |
815 | }; | |
816 | ||
817 | static int __init uhci_hcd_init(void) | |
818 | { | |
819 | int retval = -ENOMEM; | |
820 | ||
821 | printk(KERN_INFO DRIVER_DESC " " DRIVER_VERSION "\n"); | |
822 | ||
823 | if (usb_disabled()) | |
824 | return -ENODEV; | |
825 | ||
826 | if (debug) { | |
827 | errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL); | |
828 | if (!errbuf) | |
829 | goto errbuf_failed; | |
830 | } | |
831 | ||
832 | uhci_debugfs_root = debugfs_create_dir("uhci", NULL); | |
833 | if (!uhci_debugfs_root) | |
834 | goto debug_failed; | |
835 | ||
836 | uhci_up_cachep = kmem_cache_create("uhci_urb_priv", | |
837 | sizeof(struct urb_priv), 0, 0, NULL, NULL); | |
838 | if (!uhci_up_cachep) | |
839 | goto up_failed; | |
840 | ||
841 | retval = pci_register_driver(&uhci_pci_driver); | |
842 | if (retval) | |
843 | goto init_failed; | |
844 | ||
845 | return 0; | |
846 | ||
847 | init_failed: | |
848 | if (kmem_cache_destroy(uhci_up_cachep)) | |
849 | warn("not all urb_priv's were freed!"); | |
850 | ||
851 | up_failed: | |
852 | debugfs_remove(uhci_debugfs_root); | |
853 | ||
854 | debug_failed: | |
1bc3c9e1 | 855 | kfree(errbuf); |
1da177e4 LT |
856 | |
857 | errbuf_failed: | |
858 | ||
859 | return retval; | |
860 | } | |
861 | ||
862 | static void __exit uhci_hcd_cleanup(void) | |
863 | { | |
864 | pci_unregister_driver(&uhci_pci_driver); | |
865 | ||
866 | if (kmem_cache_destroy(uhci_up_cachep)) | |
867 | warn("not all urb_priv's were freed!"); | |
868 | ||
869 | debugfs_remove(uhci_debugfs_root); | |
1bc3c9e1 | 870 | kfree(errbuf); |
1da177e4 LT |
871 | } |
872 | ||
873 | module_init(uhci_hcd_init); | |
874 | module_exit(uhci_hcd_cleanup); | |
875 | ||
876 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
877 | MODULE_DESCRIPTION(DRIVER_DESC); | |
878 | MODULE_LICENSE("GPL"); |