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1da177e4 LT |
1 | #ifndef __LINUX_UHCI_HCD_H |
2 | #define __LINUX_UHCI_HCD_H | |
3 | ||
4 | #include <linux/list.h> | |
5 | #include <linux/usb.h> | |
6 | ||
7 | #define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT) | |
8 | #define PIPE_DEVEP_MASK 0x0007ff00 | |
9 | ||
8b262bd2 | 10 | |
1da177e4 LT |
11 | /* |
12 | * Universal Host Controller Interface data structures and defines | |
13 | */ | |
14 | ||
15 | /* Command register */ | |
16 | #define USBCMD 0 | |
17 | #define USBCMD_RS 0x0001 /* Run/Stop */ | |
18 | #define USBCMD_HCRESET 0x0002 /* Host reset */ | |
19 | #define USBCMD_GRESET 0x0004 /* Global reset */ | |
20 | #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */ | |
21 | #define USBCMD_FGR 0x0010 /* Force Global Resume */ | |
22 | #define USBCMD_SWDBG 0x0020 /* SW Debug mode */ | |
23 | #define USBCMD_CF 0x0040 /* Config Flag (sw only) */ | |
24 | #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */ | |
25 | ||
26 | /* Status register */ | |
27 | #define USBSTS 2 | |
28 | #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */ | |
29 | #define USBSTS_ERROR 0x0002 /* Interrupt due to error */ | |
30 | #define USBSTS_RD 0x0004 /* Resume Detect */ | |
dccf4a48 AS |
31 | #define USBSTS_HSE 0x0008 /* Host System Error: PCI problems */ |
32 | #define USBSTS_HCPE 0x0010 /* Host Controller Process Error: | |
33 | * the schedule is buggy */ | |
1da177e4 LT |
34 | #define USBSTS_HCH 0x0020 /* HC Halted */ |
35 | ||
36 | /* Interrupt enable register */ | |
37 | #define USBINTR 4 | |
38 | #define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */ | |
39 | #define USBINTR_RESUME 0x0002 /* Resume interrupt enable */ | |
40 | #define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */ | |
41 | #define USBINTR_SP 0x0008 /* Short packet interrupt enable */ | |
42 | ||
43 | #define USBFRNUM 6 | |
44 | #define USBFLBASEADD 8 | |
45 | #define USBSOF 12 | |
a8bed8b6 | 46 | #define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */ |
1da177e4 LT |
47 | |
48 | /* USB port status and control registers */ | |
49 | #define USBPORTSC1 16 | |
50 | #define USBPORTSC2 18 | |
dccf4a48 AS |
51 | #define USBPORTSC_CCS 0x0001 /* Current Connect Status |
52 | * ("device present") */ | |
1da177e4 LT |
53 | #define USBPORTSC_CSC 0x0002 /* Connect Status Change */ |
54 | #define USBPORTSC_PE 0x0004 /* Port Enable */ | |
55 | #define USBPORTSC_PEC 0x0008 /* Port Enable Change */ | |
56 | #define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */ | |
57 | #define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */ | |
58 | #define USBPORTSC_RD 0x0040 /* Resume Detect */ | |
59 | #define USBPORTSC_RES1 0x0080 /* reserved, always 1 */ | |
60 | #define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */ | |
61 | #define USBPORTSC_PR 0x0200 /* Port Reset */ | |
62 | /* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */ | |
63 | #define USBPORTSC_OC 0x0400 /* Over Current condition */ | |
64 | #define USBPORTSC_OCC 0x0800 /* Over Current Change R/WC */ | |
65 | #define USBPORTSC_SUSP 0x1000 /* Suspend */ | |
66 | #define USBPORTSC_RES2 0x2000 /* reserved, write zeroes */ | |
67 | #define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */ | |
68 | #define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */ | |
69 | ||
0d436b42 | 70 | /* PCI legacy support register */ |
1da177e4 LT |
71 | #define USBLEGSUP 0xc0 |
72 | #define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ | |
a8bed8b6 AS |
73 | #define USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ |
74 | #define USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ | |
1da177e4 | 75 | |
0d436b42 AS |
76 | /* PCI Intel-specific resume-enable register */ |
77 | #define USBRES_INTEL 0xc4 | |
78 | #define USBPORT1EN 0x01 | |
79 | #define USBPORT2EN 0x02 | |
80 | ||
51e2f62f JA |
81 | #define UHCI_PTR_BITS(uhci) cpu_to_hc32((uhci), 0x000F) |
82 | #define UHCI_PTR_TERM(uhci) cpu_to_hc32((uhci), 0x0001) | |
83 | #define UHCI_PTR_QH(uhci) cpu_to_hc32((uhci), 0x0002) | |
84 | #define UHCI_PTR_DEPTH(uhci) cpu_to_hc32((uhci), 0x0004) | |
85 | #define UHCI_PTR_BREADTH(uhci) cpu_to_hc32((uhci), 0x0000) | |
1da177e4 LT |
86 | |
87 | #define UHCI_NUMFRAMES 1024 /* in the frame list [array] */ | |
88 | #define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */ | |
dccf4a48 AS |
89 | #define CAN_SCHEDULE_FRAMES 1000 /* how far in the future frames |
90 | * can be scheduled */ | |
3ca2a321 | 91 | #define MAX_PHASE 32 /* Periodic scheduling length */ |
1da177e4 | 92 | |
84afddd7 AS |
93 | /* When no queues need Full-Speed Bandwidth Reclamation, |
94 | * delay this long before turning FSBR off */ | |
c5e3b741 | 95 | #define FSBR_OFF_DELAY msecs_to_jiffies(10) |
84afddd7 AS |
96 | |
97 | /* If a queue hasn't advanced after this much time, assume it is stuck */ | |
98 | #define QH_WAIT_TIMEOUT msecs_to_jiffies(200) | |
99 | ||
1da177e4 | 100 | |
51e2f62f JA |
101 | /* |
102 | * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to | |
103 | * __leXX (normally) or __beXX (given UHCI_BIG_ENDIAN_DESC), depending on | |
104 | * the host controller implementation. | |
105 | * | |
106 | * To facilitate the strongest possible byte-order checking from "sparse" | |
107 | * and so on, we use __leXX unless that's not practical. | |
108 | */ | |
109 | #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC | |
110 | typedef __u32 __bitwise __hc32; | |
111 | typedef __u16 __bitwise __hc16; | |
112 | #else | |
113 | #define __hc32 __le32 | |
114 | #define __hc16 __le16 | |
115 | #endif | |
116 | ||
8b262bd2 AS |
117 | /* |
118 | * Queue Headers | |
119 | */ | |
1da177e4 LT |
120 | |
121 | /* | |
dccf4a48 AS |
122 | * One role of a QH is to hold a queue of TDs for some endpoint. One QH goes |
123 | * with each endpoint, and qh->element (updated by the HC) is either: | |
124 | * - the next unprocessed TD in the endpoint's queue, or | |
125 | * - UHCI_PTR_TERM (when there's no more traffic for this endpoint). | |
1da177e4 LT |
126 | * |
127 | * The other role of a QH is to serve as a "skeleton" framelist entry, so we | |
128 | * can easily splice a QH for some endpoint into the schedule at the right | |
129 | * place. Then qh->element is UHCI_PTR_TERM. | |
130 | * | |
dccf4a48 | 131 | * In the schedule, qh->link maintains a list of QHs seen by the HC: |
1da177e4 | 132 | * skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ... |
dccf4a48 AS |
133 | * |
134 | * qh->node is the software equivalent of qh->link. The differences | |
135 | * are that the software list is doubly-linked and QHs in the UNLINKING | |
136 | * state are on the software list but not the hardware schedule. | |
137 | * | |
138 | * For bookkeeping purposes we maintain QHs even for Isochronous endpoints, | |
139 | * but they never get added to the hardware schedule. | |
1da177e4 | 140 | */ |
dccf4a48 AS |
141 | #define QH_STATE_IDLE 1 /* QH is not being used */ |
142 | #define QH_STATE_UNLINKING 2 /* QH has been removed from the | |
143 | * schedule but the hardware may | |
144 | * still be using it */ | |
145 | #define QH_STATE_ACTIVE 3 /* QH is on the schedule */ | |
146 | ||
1da177e4 LT |
147 | struct uhci_qh { |
148 | /* Hardware fields */ | |
51e2f62f JA |
149 | __hc32 link; /* Next QH in the schedule */ |
150 | __hc32 element; /* Queue element (TD) pointer */ | |
1da177e4 LT |
151 | |
152 | /* Software fields */ | |
28b9325e AS |
153 | dma_addr_t dma_handle; |
154 | ||
dccf4a48 AS |
155 | struct list_head node; /* Node in the list of QHs */ |
156 | struct usb_host_endpoint *hep; /* Endpoint information */ | |
157 | struct usb_device *udev; | |
158 | struct list_head queue; /* Queue of urbps for this QH */ | |
af0bb599 | 159 | struct uhci_td *dummy_td; /* Dummy TD to end the queue */ |
59e29ed9 | 160 | struct uhci_td *post_td; /* Last TD completed */ |
1da177e4 | 161 | |
c8155cc5 AS |
162 | struct usb_iso_packet_descriptor *iso_packet_desc; |
163 | /* Next urb->iso_frame_desc entry */ | |
84afddd7 | 164 | unsigned long advance_jiffies; /* Time of last queue advance */ |
dccf4a48 | 165 | unsigned int unlink_frame; /* When the QH was unlinked */ |
caf3827a | 166 | unsigned int period; /* For Interrupt and Isochronous QHs */ |
3ca2a321 AS |
167 | short phase; /* Between 0 and period-1 */ |
168 | short load; /* Periodic time requirement, in us */ | |
c8155cc5 | 169 | unsigned int iso_frame; /* Frame # for iso_packet_desc */ |
caf3827a | 170 | |
dccf4a48 | 171 | int state; /* QH_STATE_xxx; see above */ |
4de7d2c2 | 172 | int type; /* Queue type (control, bulk, etc) */ |
17230acd | 173 | int skel; /* Skeleton queue number */ |
0ed8fee1 AS |
174 | |
175 | unsigned int initial_toggle:1; /* Endpoint's current toggle value */ | |
176 | unsigned int needs_fixup:1; /* Must fix the TD toggle values */ | |
59e29ed9 | 177 | unsigned int is_stopped:1; /* Queue was stopped by error/unlink */ |
84afddd7 | 178 | unsigned int wait_expired:1; /* QH_WAIT_TIMEOUT has expired */ |
3ca2a321 AS |
179 | unsigned int bandwidth_reserved:1; /* Periodic bandwidth has |
180 | * been allocated */ | |
1da177e4 LT |
181 | } __attribute__((aligned(16))); |
182 | ||
183 | /* | |
184 | * We need a special accessor for the element pointer because it is | |
8b262bd2 | 185 | * subject to asynchronous updates by the controller. |
1da177e4 | 186 | */ |
bab1ff1b | 187 | #define qh_element(qh) ACCESS_ONCE((qh)->element) |
1da177e4 | 188 | |
51e2f62f JA |
189 | #define LINK_TO_QH(uhci, qh) (UHCI_PTR_QH((uhci)) | \ |
190 | cpu_to_hc32((uhci), (qh)->dma_handle)) | |
28b9325e | 191 | |
8b262bd2 AS |
192 | |
193 | /* | |
194 | * Transfer Descriptors | |
195 | */ | |
196 | ||
1da177e4 LT |
197 | /* |
198 | * for TD <status>: | |
199 | */ | |
200 | #define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ | |
201 | #define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ | |
202 | #define TD_CTRL_C_ERR_SHIFT 27 | |
203 | #define TD_CTRL_LS (1 << 26) /* Low Speed Device */ | |
204 | #define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ | |
205 | #define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ | |
206 | #define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ | |
207 | #define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ | |
208 | #define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ | |
209 | #define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ | |
210 | #define TD_CTRL_NAK (1 << 19) /* NAK Received */ | |
211 | #define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ | |
212 | #define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ | |
213 | #define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */ | |
214 | ||
1da177e4 LT |
215 | #define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT) |
216 | #define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000) | |
dccf4a48 AS |
217 | #define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & \ |
218 | TD_CTRL_ACTLEN_MASK) /* 1-based */ | |
1da177e4 LT |
219 | |
220 | /* | |
221 | * for TD <info>: (a.k.a. Token) | |
222 | */ | |
51e2f62f | 223 | #define td_token(uhci, td) hc32_to_cpu((uhci), (td)->token) |
1da177e4 LT |
224 | #define TD_TOKEN_DEVADDR_SHIFT 8 |
225 | #define TD_TOKEN_TOGGLE_SHIFT 19 | |
226 | #define TD_TOKEN_TOGGLE (1 << 19) | |
227 | #define TD_TOKEN_EXPLEN_SHIFT 21 | |
dccf4a48 | 228 | #define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n-1 */ |
1da177e4 LT |
229 | #define TD_TOKEN_PID_MASK 0xFF |
230 | ||
fa346568 AS |
231 | #define uhci_explen(len) ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \ |
232 | TD_TOKEN_EXPLEN_SHIFT) | |
1da177e4 | 233 | |
fa346568 AS |
234 | #define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \ |
235 | 1) & TD_TOKEN_EXPLEN_MASK) | |
1da177e4 LT |
236 | #define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1) |
237 | #define uhci_endpoint(token) (((token) >> 15) & 0xf) | |
238 | #define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f) | |
239 | #define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff) | |
240 | #define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK) | |
241 | #define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN) | |
242 | #define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN) | |
243 | ||
244 | /* | |
245 | * The documentation says "4 words for hardware, 4 words for software". | |
246 | * | |
247 | * That's silly, the hardware doesn't care. The hardware only cares that | |
248 | * the hardware words are 16-byte aligned, and we can have any amount of | |
8b262bd2 | 249 | * sw space after the TD entry. |
1da177e4 LT |
250 | * |
251 | * td->link points to either another TD (not necessarily for the same urb or | |
dccf4a48 | 252 | * even the same endpoint), or nothing (PTR_TERM), or a QH. |
1da177e4 LT |
253 | */ |
254 | struct uhci_td { | |
255 | /* Hardware fields */ | |
51e2f62f JA |
256 | __hc32 link; |
257 | __hc32 status; | |
258 | __hc32 token; | |
259 | __hc32 buffer; | |
1da177e4 LT |
260 | |
261 | /* Software fields */ | |
262 | dma_addr_t dma_handle; | |
263 | ||
8b262bd2 | 264 | struct list_head list; |
1da177e4 LT |
265 | |
266 | int frame; /* for iso: what frame? */ | |
8b262bd2 | 267 | struct list_head fl_list; |
1da177e4 LT |
268 | } __attribute__((aligned(16))); |
269 | ||
270 | /* | |
271 | * We need a special accessor for the control/status word because it is | |
8b262bd2 | 272 | * subject to asynchronous updates by the controller. |
1da177e4 | 273 | */ |
51e2f62f JA |
274 | #define td_status(uhci, td) hc32_to_cpu((uhci), \ |
275 | ACCESS_ONCE((td)->status)) | |
1da177e4 | 276 | |
51e2f62f | 277 | #define LINK_TO_TD(uhci, td) (cpu_to_hc32((uhci), (td)->dma_handle)) |
28b9325e | 278 | |
1da177e4 | 279 | |
8b262bd2 AS |
280 | /* |
281 | * Skeleton Queue Headers | |
282 | */ | |
283 | ||
1da177e4 | 284 | /* |
dccf4a48 AS |
285 | * The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for |
286 | * automatic queuing. To make it easy to insert entries into the schedule, | |
17230acd AS |
287 | * we have a skeleton of QHs for each predefined Interrupt latency. |
288 | * Asynchronous QHs (low-speed control, full-speed control, and bulk) | |
289 | * go onto the period-1 interrupt list, since they all get accessed on | |
290 | * every frame. | |
1da177e4 | 291 | * |
17230acd AS |
292 | * When we want to add a new QH, we add it to the list starting from the |
293 | * appropriate skeleton QH. For instance, the schedule can look like this: | |
1da177e4 LT |
294 | * |
295 | * skel int128 QH | |
296 | * dev 1 interrupt QH | |
297 | * dev 5 interrupt QH | |
298 | * skel int64 QH | |
299 | * skel int32 QH | |
300 | * ... | |
17230acd AS |
301 | * skel int1 + async QH |
302 | * dev 5 low-speed control QH | |
1da177e4 LT |
303 | * dev 1 bulk QH |
304 | * dev 2 bulk QH | |
1da177e4 | 305 | * |
17230acd AS |
306 | * There is a special terminating QH used to keep full-speed bandwidth |
307 | * reclamation active when no full-speed control or bulk QHs are linked | |
308 | * into the schedule. It has an inactive TD (to work around a PIIX bug, | |
309 | * see the Intel errata) and it points back to itself. | |
1da177e4 | 310 | * |
17230acd AS |
311 | * There's a special skeleton QH for Isochronous QHs which never appears |
312 | * on the schedule. Isochronous TDs go on the schedule before the | |
dccf4a48 AS |
313 | * the skeleton QHs. The hardware accesses them directly rather than |
314 | * through their QH, which is used only for bookkeeping purposes. | |
315 | * While the UHCI spec doesn't forbid the use of QHs for Isochronous, | |
316 | * it doesn't use them either. And the spec says that queues never | |
317 | * advance on an error completion status, which makes them totally | |
318 | * unsuitable for Isochronous transfers. | |
17230acd AS |
319 | * |
320 | * There's also a special skeleton QH used for QHs which are in the process | |
321 | * of unlinking and so may still be in use by the hardware. It too never | |
322 | * appears on the schedule. | |
1da177e4 LT |
323 | */ |
324 | ||
17230acd AS |
325 | #define UHCI_NUM_SKELQH 11 |
326 | #define SKEL_UNLINK 0 | |
327 | #define skel_unlink_qh skelqh[SKEL_UNLINK] | |
328 | #define SKEL_ISO 1 | |
329 | #define skel_iso_qh skelqh[SKEL_ISO] | |
330 | /* int128, int64, ..., int1 = 2, 3, ..., 9 */ | |
331 | #define SKEL_INDEX(exponent) (9 - exponent) | |
332 | #define SKEL_ASYNC 9 | |
333 | #define skel_async_qh skelqh[SKEL_ASYNC] | |
334 | #define SKEL_TERM 10 | |
335 | #define skel_term_qh skelqh[SKEL_TERM] | |
336 | ||
337 | /* The following entries refer to sublists of skel_async_qh */ | |
338 | #define SKEL_LS_CONTROL 20 | |
339 | #define SKEL_FS_CONTROL 21 | |
340 | #define SKEL_FSBR SKEL_FS_CONTROL | |
341 | #define SKEL_BULK 22 | |
8b262bd2 AS |
342 | |
343 | /* | |
344 | * The UHCI controller and root hub | |
345 | */ | |
346 | ||
1da177e4 | 347 | /* |
8b262bd2 | 348 | * States for the root hub: |
1da177e4 LT |
349 | * |
350 | * To prevent "bouncing" in the presence of electrical noise, | |
c8f4fe43 AS |
351 | * when there are no devices attached we delay for 1 second in the |
352 | * RUNNING_NODEVS state before switching to the AUTO_STOPPED state. | |
353 | * | |
354 | * (Note that the AUTO_STOPPED state won't be necessary once the hub | |
355 | * driver learns to autosuspend.) | |
1da177e4 | 356 | */ |
c8f4fe43 | 357 | enum uhci_rh_state { |
6c1b445c | 358 | /* In the following states the HC must be halted. |
8b262bd2 | 359 | * These two must come first. */ |
6c1b445c | 360 | UHCI_RH_RESET, |
c8f4fe43 | 361 | UHCI_RH_SUSPENDED, |
a8bed8b6 | 362 | |
c8f4fe43 AS |
363 | UHCI_RH_AUTO_STOPPED, |
364 | UHCI_RH_RESUMING, | |
365 | ||
6c1b445c AS |
366 | /* In this state the HC changes from running to halted, |
367 | * so it can legally appear either way. */ | |
c8f4fe43 AS |
368 | UHCI_RH_SUSPENDING, |
369 | ||
6c1b445c | 370 | /* In the following states it's an error if the HC is halted. |
8b262bd2 | 371 | * These two must come last. */ |
c8f4fe43 AS |
372 | UHCI_RH_RUNNING, /* The normal state */ |
373 | UHCI_RH_RUNNING_NODEVS, /* Running with no devices attached */ | |
1da177e4 LT |
374 | }; |
375 | ||
376 | /* | |
8b262bd2 | 377 | * The full UHCI controller information: |
1da177e4 LT |
378 | */ |
379 | struct uhci_hcd { | |
380 | ||
381 | /* debugfs */ | |
382 | struct dentry *dentry; | |
383 | ||
384 | /* Grabbed from PCI */ | |
385 | unsigned long io_addr; | |
386 | ||
d3219d1c JA |
387 | /* Used when registers are memory mapped */ |
388 | void __iomem *regs; | |
389 | ||
1da177e4 LT |
390 | struct dma_pool *qh_pool; |
391 | struct dma_pool *td_pool; | |
392 | ||
1da177e4 | 393 | struct uhci_td *term_td; /* Terminating TD, see UHCI bug */ |
687f5f34 | 394 | struct uhci_qh *skelqh[UHCI_NUM_SKELQH]; /* Skeleton QHs */ |
0ed8fee1 | 395 | struct uhci_qh *next_qh; /* Next QH to scan */ |
1da177e4 LT |
396 | |
397 | spinlock_t lock; | |
a1d59ce8 | 398 | |
dccf4a48 | 399 | dma_addr_t frame_dma_handle; /* Hardware frame list */ |
51e2f62f | 400 | __hc32 *frame; |
dccf4a48 | 401 | void **frame_cpu; /* CPU's frame list */ |
a1d59ce8 | 402 | |
c8f4fe43 AS |
403 | enum uhci_rh_state rh_state; |
404 | unsigned long auto_stop_time; /* When to AUTO_STOP */ | |
405 | ||
1da177e4 LT |
406 | unsigned int frame_number; /* As of last check */ |
407 | unsigned int is_stopped; | |
408 | #define UHCI_IS_STOPPED 9999 /* Larger than a frame # */ | |
c8155cc5 AS |
409 | unsigned int last_iso_frame; /* Frame of last scan */ |
410 | unsigned int cur_iso_frame; /* Frame for current scan */ | |
1da177e4 LT |
411 | |
412 | unsigned int scan_in_progress:1; /* Schedule scan is running */ | |
413 | unsigned int need_rescan:1; /* Redo the schedule scan */ | |
e323de46 | 414 | unsigned int dead:1; /* Controller has died */ |
d8f12ab5 AS |
415 | unsigned int RD_enable:1; /* Suspended root hub with |
416 | Resume-Detect interrupts | |
417 | enabled */ | |
8d402e1a | 418 | unsigned int is_initialized:1; /* Data structure is usable */ |
84afddd7 | 419 | unsigned int fsbr_is_on:1; /* FSBR is turned on */ |
c5e3b741 AS |
420 | unsigned int fsbr_is_wanted:1; /* Does any URB want FSBR? */ |
421 | unsigned int fsbr_expiring:1; /* FSBR is timing out */ | |
422 | ||
423 | struct timer_list fsbr_timer; /* For turning off FBSR */ | |
1da177e4 | 424 | |
dfeca7a8 JA |
425 | /* Silicon quirks */ |
426 | unsigned int oc_low:1; /* OverCurrent bit active low */ | |
427 | unsigned int wait_for_hp:1; /* Wait for HP port reset */ | |
8452c674 | 428 | unsigned int big_endian_mmio:1; /* Big endian registers */ |
51e2f62f | 429 | unsigned int big_endian_desc:1; /* Big endian descriptors */ |
dfeca7a8 | 430 | |
1da177e4 LT |
431 | /* Support for port suspend/resume/reset */ |
432 | unsigned long port_c_suspend; /* Bit-arrays of ports */ | |
1da177e4 LT |
433 | unsigned long resuming_ports; |
434 | unsigned long ports_timeout; /* Time to stop signalling */ | |
435 | ||
dccf4a48 AS |
436 | struct list_head idle_qh_list; /* Where the idle QHs live */ |
437 | ||
1f09df8b | 438 | int rh_numports; /* Number of root-hub ports */ |
1da177e4 LT |
439 | |
440 | wait_queue_head_t waitqh; /* endpoint_disable waiters */ | |
dccf4a48 | 441 | int num_waiting; /* Number of waiters */ |
3ca2a321 AS |
442 | |
443 | int total_load; /* Sum of array values */ | |
444 | short load[MAX_PHASE]; /* Periodic allocations */ | |
e7652e1e JA |
445 | |
446 | /* Reset host controller */ | |
447 | void (*reset_hc) (struct uhci_hcd *uhci); | |
448 | int (*check_and_reset_hc) (struct uhci_hcd *uhci); | |
449 | /* configure_hc should perform arch specific settings, if needed */ | |
450 | void (*configure_hc) (struct uhci_hcd *uhci); | |
451 | /* Check for broken resume detect interrupts */ | |
452 | int (*resume_detect_interrupts_are_broken) (struct uhci_hcd *uhci); | |
453 | /* Check for broken global suspend */ | |
454 | int (*global_suspend_mode_is_broken) (struct uhci_hcd *uhci); | |
1da177e4 LT |
455 | }; |
456 | ||
457 | /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */ | |
458 | static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd) | |
459 | { | |
460 | return (struct uhci_hcd *) (hcd->hcd_priv); | |
461 | } | |
462 | static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci) | |
463 | { | |
464 | return container_of((void *) uhci, struct usb_hcd, hcd_priv); | |
465 | } | |
466 | ||
467 | #define uhci_dev(u) (uhci_to_hcd(u)->self.controller) | |
468 | ||
c4334726 AS |
469 | /* Utility macro for comparing frame numbers */ |
470 | #define uhci_frame_before_eq(f1, f2) (0 <= (int) ((f2) - (f1))) | |
471 | ||
8b262bd2 AS |
472 | |
473 | /* | |
474 | * Private per-URB data | |
475 | */ | |
1da177e4 | 476 | struct urb_priv { |
dccf4a48 | 477 | struct list_head node; /* Node in the QH's urbp list */ |
1da177e4 LT |
478 | |
479 | struct urb *urb; | |
480 | ||
481 | struct uhci_qh *qh; /* QH for this URB */ | |
8b262bd2 | 482 | struct list_head td_list; |
1da177e4 | 483 | |
84afddd7 | 484 | unsigned fsbr:1; /* URB wants FSBR */ |
1da177e4 LT |
485 | }; |
486 | ||
8b262bd2 | 487 | |
c8f4fe43 AS |
488 | /* Some special IDs */ |
489 | ||
490 | #define PCI_VENDOR_ID_GENESYS 0x17a0 | |
491 | #define PCI_DEVICE_ID_GL880S_UHCI 0x8083 | |
c8f4fe43 | 492 | |
d3219d1c JA |
493 | /* |
494 | * Functions used to access controller registers. The UCHI spec says that host | |
495 | * controller I/O registers are mapped into PCI I/O space. For non-PCI hosts | |
496 | * we use memory mapped registers. | |
497 | */ | |
498 | ||
8452c674 | 499 | #ifndef CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC |
d3219d1c | 500 | /* Support PCI only */ |
8452c674 | 501 | static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg) |
9faa091a JA |
502 | { |
503 | return inl(uhci->io_addr + reg); | |
504 | } | |
505 | ||
8452c674 | 506 | static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg) |
9faa091a JA |
507 | { |
508 | outl(val, uhci->io_addr + reg); | |
509 | } | |
510 | ||
8452c674 | 511 | static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg) |
9faa091a JA |
512 | { |
513 | return inw(uhci->io_addr + reg); | |
514 | } | |
515 | ||
8452c674 | 516 | static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg) |
9faa091a JA |
517 | { |
518 | outw(val, uhci->io_addr + reg); | |
519 | } | |
520 | ||
8452c674 | 521 | static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg) |
9faa091a JA |
522 | { |
523 | return inb(uhci->io_addr + reg); | |
524 | } | |
525 | ||
8452c674 | 526 | static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg) |
9faa091a JA |
527 | { |
528 | outb(val, uhci->io_addr + reg); | |
529 | } | |
530 | ||
d3219d1c | 531 | #else |
8452c674 JA |
532 | /* Support non-PCI host controllers */ |
533 | #ifdef CONFIG_PCI | |
d3219d1c | 534 | /* Support PCI and non-PCI host controllers */ |
d3219d1c | 535 | #define uhci_has_pci_registers(u) ((u)->io_addr != 0) |
8452c674 JA |
536 | #else |
537 | /* Support non-PCI host controllers only */ | |
538 | #define uhci_has_pci_registers(u) 0 | |
539 | #endif | |
540 | ||
541 | #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO | |
542 | /* Support (non-PCI) big endian host controllers */ | |
543 | #define uhci_big_endian_mmio(u) ((u)->big_endian_mmio) | |
544 | #else | |
545 | #define uhci_big_endian_mmio(u) 0 | |
546 | #endif | |
d3219d1c | 547 | |
8452c674 | 548 | static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg) |
d3219d1c JA |
549 | { |
550 | if (uhci_has_pci_registers(uhci)) | |
551 | return inl(uhci->io_addr + reg); | |
8452c674 JA |
552 | #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO |
553 | else if (uhci_big_endian_mmio(uhci)) | |
554 | return readl_be(uhci->regs + reg); | |
555 | #endif | |
d3219d1c JA |
556 | else |
557 | return readl(uhci->regs + reg); | |
558 | } | |
559 | ||
8452c674 | 560 | static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg) |
d3219d1c JA |
561 | { |
562 | if (uhci_has_pci_registers(uhci)) | |
563 | outl(val, uhci->io_addr + reg); | |
8452c674 JA |
564 | #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO |
565 | else if (uhci_big_endian_mmio(uhci)) | |
566 | writel_be(val, uhci->regs + reg); | |
567 | #endif | |
d3219d1c JA |
568 | else |
569 | writel(val, uhci->regs + reg); | |
570 | } | |
571 | ||
8452c674 | 572 | static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg) |
d3219d1c JA |
573 | { |
574 | if (uhci_has_pci_registers(uhci)) | |
575 | return inw(uhci->io_addr + reg); | |
8452c674 JA |
576 | #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO |
577 | else if (uhci_big_endian_mmio(uhci)) | |
578 | return readw_be(uhci->regs + reg); | |
579 | #endif | |
d3219d1c JA |
580 | else |
581 | return readw(uhci->regs + reg); | |
582 | } | |
583 | ||
8452c674 | 584 | static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg) |
d3219d1c JA |
585 | { |
586 | if (uhci_has_pci_registers(uhci)) | |
587 | outw(val, uhci->io_addr + reg); | |
8452c674 JA |
588 | #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO |
589 | else if (uhci_big_endian_mmio(uhci)) | |
590 | writew_be(val, uhci->regs + reg); | |
591 | #endif | |
d3219d1c JA |
592 | else |
593 | writew(val, uhci->regs + reg); | |
594 | } | |
595 | ||
8452c674 | 596 | static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg) |
d3219d1c JA |
597 | { |
598 | if (uhci_has_pci_registers(uhci)) | |
599 | return inb(uhci->io_addr + reg); | |
8452c674 JA |
600 | #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO |
601 | else if (uhci_big_endian_mmio(uhci)) | |
602 | return readb_be(uhci->regs + reg); | |
603 | #endif | |
d3219d1c JA |
604 | else |
605 | return readb(uhci->regs + reg); | |
606 | } | |
607 | ||
8452c674 | 608 | static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg) |
d3219d1c JA |
609 | { |
610 | if (uhci_has_pci_registers(uhci)) | |
611 | outb(val, uhci->io_addr + reg); | |
8452c674 JA |
612 | #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO |
613 | else if (uhci_big_endian_mmio(uhci)) | |
614 | writeb_be(val, uhci->regs + reg); | |
615 | #endif | |
d3219d1c JA |
616 | else |
617 | writeb(val, uhci->regs + reg); | |
618 | } | |
8452c674 | 619 | #endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */ |
d3219d1c | 620 | |
51e2f62f JA |
621 | /* |
622 | * The GRLIB GRUSBHC controller can use big endian format for its descriptors. | |
623 | * | |
624 | * UHCI controllers accessed through PCI work normally (little-endian | |
625 | * everywhere), so we don't bother supporting a BE-only mode. | |
626 | */ | |
627 | #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC | |
628 | #define uhci_big_endian_desc(u) ((u)->big_endian_desc) | |
629 | ||
630 | /* cpu to uhci */ | |
631 | static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x) | |
632 | { | |
633 | return uhci_big_endian_desc(uhci) | |
634 | ? (__force __hc32)cpu_to_be32(x) | |
635 | : (__force __hc32)cpu_to_le32(x); | |
636 | } | |
637 | ||
638 | /* uhci to cpu */ | |
639 | static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x) | |
640 | { | |
641 | return uhci_big_endian_desc(uhci) | |
642 | ? be32_to_cpu((__force __be32)x) | |
643 | : le32_to_cpu((__force __le32)x); | |
644 | } | |
645 | ||
646 | #else | |
647 | /* cpu to uhci */ | |
648 | static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x) | |
649 | { | |
650 | return cpu_to_le32(x); | |
651 | } | |
652 | ||
653 | /* uhci to cpu */ | |
654 | static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x) | |
655 | { | |
656 | return le32_to_cpu(x); | |
657 | } | |
658 | #endif | |
659 | ||
1da177e4 | 660 | #endif |