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1da177e4 LT |
1 | #ifndef __LINUX_UHCI_HCD_H |
2 | #define __LINUX_UHCI_HCD_H | |
3 | ||
4 | #include <linux/list.h> | |
5 | #include <linux/usb.h> | |
6 | ||
7 | #define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT) | |
8 | #define PIPE_DEVEP_MASK 0x0007ff00 | |
9 | ||
10 | /* | |
11 | * Universal Host Controller Interface data structures and defines | |
12 | */ | |
13 | ||
14 | /* Command register */ | |
15 | #define USBCMD 0 | |
16 | #define USBCMD_RS 0x0001 /* Run/Stop */ | |
17 | #define USBCMD_HCRESET 0x0002 /* Host reset */ | |
18 | #define USBCMD_GRESET 0x0004 /* Global reset */ | |
19 | #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */ | |
20 | #define USBCMD_FGR 0x0010 /* Force Global Resume */ | |
21 | #define USBCMD_SWDBG 0x0020 /* SW Debug mode */ | |
22 | #define USBCMD_CF 0x0040 /* Config Flag (sw only) */ | |
23 | #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */ | |
24 | ||
25 | /* Status register */ | |
26 | #define USBSTS 2 | |
27 | #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */ | |
28 | #define USBSTS_ERROR 0x0002 /* Interrupt due to error */ | |
29 | #define USBSTS_RD 0x0004 /* Resume Detect */ | |
30 | #define USBSTS_HSE 0x0008 /* Host System Error - basically PCI problems */ | |
31 | #define USBSTS_HCPE 0x0010 /* Host Controller Process Error - the scripts were buggy */ | |
32 | #define USBSTS_HCH 0x0020 /* HC Halted */ | |
33 | ||
34 | /* Interrupt enable register */ | |
35 | #define USBINTR 4 | |
36 | #define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */ | |
37 | #define USBINTR_RESUME 0x0002 /* Resume interrupt enable */ | |
38 | #define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */ | |
39 | #define USBINTR_SP 0x0008 /* Short packet interrupt enable */ | |
40 | ||
41 | #define USBFRNUM 6 | |
42 | #define USBFLBASEADD 8 | |
43 | #define USBSOF 12 | |
a8bed8b6 | 44 | #define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */ |
1da177e4 LT |
45 | |
46 | /* USB port status and control registers */ | |
47 | #define USBPORTSC1 16 | |
48 | #define USBPORTSC2 18 | |
49 | #define USBPORTSC_CCS 0x0001 /* Current Connect Status ("device present") */ | |
50 | #define USBPORTSC_CSC 0x0002 /* Connect Status Change */ | |
51 | #define USBPORTSC_PE 0x0004 /* Port Enable */ | |
52 | #define USBPORTSC_PEC 0x0008 /* Port Enable Change */ | |
53 | #define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */ | |
54 | #define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */ | |
55 | #define USBPORTSC_RD 0x0040 /* Resume Detect */ | |
56 | #define USBPORTSC_RES1 0x0080 /* reserved, always 1 */ | |
57 | #define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */ | |
58 | #define USBPORTSC_PR 0x0200 /* Port Reset */ | |
59 | /* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */ | |
60 | #define USBPORTSC_OC 0x0400 /* Over Current condition */ | |
61 | #define USBPORTSC_OCC 0x0800 /* Over Current Change R/WC */ | |
62 | #define USBPORTSC_SUSP 0x1000 /* Suspend */ | |
63 | #define USBPORTSC_RES2 0x2000 /* reserved, write zeroes */ | |
64 | #define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */ | |
65 | #define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */ | |
66 | ||
67 | /* Legacy support register */ | |
68 | #define USBLEGSUP 0xc0 | |
69 | #define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ | |
a8bed8b6 AS |
70 | #define USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ |
71 | #define USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ | |
1da177e4 LT |
72 | |
73 | #define UHCI_NULL_DATA_SIZE 0x7FF /* for UHCI controller TD */ | |
74 | ||
75 | #define UHCI_PTR_BITS cpu_to_le32(0x000F) | |
76 | #define UHCI_PTR_TERM cpu_to_le32(0x0001) | |
77 | #define UHCI_PTR_QH cpu_to_le32(0x0002) | |
78 | #define UHCI_PTR_DEPTH cpu_to_le32(0x0004) | |
79 | #define UHCI_PTR_BREADTH cpu_to_le32(0x0000) | |
80 | ||
81 | #define UHCI_NUMFRAMES 1024 /* in the frame list [array] */ | |
82 | #define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */ | |
83 | #define CAN_SCHEDULE_FRAMES 1000 /* how far future frames can be scheduled */ | |
84 | ||
85 | struct uhci_frame_list { | |
86 | __le32 frame[UHCI_NUMFRAMES]; | |
87 | ||
88 | void *frame_cpu[UHCI_NUMFRAMES]; | |
89 | ||
90 | dma_addr_t dma_handle; | |
91 | }; | |
92 | ||
93 | struct urb_priv; | |
94 | ||
95 | /* | |
96 | * One role of a QH is to hold a queue of TDs for some endpoint. Each QH is | |
97 | * used with one URB, and qh->element (updated by the HC) is either: | |
98 | * - the next unprocessed TD for the URB, or | |
99 | * - UHCI_PTR_TERM (when there's no more traffic for this endpoint), or | |
100 | * - the QH for the next URB queued to the same endpoint. | |
101 | * | |
102 | * The other role of a QH is to serve as a "skeleton" framelist entry, so we | |
103 | * can easily splice a QH for some endpoint into the schedule at the right | |
104 | * place. Then qh->element is UHCI_PTR_TERM. | |
105 | * | |
106 | * In the frame list, qh->link maintains a list of QHs seen by the HC: | |
107 | * skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ... | |
108 | */ | |
109 | struct uhci_qh { | |
110 | /* Hardware fields */ | |
111 | __le32 link; /* Next queue */ | |
112 | __le32 element; /* Queue element pointer */ | |
113 | ||
114 | /* Software fields */ | |
115 | dma_addr_t dma_handle; | |
116 | ||
1da177e4 LT |
117 | struct urb_priv *urbp; |
118 | ||
119 | struct list_head list; /* P: uhci->frame_list_lock */ | |
120 | struct list_head remove_list; /* P: uhci->remove_list_lock */ | |
121 | } __attribute__((aligned(16))); | |
122 | ||
123 | /* | |
124 | * We need a special accessor for the element pointer because it is | |
125 | * subject to asynchronous updates by the controller | |
126 | */ | |
127 | static __le32 inline qh_element(struct uhci_qh *qh) { | |
128 | __le32 element = qh->element; | |
129 | ||
130 | barrier(); | |
131 | return element; | |
132 | } | |
133 | ||
134 | /* | |
135 | * for TD <status>: | |
136 | */ | |
137 | #define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ | |
138 | #define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ | |
139 | #define TD_CTRL_C_ERR_SHIFT 27 | |
140 | #define TD_CTRL_LS (1 << 26) /* Low Speed Device */ | |
141 | #define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ | |
142 | #define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ | |
143 | #define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ | |
144 | #define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ | |
145 | #define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ | |
146 | #define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ | |
147 | #define TD_CTRL_NAK (1 << 19) /* NAK Received */ | |
148 | #define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ | |
149 | #define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ | |
150 | #define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */ | |
151 | ||
152 | #define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \ | |
153 | TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF) | |
154 | ||
155 | #define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT) | |
156 | #define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000) | |
157 | #define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & TD_CTRL_ACTLEN_MASK) /* 1-based */ | |
158 | ||
159 | /* | |
160 | * for TD <info>: (a.k.a. Token) | |
161 | */ | |
162 | #define td_token(td) le32_to_cpu((td)->token) | |
163 | #define TD_TOKEN_DEVADDR_SHIFT 8 | |
164 | #define TD_TOKEN_TOGGLE_SHIFT 19 | |
165 | #define TD_TOKEN_TOGGLE (1 << 19) | |
166 | #define TD_TOKEN_EXPLEN_SHIFT 21 | |
167 | #define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n - 1 */ | |
168 | #define TD_TOKEN_PID_MASK 0xFF | |
169 | ||
170 | #define uhci_explen(len) ((len) << TD_TOKEN_EXPLEN_SHIFT) | |
171 | ||
172 | #define uhci_expected_length(token) ((((token) >> 21) + 1) & TD_TOKEN_EXPLEN_MASK) | |
173 | #define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1) | |
174 | #define uhci_endpoint(token) (((token) >> 15) & 0xf) | |
175 | #define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f) | |
176 | #define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff) | |
177 | #define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK) | |
178 | #define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN) | |
179 | #define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN) | |
180 | ||
181 | /* | |
182 | * The documentation says "4 words for hardware, 4 words for software". | |
183 | * | |
184 | * That's silly, the hardware doesn't care. The hardware only cares that | |
185 | * the hardware words are 16-byte aligned, and we can have any amount of | |
186 | * sw space after the TD entry as far as I can tell. | |
187 | * | |
188 | * But let's just go with the documentation, at least for 32-bit machines. | |
189 | * On 64-bit machines we probably want to take advantage of the fact that | |
190 | * hw doesn't really care about the size of the sw-only area. | |
191 | * | |
192 | * Alas, not anymore, we have more than 4 words for software, woops. | |
193 | * Everything still works tho, surprise! -jerdfelt | |
194 | * | |
195 | * td->link points to either another TD (not necessarily for the same urb or | |
196 | * even the same endpoint), or nothing (PTR_TERM), or a QH (for queued urbs) | |
197 | */ | |
198 | struct uhci_td { | |
199 | /* Hardware fields */ | |
200 | __le32 link; | |
201 | __le32 status; | |
202 | __le32 token; | |
203 | __le32 buffer; | |
204 | ||
205 | /* Software fields */ | |
206 | dma_addr_t dma_handle; | |
207 | ||
1da177e4 LT |
208 | struct urb *urb; |
209 | ||
210 | struct list_head list; /* P: urb->lock */ | |
211 | struct list_head remove_list; /* P: uhci->td_remove_list_lock */ | |
212 | ||
213 | int frame; /* for iso: what frame? */ | |
214 | struct list_head fl_list; /* P: uhci->frame_list_lock */ | |
215 | } __attribute__((aligned(16))); | |
216 | ||
217 | /* | |
218 | * We need a special accessor for the control/status word because it is | |
219 | * subject to asynchronous updates by the controller | |
220 | */ | |
221 | static u32 inline td_status(struct uhci_td *td) { | |
222 | __le32 status = td->status; | |
223 | ||
224 | barrier(); | |
225 | return le32_to_cpu(status); | |
226 | } | |
227 | ||
228 | ||
229 | /* | |
230 | * The UHCI driver places Interrupt, Control and Bulk into QH's both | |
231 | * to group together TD's for one transfer, and also to faciliate queuing | |
232 | * of URB's. To make it easy to insert entries into the schedule, we have | |
233 | * a skeleton of QH's for each predefined Interrupt latency, low-speed | |
234 | * control, full-speed control and terminating QH (see explanation for | |
235 | * the terminating QH below). | |
236 | * | |
237 | * When we want to add a new QH, we add it to the end of the list for the | |
238 | * skeleton QH. | |
239 | * | |
240 | * For instance, the queue can look like this: | |
241 | * | |
242 | * skel int128 QH | |
243 | * dev 1 interrupt QH | |
244 | * dev 5 interrupt QH | |
245 | * skel int64 QH | |
246 | * skel int32 QH | |
247 | * ... | |
248 | * skel int1 QH | |
249 | * skel low-speed control QH | |
250 | * dev 5 control QH | |
251 | * skel full-speed control QH | |
252 | * skel bulk QH | |
253 | * dev 1 bulk QH | |
254 | * dev 2 bulk QH | |
255 | * skel terminating QH | |
256 | * | |
257 | * The terminating QH is used for 2 reasons: | |
258 | * - To place a terminating TD which is used to workaround a PIIX bug | |
259 | * (see Intel errata for explanation) | |
260 | * - To loop back to the full-speed control queue for full-speed bandwidth | |
261 | * reclamation | |
262 | * | |
263 | * Isochronous transfers are stored before the start of the skeleton | |
264 | * schedule and don't use QH's. While the UHCI spec doesn't forbid the | |
265 | * use of QH's for Isochronous, it doesn't use them either. Since we don't | |
266 | * need to use them either, we follow the spec diagrams in hope that it'll | |
267 | * be more compatible with future UHCI implementations. | |
268 | */ | |
269 | ||
270 | #define UHCI_NUM_SKELQH 12 | |
271 | #define skel_int128_qh skelqh[0] | |
272 | #define skel_int64_qh skelqh[1] | |
273 | #define skel_int32_qh skelqh[2] | |
274 | #define skel_int16_qh skelqh[3] | |
275 | #define skel_int8_qh skelqh[4] | |
276 | #define skel_int4_qh skelqh[5] | |
277 | #define skel_int2_qh skelqh[6] | |
278 | #define skel_int1_qh skelqh[7] | |
279 | #define skel_ls_control_qh skelqh[8] | |
280 | #define skel_fs_control_qh skelqh[9] | |
281 | #define skel_bulk_qh skelqh[10] | |
282 | #define skel_term_qh skelqh[11] | |
283 | ||
284 | /* | |
285 | * Search tree for determining where <interval> fits in the skelqh[] | |
286 | * skeleton. | |
287 | * | |
288 | * An interrupt request should be placed into the slowest skelqh[] | |
289 | * which meets the interval/period/frequency requirement. | |
290 | * An interrupt request is allowed to be faster than <interval> but not slower. | |
291 | * | |
292 | * For a given <interval>, this function returns the appropriate/matching | |
293 | * skelqh[] index value. | |
294 | */ | |
295 | static inline int __interval_to_skel(int interval) | |
296 | { | |
297 | if (interval < 16) { | |
298 | if (interval < 4) { | |
299 | if (interval < 2) | |
300 | return 7; /* int1 for 0-1 ms */ | |
301 | return 6; /* int2 for 2-3 ms */ | |
302 | } | |
303 | if (interval < 8) | |
304 | return 5; /* int4 for 4-7 ms */ | |
305 | return 4; /* int8 for 8-15 ms */ | |
306 | } | |
307 | if (interval < 64) { | |
308 | if (interval < 32) | |
309 | return 3; /* int16 for 16-31 ms */ | |
310 | return 2; /* int32 for 32-63 ms */ | |
311 | } | |
312 | if (interval < 128) | |
313 | return 1; /* int64 for 64-127 ms */ | |
314 | return 0; /* int128 for 128-255 ms (Max.) */ | |
315 | } | |
316 | ||
317 | /* | |
c8f4fe43 | 318 | * States for the root hub. |
1da177e4 LT |
319 | * |
320 | * To prevent "bouncing" in the presence of electrical noise, | |
c8f4fe43 AS |
321 | * when there are no devices attached we delay for 1 second in the |
322 | * RUNNING_NODEVS state before switching to the AUTO_STOPPED state. | |
323 | * | |
324 | * (Note that the AUTO_STOPPED state won't be necessary once the hub | |
325 | * driver learns to autosuspend.) | |
1da177e4 | 326 | */ |
c8f4fe43 | 327 | enum uhci_rh_state { |
6c1b445c AS |
328 | /* In the following states the HC must be halted. |
329 | * These two must come first */ | |
330 | UHCI_RH_RESET, | |
c8f4fe43 | 331 | UHCI_RH_SUSPENDED, |
a8bed8b6 | 332 | |
c8f4fe43 AS |
333 | UHCI_RH_AUTO_STOPPED, |
334 | UHCI_RH_RESUMING, | |
335 | ||
6c1b445c AS |
336 | /* In this state the HC changes from running to halted, |
337 | * so it can legally appear either way. */ | |
c8f4fe43 AS |
338 | UHCI_RH_SUSPENDING, |
339 | ||
6c1b445c | 340 | /* In the following states it's an error if the HC is halted. |
a8bed8b6 | 341 | * These two must come last */ |
c8f4fe43 AS |
342 | UHCI_RH_RUNNING, /* The normal state */ |
343 | UHCI_RH_RUNNING_NODEVS, /* Running with no devices attached */ | |
1da177e4 LT |
344 | }; |
345 | ||
346 | /* | |
347 | * This describes the full uhci information. | |
1da177e4 LT |
348 | */ |
349 | struct uhci_hcd { | |
350 | ||
351 | /* debugfs */ | |
352 | struct dentry *dentry; | |
353 | ||
354 | /* Grabbed from PCI */ | |
355 | unsigned long io_addr; | |
356 | ||
357 | struct dma_pool *qh_pool; | |
358 | struct dma_pool *td_pool; | |
359 | ||
1da177e4 LT |
360 | struct uhci_td *term_td; /* Terminating TD, see UHCI bug */ |
361 | struct uhci_qh *skelqh[UHCI_NUM_SKELQH]; /* Skeleton QH's */ | |
362 | ||
363 | spinlock_t lock; | |
364 | struct uhci_frame_list *fl; /* P: uhci->lock */ | |
365 | int fsbr; /* Full-speed bandwidth reclamation */ | |
366 | unsigned long fsbrtimeout; /* FSBR delay */ | |
367 | ||
c8f4fe43 AS |
368 | enum uhci_rh_state rh_state; |
369 | unsigned long auto_stop_time; /* When to AUTO_STOP */ | |
370 | ||
1da177e4 LT |
371 | unsigned int frame_number; /* As of last check */ |
372 | unsigned int is_stopped; | |
373 | #define UHCI_IS_STOPPED 9999 /* Larger than a frame # */ | |
374 | ||
375 | unsigned int scan_in_progress:1; /* Schedule scan is running */ | |
376 | unsigned int need_rescan:1; /* Redo the schedule scan */ | |
a8bed8b6 | 377 | unsigned int hc_inaccessible:1; /* HC is suspended or dead */ |
1f09df8b AS |
378 | unsigned int working_RD:1; /* Suspended root hub doesn't |
379 | need to be polled */ | |
1da177e4 LT |
380 | |
381 | /* Support for port suspend/resume/reset */ | |
382 | unsigned long port_c_suspend; /* Bit-arrays of ports */ | |
383 | unsigned long suspended_ports; | |
384 | unsigned long resuming_ports; | |
385 | unsigned long ports_timeout; /* Time to stop signalling */ | |
386 | ||
387 | /* Main list of URB's currently controlled by this HC */ | |
388 | struct list_head urb_list; /* P: uhci->lock */ | |
389 | ||
390 | /* List of QH's that are done, but waiting to be unlinked (race) */ | |
391 | struct list_head qh_remove_list; /* P: uhci->lock */ | |
392 | unsigned int qh_remove_age; /* Age in frames */ | |
393 | ||
394 | /* List of TD's that are done, but waiting to be freed (race) */ | |
395 | struct list_head td_remove_list; /* P: uhci->lock */ | |
396 | unsigned int td_remove_age; /* Age in frames */ | |
397 | ||
398 | /* List of asynchronously unlinked URB's */ | |
399 | struct list_head urb_remove_list; /* P: uhci->lock */ | |
400 | unsigned int urb_remove_age; /* Age in frames */ | |
401 | ||
402 | /* List of URB's awaiting completion callback */ | |
403 | struct list_head complete_list; /* P: uhci->lock */ | |
404 | ||
1f09df8b | 405 | int rh_numports; /* Number of root-hub ports */ |
1da177e4 LT |
406 | |
407 | wait_queue_head_t waitqh; /* endpoint_disable waiters */ | |
408 | }; | |
409 | ||
410 | /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */ | |
411 | static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd) | |
412 | { | |
413 | return (struct uhci_hcd *) (hcd->hcd_priv); | |
414 | } | |
415 | static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci) | |
416 | { | |
417 | return container_of((void *) uhci, struct usb_hcd, hcd_priv); | |
418 | } | |
419 | ||
420 | #define uhci_dev(u) (uhci_to_hcd(u)->self.controller) | |
421 | ||
422 | struct urb_priv { | |
423 | struct list_head urb_list; | |
424 | ||
425 | struct urb *urb; | |
426 | ||
427 | struct uhci_qh *qh; /* QH for this URB */ | |
428 | struct list_head td_list; /* P: urb->lock */ | |
429 | ||
430 | unsigned fsbr : 1; /* URB turned on FSBR */ | |
431 | unsigned fsbr_timeout : 1; /* URB timed out on FSBR */ | |
432 | unsigned queued : 1; /* QH was queued (not linked in) */ | |
433 | unsigned short_control_packet : 1; /* If we get a short packet during */ | |
434 | /* a control transfer, retrigger */ | |
435 | /* the status phase */ | |
436 | ||
437 | unsigned long inserttime; /* In jiffies */ | |
438 | unsigned long fsbrtime; /* In jiffies */ | |
439 | ||
440 | struct list_head queue_list; /* P: uhci->frame_list_lock */ | |
441 | }; | |
442 | ||
443 | /* | |
444 | * Locking in uhci.c | |
445 | * | |
446 | * Almost everything relating to the hardware schedule and processing | |
447 | * of URBs is protected by uhci->lock. urb->status is protected by | |
448 | * urb->lock; that's the one exception. | |
449 | * | |
450 | * To prevent deadlocks, never lock uhci->lock while holding urb->lock. | |
451 | * The safe order of locking is: | |
452 | * | |
453 | * #1 uhci->lock | |
454 | * #2 urb->lock | |
455 | */ | |
456 | ||
c8f4fe43 AS |
457 | |
458 | /* Some special IDs */ | |
459 | ||
460 | #define PCI_VENDOR_ID_GENESYS 0x17a0 | |
461 | #define PCI_DEVICE_ID_GL880S_UHCI 0x8083 | |
462 | #define PCI_DEVICE_ID_GL880S_EHCI 0x8084 | |
463 | ||
1da177e4 | 464 | #endif |