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1da177e4 LT |
1 | #ifndef __LINUX_UHCI_HCD_H |
2 | #define __LINUX_UHCI_HCD_H | |
3 | ||
4 | #include <linux/list.h> | |
5 | #include <linux/usb.h> | |
6 | ||
7 | #define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT) | |
8 | #define PIPE_DEVEP_MASK 0x0007ff00 | |
9 | ||
8b262bd2 | 10 | |
1da177e4 LT |
11 | /* |
12 | * Universal Host Controller Interface data structures and defines | |
13 | */ | |
14 | ||
15 | /* Command register */ | |
16 | #define USBCMD 0 | |
17 | #define USBCMD_RS 0x0001 /* Run/Stop */ | |
18 | #define USBCMD_HCRESET 0x0002 /* Host reset */ | |
19 | #define USBCMD_GRESET 0x0004 /* Global reset */ | |
20 | #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */ | |
21 | #define USBCMD_FGR 0x0010 /* Force Global Resume */ | |
22 | #define USBCMD_SWDBG 0x0020 /* SW Debug mode */ | |
23 | #define USBCMD_CF 0x0040 /* Config Flag (sw only) */ | |
24 | #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */ | |
25 | ||
26 | /* Status register */ | |
27 | #define USBSTS 2 | |
28 | #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */ | |
29 | #define USBSTS_ERROR 0x0002 /* Interrupt due to error */ | |
30 | #define USBSTS_RD 0x0004 /* Resume Detect */ | |
dccf4a48 AS |
31 | #define USBSTS_HSE 0x0008 /* Host System Error: PCI problems */ |
32 | #define USBSTS_HCPE 0x0010 /* Host Controller Process Error: | |
33 | * the schedule is buggy */ | |
1da177e4 LT |
34 | #define USBSTS_HCH 0x0020 /* HC Halted */ |
35 | ||
36 | /* Interrupt enable register */ | |
37 | #define USBINTR 4 | |
38 | #define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */ | |
39 | #define USBINTR_RESUME 0x0002 /* Resume interrupt enable */ | |
40 | #define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */ | |
41 | #define USBINTR_SP 0x0008 /* Short packet interrupt enable */ | |
42 | ||
43 | #define USBFRNUM 6 | |
44 | #define USBFLBASEADD 8 | |
45 | #define USBSOF 12 | |
a8bed8b6 | 46 | #define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */ |
1da177e4 LT |
47 | |
48 | /* USB port status and control registers */ | |
49 | #define USBPORTSC1 16 | |
50 | #define USBPORTSC2 18 | |
dccf4a48 AS |
51 | #define USBPORTSC_CCS 0x0001 /* Current Connect Status |
52 | * ("device present") */ | |
1da177e4 LT |
53 | #define USBPORTSC_CSC 0x0002 /* Connect Status Change */ |
54 | #define USBPORTSC_PE 0x0004 /* Port Enable */ | |
55 | #define USBPORTSC_PEC 0x0008 /* Port Enable Change */ | |
56 | #define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */ | |
57 | #define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */ | |
58 | #define USBPORTSC_RD 0x0040 /* Resume Detect */ | |
59 | #define USBPORTSC_RES1 0x0080 /* reserved, always 1 */ | |
60 | #define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */ | |
61 | #define USBPORTSC_PR 0x0200 /* Port Reset */ | |
62 | /* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */ | |
63 | #define USBPORTSC_OC 0x0400 /* Over Current condition */ | |
64 | #define USBPORTSC_OCC 0x0800 /* Over Current Change R/WC */ | |
65 | #define USBPORTSC_SUSP 0x1000 /* Suspend */ | |
66 | #define USBPORTSC_RES2 0x2000 /* reserved, write zeroes */ | |
67 | #define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */ | |
68 | #define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */ | |
69 | ||
70 | /* Legacy support register */ | |
71 | #define USBLEGSUP 0xc0 | |
72 | #define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ | |
a8bed8b6 AS |
73 | #define USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ |
74 | #define USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ | |
1da177e4 | 75 | |
dccf4a48 AS |
76 | #define UHCI_PTR_BITS __constant_cpu_to_le32(0x000F) |
77 | #define UHCI_PTR_TERM __constant_cpu_to_le32(0x0001) | |
78 | #define UHCI_PTR_QH __constant_cpu_to_le32(0x0002) | |
79 | #define UHCI_PTR_DEPTH __constant_cpu_to_le32(0x0004) | |
80 | #define UHCI_PTR_BREADTH __constant_cpu_to_le32(0x0000) | |
1da177e4 LT |
81 | |
82 | #define UHCI_NUMFRAMES 1024 /* in the frame list [array] */ | |
83 | #define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */ | |
dccf4a48 AS |
84 | #define CAN_SCHEDULE_FRAMES 1000 /* how far in the future frames |
85 | * can be scheduled */ | |
1da177e4 | 86 | |
1da177e4 | 87 | |
8b262bd2 AS |
88 | /* |
89 | * Queue Headers | |
90 | */ | |
1da177e4 LT |
91 | |
92 | /* | |
dccf4a48 AS |
93 | * One role of a QH is to hold a queue of TDs for some endpoint. One QH goes |
94 | * with each endpoint, and qh->element (updated by the HC) is either: | |
95 | * - the next unprocessed TD in the endpoint's queue, or | |
96 | * - UHCI_PTR_TERM (when there's no more traffic for this endpoint). | |
1da177e4 LT |
97 | * |
98 | * The other role of a QH is to serve as a "skeleton" framelist entry, so we | |
99 | * can easily splice a QH for some endpoint into the schedule at the right | |
100 | * place. Then qh->element is UHCI_PTR_TERM. | |
101 | * | |
dccf4a48 | 102 | * In the schedule, qh->link maintains a list of QHs seen by the HC: |
1da177e4 | 103 | * skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ... |
dccf4a48 AS |
104 | * |
105 | * qh->node is the software equivalent of qh->link. The differences | |
106 | * are that the software list is doubly-linked and QHs in the UNLINKING | |
107 | * state are on the software list but not the hardware schedule. | |
108 | * | |
109 | * For bookkeeping purposes we maintain QHs even for Isochronous endpoints, | |
110 | * but they never get added to the hardware schedule. | |
1da177e4 | 111 | */ |
dccf4a48 AS |
112 | #define QH_STATE_IDLE 1 /* QH is not being used */ |
113 | #define QH_STATE_UNLINKING 2 /* QH has been removed from the | |
114 | * schedule but the hardware may | |
115 | * still be using it */ | |
116 | #define QH_STATE_ACTIVE 3 /* QH is on the schedule */ | |
117 | ||
1da177e4 LT |
118 | struct uhci_qh { |
119 | /* Hardware fields */ | |
dccf4a48 AS |
120 | __le32 link; /* Next QH in the schedule */ |
121 | __le32 element; /* Queue element (TD) pointer */ | |
1da177e4 LT |
122 | |
123 | /* Software fields */ | |
124 | dma_addr_t dma_handle; | |
125 | ||
dccf4a48 AS |
126 | struct list_head node; /* Node in the list of QHs */ |
127 | struct usb_host_endpoint *hep; /* Endpoint information */ | |
128 | struct usb_device *udev; | |
129 | struct list_head queue; /* Queue of urbps for this QH */ | |
130 | struct uhci_qh *skel; /* Skeleton for this QH */ | |
af0bb599 | 131 | struct uhci_td *dummy_td; /* Dummy TD to end the queue */ |
1da177e4 | 132 | |
dccf4a48 AS |
133 | unsigned int unlink_frame; /* When the QH was unlinked */ |
134 | int state; /* QH_STATE_xxx; see above */ | |
1da177e4 LT |
135 | } __attribute__((aligned(16))); |
136 | ||
137 | /* | |
138 | * We need a special accessor for the element pointer because it is | |
8b262bd2 | 139 | * subject to asynchronous updates by the controller. |
1da177e4 | 140 | */ |
dccf4a48 | 141 | static inline __le32 qh_element(struct uhci_qh *qh) { |
1da177e4 LT |
142 | __le32 element = qh->element; |
143 | ||
144 | barrier(); | |
145 | return element; | |
146 | } | |
147 | ||
8b262bd2 AS |
148 | |
149 | /* | |
150 | * Transfer Descriptors | |
151 | */ | |
152 | ||
1da177e4 LT |
153 | /* |
154 | * for TD <status>: | |
155 | */ | |
156 | #define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ | |
157 | #define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ | |
158 | #define TD_CTRL_C_ERR_SHIFT 27 | |
159 | #define TD_CTRL_LS (1 << 26) /* Low Speed Device */ | |
160 | #define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ | |
161 | #define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ | |
162 | #define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ | |
163 | #define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ | |
164 | #define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ | |
165 | #define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ | |
166 | #define TD_CTRL_NAK (1 << 19) /* NAK Received */ | |
167 | #define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ | |
168 | #define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ | |
169 | #define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */ | |
170 | ||
171 | #define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \ | |
dccf4a48 AS |
172 | TD_CTRL_BABBLE | TD_CTRL_CRCTIME | \ |
173 | TD_CTRL_BITSTUFF) | |
1da177e4 LT |
174 | |
175 | #define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT) | |
176 | #define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000) | |
dccf4a48 AS |
177 | #define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & \ |
178 | TD_CTRL_ACTLEN_MASK) /* 1-based */ | |
1da177e4 LT |
179 | |
180 | /* | |
181 | * for TD <info>: (a.k.a. Token) | |
182 | */ | |
183 | #define td_token(td) le32_to_cpu((td)->token) | |
184 | #define TD_TOKEN_DEVADDR_SHIFT 8 | |
185 | #define TD_TOKEN_TOGGLE_SHIFT 19 | |
186 | #define TD_TOKEN_TOGGLE (1 << 19) | |
187 | #define TD_TOKEN_EXPLEN_SHIFT 21 | |
dccf4a48 | 188 | #define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n-1 */ |
1da177e4 LT |
189 | #define TD_TOKEN_PID_MASK 0xFF |
190 | ||
fa346568 AS |
191 | #define uhci_explen(len) ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \ |
192 | TD_TOKEN_EXPLEN_SHIFT) | |
1da177e4 | 193 | |
fa346568 AS |
194 | #define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \ |
195 | 1) & TD_TOKEN_EXPLEN_MASK) | |
1da177e4 LT |
196 | #define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1) |
197 | #define uhci_endpoint(token) (((token) >> 15) & 0xf) | |
198 | #define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f) | |
199 | #define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff) | |
200 | #define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK) | |
201 | #define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN) | |
202 | #define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN) | |
203 | ||
204 | /* | |
205 | * The documentation says "4 words for hardware, 4 words for software". | |
206 | * | |
207 | * That's silly, the hardware doesn't care. The hardware only cares that | |
208 | * the hardware words are 16-byte aligned, and we can have any amount of | |
8b262bd2 | 209 | * sw space after the TD entry. |
1da177e4 LT |
210 | * |
211 | * td->link points to either another TD (not necessarily for the same urb or | |
dccf4a48 | 212 | * even the same endpoint), or nothing (PTR_TERM), or a QH. |
1da177e4 LT |
213 | */ |
214 | struct uhci_td { | |
215 | /* Hardware fields */ | |
216 | __le32 link; | |
217 | __le32 status; | |
218 | __le32 token; | |
219 | __le32 buffer; | |
220 | ||
221 | /* Software fields */ | |
222 | dma_addr_t dma_handle; | |
223 | ||
8b262bd2 AS |
224 | struct list_head list; |
225 | struct list_head remove_list; | |
1da177e4 LT |
226 | |
227 | int frame; /* for iso: what frame? */ | |
8b262bd2 | 228 | struct list_head fl_list; |
1da177e4 LT |
229 | } __attribute__((aligned(16))); |
230 | ||
231 | /* | |
232 | * We need a special accessor for the control/status word because it is | |
8b262bd2 | 233 | * subject to asynchronous updates by the controller. |
1da177e4 | 234 | */ |
dccf4a48 | 235 | static inline u32 td_status(struct uhci_td *td) { |
1da177e4 LT |
236 | __le32 status = td->status; |
237 | ||
238 | barrier(); | |
239 | return le32_to_cpu(status); | |
240 | } | |
241 | ||
242 | ||
8b262bd2 AS |
243 | /* |
244 | * Skeleton Queue Headers | |
245 | */ | |
246 | ||
1da177e4 | 247 | /* |
dccf4a48 AS |
248 | * The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for |
249 | * automatic queuing. To make it easy to insert entries into the schedule, | |
250 | * we have a skeleton of QHs for each predefined Interrupt latency, | |
251 | * low-speed control, full-speed control, bulk, and terminating QH | |
252 | * (see explanation for the terminating QH below). | |
1da177e4 LT |
253 | * |
254 | * When we want to add a new QH, we add it to the end of the list for the | |
dccf4a48 | 255 | * skeleton QH. For instance, the schedule list can look like this: |
1da177e4 LT |
256 | * |
257 | * skel int128 QH | |
258 | * dev 1 interrupt QH | |
259 | * dev 5 interrupt QH | |
260 | * skel int64 QH | |
261 | * skel int32 QH | |
262 | * ... | |
263 | * skel int1 QH | |
264 | * skel low-speed control QH | |
265 | * dev 5 control QH | |
266 | * skel full-speed control QH | |
267 | * skel bulk QH | |
268 | * dev 1 bulk QH | |
269 | * dev 2 bulk QH | |
270 | * skel terminating QH | |
271 | * | |
272 | * The terminating QH is used for 2 reasons: | |
273 | * - To place a terminating TD which is used to workaround a PIIX bug | |
8b262bd2 | 274 | * (see Intel errata for explanation), and |
1da177e4 | 275 | * - To loop back to the full-speed control queue for full-speed bandwidth |
8b262bd2 | 276 | * reclamation. |
1da177e4 | 277 | * |
dccf4a48 AS |
278 | * There's a special skeleton QH for Isochronous QHs. It never appears |
279 | * on the schedule, and Isochronous TDs go on the schedule before the | |
280 | * the skeleton QHs. The hardware accesses them directly rather than | |
281 | * through their QH, which is used only for bookkeeping purposes. | |
282 | * While the UHCI spec doesn't forbid the use of QHs for Isochronous, | |
283 | * it doesn't use them either. And the spec says that queues never | |
284 | * advance on an error completion status, which makes them totally | |
285 | * unsuitable for Isochronous transfers. | |
1da177e4 LT |
286 | */ |
287 | ||
dccf4a48 AS |
288 | #define UHCI_NUM_SKELQH 14 |
289 | #define skel_unlink_qh skelqh[0] | |
290 | #define skel_iso_qh skelqh[1] | |
291 | #define skel_int128_qh skelqh[2] | |
292 | #define skel_int64_qh skelqh[3] | |
293 | #define skel_int32_qh skelqh[4] | |
294 | #define skel_int16_qh skelqh[5] | |
295 | #define skel_int8_qh skelqh[6] | |
296 | #define skel_int4_qh skelqh[7] | |
297 | #define skel_int2_qh skelqh[8] | |
298 | #define skel_int1_qh skelqh[9] | |
299 | #define skel_ls_control_qh skelqh[10] | |
300 | #define skel_fs_control_qh skelqh[11] | |
301 | #define skel_bulk_qh skelqh[12] | |
302 | #define skel_term_qh skelqh[13] | |
1da177e4 LT |
303 | |
304 | /* | |
305 | * Search tree for determining where <interval> fits in the skelqh[] | |
306 | * skeleton. | |
307 | * | |
308 | * An interrupt request should be placed into the slowest skelqh[] | |
309 | * which meets the interval/period/frequency requirement. | |
310 | * An interrupt request is allowed to be faster than <interval> but not slower. | |
311 | * | |
312 | * For a given <interval>, this function returns the appropriate/matching | |
313 | * skelqh[] index value. | |
314 | */ | |
315 | static inline int __interval_to_skel(int interval) | |
316 | { | |
317 | if (interval < 16) { | |
318 | if (interval < 4) { | |
319 | if (interval < 2) | |
dccf4a48 AS |
320 | return 9; /* int1 for 0-1 ms */ |
321 | return 8; /* int2 for 2-3 ms */ | |
1da177e4 LT |
322 | } |
323 | if (interval < 8) | |
dccf4a48 AS |
324 | return 7; /* int4 for 4-7 ms */ |
325 | return 6; /* int8 for 8-15 ms */ | |
1da177e4 LT |
326 | } |
327 | if (interval < 64) { | |
328 | if (interval < 32) | |
dccf4a48 AS |
329 | return 5; /* int16 for 16-31 ms */ |
330 | return 4; /* int32 for 32-63 ms */ | |
1da177e4 LT |
331 | } |
332 | if (interval < 128) | |
dccf4a48 AS |
333 | return 3; /* int64 for 64-127 ms */ |
334 | return 2; /* int128 for 128-255 ms (Max.) */ | |
1da177e4 LT |
335 | } |
336 | ||
8b262bd2 AS |
337 | |
338 | /* | |
339 | * The UHCI controller and root hub | |
340 | */ | |
341 | ||
1da177e4 | 342 | /* |
8b262bd2 | 343 | * States for the root hub: |
1da177e4 LT |
344 | * |
345 | * To prevent "bouncing" in the presence of electrical noise, | |
c8f4fe43 AS |
346 | * when there are no devices attached we delay for 1 second in the |
347 | * RUNNING_NODEVS state before switching to the AUTO_STOPPED state. | |
348 | * | |
349 | * (Note that the AUTO_STOPPED state won't be necessary once the hub | |
350 | * driver learns to autosuspend.) | |
1da177e4 | 351 | */ |
c8f4fe43 | 352 | enum uhci_rh_state { |
6c1b445c | 353 | /* In the following states the HC must be halted. |
8b262bd2 | 354 | * These two must come first. */ |
6c1b445c | 355 | UHCI_RH_RESET, |
c8f4fe43 | 356 | UHCI_RH_SUSPENDED, |
a8bed8b6 | 357 | |
c8f4fe43 AS |
358 | UHCI_RH_AUTO_STOPPED, |
359 | UHCI_RH_RESUMING, | |
360 | ||
6c1b445c AS |
361 | /* In this state the HC changes from running to halted, |
362 | * so it can legally appear either way. */ | |
c8f4fe43 AS |
363 | UHCI_RH_SUSPENDING, |
364 | ||
6c1b445c | 365 | /* In the following states it's an error if the HC is halted. |
8b262bd2 | 366 | * These two must come last. */ |
c8f4fe43 AS |
367 | UHCI_RH_RUNNING, /* The normal state */ |
368 | UHCI_RH_RUNNING_NODEVS, /* Running with no devices attached */ | |
1da177e4 LT |
369 | }; |
370 | ||
371 | /* | |
8b262bd2 | 372 | * The full UHCI controller information: |
1da177e4 LT |
373 | */ |
374 | struct uhci_hcd { | |
375 | ||
376 | /* debugfs */ | |
377 | struct dentry *dentry; | |
378 | ||
379 | /* Grabbed from PCI */ | |
380 | unsigned long io_addr; | |
381 | ||
382 | struct dma_pool *qh_pool; | |
383 | struct dma_pool *td_pool; | |
384 | ||
1da177e4 | 385 | struct uhci_td *term_td; /* Terminating TD, see UHCI bug */ |
687f5f34 | 386 | struct uhci_qh *skelqh[UHCI_NUM_SKELQH]; /* Skeleton QHs */ |
1da177e4 LT |
387 | |
388 | spinlock_t lock; | |
a1d59ce8 | 389 | |
dccf4a48 | 390 | dma_addr_t frame_dma_handle; /* Hardware frame list */ |
8b262bd2 | 391 | __le32 *frame; |
dccf4a48 | 392 | void **frame_cpu; /* CPU's frame list */ |
a1d59ce8 | 393 | |
dccf4a48 AS |
394 | int fsbr; /* Full-speed bandwidth reclamation */ |
395 | unsigned long fsbrtimeout; /* FSBR delay */ | |
1da177e4 | 396 | |
c8f4fe43 AS |
397 | enum uhci_rh_state rh_state; |
398 | unsigned long auto_stop_time; /* When to AUTO_STOP */ | |
399 | ||
1da177e4 LT |
400 | unsigned int frame_number; /* As of last check */ |
401 | unsigned int is_stopped; | |
402 | #define UHCI_IS_STOPPED 9999 /* Larger than a frame # */ | |
403 | ||
404 | unsigned int scan_in_progress:1; /* Schedule scan is running */ | |
405 | unsigned int need_rescan:1; /* Redo the schedule scan */ | |
a8bed8b6 | 406 | unsigned int hc_inaccessible:1; /* HC is suspended or dead */ |
1f09df8b AS |
407 | unsigned int working_RD:1; /* Suspended root hub doesn't |
408 | need to be polled */ | |
1da177e4 LT |
409 | |
410 | /* Support for port suspend/resume/reset */ | |
411 | unsigned long port_c_suspend; /* Bit-arrays of ports */ | |
412 | unsigned long suspended_ports; | |
413 | unsigned long resuming_ports; | |
414 | unsigned long ports_timeout; /* Time to stop signalling */ | |
415 | ||
687f5f34 | 416 | /* Main list of URBs currently controlled by this HC */ |
8b262bd2 | 417 | struct list_head urb_list; |
1da177e4 | 418 | |
687f5f34 | 419 | /* List of TDs that are done, but waiting to be freed (race) */ |
8b262bd2 | 420 | struct list_head td_remove_list; |
1da177e4 LT |
421 | unsigned int td_remove_age; /* Age in frames */ |
422 | ||
687f5f34 | 423 | /* List of URBs awaiting completion callback */ |
8b262bd2 | 424 | struct list_head complete_list; |
1da177e4 | 425 | |
dccf4a48 AS |
426 | struct list_head idle_qh_list; /* Where the idle QHs live */ |
427 | ||
1f09df8b | 428 | int rh_numports; /* Number of root-hub ports */ |
1da177e4 LT |
429 | |
430 | wait_queue_head_t waitqh; /* endpoint_disable waiters */ | |
dccf4a48 | 431 | int num_waiting; /* Number of waiters */ |
1da177e4 LT |
432 | }; |
433 | ||
434 | /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */ | |
435 | static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd) | |
436 | { | |
437 | return (struct uhci_hcd *) (hcd->hcd_priv); | |
438 | } | |
439 | static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci) | |
440 | { | |
441 | return container_of((void *) uhci, struct usb_hcd, hcd_priv); | |
442 | } | |
443 | ||
444 | #define uhci_dev(u) (uhci_to_hcd(u)->self.controller) | |
445 | ||
8b262bd2 AS |
446 | |
447 | /* | |
448 | * Private per-URB data | |
449 | */ | |
1da177e4 LT |
450 | struct urb_priv { |
451 | struct list_head urb_list; | |
dccf4a48 | 452 | struct list_head node; /* Node in the QH's urbp list */ |
1da177e4 LT |
453 | |
454 | struct urb *urb; | |
455 | ||
456 | struct uhci_qh *qh; /* QH for this URB */ | |
8b262bd2 | 457 | struct list_head td_list; |
1da177e4 | 458 | |
1da177e4 LT |
459 | unsigned long fsbrtime; /* In jiffies */ |
460 | ||
dccf4a48 AS |
461 | unsigned fsbr : 1; /* URB turned on FSBR */ |
462 | unsigned fsbr_timeout : 1; /* URB timed out on FSBR */ | |
463 | unsigned short_transfer : 1; /* URB got a short transfer, no | |
464 | * need to rescan */ | |
1da177e4 LT |
465 | }; |
466 | ||
8b262bd2 | 467 | |
1da177e4 LT |
468 | /* |
469 | * Locking in uhci.c | |
470 | * | |
471 | * Almost everything relating to the hardware schedule and processing | |
472 | * of URBs is protected by uhci->lock. urb->status is protected by | |
473 | * urb->lock; that's the one exception. | |
474 | * | |
475 | * To prevent deadlocks, never lock uhci->lock while holding urb->lock. | |
476 | * The safe order of locking is: | |
477 | * | |
478 | * #1 uhci->lock | |
479 | * #2 urb->lock | |
480 | */ | |
481 | ||
c8f4fe43 AS |
482 | |
483 | /* Some special IDs */ | |
484 | ||
485 | #define PCI_VENDOR_ID_GENESYS 0x17a0 | |
486 | #define PCI_DEVICE_ID_GL880S_UHCI 0x8083 | |
c8f4fe43 | 487 | |
1da177e4 | 488 | #endif |