Commit | Line | Data |
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0f2a7930 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
ddba5cd0 MN |
23 | |
24 | #include <linux/slab.h> | |
0f2a7930 SS |
25 | #include <asm/unaligned.h> |
26 | ||
27 | #include "xhci.h" | |
4bdfe4c3 | 28 | #include "xhci-trace.h" |
0f2a7930 | 29 | |
9777e3ce AX |
30 | #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) |
31 | #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ | |
32 | PORT_RC | PORT_PLC | PORT_PE) | |
33 | ||
5693e0b7 MN |
34 | /* USB 3 BOS descriptor and a capability descriptors, combined. |
35 | * Fields will be adjusted and added later in xhci_create_usb3_bos_desc() | |
36 | */ | |
48e82361 SS |
37 | static u8 usb_bos_descriptor [] = { |
38 | USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */ | |
39 | USB_DT_BOS, /* __u8 bDescriptorType */ | |
40 | 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */ | |
41 | 0x1, /* __u8 bNumDeviceCaps */ | |
5693e0b7 | 42 | /* First device capability, SuperSpeed */ |
48e82361 SS |
43 | USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */ |
44 | USB_DT_DEVICE_CAPABILITY, /* Device Capability */ | |
45 | USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */ | |
46 | 0x00, /* bmAttributes, LTM off by default */ | |
47 | USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */ | |
48 | 0x03, /* bFunctionalitySupport, | |
49 | USB 3.0 speed only */ | |
50 | 0x00, /* bU1DevExitLat, set later. */ | |
5693e0b7 MN |
51 | 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */ |
52 | /* Second device capability, SuperSpeedPlus */ | |
53 | 0x0c, /* bLength 12, will be adjusted later */ | |
54 | USB_DT_DEVICE_CAPABILITY, /* Device Capability */ | |
55 | USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */ | |
56 | 0x00, /* bReserved 0 */ | |
57 | 0x00, 0x00, 0x00, 0x00, /* bmAttributes, get from xhci psic */ | |
58 | 0x00, 0x00, /* wFunctionalitySupport */ | |
59 | 0x00, 0x00, /* wReserved 0 */ | |
60 | /* Sublink Speed Attributes are added in xhci_create_usb3_bos_desc() */ | |
48e82361 SS |
61 | }; |
62 | ||
5693e0b7 MN |
63 | static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf, |
64 | u16 wLength) | |
65 | { | |
66 | int i, ssa_count; | |
67 | u32 temp; | |
68 | u16 desc_size, ssp_cap_size, ssa_size = 0; | |
69 | bool usb3_1 = false; | |
70 | ||
71 | desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; | |
72 | ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size; | |
73 | ||
74 | /* does xhci support USB 3.1 Enhanced SuperSpeed */ | |
75 | if (xhci->usb3_rhub.min_rev >= 0x01 && xhci->usb3_rhub.psi_uid_count) { | |
76 | /* two SSA entries for each unique PSI ID, one RX and one TX */ | |
77 | ssa_count = xhci->usb3_rhub.psi_uid_count * 2; | |
78 | ssa_size = ssa_count * sizeof(u32); | |
79 | desc_size += ssp_cap_size; | |
80 | usb3_1 = true; | |
81 | } | |
82 | memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength)); | |
83 | ||
84 | if (usb3_1) { | |
85 | /* modify bos descriptor bNumDeviceCaps and wTotalLength */ | |
86 | buf[4] += 1; | |
87 | put_unaligned_le16(desc_size + ssa_size, &buf[2]); | |
88 | } | |
89 | ||
90 | if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE) | |
91 | return wLength; | |
92 | ||
93 | /* Indicate whether the host has LTM support. */ | |
94 | temp = readl(&xhci->cap_regs->hcc_params); | |
95 | if (HCC_LTC(temp)) | |
96 | buf[8] |= USB_LTM_SUPPORT; | |
97 | ||
98 | /* Set the U1 and U2 exit latencies. */ | |
99 | if ((xhci->quirks & XHCI_LPM_SUPPORT)) { | |
100 | temp = readl(&xhci->cap_regs->hcs_params3); | |
101 | buf[12] = HCS_U1_LATENCY(temp); | |
102 | put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); | |
103 | } | |
104 | ||
105 | if (usb3_1) { | |
106 | u32 ssp_cap_base, bm_attrib, psi; | |
107 | int offset; | |
108 | ||
109 | ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; | |
110 | ||
111 | if (wLength < desc_size) | |
112 | return wLength; | |
113 | buf[ssp_cap_base] = ssp_cap_size + ssa_size; | |
114 | ||
115 | /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */ | |
116 | bm_attrib = (ssa_count - 1) & 0x1f; | |
117 | bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5; | |
118 | put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]); | |
119 | ||
120 | if (wLength < desc_size + ssa_size) | |
121 | return wLength; | |
122 | /* | |
123 | * Create the Sublink Speed Attributes (SSA) array. | |
124 | * The xhci PSI field and USB 3.1 SSA fields are very similar, | |
125 | * but link type bits 7:6 differ for values 01b and 10b. | |
126 | * xhci has also only one PSI entry for a symmetric link when | |
127 | * USB 3.1 requires two SSA entries (RX and TX) for every link | |
128 | */ | |
129 | offset = desc_size; | |
130 | for (i = 0; i < xhci->usb3_rhub.psi_count; i++) { | |
131 | psi = xhci->usb3_rhub.psi[i]; | |
132 | psi &= ~USB_SSP_SUBLINK_SPEED_RSVD; | |
133 | if ((psi & PLT_MASK) == PLT_SYM) { | |
134 | /* Symmetric, create SSA RX and TX from one PSI entry */ | |
135 | put_unaligned_le32(psi, &buf[offset]); | |
136 | psi |= 1 << 7; /* turn entry to TX */ | |
137 | offset += 4; | |
138 | if (offset >= desc_size + ssa_size) | |
139 | return desc_size + ssa_size; | |
140 | } else if ((psi & PLT_MASK) == PLT_ASYM_RX) { | |
141 | /* Asymetric RX, flip bits 7:6 for SSA */ | |
142 | psi ^= PLT_MASK; | |
143 | } | |
144 | put_unaligned_le32(psi, &buf[offset]); | |
145 | offset += 4; | |
146 | if (offset >= desc_size + ssa_size) | |
147 | return desc_size + ssa_size; | |
148 | } | |
149 | } | |
150 | /* ssa_size is 0 for other than usb 3.1 hosts */ | |
151 | return desc_size + ssa_size; | |
152 | } | |
48e82361 | 153 | |
4bbb0ace SS |
154 | static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, |
155 | struct usb_hub_descriptor *desc, int ports) | |
0f2a7930 | 156 | { |
0f2a7930 SS |
157 | u16 temp; |
158 | ||
0f2a7930 SS |
159 | desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */ |
160 | desc->bHubContrCurrent = 0; | |
161 | ||
162 | desc->bNbrPorts = ports; | |
0f2a7930 | 163 | temp = 0; |
c8421147 | 164 | /* Bits 1:0 - support per-port power switching, or power always on */ |
0f2a7930 | 165 | if (HCC_PPC(xhci->hcc_params)) |
c8421147 | 166 | temp |= HUB_CHAR_INDV_PORT_LPSM; |
0f2a7930 | 167 | else |
c8421147 | 168 | temp |= HUB_CHAR_NO_LPSM; |
0f2a7930 SS |
169 | /* Bit 2 - root hubs are not part of a compound device */ |
170 | /* Bits 4:3 - individual port over current protection */ | |
c8421147 | 171 | temp |= HUB_CHAR_INDV_PORT_OCPM; |
0f2a7930 SS |
172 | /* Bits 6:5 - no TTs in root ports */ |
173 | /* Bit 7 - no port indicators */ | |
28ccd296 | 174 | desc->wHubCharacteristics = cpu_to_le16(temp); |
0f2a7930 SS |
175 | } |
176 | ||
4bbb0ace SS |
177 | /* Fill in the USB 2.0 roothub descriptor */ |
178 | static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
179 | struct usb_hub_descriptor *desc) | |
180 | { | |
181 | int ports; | |
182 | u16 temp; | |
183 | __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; | |
184 | u32 portsc; | |
185 | unsigned int i; | |
186 | ||
187 | ports = xhci->num_usb2_ports; | |
188 | ||
189 | xhci_common_hub_descriptor(xhci, desc, ports); | |
c8421147 | 190 | desc->bDescriptorType = USB_DT_HUB; |
4bbb0ace | 191 | temp = 1 + (ports / 8); |
c8421147 | 192 | desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; |
4bbb0ace SS |
193 | |
194 | /* The Device Removable bits are reported on a byte granularity. | |
195 | * If the port doesn't exist within that byte, the bit is set to 0. | |
196 | */ | |
197 | memset(port_removable, 0, sizeof(port_removable)); | |
198 | for (i = 0; i < ports; i++) { | |
b0ba9720 | 199 | portsc = readl(xhci->usb2_ports[i]); |
4bbb0ace SS |
200 | /* If a device is removable, PORTSC reports a 0, same as in the |
201 | * hub descriptor DeviceRemovable bits. | |
202 | */ | |
203 | if (portsc & PORT_DEV_REMOVE) | |
204 | /* This math is hairy because bit 0 of DeviceRemovable | |
205 | * is reserved, and bit 1 is for port 1, etc. | |
206 | */ | |
207 | port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); | |
208 | } | |
209 | ||
210 | /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN | |
211 | * ports on it. The USB 2.0 specification says that there are two | |
212 | * variable length fields at the end of the hub descriptor: | |
213 | * DeviceRemovable and PortPwrCtrlMask. But since we can have less than | |
214 | * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array | |
215 | * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to | |
216 | * 0xFF, so we initialize the both arrays (DeviceRemovable and | |
217 | * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each | |
218 | * set of ports that actually exist. | |
219 | */ | |
220 | memset(desc->u.hs.DeviceRemovable, 0xff, | |
221 | sizeof(desc->u.hs.DeviceRemovable)); | |
222 | memset(desc->u.hs.PortPwrCtrlMask, 0xff, | |
223 | sizeof(desc->u.hs.PortPwrCtrlMask)); | |
224 | ||
225 | for (i = 0; i < (ports + 1 + 7) / 8; i++) | |
226 | memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], | |
227 | sizeof(__u8)); | |
228 | } | |
229 | ||
230 | /* Fill in the USB 3.0 roothub descriptor */ | |
231 | static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
232 | struct usb_hub_descriptor *desc) | |
233 | { | |
234 | int ports; | |
235 | u16 port_removable; | |
236 | u32 portsc; | |
237 | unsigned int i; | |
238 | ||
239 | ports = xhci->num_usb3_ports; | |
240 | xhci_common_hub_descriptor(xhci, desc, ports); | |
c8421147 AD |
241 | desc->bDescriptorType = USB_DT_SS_HUB; |
242 | desc->bDescLength = USB_DT_SS_HUB_SIZE; | |
4bbb0ace SS |
243 | |
244 | /* header decode latency should be zero for roothubs, | |
245 | * see section 4.23.5.2. | |
246 | */ | |
247 | desc->u.ss.bHubHdrDecLat = 0; | |
248 | desc->u.ss.wHubDelay = 0; | |
249 | ||
250 | port_removable = 0; | |
251 | /* bit 0 is reserved, bit 1 is for port 1, etc. */ | |
252 | for (i = 0; i < ports; i++) { | |
b0ba9720 | 253 | portsc = readl(xhci->usb3_ports[i]); |
4bbb0ace SS |
254 | if (portsc & PORT_DEV_REMOVE) |
255 | port_removable |= 1 << (i + 1); | |
256 | } | |
27c411c9 LT |
257 | |
258 | desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable); | |
4bbb0ace SS |
259 | } |
260 | ||
261 | static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
262 | struct usb_hub_descriptor *desc) | |
263 | { | |
264 | ||
b50107bb | 265 | if (hcd->speed >= HCD_USB3) |
4bbb0ace SS |
266 | xhci_usb3_hub_descriptor(hcd, xhci, desc); |
267 | else | |
268 | xhci_usb2_hub_descriptor(hcd, xhci, desc); | |
269 | ||
270 | } | |
271 | ||
0f2a7930 SS |
272 | static unsigned int xhci_port_speed(unsigned int port_status) |
273 | { | |
274 | if (DEV_LOWSPEED(port_status)) | |
288ead45 | 275 | return USB_PORT_STAT_LOW_SPEED; |
0f2a7930 | 276 | if (DEV_HIGHSPEED(port_status)) |
288ead45 | 277 | return USB_PORT_STAT_HIGH_SPEED; |
0f2a7930 SS |
278 | /* |
279 | * FIXME: Yes, we should check for full speed, but the core uses that as | |
280 | * a default in portspeed() in usb/core/hub.c (which is the only place | |
288ead45 | 281 | * USB_PORT_STAT_*_SPEED is used). |
0f2a7930 SS |
282 | */ |
283 | return 0; | |
284 | } | |
285 | ||
286 | /* | |
287 | * These bits are Read Only (RO) and should be saved and written to the | |
288 | * registers: 0, 3, 10:13, 30 | |
289 | * connect status, over-current status, port speed, and device removable. | |
290 | * connect status and port speed are also sticky - meaning they're in | |
291 | * the AUX well and they aren't changed by a hot, warm, or cold reset. | |
292 | */ | |
293 | #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) | |
294 | /* | |
295 | * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: | |
296 | * bits 5:8, 9, 14:15, 25:27 | |
297 | * link state, port power, port indicator state, "wake on" enable state | |
298 | */ | |
299 | #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) | |
300 | /* | |
301 | * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: | |
302 | * bit 4 (port reset) | |
303 | */ | |
304 | #define XHCI_PORT_RW1S ((1<<4)) | |
305 | /* | |
306 | * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: | |
307 | * bits 1, 17, 18, 19, 20, 21, 22, 23 | |
308 | * port enable/disable, and | |
309 | * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), | |
310 | * over-current, reset, link state, and L1 change | |
311 | */ | |
312 | #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) | |
313 | /* | |
314 | * Bit 16 is RW, and writing a '1' to it causes the link state control to be | |
315 | * latched in | |
316 | */ | |
317 | #define XHCI_PORT_RW ((1<<16)) | |
318 | /* | |
319 | * These bits are Reserved Zero (RsvdZ) and zero should be written to them: | |
320 | * bits 2, 24, 28:31 | |
321 | */ | |
322 | #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) | |
323 | ||
324 | /* | |
325 | * Given a port state, this function returns a value that would result in the | |
326 | * port being in the same state, if the value was written to the port status | |
327 | * control register. | |
328 | * Save Read Only (RO) bits and save read/write bits where | |
329 | * writing a 0 clears the bit and writing a 1 sets the bit (RWS). | |
330 | * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. | |
331 | */ | |
56192531 | 332 | u32 xhci_port_state_to_neutral(u32 state) |
0f2a7930 SS |
333 | { |
334 | /* Save read-only status and port state */ | |
335 | return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); | |
336 | } | |
337 | ||
be88fe4f AX |
338 | /* |
339 | * find slot id based on port number. | |
f6ff0ac8 | 340 | * @port: The one-based port number from one of the two split roothubs. |
be88fe4f | 341 | */ |
5233630f SS |
342 | int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, |
343 | u16 port) | |
be88fe4f AX |
344 | { |
345 | int slot_id; | |
346 | int i; | |
f6ff0ac8 | 347 | enum usb_device_speed speed; |
be88fe4f AX |
348 | |
349 | slot_id = 0; | |
350 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
351 | if (!xhci->devs[i]) | |
352 | continue; | |
f6ff0ac8 | 353 | speed = xhci->devs[i]->udev->speed; |
b50107bb | 354 | if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3)) |
fe30182c | 355 | && xhci->devs[i]->fake_port == port) { |
be88fe4f AX |
356 | slot_id = i; |
357 | break; | |
358 | } | |
359 | } | |
360 | ||
361 | return slot_id; | |
362 | } | |
363 | ||
364 | /* | |
365 | * Stop device | |
366 | * It issues stop endpoint command for EP 0 to 30. And wait the last command | |
367 | * to complete. | |
368 | * suspend will set to 1, if suspend bit need to set in command. | |
369 | */ | |
370 | static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) | |
371 | { | |
372 | struct xhci_virt_device *virt_dev; | |
373 | struct xhci_command *cmd; | |
374 | unsigned long flags; | |
be88fe4f AX |
375 | int ret; |
376 | int i; | |
377 | ||
378 | ret = 0; | |
379 | virt_dev = xhci->devs[slot_id]; | |
380 | cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); | |
381 | if (!cmd) { | |
382 | xhci_dbg(xhci, "Couldn't allocate command structure.\n"); | |
383 | return -ENOMEM; | |
384 | } | |
385 | ||
386 | spin_lock_irqsave(&xhci->lock, flags); | |
387 | for (i = LAST_EP_INDEX; i > 0; i--) { | |
ddba5cd0 MN |
388 | if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) { |
389 | struct xhci_command *command; | |
390 | command = xhci_alloc_command(xhci, false, false, | |
be3de321 | 391 | GFP_NOWAIT); |
ddba5cd0 MN |
392 | if (!command) { |
393 | spin_unlock_irqrestore(&xhci->lock, flags); | |
394 | xhci_free_command(xhci, cmd); | |
395 | return -ENOMEM; | |
396 | ||
397 | } | |
398 | xhci_queue_stop_endpoint(xhci, command, slot_id, i, | |
399 | suspend); | |
400 | } | |
be88fe4f | 401 | } |
ddba5cd0 | 402 | xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend); |
be88fe4f AX |
403 | xhci_ring_cmd_db(xhci); |
404 | spin_unlock_irqrestore(&xhci->lock, flags); | |
405 | ||
406 | /* Wait for last stop endpoint command to finish */ | |
c311e391 MN |
407 | wait_for_completion(cmd->completion); |
408 | ||
409 | if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) { | |
410 | xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n"); | |
be88fe4f | 411 | ret = -ETIME; |
be88fe4f | 412 | } |
be88fe4f AX |
413 | xhci_free_command(xhci, cmd); |
414 | return ret; | |
415 | } | |
416 | ||
417 | /* | |
418 | * Ring device, it rings the all doorbells unconditionally. | |
419 | */ | |
56192531 | 420 | void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) |
be88fe4f | 421 | { |
b7f9696b HG |
422 | int i, s; |
423 | struct xhci_virt_ep *ep; | |
424 | ||
425 | for (i = 0; i < LAST_EP_INDEX + 1; i++) { | |
426 | ep = &xhci->devs[slot_id]->eps[i]; | |
be88fe4f | 427 | |
b7f9696b HG |
428 | if (ep->ep_state & EP_HAS_STREAMS) { |
429 | for (s = 1; s < ep->stream_info->num_streams; s++) | |
430 | xhci_ring_ep_doorbell(xhci, slot_id, i, s); | |
431 | } else if (ep->ring && ep->ring->dequeue) { | |
be88fe4f | 432 | xhci_ring_ep_doorbell(xhci, slot_id, i, 0); |
b7f9696b HG |
433 | } |
434 | } | |
be88fe4f AX |
435 | |
436 | return; | |
437 | } | |
438 | ||
f6ff0ac8 | 439 | static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, |
28ccd296 | 440 | u16 wIndex, __le32 __iomem *addr, u32 port_status) |
6219c047 | 441 | { |
6dd0a3a7 | 442 | /* Don't allow the USB core to disable SuperSpeed ports. */ |
b50107bb | 443 | if (hcd->speed >= HCD_USB3) { |
6dd0a3a7 SS |
444 | xhci_dbg(xhci, "Ignoring request to disable " |
445 | "SuperSpeed port.\n"); | |
446 | return; | |
447 | } | |
448 | ||
6219c047 | 449 | /* Write 1 to disable the port */ |
204b7793 | 450 | writel(port_status | PORT_PE, addr); |
b0ba9720 | 451 | port_status = readl(addr); |
6219c047 SS |
452 | xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n", |
453 | wIndex, port_status); | |
454 | } | |
455 | ||
34fb562a | 456 | static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, |
28ccd296 | 457 | u16 wIndex, __le32 __iomem *addr, u32 port_status) |
34fb562a SS |
458 | { |
459 | char *port_change_bit; | |
460 | u32 status; | |
461 | ||
462 | switch (wValue) { | |
463 | case USB_PORT_FEAT_C_RESET: | |
464 | status = PORT_RC; | |
465 | port_change_bit = "reset"; | |
466 | break; | |
a11496eb AX |
467 | case USB_PORT_FEAT_C_BH_PORT_RESET: |
468 | status = PORT_WRC; | |
469 | port_change_bit = "warm(BH) reset"; | |
470 | break; | |
34fb562a SS |
471 | case USB_PORT_FEAT_C_CONNECTION: |
472 | status = PORT_CSC; | |
473 | port_change_bit = "connect"; | |
474 | break; | |
475 | case USB_PORT_FEAT_C_OVER_CURRENT: | |
476 | status = PORT_OCC; | |
477 | port_change_bit = "over-current"; | |
478 | break; | |
6219c047 SS |
479 | case USB_PORT_FEAT_C_ENABLE: |
480 | status = PORT_PEC; | |
481 | port_change_bit = "enable/disable"; | |
482 | break; | |
be88fe4f AX |
483 | case USB_PORT_FEAT_C_SUSPEND: |
484 | status = PORT_PLC; | |
485 | port_change_bit = "suspend/resume"; | |
486 | break; | |
85387c0e AX |
487 | case USB_PORT_FEAT_C_PORT_LINK_STATE: |
488 | status = PORT_PLC; | |
489 | port_change_bit = "link state"; | |
490 | break; | |
9425183d LB |
491 | case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: |
492 | status = PORT_CEC; | |
493 | port_change_bit = "config error"; | |
494 | break; | |
34fb562a SS |
495 | default: |
496 | /* Should never happen */ | |
497 | return; | |
498 | } | |
499 | /* Change bits are all write 1 to clear */ | |
204b7793 | 500 | writel(port_status | status, addr); |
b0ba9720 | 501 | port_status = readl(addr); |
34fb562a SS |
502 | xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n", |
503 | port_change_bit, wIndex, port_status); | |
504 | } | |
505 | ||
a0885924 | 506 | static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array) |
507 | { | |
508 | int max_ports; | |
509 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
510 | ||
b50107bb | 511 | if (hcd->speed >= HCD_USB3) { |
a0885924 | 512 | max_ports = xhci->num_usb3_ports; |
513 | *port_array = xhci->usb3_ports; | |
514 | } else { | |
515 | max_ports = xhci->num_usb2_ports; | |
516 | *port_array = xhci->usb2_ports; | |
517 | } | |
518 | ||
519 | return max_ports; | |
520 | } | |
521 | ||
c9682dff AX |
522 | void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, |
523 | int port_id, u32 link_state) | |
524 | { | |
525 | u32 temp; | |
526 | ||
b0ba9720 | 527 | temp = readl(port_array[port_id]); |
c9682dff AX |
528 | temp = xhci_port_state_to_neutral(temp); |
529 | temp &= ~PORT_PLS_MASK; | |
530 | temp |= PORT_LINK_STROBE | link_state; | |
204b7793 | 531 | writel(temp, port_array[port_id]); |
c9682dff AX |
532 | } |
533 | ||
ed384bd3 | 534 | static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, |
4296c70a SS |
535 | __le32 __iomem **port_array, int port_id, u16 wake_mask) |
536 | { | |
537 | u32 temp; | |
538 | ||
b0ba9720 | 539 | temp = readl(port_array[port_id]); |
4296c70a SS |
540 | temp = xhci_port_state_to_neutral(temp); |
541 | ||
542 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) | |
543 | temp |= PORT_WKCONN_E; | |
544 | else | |
545 | temp &= ~PORT_WKCONN_E; | |
546 | ||
547 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT) | |
548 | temp |= PORT_WKDISC_E; | |
549 | else | |
550 | temp &= ~PORT_WKDISC_E; | |
551 | ||
552 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT) | |
553 | temp |= PORT_WKOC_E; | |
554 | else | |
555 | temp &= ~PORT_WKOC_E; | |
556 | ||
204b7793 | 557 | writel(temp, port_array[port_id]); |
4296c70a SS |
558 | } |
559 | ||
d2f52c9e AX |
560 | /* Test and clear port RWC bit */ |
561 | void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, | |
562 | int port_id, u32 port_bit) | |
563 | { | |
564 | u32 temp; | |
565 | ||
b0ba9720 | 566 | temp = readl(port_array[port_id]); |
d2f52c9e AX |
567 | if (temp & port_bit) { |
568 | temp = xhci_port_state_to_neutral(temp); | |
569 | temp |= port_bit; | |
204b7793 | 570 | writel(temp, port_array[port_id]); |
d2f52c9e AX |
571 | } |
572 | } | |
573 | ||
063ebeb4 SS |
574 | /* Updates Link Status for USB 2.1 port */ |
575 | static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg) | |
576 | { | |
577 | if ((status_reg & PORT_PLS_MASK) == XDEV_U2) | |
578 | *status |= USB_PORT_STAT_L1; | |
579 | } | |
580 | ||
8bea2bd3 | 581 | /* Updates Link Status for super Speed port */ |
96908589 FB |
582 | static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci, |
583 | u32 *status, u32 status_reg) | |
8bea2bd3 SL |
584 | { |
585 | u32 pls = status_reg & PORT_PLS_MASK; | |
586 | ||
587 | /* resume state is a xHCI internal state. | |
243292a2 ZJC |
588 | * Do not report it to usb core, instead, pretend to be U3, |
589 | * thus usb core knows it's not ready for transfer | |
8bea2bd3 | 590 | */ |
243292a2 ZJC |
591 | if (pls == XDEV_RESUME) { |
592 | *status |= USB_SS_PORT_LS_U3; | |
8bea2bd3 | 593 | return; |
243292a2 | 594 | } |
8bea2bd3 SL |
595 | |
596 | /* When the CAS bit is set then warm reset | |
597 | * should be performed on port | |
598 | */ | |
599 | if (status_reg & PORT_CAS) { | |
600 | /* The CAS bit can be set while the port is | |
601 | * in any link state. | |
602 | * Only roothubs have CAS bit, so we | |
603 | * pretend to be in compliance mode | |
604 | * unless we're already in compliance | |
605 | * or the inactive state. | |
606 | */ | |
607 | if (pls != USB_SS_PORT_LS_COMP_MOD && | |
608 | pls != USB_SS_PORT_LS_SS_INACTIVE) { | |
609 | pls = USB_SS_PORT_LS_COMP_MOD; | |
610 | } | |
611 | /* Return also connection bit - | |
612 | * hub state machine resets port | |
613 | * when this bit is set. | |
614 | */ | |
615 | pls |= USB_PORT_STAT_CONNECTION; | |
71c731a2 AC |
616 | } else { |
617 | /* | |
618 | * If CAS bit isn't set but the Port is already at | |
619 | * Compliance Mode, fake a connection so the USB core | |
620 | * notices the Compliance state and resets the port. | |
621 | * This resolves an issue generated by the SN65LVPE502CP | |
622 | * in which sometimes the port enters compliance mode | |
623 | * caused by a delay on the host-device negotiation. | |
624 | */ | |
96908589 FB |
625 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && |
626 | (pls == USB_SS_PORT_LS_COMP_MOD)) | |
71c731a2 | 627 | pls |= USB_PORT_STAT_CONNECTION; |
8bea2bd3 | 628 | } |
71c731a2 | 629 | |
8bea2bd3 SL |
630 | /* update status field */ |
631 | *status |= pls; | |
632 | } | |
633 | ||
71c731a2 AC |
634 | /* |
635 | * Function for Compliance Mode Quirk. | |
636 | * | |
637 | * This Function verifies if all xhc USB3 ports have entered U0, if so, | |
638 | * the compliance mode timer is deleted. A port won't enter | |
639 | * compliance mode if it has previously entered U0. | |
640 | */ | |
5f20cf12 SK |
641 | static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, |
642 | u16 wIndex) | |
71c731a2 AC |
643 | { |
644 | u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1); | |
645 | bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0); | |
646 | ||
647 | if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK)) | |
648 | return; | |
649 | ||
650 | if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) { | |
651 | xhci->port_status_u0 |= 1 << wIndex; | |
652 | if (xhci->port_status_u0 == all_ports_seen_u0) { | |
653 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
654 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
655 | "All USB3 ports have entered U0 already!"); | |
656 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
657 | "Compliance Mode Recovery Timer Deleted."); | |
71c731a2 AC |
658 | } |
659 | } | |
660 | } | |
661 | ||
395f5409 MN |
662 | static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li) |
663 | { | |
664 | u32 ext_stat = 0; | |
665 | int speed_id; | |
666 | ||
667 | /* only support rx and tx lane counts of 1 in usb3.1 spec */ | |
668 | speed_id = DEV_PORT_SPEED(raw_port_status); | |
669 | ext_stat |= speed_id; /* bits 3:0, RX speed id */ | |
670 | ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */ | |
671 | ||
672 | ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */ | |
673 | ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */ | |
674 | ||
675 | return ext_stat; | |
676 | } | |
677 | ||
eae5b176 SS |
678 | /* |
679 | * Converts a raw xHCI port status into the format that external USB 2.0 or USB | |
680 | * 3.0 hubs use. | |
681 | * | |
682 | * Possible side effects: | |
683 | * - Mark a port as being done with device resume, | |
684 | * and ring the endpoint doorbells. | |
685 | * - Stop the Synopsys redriver Compliance Mode polling. | |
8b3d4570 | 686 | * - Drop and reacquire the xHCI lock, in order to wait for port resume. |
eae5b176 SS |
687 | */ |
688 | static u32 xhci_get_port_status(struct usb_hcd *hcd, | |
689 | struct xhci_bus_state *bus_state, | |
690 | __le32 __iomem **port_array, | |
8b3d4570 SS |
691 | u16 wIndex, u32 raw_port_status, |
692 | unsigned long flags) | |
693 | __releases(&xhci->lock) | |
694 | __acquires(&xhci->lock) | |
eae5b176 SS |
695 | { |
696 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
697 | u32 status = 0; | |
698 | int slot_id; | |
699 | ||
700 | /* wPortChange bits */ | |
701 | if (raw_port_status & PORT_CSC) | |
702 | status |= USB_PORT_STAT_C_CONNECTION << 16; | |
703 | if (raw_port_status & PORT_PEC) | |
704 | status |= USB_PORT_STAT_C_ENABLE << 16; | |
705 | if ((raw_port_status & PORT_OCC)) | |
706 | status |= USB_PORT_STAT_C_OVERCURRENT << 16; | |
707 | if ((raw_port_status & PORT_RC)) | |
708 | status |= USB_PORT_STAT_C_RESET << 16; | |
709 | /* USB3.0 only */ | |
b50107bb | 710 | if (hcd->speed >= HCD_USB3) { |
aca3a048 ZJC |
711 | /* Port link change with port in resume state should not be |
712 | * reported to usbcore, as this is an internal state to be | |
713 | * handled by xhci driver. Reporting PLC to usbcore may | |
714 | * cause usbcore clearing PLC first and port change event | |
715 | * irq won't be generated. | |
716 | */ | |
717 | if ((raw_port_status & PORT_PLC) && | |
718 | (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) | |
eae5b176 SS |
719 | status |= USB_PORT_STAT_C_LINK_STATE << 16; |
720 | if ((raw_port_status & PORT_WRC)) | |
721 | status |= USB_PORT_STAT_C_BH_RESET << 16; | |
9425183d LB |
722 | if ((raw_port_status & PORT_CEC)) |
723 | status |= USB_PORT_STAT_C_CONFIG_ERROR << 16; | |
eae5b176 SS |
724 | } |
725 | ||
b50107bb | 726 | if (hcd->speed < HCD_USB3) { |
eae5b176 SS |
727 | if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3 |
728 | && (raw_port_status & PORT_POWER)) | |
729 | status |= USB_PORT_STAT_SUSPEND; | |
730 | } | |
731 | if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME && | |
2338b9e4 | 732 | !DEV_SUPERSPEED_ANY(raw_port_status)) { |
eae5b176 SS |
733 | if ((raw_port_status & PORT_RESET) || |
734 | !(raw_port_status & PORT_PE)) | |
735 | return 0xffffffff; | |
f69115fd MN |
736 | /* did port event handler already start resume timing? */ |
737 | if (!bus_state->resume_done[wIndex]) { | |
738 | /* If not, maybe we are in a host initated resume? */ | |
739 | if (test_bit(wIndex, &bus_state->resuming_ports)) { | |
740 | /* Host initated resume doesn't time the resume | |
741 | * signalling using resume_done[]. | |
742 | * It manually sets RESUME state, sleeps 20ms | |
743 | * and sets U0 state. This should probably be | |
744 | * changed, but not right now. | |
745 | */ | |
746 | } else { | |
747 | /* port resume was discovered now and here, | |
748 | * start resume timing | |
749 | */ | |
750 | unsigned long timeout = jiffies + | |
751 | msecs_to_jiffies(USB_RESUME_TIMEOUT); | |
752 | ||
753 | set_bit(wIndex, &bus_state->resuming_ports); | |
754 | bus_state->resume_done[wIndex] = timeout; | |
755 | mod_timer(&hcd->rh_timer, timeout); | |
756 | } | |
757 | /* Has resume been signalled for USB_RESUME_TIME yet? */ | |
758 | } else if (time_after_eq(jiffies, | |
759 | bus_state->resume_done[wIndex])) { | |
8b3d4570 SS |
760 | int time_left; |
761 | ||
eae5b176 SS |
762 | xhci_dbg(xhci, "Resume USB2 port %d\n", |
763 | wIndex + 1); | |
764 | bus_state->resume_done[wIndex] = 0; | |
765 | clear_bit(wIndex, &bus_state->resuming_ports); | |
8b3d4570 SS |
766 | |
767 | set_bit(wIndex, &bus_state->rexit_ports); | |
eae5b176 SS |
768 | xhci_set_link_state(xhci, port_array, wIndex, |
769 | XDEV_U0); | |
8b3d4570 SS |
770 | |
771 | spin_unlock_irqrestore(&xhci->lock, flags); | |
772 | time_left = wait_for_completion_timeout( | |
773 | &bus_state->rexit_done[wIndex], | |
774 | msecs_to_jiffies( | |
775 | XHCI_MAX_REXIT_TIMEOUT)); | |
776 | spin_lock_irqsave(&xhci->lock, flags); | |
777 | ||
778 | if (time_left) { | |
779 | slot_id = xhci_find_slot_id_by_port(hcd, | |
780 | xhci, wIndex + 1); | |
781 | if (!slot_id) { | |
782 | xhci_dbg(xhci, "slot_id is zero\n"); | |
783 | return 0xffffffff; | |
784 | } | |
785 | xhci_ring_device(xhci, slot_id); | |
786 | } else { | |
b0ba9720 | 787 | int port_status = readl(port_array[wIndex]); |
8b3d4570 SS |
788 | xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n", |
789 | XHCI_MAX_REXIT_TIMEOUT, | |
790 | port_status); | |
791 | status |= USB_PORT_STAT_SUSPEND; | |
792 | clear_bit(wIndex, &bus_state->rexit_ports); | |
eae5b176 | 793 | } |
8b3d4570 | 794 | |
eae5b176 SS |
795 | bus_state->port_c_suspend |= 1 << wIndex; |
796 | bus_state->suspended_ports &= ~(1 << wIndex); | |
797 | } else { | |
798 | /* | |
799 | * The resume has been signaling for less than | |
f69115fd MN |
800 | * USB_RESUME_TIME. Report the port status as SUSPEND, |
801 | * let the usbcore check port status again and clear | |
802 | * resume signaling later. | |
eae5b176 SS |
803 | */ |
804 | status |= USB_PORT_STAT_SUSPEND; | |
805 | } | |
806 | } | |
f69115fd MN |
807 | /* |
808 | * Clear stale usb2 resume signalling variables in case port changed | |
809 | * state during resume signalling. For example on error | |
810 | */ | |
811 | if ((bus_state->resume_done[wIndex] || | |
812 | test_bit(wIndex, &bus_state->resuming_ports)) && | |
813 | (raw_port_status & PORT_PLS_MASK) != XDEV_U3 && | |
814 | (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) { | |
815 | bus_state->resume_done[wIndex] = 0; | |
816 | clear_bit(wIndex, &bus_state->resuming_ports); | |
817 | } | |
818 | ||
819 | ||
dad67d5f MN |
820 | if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 && |
821 | (raw_port_status & PORT_POWER)) { | |
822 | if (bus_state->suspended_ports & (1 << wIndex)) { | |
823 | bus_state->suspended_ports &= ~(1 << wIndex); | |
824 | if (hcd->speed < HCD_USB3) | |
825 | bus_state->port_c_suspend |= 1 << wIndex; | |
826 | } | |
827 | bus_state->resume_done[wIndex] = 0; | |
828 | clear_bit(wIndex, &bus_state->resuming_ports); | |
eae5b176 SS |
829 | } |
830 | if (raw_port_status & PORT_CONNECT) { | |
831 | status |= USB_PORT_STAT_CONNECTION; | |
832 | status |= xhci_port_speed(raw_port_status); | |
833 | } | |
834 | if (raw_port_status & PORT_PE) | |
835 | status |= USB_PORT_STAT_ENABLE; | |
836 | if (raw_port_status & PORT_OC) | |
837 | status |= USB_PORT_STAT_OVERCURRENT; | |
838 | if (raw_port_status & PORT_RESET) | |
839 | status |= USB_PORT_STAT_RESET; | |
840 | if (raw_port_status & PORT_POWER) { | |
b50107bb | 841 | if (hcd->speed >= HCD_USB3) |
eae5b176 SS |
842 | status |= USB_SS_PORT_STAT_POWER; |
843 | else | |
844 | status |= USB_PORT_STAT_POWER; | |
845 | } | |
063ebeb4 | 846 | /* Update Port Link State */ |
b50107bb | 847 | if (hcd->speed >= HCD_USB3) { |
96908589 | 848 | xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status); |
eae5b176 SS |
849 | /* |
850 | * Verify if all USB3 Ports Have entered U0 already. | |
851 | * Delete Compliance Mode Timer if so. | |
852 | */ | |
853 | xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex); | |
063ebeb4 SS |
854 | } else { |
855 | xhci_hub_report_usb2_link_state(&status, raw_port_status); | |
eae5b176 SS |
856 | } |
857 | if (bus_state->port_c_suspend & (1 << wIndex)) | |
858 | status |= 1 << USB_PORT_FEAT_C_SUSPEND; | |
859 | ||
860 | return status; | |
861 | } | |
862 | ||
0f2a7930 SS |
863 | int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, |
864 | u16 wIndex, char *buf, u16 wLength) | |
865 | { | |
866 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
a0885924 | 867 | int max_ports; |
0f2a7930 | 868 | unsigned long flags; |
c9682dff | 869 | u32 temp, status; |
0f2a7930 | 870 | int retval = 0; |
28ccd296 | 871 | __le32 __iomem **port_array; |
be88fe4f | 872 | int slot_id; |
20b67cf5 | 873 | struct xhci_bus_state *bus_state; |
2c441780 | 874 | u16 link_state = 0; |
4296c70a | 875 | u16 wake_mask = 0; |
797b0ca5 | 876 | u16 timeout = 0; |
0f2a7930 | 877 | |
a0885924 | 878 | max_ports = xhci_get_ports(hcd, &port_array); |
20b67cf5 | 879 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
0f2a7930 SS |
880 | |
881 | spin_lock_irqsave(&xhci->lock, flags); | |
882 | switch (typeReq) { | |
883 | case GetHubStatus: | |
884 | /* No power source, over-current reported per port */ | |
885 | memset(buf, 0, 4); | |
886 | break; | |
887 | case GetHubDescriptor: | |
4bbb0ace SS |
888 | /* Check to make sure userspace is asking for the USB 3.0 hub |
889 | * descriptor for the USB 3.0 roothub. If not, we stall the | |
890 | * endpoint, like external hubs do. | |
891 | */ | |
b50107bb | 892 | if (hcd->speed >= HCD_USB3 && |
4bbb0ace SS |
893 | (wLength < USB_DT_SS_HUB_SIZE || |
894 | wValue != (USB_DT_SS_HUB << 8))) { | |
895 | xhci_dbg(xhci, "Wrong hub descriptor type for " | |
896 | "USB 3.0 roothub.\n"); | |
897 | goto error; | |
898 | } | |
f6ff0ac8 SS |
899 | xhci_hub_descriptor(hcd, xhci, |
900 | (struct usb_hub_descriptor *) buf); | |
0f2a7930 | 901 | break; |
48e82361 SS |
902 | case DeviceRequest | USB_REQ_GET_DESCRIPTOR: |
903 | if ((wValue & 0xff00) != (USB_DT_BOS << 8)) | |
904 | goto error; | |
905 | ||
5693e0b7 | 906 | if (hcd->speed < HCD_USB3) |
48e82361 SS |
907 | goto error; |
908 | ||
5693e0b7 | 909 | retval = xhci_create_usb3_bos_desc(xhci, buf, wLength); |
48e82361 | 910 | spin_unlock_irqrestore(&xhci->lock, flags); |
5693e0b7 | 911 | return retval; |
0f2a7930 | 912 | case GetPortStatus: |
a0885924 | 913 | if (!wIndex || wIndex > max_ports) |
0f2a7930 SS |
914 | goto error; |
915 | wIndex--; | |
b0ba9720 | 916 | temp = readl(port_array[wIndex]); |
f9de8151 SS |
917 | if (temp == 0xffffffff) { |
918 | retval = -ENODEV; | |
919 | break; | |
920 | } | |
eae5b176 | 921 | status = xhci_get_port_status(hcd, bus_state, port_array, |
8b3d4570 | 922 | wIndex, temp, flags); |
eae5b176 SS |
923 | if (status == 0xffffffff) |
924 | goto error; | |
0ed9a57e | 925 | |
eae5b176 SS |
926 | xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", |
927 | wIndex, temp); | |
0f2a7930 | 928 | xhci_dbg(xhci, "Get port status returned 0x%x\n", status); |
eae5b176 | 929 | |
0f2a7930 | 930 | put_unaligned(cpu_to_le32(status), (__le32 *) buf); |
395f5409 MN |
931 | /* if USB 3.1 extended port status return additional 4 bytes */ |
932 | if (wValue == 0x02) { | |
933 | u32 port_li; | |
934 | ||
935 | if (hcd->speed < HCD_USB31 || wLength != 8) { | |
936 | xhci_err(xhci, "get ext port status invalid parameter\n"); | |
937 | retval = -EINVAL; | |
938 | break; | |
939 | } | |
940 | port_li = readl(port_array[wIndex] + PORTLI); | |
941 | status = xhci_get_ext_port_status(temp, port_li); | |
942 | put_unaligned_le32(cpu_to_le32(status), &buf[4]); | |
943 | } | |
0f2a7930 SS |
944 | break; |
945 | case SetPortFeature: | |
2c441780 AX |
946 | if (wValue == USB_PORT_FEAT_LINK_STATE) |
947 | link_state = (wIndex & 0xff00) >> 3; | |
4296c70a SS |
948 | if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK) |
949 | wake_mask = wIndex & 0xff00; | |
797b0ca5 SS |
950 | /* The MSB of wIndex is the U1/U2 timeout */ |
951 | timeout = (wIndex & 0xff00) >> 8; | |
0f2a7930 | 952 | wIndex &= 0xff; |
a0885924 | 953 | if (!wIndex || wIndex > max_ports) |
0f2a7930 SS |
954 | goto error; |
955 | wIndex--; | |
b0ba9720 | 956 | temp = readl(port_array[wIndex]); |
f9de8151 SS |
957 | if (temp == 0xffffffff) { |
958 | retval = -ENODEV; | |
959 | break; | |
960 | } | |
0f2a7930 | 961 | temp = xhci_port_state_to_neutral(temp); |
4bbb0ace | 962 | /* FIXME: What new port features do we need to support? */ |
0f2a7930 | 963 | switch (wValue) { |
be88fe4f | 964 | case USB_PORT_FEAT_SUSPEND: |
b0ba9720 | 965 | temp = readl(port_array[wIndex]); |
65580b43 AX |
966 | if ((temp & PORT_PLS_MASK) != XDEV_U0) { |
967 | /* Resume the port to U0 first */ | |
968 | xhci_set_link_state(xhci, port_array, wIndex, | |
969 | XDEV_U0); | |
970 | spin_unlock_irqrestore(&xhci->lock, flags); | |
971 | msleep(10); | |
972 | spin_lock_irqsave(&xhci->lock, flags); | |
973 | } | |
be88fe4f AX |
974 | /* In spec software should not attempt to suspend |
975 | * a port unless the port reports that it is in the | |
976 | * enabled (PED = ‘1’,PLS < ‘3’) state. | |
977 | */ | |
b0ba9720 | 978 | temp = readl(port_array[wIndex]); |
be88fe4f AX |
979 | if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) |
980 | || (temp & PORT_PLS_MASK) >= XDEV_U3) { | |
981 | xhci_warn(xhci, "USB core suspending device " | |
982 | "not in U0/U1/U2.\n"); | |
983 | goto error; | |
984 | } | |
985 | ||
5233630f SS |
986 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
987 | wIndex + 1); | |
be88fe4f AX |
988 | if (!slot_id) { |
989 | xhci_warn(xhci, "slot_id is zero\n"); | |
990 | goto error; | |
991 | } | |
992 | /* unlock to execute stop endpoint commands */ | |
993 | spin_unlock_irqrestore(&xhci->lock, flags); | |
994 | xhci_stop_device(xhci, slot_id, 1); | |
995 | spin_lock_irqsave(&xhci->lock, flags); | |
996 | ||
c9682dff | 997 | xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3); |
be88fe4f AX |
998 | |
999 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1000 | msleep(10); /* wait device to enter */ | |
1001 | spin_lock_irqsave(&xhci->lock, flags); | |
1002 | ||
b0ba9720 | 1003 | temp = readl(port_array[wIndex]); |
20b67cf5 | 1004 | bus_state->suspended_ports |= 1 << wIndex; |
be88fe4f | 1005 | break; |
2c441780 | 1006 | case USB_PORT_FEAT_LINK_STATE: |
b0ba9720 | 1007 | temp = readl(port_array[wIndex]); |
41e7e056 SS |
1008 | |
1009 | /* Disable port */ | |
1010 | if (link_state == USB_SS_PORT_LS_SS_DISABLED) { | |
1011 | xhci_dbg(xhci, "Disable port %d\n", wIndex); | |
1012 | temp = xhci_port_state_to_neutral(temp); | |
1013 | /* | |
1014 | * Clear all change bits, so that we get a new | |
1015 | * connection event. | |
1016 | */ | |
1017 | temp |= PORT_CSC | PORT_PEC | PORT_WRC | | |
1018 | PORT_OCC | PORT_RC | PORT_PLC | | |
1019 | PORT_CEC; | |
204b7793 | 1020 | writel(temp | PORT_PE, port_array[wIndex]); |
b0ba9720 | 1021 | temp = readl(port_array[wIndex]); |
41e7e056 SS |
1022 | break; |
1023 | } | |
1024 | ||
1025 | /* Put link in RxDetect (enable port) */ | |
1026 | if (link_state == USB_SS_PORT_LS_RX_DETECT) { | |
1027 | xhci_dbg(xhci, "Enable port %d\n", wIndex); | |
1028 | xhci_set_link_state(xhci, port_array, wIndex, | |
1029 | link_state); | |
b0ba9720 | 1030 | temp = readl(port_array[wIndex]); |
41e7e056 SS |
1031 | break; |
1032 | } | |
1033 | ||
2c441780 | 1034 | /* Software should not attempt to set |
41e7e056 | 1035 | * port link state above '3' (U3) and the port |
2c441780 AX |
1036 | * must be enabled. |
1037 | */ | |
1038 | if ((temp & PORT_PE) == 0 || | |
41e7e056 | 1039 | (link_state > USB_SS_PORT_LS_U3)) { |
2c441780 AX |
1040 | xhci_warn(xhci, "Cannot set link state.\n"); |
1041 | goto error; | |
1042 | } | |
1043 | ||
1044 | if (link_state == USB_SS_PORT_LS_U3) { | |
1045 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, | |
1046 | wIndex + 1); | |
1047 | if (slot_id) { | |
1048 | /* unlock to execute stop endpoint | |
1049 | * commands */ | |
1050 | spin_unlock_irqrestore(&xhci->lock, | |
1051 | flags); | |
1052 | xhci_stop_device(xhci, slot_id, 1); | |
1053 | spin_lock_irqsave(&xhci->lock, flags); | |
1054 | } | |
1055 | } | |
1056 | ||
c9682dff AX |
1057 | xhci_set_link_state(xhci, port_array, wIndex, |
1058 | link_state); | |
2c441780 AX |
1059 | |
1060 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1061 | msleep(20); /* wait device to enter */ | |
1062 | spin_lock_irqsave(&xhci->lock, flags); | |
1063 | ||
b0ba9720 | 1064 | temp = readl(port_array[wIndex]); |
2c441780 AX |
1065 | if (link_state == USB_SS_PORT_LS_U3) |
1066 | bus_state->suspended_ports |= 1 << wIndex; | |
1067 | break; | |
0f2a7930 SS |
1068 | case USB_PORT_FEAT_POWER: |
1069 | /* | |
1070 | * Turn on ports, even if there isn't per-port switching. | |
1071 | * HC will report connect events even before this is set. | |
37ebb549 | 1072 | * However, hub_wq will ignore the roothub events until |
0f2a7930 SS |
1073 | * the roothub is registered. |
1074 | */ | |
204b7793 | 1075 | writel(temp | PORT_POWER, port_array[wIndex]); |
0f2a7930 | 1076 | |
b0ba9720 | 1077 | temp = readl(port_array[wIndex]); |
0f2a7930 | 1078 | xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); |
f7ac7787 | 1079 | |
170ed807 | 1080 | spin_unlock_irqrestore(&xhci->lock, flags); |
f7ac7787 LT |
1081 | temp = usb_acpi_power_manageable(hcd->self.root_hub, |
1082 | wIndex); | |
1083 | if (temp) | |
1084 | usb_acpi_set_power_state(hcd->self.root_hub, | |
1085 | wIndex, true); | |
170ed807 | 1086 | spin_lock_irqsave(&xhci->lock, flags); |
0f2a7930 SS |
1087 | break; |
1088 | case USB_PORT_FEAT_RESET: | |
1089 | temp = (temp | PORT_RESET); | |
204b7793 | 1090 | writel(temp, port_array[wIndex]); |
0f2a7930 | 1091 | |
b0ba9720 | 1092 | temp = readl(port_array[wIndex]); |
0f2a7930 SS |
1093 | xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); |
1094 | break; | |
4296c70a SS |
1095 | case USB_PORT_FEAT_REMOTE_WAKE_MASK: |
1096 | xhci_set_remote_wake_mask(xhci, port_array, | |
1097 | wIndex, wake_mask); | |
b0ba9720 | 1098 | temp = readl(port_array[wIndex]); |
4296c70a SS |
1099 | xhci_dbg(xhci, "set port remote wake mask, " |
1100 | "actual port %d status = 0x%x\n", | |
1101 | wIndex, temp); | |
1102 | break; | |
a11496eb AX |
1103 | case USB_PORT_FEAT_BH_PORT_RESET: |
1104 | temp |= PORT_WR; | |
204b7793 | 1105 | writel(temp, port_array[wIndex]); |
a11496eb | 1106 | |
b0ba9720 | 1107 | temp = readl(port_array[wIndex]); |
a11496eb | 1108 | break; |
797b0ca5 | 1109 | case USB_PORT_FEAT_U1_TIMEOUT: |
b50107bb | 1110 | if (hcd->speed < HCD_USB3) |
797b0ca5 | 1111 | goto error; |
b0ba9720 | 1112 | temp = readl(port_array[wIndex] + PORTPMSC); |
797b0ca5 SS |
1113 | temp &= ~PORT_U1_TIMEOUT_MASK; |
1114 | temp |= PORT_U1_TIMEOUT(timeout); | |
204b7793 | 1115 | writel(temp, port_array[wIndex] + PORTPMSC); |
797b0ca5 SS |
1116 | break; |
1117 | case USB_PORT_FEAT_U2_TIMEOUT: | |
b50107bb | 1118 | if (hcd->speed < HCD_USB3) |
797b0ca5 | 1119 | goto error; |
b0ba9720 | 1120 | temp = readl(port_array[wIndex] + PORTPMSC); |
797b0ca5 SS |
1121 | temp &= ~PORT_U2_TIMEOUT_MASK; |
1122 | temp |= PORT_U2_TIMEOUT(timeout); | |
204b7793 | 1123 | writel(temp, port_array[wIndex] + PORTPMSC); |
797b0ca5 | 1124 | break; |
0f2a7930 SS |
1125 | default: |
1126 | goto error; | |
1127 | } | |
5308a91b | 1128 | /* unblock any posted writes */ |
b0ba9720 | 1129 | temp = readl(port_array[wIndex]); |
0f2a7930 SS |
1130 | break; |
1131 | case ClearPortFeature: | |
a0885924 | 1132 | if (!wIndex || wIndex > max_ports) |
0f2a7930 SS |
1133 | goto error; |
1134 | wIndex--; | |
b0ba9720 | 1135 | temp = readl(port_array[wIndex]); |
f9de8151 SS |
1136 | if (temp == 0xffffffff) { |
1137 | retval = -ENODEV; | |
1138 | break; | |
1139 | } | |
4bbb0ace | 1140 | /* FIXME: What new port features do we need to support? */ |
0f2a7930 SS |
1141 | temp = xhci_port_state_to_neutral(temp); |
1142 | switch (wValue) { | |
be88fe4f | 1143 | case USB_PORT_FEAT_SUSPEND: |
b0ba9720 | 1144 | temp = readl(port_array[wIndex]); |
be88fe4f AX |
1145 | xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); |
1146 | xhci_dbg(xhci, "PORTSC %04x\n", temp); | |
1147 | if (temp & PORT_RESET) | |
1148 | goto error; | |
5ac04bf1 | 1149 | if ((temp & PORT_PLS_MASK) == XDEV_U3) { |
be88fe4f AX |
1150 | if ((temp & PORT_PE) == 0) |
1151 | goto error; | |
be88fe4f | 1152 | |
f69115fd | 1153 | set_bit(wIndex, &bus_state->resuming_ports); |
c9682dff AX |
1154 | xhci_set_link_state(xhci, port_array, wIndex, |
1155 | XDEV_RESUME); | |
1156 | spin_unlock_irqrestore(&xhci->lock, flags); | |
a7114230 AX |
1157 | msleep(20); |
1158 | spin_lock_irqsave(&xhci->lock, flags); | |
c9682dff AX |
1159 | xhci_set_link_state(xhci, port_array, wIndex, |
1160 | XDEV_U0); | |
f69115fd | 1161 | clear_bit(wIndex, &bus_state->resuming_ports); |
be88fe4f | 1162 | } |
a7114230 | 1163 | bus_state->port_c_suspend |= 1 << wIndex; |
be88fe4f | 1164 | |
5233630f SS |
1165 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1166 | wIndex + 1); | |
be88fe4f AX |
1167 | if (!slot_id) { |
1168 | xhci_dbg(xhci, "slot_id is zero\n"); | |
1169 | goto error; | |
1170 | } | |
1171 | xhci_ring_device(xhci, slot_id); | |
1172 | break; | |
1173 | case USB_PORT_FEAT_C_SUSPEND: | |
20b67cf5 | 1174 | bus_state->port_c_suspend &= ~(1 << wIndex); |
0f2a7930 | 1175 | case USB_PORT_FEAT_C_RESET: |
a11496eb | 1176 | case USB_PORT_FEAT_C_BH_PORT_RESET: |
0f2a7930 | 1177 | case USB_PORT_FEAT_C_CONNECTION: |
0f2a7930 | 1178 | case USB_PORT_FEAT_C_OVER_CURRENT: |
6219c047 | 1179 | case USB_PORT_FEAT_C_ENABLE: |
85387c0e | 1180 | case USB_PORT_FEAT_C_PORT_LINK_STATE: |
9425183d | 1181 | case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: |
34fb562a | 1182 | xhci_clear_port_change_bit(xhci, wValue, wIndex, |
5308a91b | 1183 | port_array[wIndex], temp); |
0f2a7930 | 1184 | break; |
6219c047 | 1185 | case USB_PORT_FEAT_ENABLE: |
f6ff0ac8 | 1186 | xhci_disable_port(hcd, xhci, wIndex, |
5308a91b | 1187 | port_array[wIndex], temp); |
6219c047 | 1188 | break; |
693d8eb8 | 1189 | case USB_PORT_FEAT_POWER: |
204b7793 | 1190 | writel(temp & ~PORT_POWER, port_array[wIndex]); |
f7ac7787 | 1191 | |
170ed807 | 1192 | spin_unlock_irqrestore(&xhci->lock, flags); |
f7ac7787 LT |
1193 | temp = usb_acpi_power_manageable(hcd->self.root_hub, |
1194 | wIndex); | |
1195 | if (temp) | |
1196 | usb_acpi_set_power_state(hcd->self.root_hub, | |
1197 | wIndex, false); | |
170ed807 | 1198 | spin_lock_irqsave(&xhci->lock, flags); |
693d8eb8 | 1199 | break; |
0f2a7930 SS |
1200 | default: |
1201 | goto error; | |
1202 | } | |
0f2a7930 SS |
1203 | break; |
1204 | default: | |
1205 | error: | |
1206 | /* "stall" on error */ | |
1207 | retval = -EPIPE; | |
1208 | } | |
1209 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1210 | return retval; | |
1211 | } | |
1212 | ||
1213 | /* | |
1214 | * Returns 0 if the status hasn't changed, or the number of bytes in buf. | |
1215 | * Ports are 0-indexed from the HCD point of view, | |
1216 | * and 1-indexed from the USB core pointer of view. | |
0f2a7930 SS |
1217 | * |
1218 | * Note that the status change bits will be cleared as soon as a port status | |
1219 | * change event is generated, so we use the saved status from that event. | |
1220 | */ | |
1221 | int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) | |
1222 | { | |
1223 | unsigned long flags; | |
1224 | u32 temp, status; | |
56192531 | 1225 | u32 mask; |
0f2a7930 SS |
1226 | int i, retval; |
1227 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
a0885924 | 1228 | int max_ports; |
28ccd296 | 1229 | __le32 __iomem **port_array; |
20b67cf5 | 1230 | struct xhci_bus_state *bus_state; |
c52804a4 | 1231 | bool reset_change = false; |
0f2a7930 | 1232 | |
a0885924 | 1233 | max_ports = xhci_get_ports(hcd, &port_array); |
20b67cf5 | 1234 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
0f2a7930 SS |
1235 | |
1236 | /* Initial status is no changes */ | |
a0885924 | 1237 | retval = (max_ports + 8) / 8; |
419a8e81 | 1238 | memset(buf, 0, retval); |
f370b996 AX |
1239 | |
1240 | /* | |
1241 | * Inform the usbcore about resume-in-progress by returning | |
1242 | * a non-zero value even if there are no status changes. | |
1243 | */ | |
1244 | status = bus_state->resuming_ports; | |
0f2a7930 | 1245 | |
9425183d | 1246 | mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC; |
56192531 | 1247 | |
0f2a7930 SS |
1248 | spin_lock_irqsave(&xhci->lock, flags); |
1249 | /* For each port, did anything change? If so, set that bit in buf. */ | |
a0885924 | 1250 | for (i = 0; i < max_ports; i++) { |
b0ba9720 | 1251 | temp = readl(port_array[i]); |
f9de8151 SS |
1252 | if (temp == 0xffffffff) { |
1253 | retval = -ENODEV; | |
1254 | break; | |
1255 | } | |
56192531 | 1256 | if ((temp & mask) != 0 || |
20b67cf5 SS |
1257 | (bus_state->port_c_suspend & 1 << i) || |
1258 | (bus_state->resume_done[i] && time_after_eq( | |
1259 | jiffies, bus_state->resume_done[i]))) { | |
419a8e81 | 1260 | buf[(i + 1) / 8] |= 1 << (i + 1) % 8; |
0f2a7930 SS |
1261 | status = 1; |
1262 | } | |
c52804a4 SS |
1263 | if ((temp & PORT_RC)) |
1264 | reset_change = true; | |
1265 | } | |
1266 | if (!status && !reset_change) { | |
1267 | xhci_dbg(xhci, "%s: stopping port polling.\n", __func__); | |
1268 | clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
0f2a7930 SS |
1269 | } |
1270 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1271 | return status ? retval : 0; | |
1272 | } | |
9777e3ce AX |
1273 | |
1274 | #ifdef CONFIG_PM | |
1275 | ||
1276 | int xhci_bus_suspend(struct usb_hcd *hcd) | |
1277 | { | |
1278 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
518e848e | 1279 | int max_ports, port_index; |
28ccd296 | 1280 | __le32 __iomem **port_array; |
20b67cf5 | 1281 | struct xhci_bus_state *bus_state; |
9777e3ce AX |
1282 | unsigned long flags; |
1283 | ||
a0885924 | 1284 | max_ports = xhci_get_ports(hcd, &port_array); |
20b67cf5 | 1285 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
9777e3ce AX |
1286 | |
1287 | spin_lock_irqsave(&xhci->lock, flags); | |
1288 | ||
1289 | if (hcd->self.root_hub->do_remote_wakeup) { | |
fac4271d ZJC |
1290 | if (bus_state->resuming_ports || /* USB2 */ |
1291 | bus_state->port_remote_wakeup) { /* USB3 */ | |
f370b996 | 1292 | spin_unlock_irqrestore(&xhci->lock, flags); |
fac4271d | 1293 | xhci_dbg(xhci, "suspend failed because a port is resuming\n"); |
f370b996 | 1294 | return -EBUSY; |
9777e3ce AX |
1295 | } |
1296 | } | |
1297 | ||
518e848e | 1298 | port_index = max_ports; |
20b67cf5 | 1299 | bus_state->bus_suspended = 0; |
518e848e | 1300 | while (port_index--) { |
9777e3ce | 1301 | /* suspend the port if the port is not suspended */ |
9777e3ce AX |
1302 | u32 t1, t2; |
1303 | int slot_id; | |
1304 | ||
b0ba9720 | 1305 | t1 = readl(port_array[port_index]); |
9777e3ce AX |
1306 | t2 = xhci_port_state_to_neutral(t1); |
1307 | ||
1308 | if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) { | |
518e848e | 1309 | xhci_dbg(xhci, "port %d not suspended\n", port_index); |
5233630f | 1310 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
518e848e | 1311 | port_index + 1); |
9777e3ce AX |
1312 | if (slot_id) { |
1313 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1314 | xhci_stop_device(xhci, slot_id, 1); | |
1315 | spin_lock_irqsave(&xhci->lock, flags); | |
1316 | } | |
1317 | t2 &= ~PORT_PLS_MASK; | |
1318 | t2 |= PORT_LINK_STROBE | XDEV_U3; | |
20b67cf5 | 1319 | set_bit(port_index, &bus_state->bus_suspended); |
9777e3ce | 1320 | } |
4296c70a | 1321 | /* USB core sets remote wake mask for USB 3.0 hubs, |
ceb6c9c8 | 1322 | * including the USB 3.0 roothub, but only if CONFIG_PM |
4296c70a SS |
1323 | * is enabled, so also enable remote wake here. |
1324 | */ | |
9b41ebd3 | 1325 | if (hcd->self.root_hub->do_remote_wakeup) { |
9777e3ce AX |
1326 | if (t1 & PORT_CONNECT) { |
1327 | t2 |= PORT_WKOC_E | PORT_WKDISC_E; | |
1328 | t2 &= ~PORT_WKCONN_E; | |
1329 | } else { | |
1330 | t2 |= PORT_WKOC_E | PORT_WKCONN_E; | |
1331 | t2 &= ~PORT_WKDISC_E; | |
1332 | } | |
1333 | } else | |
1334 | t2 &= ~PORT_WAKE_BITS; | |
1335 | ||
1336 | t1 = xhci_port_state_to_neutral(t1); | |
1337 | if (t1 != t2) | |
204b7793 | 1338 | writel(t2, port_array[port_index]); |
9777e3ce AX |
1339 | } |
1340 | hcd->state = HC_STATE_SUSPENDED; | |
20b67cf5 | 1341 | bus_state->next_statechange = jiffies + msecs_to_jiffies(10); |
9777e3ce AX |
1342 | spin_unlock_irqrestore(&xhci->lock, flags); |
1343 | return 0; | |
1344 | } | |
1345 | ||
1346 | int xhci_bus_resume(struct usb_hcd *hcd) | |
1347 | { | |
1348 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
518e848e | 1349 | int max_ports, port_index; |
28ccd296 | 1350 | __le32 __iomem **port_array; |
20b67cf5 | 1351 | struct xhci_bus_state *bus_state; |
9777e3ce AX |
1352 | u32 temp; |
1353 | unsigned long flags; | |
41485a90 MN |
1354 | unsigned long port_was_suspended = 0; |
1355 | bool need_usb2_u3_exit = false; | |
1356 | int slot_id; | |
1357 | int sret; | |
9777e3ce | 1358 | |
a0885924 | 1359 | max_ports = xhci_get_ports(hcd, &port_array); |
20b67cf5 | 1360 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
9777e3ce | 1361 | |
20b67cf5 | 1362 | if (time_before(jiffies, bus_state->next_statechange)) |
9777e3ce AX |
1363 | msleep(5); |
1364 | ||
1365 | spin_lock_irqsave(&xhci->lock, flags); | |
1366 | if (!HCD_HW_ACCESSIBLE(hcd)) { | |
1367 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1368 | return -ESHUTDOWN; | |
1369 | } | |
1370 | ||
1371 | /* delay the irqs */ | |
b0ba9720 | 1372 | temp = readl(&xhci->op_regs->command); |
9777e3ce | 1373 | temp &= ~CMD_EIE; |
204b7793 | 1374 | writel(temp, &xhci->op_regs->command); |
9777e3ce | 1375 | |
518e848e SS |
1376 | port_index = max_ports; |
1377 | while (port_index--) { | |
9777e3ce AX |
1378 | /* Check whether need resume ports. If needed |
1379 | resume port and disable remote wakeup */ | |
9777e3ce | 1380 | u32 temp; |
9777e3ce | 1381 | |
b0ba9720 | 1382 | temp = readl(port_array[port_index]); |
2338b9e4 | 1383 | if (DEV_SUPERSPEED_ANY(temp)) |
9777e3ce AX |
1384 | temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); |
1385 | else | |
1386 | temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); | |
20b67cf5 | 1387 | if (test_bit(port_index, &bus_state->bus_suspended) && |
9777e3ce | 1388 | (temp & PORT_PLS_MASK)) { |
41485a90 | 1389 | set_bit(port_index, &port_was_suspended); |
2338b9e4 | 1390 | if (!DEV_SUPERSPEED_ANY(temp)) { |
c9682dff AX |
1391 | xhci_set_link_state(xhci, port_array, |
1392 | port_index, XDEV_RESUME); | |
41485a90 | 1393 | need_usb2_u3_exit = true; |
9777e3ce | 1394 | } |
9777e3ce | 1395 | } else |
204b7793 | 1396 | writel(temp, port_array[port_index]); |
9777e3ce AX |
1397 | } |
1398 | ||
41485a90 MN |
1399 | if (need_usb2_u3_exit) { |
1400 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1401 | msleep(20); | |
1402 | spin_lock_irqsave(&xhci->lock, flags); | |
1403 | } | |
1404 | ||
1405 | port_index = max_ports; | |
1406 | while (port_index--) { | |
1407 | if (!(port_was_suspended & BIT(port_index))) | |
1408 | continue; | |
1409 | /* Clear PLC to poll it later after XDEV_U0 */ | |
1410 | xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC); | |
1411 | xhci_set_link_state(xhci, port_array, port_index, XDEV_U0); | |
1412 | } | |
1413 | ||
1414 | port_index = max_ports; | |
1415 | while (port_index--) { | |
1416 | if (!(port_was_suspended & BIT(port_index))) | |
1417 | continue; | |
1418 | /* Poll and Clear PLC */ | |
1419 | sret = xhci_handshake(port_array[port_index], PORT_PLC, | |
1420 | PORT_PLC, 10 * 1000); | |
1421 | if (sret) | |
1422 | xhci_warn(xhci, "port %d resume PLC timeout\n", | |
1423 | port_index); | |
1424 | xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC); | |
1425 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1); | |
1426 | if (slot_id) | |
1427 | xhci_ring_device(xhci, slot_id); | |
1428 | } | |
1429 | ||
b0ba9720 | 1430 | (void) readl(&xhci->op_regs->command); |
9777e3ce | 1431 | |
20b67cf5 | 1432 | bus_state->next_statechange = jiffies + msecs_to_jiffies(5); |
9777e3ce | 1433 | /* re-enable irqs */ |
b0ba9720 | 1434 | temp = readl(&xhci->op_regs->command); |
9777e3ce | 1435 | temp |= CMD_EIE; |
204b7793 | 1436 | writel(temp, &xhci->op_regs->command); |
b0ba9720 | 1437 | temp = readl(&xhci->op_regs->command); |
9777e3ce AX |
1438 | |
1439 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1440 | return 0; | |
1441 | } | |
1442 | ||
436a3890 | 1443 | #endif /* CONFIG_PM */ |