Commit | Line | Data |
---|---|---|
0f2a7930 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
ddba5cd0 MN |
23 | |
24 | #include <linux/slab.h> | |
0f2a7930 SS |
25 | #include <asm/unaligned.h> |
26 | ||
27 | #include "xhci.h" | |
4bdfe4c3 | 28 | #include "xhci-trace.h" |
0f2a7930 | 29 | |
9777e3ce AX |
30 | #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) |
31 | #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ | |
32 | PORT_RC | PORT_PLC | PORT_PE) | |
33 | ||
3415fc94 | 34 | /* USB 3.0 BOS descriptor and a capability descriptor, combined */ |
48e82361 SS |
35 | static u8 usb_bos_descriptor [] = { |
36 | USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */ | |
37 | USB_DT_BOS, /* __u8 bDescriptorType */ | |
38 | 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */ | |
39 | 0x1, /* __u8 bNumDeviceCaps */ | |
40 | /* First device capability */ | |
41 | USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */ | |
42 | USB_DT_DEVICE_CAPABILITY, /* Device Capability */ | |
43 | USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */ | |
44 | 0x00, /* bmAttributes, LTM off by default */ | |
45 | USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */ | |
46 | 0x03, /* bFunctionalitySupport, | |
47 | USB 3.0 speed only */ | |
48 | 0x00, /* bU1DevExitLat, set later. */ | |
49 | 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */ | |
50 | }; | |
51 | ||
52 | ||
4bbb0ace SS |
53 | static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, |
54 | struct usb_hub_descriptor *desc, int ports) | |
0f2a7930 | 55 | { |
0f2a7930 SS |
56 | u16 temp; |
57 | ||
0f2a7930 SS |
58 | desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */ |
59 | desc->bHubContrCurrent = 0; | |
60 | ||
61 | desc->bNbrPorts = ports; | |
0f2a7930 | 62 | temp = 0; |
c8421147 | 63 | /* Bits 1:0 - support per-port power switching, or power always on */ |
0f2a7930 | 64 | if (HCC_PPC(xhci->hcc_params)) |
c8421147 | 65 | temp |= HUB_CHAR_INDV_PORT_LPSM; |
0f2a7930 | 66 | else |
c8421147 | 67 | temp |= HUB_CHAR_NO_LPSM; |
0f2a7930 SS |
68 | /* Bit 2 - root hubs are not part of a compound device */ |
69 | /* Bits 4:3 - individual port over current protection */ | |
c8421147 | 70 | temp |= HUB_CHAR_INDV_PORT_OCPM; |
0f2a7930 SS |
71 | /* Bits 6:5 - no TTs in root ports */ |
72 | /* Bit 7 - no port indicators */ | |
28ccd296 | 73 | desc->wHubCharacteristics = cpu_to_le16(temp); |
0f2a7930 SS |
74 | } |
75 | ||
4bbb0ace SS |
76 | /* Fill in the USB 2.0 roothub descriptor */ |
77 | static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
78 | struct usb_hub_descriptor *desc) | |
79 | { | |
80 | int ports; | |
81 | u16 temp; | |
82 | __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; | |
83 | u32 portsc; | |
84 | unsigned int i; | |
85 | ||
86 | ports = xhci->num_usb2_ports; | |
87 | ||
88 | xhci_common_hub_descriptor(xhci, desc, ports); | |
c8421147 | 89 | desc->bDescriptorType = USB_DT_HUB; |
4bbb0ace | 90 | temp = 1 + (ports / 8); |
c8421147 | 91 | desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; |
4bbb0ace SS |
92 | |
93 | /* The Device Removable bits are reported on a byte granularity. | |
94 | * If the port doesn't exist within that byte, the bit is set to 0. | |
95 | */ | |
96 | memset(port_removable, 0, sizeof(port_removable)); | |
97 | for (i = 0; i < ports; i++) { | |
b0ba9720 | 98 | portsc = readl(xhci->usb2_ports[i]); |
4bbb0ace SS |
99 | /* If a device is removable, PORTSC reports a 0, same as in the |
100 | * hub descriptor DeviceRemovable bits. | |
101 | */ | |
102 | if (portsc & PORT_DEV_REMOVE) | |
103 | /* This math is hairy because bit 0 of DeviceRemovable | |
104 | * is reserved, and bit 1 is for port 1, etc. | |
105 | */ | |
106 | port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); | |
107 | } | |
108 | ||
109 | /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN | |
110 | * ports on it. The USB 2.0 specification says that there are two | |
111 | * variable length fields at the end of the hub descriptor: | |
112 | * DeviceRemovable and PortPwrCtrlMask. But since we can have less than | |
113 | * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array | |
114 | * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to | |
115 | * 0xFF, so we initialize the both arrays (DeviceRemovable and | |
116 | * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each | |
117 | * set of ports that actually exist. | |
118 | */ | |
119 | memset(desc->u.hs.DeviceRemovable, 0xff, | |
120 | sizeof(desc->u.hs.DeviceRemovable)); | |
121 | memset(desc->u.hs.PortPwrCtrlMask, 0xff, | |
122 | sizeof(desc->u.hs.PortPwrCtrlMask)); | |
123 | ||
124 | for (i = 0; i < (ports + 1 + 7) / 8; i++) | |
125 | memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], | |
126 | sizeof(__u8)); | |
127 | } | |
128 | ||
129 | /* Fill in the USB 3.0 roothub descriptor */ | |
130 | static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
131 | struct usb_hub_descriptor *desc) | |
132 | { | |
133 | int ports; | |
134 | u16 port_removable; | |
135 | u32 portsc; | |
136 | unsigned int i; | |
137 | ||
138 | ports = xhci->num_usb3_ports; | |
139 | xhci_common_hub_descriptor(xhci, desc, ports); | |
c8421147 AD |
140 | desc->bDescriptorType = USB_DT_SS_HUB; |
141 | desc->bDescLength = USB_DT_SS_HUB_SIZE; | |
4bbb0ace SS |
142 | |
143 | /* header decode latency should be zero for roothubs, | |
144 | * see section 4.23.5.2. | |
145 | */ | |
146 | desc->u.ss.bHubHdrDecLat = 0; | |
147 | desc->u.ss.wHubDelay = 0; | |
148 | ||
149 | port_removable = 0; | |
150 | /* bit 0 is reserved, bit 1 is for port 1, etc. */ | |
151 | for (i = 0; i < ports; i++) { | |
b0ba9720 | 152 | portsc = readl(xhci->usb3_ports[i]); |
4bbb0ace SS |
153 | if (portsc & PORT_DEV_REMOVE) |
154 | port_removable |= 1 << (i + 1); | |
155 | } | |
27c411c9 LT |
156 | |
157 | desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable); | |
4bbb0ace SS |
158 | } |
159 | ||
160 | static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
161 | struct usb_hub_descriptor *desc) | |
162 | { | |
163 | ||
164 | if (hcd->speed == HCD_USB3) | |
165 | xhci_usb3_hub_descriptor(hcd, xhci, desc); | |
166 | else | |
167 | xhci_usb2_hub_descriptor(hcd, xhci, desc); | |
168 | ||
169 | } | |
170 | ||
0f2a7930 SS |
171 | static unsigned int xhci_port_speed(unsigned int port_status) |
172 | { | |
173 | if (DEV_LOWSPEED(port_status)) | |
288ead45 | 174 | return USB_PORT_STAT_LOW_SPEED; |
0f2a7930 | 175 | if (DEV_HIGHSPEED(port_status)) |
288ead45 | 176 | return USB_PORT_STAT_HIGH_SPEED; |
0f2a7930 SS |
177 | /* |
178 | * FIXME: Yes, we should check for full speed, but the core uses that as | |
179 | * a default in portspeed() in usb/core/hub.c (which is the only place | |
288ead45 | 180 | * USB_PORT_STAT_*_SPEED is used). |
0f2a7930 SS |
181 | */ |
182 | return 0; | |
183 | } | |
184 | ||
185 | /* | |
186 | * These bits are Read Only (RO) and should be saved and written to the | |
187 | * registers: 0, 3, 10:13, 30 | |
188 | * connect status, over-current status, port speed, and device removable. | |
189 | * connect status and port speed are also sticky - meaning they're in | |
190 | * the AUX well and they aren't changed by a hot, warm, or cold reset. | |
191 | */ | |
192 | #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) | |
193 | /* | |
194 | * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: | |
195 | * bits 5:8, 9, 14:15, 25:27 | |
196 | * link state, port power, port indicator state, "wake on" enable state | |
197 | */ | |
198 | #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) | |
199 | /* | |
200 | * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: | |
201 | * bit 4 (port reset) | |
202 | */ | |
203 | #define XHCI_PORT_RW1S ((1<<4)) | |
204 | /* | |
205 | * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: | |
206 | * bits 1, 17, 18, 19, 20, 21, 22, 23 | |
207 | * port enable/disable, and | |
208 | * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), | |
209 | * over-current, reset, link state, and L1 change | |
210 | */ | |
211 | #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) | |
212 | /* | |
213 | * Bit 16 is RW, and writing a '1' to it causes the link state control to be | |
214 | * latched in | |
215 | */ | |
216 | #define XHCI_PORT_RW ((1<<16)) | |
217 | /* | |
218 | * These bits are Reserved Zero (RsvdZ) and zero should be written to them: | |
219 | * bits 2, 24, 28:31 | |
220 | */ | |
221 | #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) | |
222 | ||
223 | /* | |
224 | * Given a port state, this function returns a value that would result in the | |
225 | * port being in the same state, if the value was written to the port status | |
226 | * control register. | |
227 | * Save Read Only (RO) bits and save read/write bits where | |
228 | * writing a 0 clears the bit and writing a 1 sets the bit (RWS). | |
229 | * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. | |
230 | */ | |
56192531 | 231 | u32 xhci_port_state_to_neutral(u32 state) |
0f2a7930 SS |
232 | { |
233 | /* Save read-only status and port state */ | |
234 | return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); | |
235 | } | |
236 | ||
be88fe4f AX |
237 | /* |
238 | * find slot id based on port number. | |
f6ff0ac8 | 239 | * @port: The one-based port number from one of the two split roothubs. |
be88fe4f | 240 | */ |
5233630f SS |
241 | int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, |
242 | u16 port) | |
be88fe4f AX |
243 | { |
244 | int slot_id; | |
245 | int i; | |
f6ff0ac8 | 246 | enum usb_device_speed speed; |
be88fe4f AX |
247 | |
248 | slot_id = 0; | |
249 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
250 | if (!xhci->devs[i]) | |
251 | continue; | |
f6ff0ac8 SS |
252 | speed = xhci->devs[i]->udev->speed; |
253 | if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3)) | |
fe30182c | 254 | && xhci->devs[i]->fake_port == port) { |
be88fe4f AX |
255 | slot_id = i; |
256 | break; | |
257 | } | |
258 | } | |
259 | ||
260 | return slot_id; | |
261 | } | |
262 | ||
263 | /* | |
264 | * Stop device | |
265 | * It issues stop endpoint command for EP 0 to 30. And wait the last command | |
266 | * to complete. | |
267 | * suspend will set to 1, if suspend bit need to set in command. | |
268 | */ | |
269 | static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) | |
270 | { | |
271 | struct xhci_virt_device *virt_dev; | |
272 | struct xhci_command *cmd; | |
273 | unsigned long flags; | |
be88fe4f AX |
274 | int ret; |
275 | int i; | |
276 | ||
277 | ret = 0; | |
278 | virt_dev = xhci->devs[slot_id]; | |
279 | cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); | |
280 | if (!cmd) { | |
281 | xhci_dbg(xhci, "Couldn't allocate command structure.\n"); | |
282 | return -ENOMEM; | |
283 | } | |
284 | ||
285 | spin_lock_irqsave(&xhci->lock, flags); | |
286 | for (i = LAST_EP_INDEX; i > 0; i--) { | |
ddba5cd0 MN |
287 | if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) { |
288 | struct xhci_command *command; | |
289 | command = xhci_alloc_command(xhci, false, false, | |
be3de321 | 290 | GFP_NOWAIT); |
ddba5cd0 MN |
291 | if (!command) { |
292 | spin_unlock_irqrestore(&xhci->lock, flags); | |
293 | xhci_free_command(xhci, cmd); | |
294 | return -ENOMEM; | |
295 | ||
296 | } | |
297 | xhci_queue_stop_endpoint(xhci, command, slot_id, i, | |
298 | suspend); | |
299 | } | |
be88fe4f | 300 | } |
ddba5cd0 | 301 | xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend); |
be88fe4f AX |
302 | xhci_ring_cmd_db(xhci); |
303 | spin_unlock_irqrestore(&xhci->lock, flags); | |
304 | ||
305 | /* Wait for last stop endpoint command to finish */ | |
c311e391 MN |
306 | wait_for_completion(cmd->completion); |
307 | ||
308 | if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) { | |
309 | xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n"); | |
be88fe4f | 310 | ret = -ETIME; |
be88fe4f | 311 | } |
be88fe4f AX |
312 | xhci_free_command(xhci, cmd); |
313 | return ret; | |
314 | } | |
315 | ||
316 | /* | |
317 | * Ring device, it rings the all doorbells unconditionally. | |
318 | */ | |
56192531 | 319 | void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) |
be88fe4f | 320 | { |
b7f9696b HG |
321 | int i, s; |
322 | struct xhci_virt_ep *ep; | |
323 | ||
324 | for (i = 0; i < LAST_EP_INDEX + 1; i++) { | |
325 | ep = &xhci->devs[slot_id]->eps[i]; | |
be88fe4f | 326 | |
b7f9696b HG |
327 | if (ep->ep_state & EP_HAS_STREAMS) { |
328 | for (s = 1; s < ep->stream_info->num_streams; s++) | |
329 | xhci_ring_ep_doorbell(xhci, slot_id, i, s); | |
330 | } else if (ep->ring && ep->ring->dequeue) { | |
be88fe4f | 331 | xhci_ring_ep_doorbell(xhci, slot_id, i, 0); |
b7f9696b HG |
332 | } |
333 | } | |
be88fe4f AX |
334 | |
335 | return; | |
336 | } | |
337 | ||
f6ff0ac8 | 338 | static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, |
28ccd296 | 339 | u16 wIndex, __le32 __iomem *addr, u32 port_status) |
6219c047 | 340 | { |
6dd0a3a7 | 341 | /* Don't allow the USB core to disable SuperSpeed ports. */ |
f6ff0ac8 | 342 | if (hcd->speed == HCD_USB3) { |
6dd0a3a7 SS |
343 | xhci_dbg(xhci, "Ignoring request to disable " |
344 | "SuperSpeed port.\n"); | |
345 | return; | |
346 | } | |
347 | ||
6219c047 | 348 | /* Write 1 to disable the port */ |
204b7793 | 349 | writel(port_status | PORT_PE, addr); |
b0ba9720 | 350 | port_status = readl(addr); |
6219c047 SS |
351 | xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n", |
352 | wIndex, port_status); | |
353 | } | |
354 | ||
34fb562a | 355 | static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, |
28ccd296 | 356 | u16 wIndex, __le32 __iomem *addr, u32 port_status) |
34fb562a SS |
357 | { |
358 | char *port_change_bit; | |
359 | u32 status; | |
360 | ||
361 | switch (wValue) { | |
362 | case USB_PORT_FEAT_C_RESET: | |
363 | status = PORT_RC; | |
364 | port_change_bit = "reset"; | |
365 | break; | |
a11496eb AX |
366 | case USB_PORT_FEAT_C_BH_PORT_RESET: |
367 | status = PORT_WRC; | |
368 | port_change_bit = "warm(BH) reset"; | |
369 | break; | |
34fb562a SS |
370 | case USB_PORT_FEAT_C_CONNECTION: |
371 | status = PORT_CSC; | |
372 | port_change_bit = "connect"; | |
373 | break; | |
374 | case USB_PORT_FEAT_C_OVER_CURRENT: | |
375 | status = PORT_OCC; | |
376 | port_change_bit = "over-current"; | |
377 | break; | |
6219c047 SS |
378 | case USB_PORT_FEAT_C_ENABLE: |
379 | status = PORT_PEC; | |
380 | port_change_bit = "enable/disable"; | |
381 | break; | |
be88fe4f AX |
382 | case USB_PORT_FEAT_C_SUSPEND: |
383 | status = PORT_PLC; | |
384 | port_change_bit = "suspend/resume"; | |
385 | break; | |
85387c0e AX |
386 | case USB_PORT_FEAT_C_PORT_LINK_STATE: |
387 | status = PORT_PLC; | |
388 | port_change_bit = "link state"; | |
389 | break; | |
9425183d LB |
390 | case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: |
391 | status = PORT_CEC; | |
392 | port_change_bit = "config error"; | |
393 | break; | |
34fb562a SS |
394 | default: |
395 | /* Should never happen */ | |
396 | return; | |
397 | } | |
398 | /* Change bits are all write 1 to clear */ | |
204b7793 | 399 | writel(port_status | status, addr); |
b0ba9720 | 400 | port_status = readl(addr); |
34fb562a SS |
401 | xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n", |
402 | port_change_bit, wIndex, port_status); | |
403 | } | |
404 | ||
a0885924 | 405 | static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array) |
406 | { | |
407 | int max_ports; | |
408 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
409 | ||
410 | if (hcd->speed == HCD_USB3) { | |
411 | max_ports = xhci->num_usb3_ports; | |
412 | *port_array = xhci->usb3_ports; | |
413 | } else { | |
414 | max_ports = xhci->num_usb2_ports; | |
415 | *port_array = xhci->usb2_ports; | |
416 | } | |
417 | ||
418 | return max_ports; | |
419 | } | |
420 | ||
c9682dff AX |
421 | void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, |
422 | int port_id, u32 link_state) | |
423 | { | |
424 | u32 temp; | |
425 | ||
b0ba9720 | 426 | temp = readl(port_array[port_id]); |
c9682dff AX |
427 | temp = xhci_port_state_to_neutral(temp); |
428 | temp &= ~PORT_PLS_MASK; | |
429 | temp |= PORT_LINK_STROBE | link_state; | |
204b7793 | 430 | writel(temp, port_array[port_id]); |
c9682dff AX |
431 | } |
432 | ||
ed384bd3 | 433 | static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, |
4296c70a SS |
434 | __le32 __iomem **port_array, int port_id, u16 wake_mask) |
435 | { | |
436 | u32 temp; | |
437 | ||
b0ba9720 | 438 | temp = readl(port_array[port_id]); |
4296c70a SS |
439 | temp = xhci_port_state_to_neutral(temp); |
440 | ||
441 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) | |
442 | temp |= PORT_WKCONN_E; | |
443 | else | |
444 | temp &= ~PORT_WKCONN_E; | |
445 | ||
446 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT) | |
447 | temp |= PORT_WKDISC_E; | |
448 | else | |
449 | temp &= ~PORT_WKDISC_E; | |
450 | ||
451 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT) | |
452 | temp |= PORT_WKOC_E; | |
453 | else | |
454 | temp &= ~PORT_WKOC_E; | |
455 | ||
204b7793 | 456 | writel(temp, port_array[port_id]); |
4296c70a SS |
457 | } |
458 | ||
d2f52c9e AX |
459 | /* Test and clear port RWC bit */ |
460 | void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, | |
461 | int port_id, u32 port_bit) | |
462 | { | |
463 | u32 temp; | |
464 | ||
b0ba9720 | 465 | temp = readl(port_array[port_id]); |
d2f52c9e AX |
466 | if (temp & port_bit) { |
467 | temp = xhci_port_state_to_neutral(temp); | |
468 | temp |= port_bit; | |
204b7793 | 469 | writel(temp, port_array[port_id]); |
d2f52c9e AX |
470 | } |
471 | } | |
472 | ||
063ebeb4 SS |
473 | /* Updates Link Status for USB 2.1 port */ |
474 | static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg) | |
475 | { | |
476 | if ((status_reg & PORT_PLS_MASK) == XDEV_U2) | |
477 | *status |= USB_PORT_STAT_L1; | |
478 | } | |
479 | ||
8bea2bd3 | 480 | /* Updates Link Status for super Speed port */ |
96908589 FB |
481 | static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci, |
482 | u32 *status, u32 status_reg) | |
8bea2bd3 SL |
483 | { |
484 | u32 pls = status_reg & PORT_PLS_MASK; | |
485 | ||
486 | /* resume state is a xHCI internal state. | |
243292a2 ZJC |
487 | * Do not report it to usb core, instead, pretend to be U3, |
488 | * thus usb core knows it's not ready for transfer | |
8bea2bd3 | 489 | */ |
243292a2 ZJC |
490 | if (pls == XDEV_RESUME) { |
491 | *status |= USB_SS_PORT_LS_U3; | |
8bea2bd3 | 492 | return; |
243292a2 | 493 | } |
8bea2bd3 SL |
494 | |
495 | /* When the CAS bit is set then warm reset | |
496 | * should be performed on port | |
497 | */ | |
498 | if (status_reg & PORT_CAS) { | |
499 | /* The CAS bit can be set while the port is | |
500 | * in any link state. | |
501 | * Only roothubs have CAS bit, so we | |
502 | * pretend to be in compliance mode | |
503 | * unless we're already in compliance | |
504 | * or the inactive state. | |
505 | */ | |
506 | if (pls != USB_SS_PORT_LS_COMP_MOD && | |
507 | pls != USB_SS_PORT_LS_SS_INACTIVE) { | |
508 | pls = USB_SS_PORT_LS_COMP_MOD; | |
509 | } | |
510 | /* Return also connection bit - | |
511 | * hub state machine resets port | |
512 | * when this bit is set. | |
513 | */ | |
514 | pls |= USB_PORT_STAT_CONNECTION; | |
71c731a2 AC |
515 | } else { |
516 | /* | |
517 | * If CAS bit isn't set but the Port is already at | |
518 | * Compliance Mode, fake a connection so the USB core | |
519 | * notices the Compliance state and resets the port. | |
520 | * This resolves an issue generated by the SN65LVPE502CP | |
521 | * in which sometimes the port enters compliance mode | |
522 | * caused by a delay on the host-device negotiation. | |
523 | */ | |
96908589 FB |
524 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && |
525 | (pls == USB_SS_PORT_LS_COMP_MOD)) | |
71c731a2 | 526 | pls |= USB_PORT_STAT_CONNECTION; |
8bea2bd3 | 527 | } |
71c731a2 | 528 | |
8bea2bd3 SL |
529 | /* update status field */ |
530 | *status |= pls; | |
531 | } | |
532 | ||
71c731a2 AC |
533 | /* |
534 | * Function for Compliance Mode Quirk. | |
535 | * | |
536 | * This Function verifies if all xhc USB3 ports have entered U0, if so, | |
537 | * the compliance mode timer is deleted. A port won't enter | |
538 | * compliance mode if it has previously entered U0. | |
539 | */ | |
5f20cf12 SK |
540 | static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, |
541 | u16 wIndex) | |
71c731a2 AC |
542 | { |
543 | u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1); | |
544 | bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0); | |
545 | ||
546 | if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK)) | |
547 | return; | |
548 | ||
549 | if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) { | |
550 | xhci->port_status_u0 |= 1 << wIndex; | |
551 | if (xhci->port_status_u0 == all_ports_seen_u0) { | |
552 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
553 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
554 | "All USB3 ports have entered U0 already!"); | |
555 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
556 | "Compliance Mode Recovery Timer Deleted."); | |
71c731a2 AC |
557 | } |
558 | } | |
559 | } | |
560 | ||
eae5b176 SS |
561 | /* |
562 | * Converts a raw xHCI port status into the format that external USB 2.0 or USB | |
563 | * 3.0 hubs use. | |
564 | * | |
565 | * Possible side effects: | |
566 | * - Mark a port as being done with device resume, | |
567 | * and ring the endpoint doorbells. | |
568 | * - Stop the Synopsys redriver Compliance Mode polling. | |
8b3d4570 | 569 | * - Drop and reacquire the xHCI lock, in order to wait for port resume. |
eae5b176 SS |
570 | */ |
571 | static u32 xhci_get_port_status(struct usb_hcd *hcd, | |
572 | struct xhci_bus_state *bus_state, | |
573 | __le32 __iomem **port_array, | |
8b3d4570 SS |
574 | u16 wIndex, u32 raw_port_status, |
575 | unsigned long flags) | |
576 | __releases(&xhci->lock) | |
577 | __acquires(&xhci->lock) | |
eae5b176 SS |
578 | { |
579 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
580 | u32 status = 0; | |
581 | int slot_id; | |
582 | ||
583 | /* wPortChange bits */ | |
584 | if (raw_port_status & PORT_CSC) | |
585 | status |= USB_PORT_STAT_C_CONNECTION << 16; | |
586 | if (raw_port_status & PORT_PEC) | |
587 | status |= USB_PORT_STAT_C_ENABLE << 16; | |
588 | if ((raw_port_status & PORT_OCC)) | |
589 | status |= USB_PORT_STAT_C_OVERCURRENT << 16; | |
590 | if ((raw_port_status & PORT_RC)) | |
591 | status |= USB_PORT_STAT_C_RESET << 16; | |
592 | /* USB3.0 only */ | |
593 | if (hcd->speed == HCD_USB3) { | |
aca3a048 ZJC |
594 | /* Port link change with port in resume state should not be |
595 | * reported to usbcore, as this is an internal state to be | |
596 | * handled by xhci driver. Reporting PLC to usbcore may | |
597 | * cause usbcore clearing PLC first and port change event | |
598 | * irq won't be generated. | |
599 | */ | |
600 | if ((raw_port_status & PORT_PLC) && | |
601 | (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) | |
eae5b176 SS |
602 | status |= USB_PORT_STAT_C_LINK_STATE << 16; |
603 | if ((raw_port_status & PORT_WRC)) | |
604 | status |= USB_PORT_STAT_C_BH_RESET << 16; | |
9425183d LB |
605 | if ((raw_port_status & PORT_CEC)) |
606 | status |= USB_PORT_STAT_C_CONFIG_ERROR << 16; | |
eae5b176 SS |
607 | } |
608 | ||
609 | if (hcd->speed != HCD_USB3) { | |
610 | if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3 | |
611 | && (raw_port_status & PORT_POWER)) | |
612 | status |= USB_PORT_STAT_SUSPEND; | |
613 | } | |
614 | if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME && | |
615 | !DEV_SUPERSPEED(raw_port_status)) { | |
616 | if ((raw_port_status & PORT_RESET) || | |
617 | !(raw_port_status & PORT_PE)) | |
618 | return 0xffffffff; | |
619 | if (time_after_eq(jiffies, | |
620 | bus_state->resume_done[wIndex])) { | |
8b3d4570 SS |
621 | int time_left; |
622 | ||
eae5b176 SS |
623 | xhci_dbg(xhci, "Resume USB2 port %d\n", |
624 | wIndex + 1); | |
625 | bus_state->resume_done[wIndex] = 0; | |
626 | clear_bit(wIndex, &bus_state->resuming_ports); | |
8b3d4570 SS |
627 | |
628 | set_bit(wIndex, &bus_state->rexit_ports); | |
eae5b176 SS |
629 | xhci_set_link_state(xhci, port_array, wIndex, |
630 | XDEV_U0); | |
8b3d4570 SS |
631 | |
632 | spin_unlock_irqrestore(&xhci->lock, flags); | |
633 | time_left = wait_for_completion_timeout( | |
634 | &bus_state->rexit_done[wIndex], | |
635 | msecs_to_jiffies( | |
636 | XHCI_MAX_REXIT_TIMEOUT)); | |
637 | spin_lock_irqsave(&xhci->lock, flags); | |
638 | ||
639 | if (time_left) { | |
640 | slot_id = xhci_find_slot_id_by_port(hcd, | |
641 | xhci, wIndex + 1); | |
642 | if (!slot_id) { | |
643 | xhci_dbg(xhci, "slot_id is zero\n"); | |
644 | return 0xffffffff; | |
645 | } | |
646 | xhci_ring_device(xhci, slot_id); | |
647 | } else { | |
b0ba9720 | 648 | int port_status = readl(port_array[wIndex]); |
8b3d4570 SS |
649 | xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n", |
650 | XHCI_MAX_REXIT_TIMEOUT, | |
651 | port_status); | |
652 | status |= USB_PORT_STAT_SUSPEND; | |
653 | clear_bit(wIndex, &bus_state->rexit_ports); | |
eae5b176 | 654 | } |
8b3d4570 | 655 | |
eae5b176 SS |
656 | bus_state->port_c_suspend |= 1 << wIndex; |
657 | bus_state->suspended_ports &= ~(1 << wIndex); | |
658 | } else { | |
659 | /* | |
660 | * The resume has been signaling for less than | |
661 | * 20ms. Report the port status as SUSPEND, | |
662 | * let the usbcore check port status again | |
663 | * and clear resume signaling later. | |
664 | */ | |
665 | status |= USB_PORT_STAT_SUSPEND; | |
666 | } | |
667 | } | |
668 | if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 | |
669 | && (raw_port_status & PORT_POWER) | |
670 | && (bus_state->suspended_ports & (1 << wIndex))) { | |
671 | bus_state->suspended_ports &= ~(1 << wIndex); | |
672 | if (hcd->speed != HCD_USB3) | |
673 | bus_state->port_c_suspend |= 1 << wIndex; | |
674 | } | |
675 | if (raw_port_status & PORT_CONNECT) { | |
676 | status |= USB_PORT_STAT_CONNECTION; | |
677 | status |= xhci_port_speed(raw_port_status); | |
678 | } | |
679 | if (raw_port_status & PORT_PE) | |
680 | status |= USB_PORT_STAT_ENABLE; | |
681 | if (raw_port_status & PORT_OC) | |
682 | status |= USB_PORT_STAT_OVERCURRENT; | |
683 | if (raw_port_status & PORT_RESET) | |
684 | status |= USB_PORT_STAT_RESET; | |
685 | if (raw_port_status & PORT_POWER) { | |
686 | if (hcd->speed == HCD_USB3) | |
687 | status |= USB_SS_PORT_STAT_POWER; | |
688 | else | |
689 | status |= USB_PORT_STAT_POWER; | |
690 | } | |
063ebeb4 | 691 | /* Update Port Link State */ |
eae5b176 | 692 | if (hcd->speed == HCD_USB3) { |
96908589 | 693 | xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status); |
eae5b176 SS |
694 | /* |
695 | * Verify if all USB3 Ports Have entered U0 already. | |
696 | * Delete Compliance Mode Timer if so. | |
697 | */ | |
698 | xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex); | |
063ebeb4 SS |
699 | } else { |
700 | xhci_hub_report_usb2_link_state(&status, raw_port_status); | |
eae5b176 SS |
701 | } |
702 | if (bus_state->port_c_suspend & (1 << wIndex)) | |
703 | status |= 1 << USB_PORT_FEAT_C_SUSPEND; | |
704 | ||
705 | return status; | |
706 | } | |
707 | ||
0f2a7930 SS |
708 | int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, |
709 | u16 wIndex, char *buf, u16 wLength) | |
710 | { | |
711 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
a0885924 | 712 | int max_ports; |
0f2a7930 | 713 | unsigned long flags; |
c9682dff | 714 | u32 temp, status; |
0f2a7930 | 715 | int retval = 0; |
28ccd296 | 716 | __le32 __iomem **port_array; |
be88fe4f | 717 | int slot_id; |
20b67cf5 | 718 | struct xhci_bus_state *bus_state; |
2c441780 | 719 | u16 link_state = 0; |
4296c70a | 720 | u16 wake_mask = 0; |
797b0ca5 | 721 | u16 timeout = 0; |
0f2a7930 | 722 | |
a0885924 | 723 | max_ports = xhci_get_ports(hcd, &port_array); |
20b67cf5 | 724 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
0f2a7930 SS |
725 | |
726 | spin_lock_irqsave(&xhci->lock, flags); | |
727 | switch (typeReq) { | |
728 | case GetHubStatus: | |
729 | /* No power source, over-current reported per port */ | |
730 | memset(buf, 0, 4); | |
731 | break; | |
732 | case GetHubDescriptor: | |
4bbb0ace SS |
733 | /* Check to make sure userspace is asking for the USB 3.0 hub |
734 | * descriptor for the USB 3.0 roothub. If not, we stall the | |
735 | * endpoint, like external hubs do. | |
736 | */ | |
737 | if (hcd->speed == HCD_USB3 && | |
738 | (wLength < USB_DT_SS_HUB_SIZE || | |
739 | wValue != (USB_DT_SS_HUB << 8))) { | |
740 | xhci_dbg(xhci, "Wrong hub descriptor type for " | |
741 | "USB 3.0 roothub.\n"); | |
742 | goto error; | |
743 | } | |
f6ff0ac8 SS |
744 | xhci_hub_descriptor(hcd, xhci, |
745 | (struct usb_hub_descriptor *) buf); | |
0f2a7930 | 746 | break; |
48e82361 SS |
747 | case DeviceRequest | USB_REQ_GET_DESCRIPTOR: |
748 | if ((wValue & 0xff00) != (USB_DT_BOS << 8)) | |
749 | goto error; | |
750 | ||
751 | if (hcd->speed != HCD_USB3) | |
752 | goto error; | |
753 | ||
af3a23ef | 754 | /* Set the U1 and U2 exit latencies. */ |
48e82361 SS |
755 | memcpy(buf, &usb_bos_descriptor, |
756 | USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE); | |
25cd2882 SS |
757 | if ((xhci->quirks & XHCI_LPM_SUPPORT)) { |
758 | temp = readl(&xhci->cap_regs->hcs_params3); | |
759 | buf[12] = HCS_U1_LATENCY(temp); | |
760 | put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); | |
761 | } | |
48e82361 | 762 | |
af3a23ef | 763 | /* Indicate whether the host has LTM support. */ |
b0ba9720 | 764 | temp = readl(&xhci->cap_regs->hcc_params); |
af3a23ef SS |
765 | if (HCC_LTC(temp)) |
766 | buf[8] |= USB_LTM_SUPPORT; | |
767 | ||
48e82361 SS |
768 | spin_unlock_irqrestore(&xhci->lock, flags); |
769 | return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; | |
0f2a7930 | 770 | case GetPortStatus: |
a0885924 | 771 | if (!wIndex || wIndex > max_ports) |
0f2a7930 SS |
772 | goto error; |
773 | wIndex--; | |
b0ba9720 | 774 | temp = readl(port_array[wIndex]); |
f9de8151 SS |
775 | if (temp == 0xffffffff) { |
776 | retval = -ENODEV; | |
777 | break; | |
778 | } | |
eae5b176 | 779 | status = xhci_get_port_status(hcd, bus_state, port_array, |
8b3d4570 | 780 | wIndex, temp, flags); |
eae5b176 SS |
781 | if (status == 0xffffffff) |
782 | goto error; | |
0ed9a57e | 783 | |
eae5b176 SS |
784 | xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", |
785 | wIndex, temp); | |
0f2a7930 | 786 | xhci_dbg(xhci, "Get port status returned 0x%x\n", status); |
eae5b176 | 787 | |
0f2a7930 SS |
788 | put_unaligned(cpu_to_le32(status), (__le32 *) buf); |
789 | break; | |
790 | case SetPortFeature: | |
2c441780 AX |
791 | if (wValue == USB_PORT_FEAT_LINK_STATE) |
792 | link_state = (wIndex & 0xff00) >> 3; | |
4296c70a SS |
793 | if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK) |
794 | wake_mask = wIndex & 0xff00; | |
797b0ca5 SS |
795 | /* The MSB of wIndex is the U1/U2 timeout */ |
796 | timeout = (wIndex & 0xff00) >> 8; | |
0f2a7930 | 797 | wIndex &= 0xff; |
a0885924 | 798 | if (!wIndex || wIndex > max_ports) |
0f2a7930 SS |
799 | goto error; |
800 | wIndex--; | |
b0ba9720 | 801 | temp = readl(port_array[wIndex]); |
f9de8151 SS |
802 | if (temp == 0xffffffff) { |
803 | retval = -ENODEV; | |
804 | break; | |
805 | } | |
0f2a7930 | 806 | temp = xhci_port_state_to_neutral(temp); |
4bbb0ace | 807 | /* FIXME: What new port features do we need to support? */ |
0f2a7930 | 808 | switch (wValue) { |
be88fe4f | 809 | case USB_PORT_FEAT_SUSPEND: |
b0ba9720 | 810 | temp = readl(port_array[wIndex]); |
65580b43 AX |
811 | if ((temp & PORT_PLS_MASK) != XDEV_U0) { |
812 | /* Resume the port to U0 first */ | |
813 | xhci_set_link_state(xhci, port_array, wIndex, | |
814 | XDEV_U0); | |
815 | spin_unlock_irqrestore(&xhci->lock, flags); | |
816 | msleep(10); | |
817 | spin_lock_irqsave(&xhci->lock, flags); | |
818 | } | |
be88fe4f AX |
819 | /* In spec software should not attempt to suspend |
820 | * a port unless the port reports that it is in the | |
821 | * enabled (PED = ‘1’,PLS < ‘3’) state. | |
822 | */ | |
b0ba9720 | 823 | temp = readl(port_array[wIndex]); |
be88fe4f AX |
824 | if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) |
825 | || (temp & PORT_PLS_MASK) >= XDEV_U3) { | |
826 | xhci_warn(xhci, "USB core suspending device " | |
827 | "not in U0/U1/U2.\n"); | |
828 | goto error; | |
829 | } | |
830 | ||
5233630f SS |
831 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
832 | wIndex + 1); | |
be88fe4f AX |
833 | if (!slot_id) { |
834 | xhci_warn(xhci, "slot_id is zero\n"); | |
835 | goto error; | |
836 | } | |
837 | /* unlock to execute stop endpoint commands */ | |
838 | spin_unlock_irqrestore(&xhci->lock, flags); | |
839 | xhci_stop_device(xhci, slot_id, 1); | |
840 | spin_lock_irqsave(&xhci->lock, flags); | |
841 | ||
c9682dff | 842 | xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3); |
be88fe4f AX |
843 | |
844 | spin_unlock_irqrestore(&xhci->lock, flags); | |
845 | msleep(10); /* wait device to enter */ | |
846 | spin_lock_irqsave(&xhci->lock, flags); | |
847 | ||
b0ba9720 | 848 | temp = readl(port_array[wIndex]); |
20b67cf5 | 849 | bus_state->suspended_ports |= 1 << wIndex; |
be88fe4f | 850 | break; |
2c441780 | 851 | case USB_PORT_FEAT_LINK_STATE: |
b0ba9720 | 852 | temp = readl(port_array[wIndex]); |
41e7e056 SS |
853 | |
854 | /* Disable port */ | |
855 | if (link_state == USB_SS_PORT_LS_SS_DISABLED) { | |
856 | xhci_dbg(xhci, "Disable port %d\n", wIndex); | |
857 | temp = xhci_port_state_to_neutral(temp); | |
858 | /* | |
859 | * Clear all change bits, so that we get a new | |
860 | * connection event. | |
861 | */ | |
862 | temp |= PORT_CSC | PORT_PEC | PORT_WRC | | |
863 | PORT_OCC | PORT_RC | PORT_PLC | | |
864 | PORT_CEC; | |
204b7793 | 865 | writel(temp | PORT_PE, port_array[wIndex]); |
b0ba9720 | 866 | temp = readl(port_array[wIndex]); |
41e7e056 SS |
867 | break; |
868 | } | |
869 | ||
870 | /* Put link in RxDetect (enable port) */ | |
871 | if (link_state == USB_SS_PORT_LS_RX_DETECT) { | |
872 | xhci_dbg(xhci, "Enable port %d\n", wIndex); | |
873 | xhci_set_link_state(xhci, port_array, wIndex, | |
874 | link_state); | |
b0ba9720 | 875 | temp = readl(port_array[wIndex]); |
41e7e056 SS |
876 | break; |
877 | } | |
878 | ||
2c441780 | 879 | /* Software should not attempt to set |
41e7e056 | 880 | * port link state above '3' (U3) and the port |
2c441780 AX |
881 | * must be enabled. |
882 | */ | |
883 | if ((temp & PORT_PE) == 0 || | |
41e7e056 | 884 | (link_state > USB_SS_PORT_LS_U3)) { |
2c441780 AX |
885 | xhci_warn(xhci, "Cannot set link state.\n"); |
886 | goto error; | |
887 | } | |
888 | ||
889 | if (link_state == USB_SS_PORT_LS_U3) { | |
890 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, | |
891 | wIndex + 1); | |
892 | if (slot_id) { | |
893 | /* unlock to execute stop endpoint | |
894 | * commands */ | |
895 | spin_unlock_irqrestore(&xhci->lock, | |
896 | flags); | |
897 | xhci_stop_device(xhci, slot_id, 1); | |
898 | spin_lock_irqsave(&xhci->lock, flags); | |
899 | } | |
900 | } | |
901 | ||
c9682dff AX |
902 | xhci_set_link_state(xhci, port_array, wIndex, |
903 | link_state); | |
2c441780 AX |
904 | |
905 | spin_unlock_irqrestore(&xhci->lock, flags); | |
906 | msleep(20); /* wait device to enter */ | |
907 | spin_lock_irqsave(&xhci->lock, flags); | |
908 | ||
b0ba9720 | 909 | temp = readl(port_array[wIndex]); |
2c441780 AX |
910 | if (link_state == USB_SS_PORT_LS_U3) |
911 | bus_state->suspended_ports |= 1 << wIndex; | |
912 | break; | |
0f2a7930 SS |
913 | case USB_PORT_FEAT_POWER: |
914 | /* | |
915 | * Turn on ports, even if there isn't per-port switching. | |
916 | * HC will report connect events even before this is set. | |
37ebb549 | 917 | * However, hub_wq will ignore the roothub events until |
0f2a7930 SS |
918 | * the roothub is registered. |
919 | */ | |
204b7793 | 920 | writel(temp | PORT_POWER, port_array[wIndex]); |
0f2a7930 | 921 | |
b0ba9720 | 922 | temp = readl(port_array[wIndex]); |
0f2a7930 | 923 | xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); |
f7ac7787 | 924 | |
170ed807 | 925 | spin_unlock_irqrestore(&xhci->lock, flags); |
f7ac7787 LT |
926 | temp = usb_acpi_power_manageable(hcd->self.root_hub, |
927 | wIndex); | |
928 | if (temp) | |
929 | usb_acpi_set_power_state(hcd->self.root_hub, | |
930 | wIndex, true); | |
170ed807 | 931 | spin_lock_irqsave(&xhci->lock, flags); |
0f2a7930 SS |
932 | break; |
933 | case USB_PORT_FEAT_RESET: | |
934 | temp = (temp | PORT_RESET); | |
204b7793 | 935 | writel(temp, port_array[wIndex]); |
0f2a7930 | 936 | |
b0ba9720 | 937 | temp = readl(port_array[wIndex]); |
0f2a7930 SS |
938 | xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); |
939 | break; | |
4296c70a SS |
940 | case USB_PORT_FEAT_REMOTE_WAKE_MASK: |
941 | xhci_set_remote_wake_mask(xhci, port_array, | |
942 | wIndex, wake_mask); | |
b0ba9720 | 943 | temp = readl(port_array[wIndex]); |
4296c70a SS |
944 | xhci_dbg(xhci, "set port remote wake mask, " |
945 | "actual port %d status = 0x%x\n", | |
946 | wIndex, temp); | |
947 | break; | |
a11496eb AX |
948 | case USB_PORT_FEAT_BH_PORT_RESET: |
949 | temp |= PORT_WR; | |
204b7793 | 950 | writel(temp, port_array[wIndex]); |
a11496eb | 951 | |
b0ba9720 | 952 | temp = readl(port_array[wIndex]); |
a11496eb | 953 | break; |
797b0ca5 SS |
954 | case USB_PORT_FEAT_U1_TIMEOUT: |
955 | if (hcd->speed != HCD_USB3) | |
956 | goto error; | |
b0ba9720 | 957 | temp = readl(port_array[wIndex] + PORTPMSC); |
797b0ca5 SS |
958 | temp &= ~PORT_U1_TIMEOUT_MASK; |
959 | temp |= PORT_U1_TIMEOUT(timeout); | |
204b7793 | 960 | writel(temp, port_array[wIndex] + PORTPMSC); |
797b0ca5 SS |
961 | break; |
962 | case USB_PORT_FEAT_U2_TIMEOUT: | |
963 | if (hcd->speed != HCD_USB3) | |
964 | goto error; | |
b0ba9720 | 965 | temp = readl(port_array[wIndex] + PORTPMSC); |
797b0ca5 SS |
966 | temp &= ~PORT_U2_TIMEOUT_MASK; |
967 | temp |= PORT_U2_TIMEOUT(timeout); | |
204b7793 | 968 | writel(temp, port_array[wIndex] + PORTPMSC); |
797b0ca5 | 969 | break; |
0f2a7930 SS |
970 | default: |
971 | goto error; | |
972 | } | |
5308a91b | 973 | /* unblock any posted writes */ |
b0ba9720 | 974 | temp = readl(port_array[wIndex]); |
0f2a7930 SS |
975 | break; |
976 | case ClearPortFeature: | |
a0885924 | 977 | if (!wIndex || wIndex > max_ports) |
0f2a7930 SS |
978 | goto error; |
979 | wIndex--; | |
b0ba9720 | 980 | temp = readl(port_array[wIndex]); |
f9de8151 SS |
981 | if (temp == 0xffffffff) { |
982 | retval = -ENODEV; | |
983 | break; | |
984 | } | |
4bbb0ace | 985 | /* FIXME: What new port features do we need to support? */ |
0f2a7930 SS |
986 | temp = xhci_port_state_to_neutral(temp); |
987 | switch (wValue) { | |
be88fe4f | 988 | case USB_PORT_FEAT_SUSPEND: |
b0ba9720 | 989 | temp = readl(port_array[wIndex]); |
be88fe4f AX |
990 | xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); |
991 | xhci_dbg(xhci, "PORTSC %04x\n", temp); | |
992 | if (temp & PORT_RESET) | |
993 | goto error; | |
5ac04bf1 | 994 | if ((temp & PORT_PLS_MASK) == XDEV_U3) { |
be88fe4f AX |
995 | if ((temp & PORT_PE) == 0) |
996 | goto error; | |
be88fe4f | 997 | |
c9682dff AX |
998 | xhci_set_link_state(xhci, port_array, wIndex, |
999 | XDEV_RESUME); | |
1000 | spin_unlock_irqrestore(&xhci->lock, flags); | |
a7114230 AX |
1001 | msleep(20); |
1002 | spin_lock_irqsave(&xhci->lock, flags); | |
c9682dff AX |
1003 | xhci_set_link_state(xhci, port_array, wIndex, |
1004 | XDEV_U0); | |
be88fe4f | 1005 | } |
a7114230 | 1006 | bus_state->port_c_suspend |= 1 << wIndex; |
be88fe4f | 1007 | |
5233630f SS |
1008 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1009 | wIndex + 1); | |
be88fe4f AX |
1010 | if (!slot_id) { |
1011 | xhci_dbg(xhci, "slot_id is zero\n"); | |
1012 | goto error; | |
1013 | } | |
1014 | xhci_ring_device(xhci, slot_id); | |
1015 | break; | |
1016 | case USB_PORT_FEAT_C_SUSPEND: | |
20b67cf5 | 1017 | bus_state->port_c_suspend &= ~(1 << wIndex); |
0f2a7930 | 1018 | case USB_PORT_FEAT_C_RESET: |
a11496eb | 1019 | case USB_PORT_FEAT_C_BH_PORT_RESET: |
0f2a7930 | 1020 | case USB_PORT_FEAT_C_CONNECTION: |
0f2a7930 | 1021 | case USB_PORT_FEAT_C_OVER_CURRENT: |
6219c047 | 1022 | case USB_PORT_FEAT_C_ENABLE: |
85387c0e | 1023 | case USB_PORT_FEAT_C_PORT_LINK_STATE: |
9425183d | 1024 | case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: |
34fb562a | 1025 | xhci_clear_port_change_bit(xhci, wValue, wIndex, |
5308a91b | 1026 | port_array[wIndex], temp); |
0f2a7930 | 1027 | break; |
6219c047 | 1028 | case USB_PORT_FEAT_ENABLE: |
f6ff0ac8 | 1029 | xhci_disable_port(hcd, xhci, wIndex, |
5308a91b | 1030 | port_array[wIndex], temp); |
6219c047 | 1031 | break; |
693d8eb8 | 1032 | case USB_PORT_FEAT_POWER: |
204b7793 | 1033 | writel(temp & ~PORT_POWER, port_array[wIndex]); |
f7ac7787 | 1034 | |
170ed807 | 1035 | spin_unlock_irqrestore(&xhci->lock, flags); |
f7ac7787 LT |
1036 | temp = usb_acpi_power_manageable(hcd->self.root_hub, |
1037 | wIndex); | |
1038 | if (temp) | |
1039 | usb_acpi_set_power_state(hcd->self.root_hub, | |
1040 | wIndex, false); | |
170ed807 | 1041 | spin_lock_irqsave(&xhci->lock, flags); |
693d8eb8 | 1042 | break; |
0f2a7930 SS |
1043 | default: |
1044 | goto error; | |
1045 | } | |
0f2a7930 SS |
1046 | break; |
1047 | default: | |
1048 | error: | |
1049 | /* "stall" on error */ | |
1050 | retval = -EPIPE; | |
1051 | } | |
1052 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1053 | return retval; | |
1054 | } | |
1055 | ||
1056 | /* | |
1057 | * Returns 0 if the status hasn't changed, or the number of bytes in buf. | |
1058 | * Ports are 0-indexed from the HCD point of view, | |
1059 | * and 1-indexed from the USB core pointer of view. | |
0f2a7930 SS |
1060 | * |
1061 | * Note that the status change bits will be cleared as soon as a port status | |
1062 | * change event is generated, so we use the saved status from that event. | |
1063 | */ | |
1064 | int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) | |
1065 | { | |
1066 | unsigned long flags; | |
1067 | u32 temp, status; | |
56192531 | 1068 | u32 mask; |
0f2a7930 SS |
1069 | int i, retval; |
1070 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
a0885924 | 1071 | int max_ports; |
28ccd296 | 1072 | __le32 __iomem **port_array; |
20b67cf5 | 1073 | struct xhci_bus_state *bus_state; |
c52804a4 | 1074 | bool reset_change = false; |
0f2a7930 | 1075 | |
a0885924 | 1076 | max_ports = xhci_get_ports(hcd, &port_array); |
20b67cf5 | 1077 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
0f2a7930 SS |
1078 | |
1079 | /* Initial status is no changes */ | |
a0885924 | 1080 | retval = (max_ports + 8) / 8; |
419a8e81 | 1081 | memset(buf, 0, retval); |
f370b996 AX |
1082 | |
1083 | /* | |
1084 | * Inform the usbcore about resume-in-progress by returning | |
1085 | * a non-zero value even if there are no status changes. | |
1086 | */ | |
1087 | status = bus_state->resuming_ports; | |
0f2a7930 | 1088 | |
9425183d | 1089 | mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC; |
56192531 | 1090 | |
0f2a7930 SS |
1091 | spin_lock_irqsave(&xhci->lock, flags); |
1092 | /* For each port, did anything change? If so, set that bit in buf. */ | |
a0885924 | 1093 | for (i = 0; i < max_ports; i++) { |
b0ba9720 | 1094 | temp = readl(port_array[i]); |
f9de8151 SS |
1095 | if (temp == 0xffffffff) { |
1096 | retval = -ENODEV; | |
1097 | break; | |
1098 | } | |
56192531 | 1099 | if ((temp & mask) != 0 || |
20b67cf5 SS |
1100 | (bus_state->port_c_suspend & 1 << i) || |
1101 | (bus_state->resume_done[i] && time_after_eq( | |
1102 | jiffies, bus_state->resume_done[i]))) { | |
419a8e81 | 1103 | buf[(i + 1) / 8] |= 1 << (i + 1) % 8; |
0f2a7930 SS |
1104 | status = 1; |
1105 | } | |
c52804a4 SS |
1106 | if ((temp & PORT_RC)) |
1107 | reset_change = true; | |
1108 | } | |
1109 | if (!status && !reset_change) { | |
1110 | xhci_dbg(xhci, "%s: stopping port polling.\n", __func__); | |
1111 | clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
0f2a7930 SS |
1112 | } |
1113 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1114 | return status ? retval : 0; | |
1115 | } | |
9777e3ce AX |
1116 | |
1117 | #ifdef CONFIG_PM | |
1118 | ||
1119 | int xhci_bus_suspend(struct usb_hcd *hcd) | |
1120 | { | |
1121 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
518e848e | 1122 | int max_ports, port_index; |
28ccd296 | 1123 | __le32 __iomem **port_array; |
20b67cf5 | 1124 | struct xhci_bus_state *bus_state; |
9777e3ce AX |
1125 | unsigned long flags; |
1126 | ||
a0885924 | 1127 | max_ports = xhci_get_ports(hcd, &port_array); |
20b67cf5 | 1128 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
9777e3ce AX |
1129 | |
1130 | spin_lock_irqsave(&xhci->lock, flags); | |
1131 | ||
1132 | if (hcd->self.root_hub->do_remote_wakeup) { | |
fac4271d ZJC |
1133 | if (bus_state->resuming_ports || /* USB2 */ |
1134 | bus_state->port_remote_wakeup) { /* USB3 */ | |
f370b996 | 1135 | spin_unlock_irqrestore(&xhci->lock, flags); |
fac4271d | 1136 | xhci_dbg(xhci, "suspend failed because a port is resuming\n"); |
f370b996 | 1137 | return -EBUSY; |
9777e3ce AX |
1138 | } |
1139 | } | |
1140 | ||
518e848e | 1141 | port_index = max_ports; |
20b67cf5 | 1142 | bus_state->bus_suspended = 0; |
518e848e | 1143 | while (port_index--) { |
9777e3ce | 1144 | /* suspend the port if the port is not suspended */ |
9777e3ce AX |
1145 | u32 t1, t2; |
1146 | int slot_id; | |
1147 | ||
b0ba9720 | 1148 | t1 = readl(port_array[port_index]); |
9777e3ce AX |
1149 | t2 = xhci_port_state_to_neutral(t1); |
1150 | ||
1151 | if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) { | |
518e848e | 1152 | xhci_dbg(xhci, "port %d not suspended\n", port_index); |
5233630f | 1153 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
518e848e | 1154 | port_index + 1); |
9777e3ce AX |
1155 | if (slot_id) { |
1156 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1157 | xhci_stop_device(xhci, slot_id, 1); | |
1158 | spin_lock_irqsave(&xhci->lock, flags); | |
1159 | } | |
1160 | t2 &= ~PORT_PLS_MASK; | |
1161 | t2 |= PORT_LINK_STROBE | XDEV_U3; | |
20b67cf5 | 1162 | set_bit(port_index, &bus_state->bus_suspended); |
9777e3ce | 1163 | } |
4296c70a | 1164 | /* USB core sets remote wake mask for USB 3.0 hubs, |
ceb6c9c8 | 1165 | * including the USB 3.0 roothub, but only if CONFIG_PM |
4296c70a SS |
1166 | * is enabled, so also enable remote wake here. |
1167 | */ | |
9b41ebd3 | 1168 | if (hcd->self.root_hub->do_remote_wakeup) { |
9777e3ce AX |
1169 | if (t1 & PORT_CONNECT) { |
1170 | t2 |= PORT_WKOC_E | PORT_WKDISC_E; | |
1171 | t2 &= ~PORT_WKCONN_E; | |
1172 | } else { | |
1173 | t2 |= PORT_WKOC_E | PORT_WKCONN_E; | |
1174 | t2 &= ~PORT_WKDISC_E; | |
1175 | } | |
1176 | } else | |
1177 | t2 &= ~PORT_WAKE_BITS; | |
1178 | ||
1179 | t1 = xhci_port_state_to_neutral(t1); | |
1180 | if (t1 != t2) | |
204b7793 | 1181 | writel(t2, port_array[port_index]); |
9777e3ce AX |
1182 | } |
1183 | hcd->state = HC_STATE_SUSPENDED; | |
20b67cf5 | 1184 | bus_state->next_statechange = jiffies + msecs_to_jiffies(10); |
9777e3ce AX |
1185 | spin_unlock_irqrestore(&xhci->lock, flags); |
1186 | return 0; | |
1187 | } | |
1188 | ||
1189 | int xhci_bus_resume(struct usb_hcd *hcd) | |
1190 | { | |
1191 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
518e848e | 1192 | int max_ports, port_index; |
28ccd296 | 1193 | __le32 __iomem **port_array; |
20b67cf5 | 1194 | struct xhci_bus_state *bus_state; |
9777e3ce AX |
1195 | u32 temp; |
1196 | unsigned long flags; | |
41485a90 MN |
1197 | unsigned long port_was_suspended = 0; |
1198 | bool need_usb2_u3_exit = false; | |
1199 | int slot_id; | |
1200 | int sret; | |
9777e3ce | 1201 | |
a0885924 | 1202 | max_ports = xhci_get_ports(hcd, &port_array); |
20b67cf5 | 1203 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
9777e3ce | 1204 | |
20b67cf5 | 1205 | if (time_before(jiffies, bus_state->next_statechange)) |
9777e3ce AX |
1206 | msleep(5); |
1207 | ||
1208 | spin_lock_irqsave(&xhci->lock, flags); | |
1209 | if (!HCD_HW_ACCESSIBLE(hcd)) { | |
1210 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1211 | return -ESHUTDOWN; | |
1212 | } | |
1213 | ||
1214 | /* delay the irqs */ | |
b0ba9720 | 1215 | temp = readl(&xhci->op_regs->command); |
9777e3ce | 1216 | temp &= ~CMD_EIE; |
204b7793 | 1217 | writel(temp, &xhci->op_regs->command); |
9777e3ce | 1218 | |
518e848e SS |
1219 | port_index = max_ports; |
1220 | while (port_index--) { | |
9777e3ce AX |
1221 | /* Check whether need resume ports. If needed |
1222 | resume port and disable remote wakeup */ | |
9777e3ce | 1223 | u32 temp; |
9777e3ce | 1224 | |
b0ba9720 | 1225 | temp = readl(port_array[port_index]); |
9777e3ce AX |
1226 | if (DEV_SUPERSPEED(temp)) |
1227 | temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); | |
1228 | else | |
1229 | temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); | |
20b67cf5 | 1230 | if (test_bit(port_index, &bus_state->bus_suspended) && |
9777e3ce | 1231 | (temp & PORT_PLS_MASK)) { |
41485a90 MN |
1232 | set_bit(port_index, &port_was_suspended); |
1233 | if (!DEV_SUPERSPEED(temp)) { | |
c9682dff AX |
1234 | xhci_set_link_state(xhci, port_array, |
1235 | port_index, XDEV_RESUME); | |
41485a90 | 1236 | need_usb2_u3_exit = true; |
9777e3ce | 1237 | } |
9777e3ce | 1238 | } else |
204b7793 | 1239 | writel(temp, port_array[port_index]); |
9777e3ce AX |
1240 | } |
1241 | ||
41485a90 MN |
1242 | if (need_usb2_u3_exit) { |
1243 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1244 | msleep(20); | |
1245 | spin_lock_irqsave(&xhci->lock, flags); | |
1246 | } | |
1247 | ||
1248 | port_index = max_ports; | |
1249 | while (port_index--) { | |
1250 | if (!(port_was_suspended & BIT(port_index))) | |
1251 | continue; | |
1252 | /* Clear PLC to poll it later after XDEV_U0 */ | |
1253 | xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC); | |
1254 | xhci_set_link_state(xhci, port_array, port_index, XDEV_U0); | |
1255 | } | |
1256 | ||
1257 | port_index = max_ports; | |
1258 | while (port_index--) { | |
1259 | if (!(port_was_suspended & BIT(port_index))) | |
1260 | continue; | |
1261 | /* Poll and Clear PLC */ | |
1262 | sret = xhci_handshake(port_array[port_index], PORT_PLC, | |
1263 | PORT_PLC, 10 * 1000); | |
1264 | if (sret) | |
1265 | xhci_warn(xhci, "port %d resume PLC timeout\n", | |
1266 | port_index); | |
1267 | xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC); | |
1268 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1); | |
1269 | if (slot_id) | |
1270 | xhci_ring_device(xhci, slot_id); | |
1271 | } | |
1272 | ||
b0ba9720 | 1273 | (void) readl(&xhci->op_regs->command); |
9777e3ce | 1274 | |
20b67cf5 | 1275 | bus_state->next_statechange = jiffies + msecs_to_jiffies(5); |
9777e3ce | 1276 | /* re-enable irqs */ |
b0ba9720 | 1277 | temp = readl(&xhci->op_regs->command); |
9777e3ce | 1278 | temp |= CMD_EIE; |
204b7793 | 1279 | writel(temp, &xhci->op_regs->command); |
b0ba9720 | 1280 | temp = readl(&xhci->op_regs->command); |
9777e3ce AX |
1281 | |
1282 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1283 | return 0; | |
1284 | } | |
1285 | ||
436a3890 | 1286 | #endif /* CONFIG_PM */ |