Commit | Line | Data |
---|---|---|
66d4eadd SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/usb.h> | |
0ebbab37 | 24 | #include <linux/pci.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
527c6d7f | 26 | #include <linux/dmapool.h> |
66d4eadd SS |
27 | |
28 | #include "xhci.h" | |
29 | ||
0ebbab37 SS |
30 | /* |
31 | * Allocates a generic ring segment from the ring pool, sets the dma address, | |
32 | * initializes the segment to zero, and sets the private next pointer to NULL. | |
33 | * | |
34 | * Section 4.11.1.1: | |
35 | * "All components of all Command and Transfer TRBs shall be initialized to '0'" | |
36 | */ | |
37 | static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags) | |
38 | { | |
39 | struct xhci_segment *seg; | |
40 | dma_addr_t dma; | |
41 | ||
42 | seg = kzalloc(sizeof *seg, flags); | |
43 | if (!seg) | |
44 | return 0; | |
700e2052 | 45 | xhci_dbg(xhci, "Allocating priv segment structure at %p\n", seg); |
0ebbab37 SS |
46 | |
47 | seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma); | |
48 | if (!seg->trbs) { | |
49 | kfree(seg); | |
50 | return 0; | |
51 | } | |
700e2052 GKH |
52 | xhci_dbg(xhci, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n", |
53 | seg->trbs, (unsigned long long)dma); | |
0ebbab37 SS |
54 | |
55 | memset(seg->trbs, 0, SEGMENT_SIZE); | |
56 | seg->dma = dma; | |
57 | seg->next = NULL; | |
58 | ||
59 | return seg; | |
60 | } | |
61 | ||
62 | static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg) | |
63 | { | |
64 | if (!seg) | |
65 | return; | |
66 | if (seg->trbs) { | |
700e2052 GKH |
67 | xhci_dbg(xhci, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n", |
68 | seg->trbs, (unsigned long long)seg->dma); | |
0ebbab37 SS |
69 | dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma); |
70 | seg->trbs = NULL; | |
71 | } | |
700e2052 | 72 | xhci_dbg(xhci, "Freeing priv segment structure at %p\n", seg); |
0ebbab37 SS |
73 | kfree(seg); |
74 | } | |
75 | ||
76 | /* | |
77 | * Make the prev segment point to the next segment. | |
78 | * | |
79 | * Change the last TRB in the prev segment to be a Link TRB which points to the | |
80 | * DMA address of the next segment. The caller needs to set any Link TRB | |
81 | * related flags, such as End TRB, Toggle Cycle, and no snoop. | |
82 | */ | |
83 | static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev, | |
84 | struct xhci_segment *next, bool link_trbs) | |
85 | { | |
86 | u32 val; | |
87 | ||
88 | if (!prev || !next) | |
89 | return; | |
90 | prev->next = next; | |
91 | if (link_trbs) { | |
8e595a5d | 92 | prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = next->dma; |
0ebbab37 SS |
93 | |
94 | /* Set the last TRB in the segment to have a TRB type ID of Link TRB */ | |
95 | val = prev->trbs[TRBS_PER_SEGMENT-1].link.control; | |
96 | val &= ~TRB_TYPE_BITMASK; | |
97 | val |= TRB_TYPE(TRB_LINK); | |
b0567b3f SS |
98 | /* Always set the chain bit with 0.95 hardware */ |
99 | if (xhci_link_trb_quirk(xhci)) | |
100 | val |= TRB_CHAIN; | |
0ebbab37 SS |
101 | prev->trbs[TRBS_PER_SEGMENT-1].link.control = val; |
102 | } | |
700e2052 GKH |
103 | xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n", |
104 | (unsigned long long)prev->dma, | |
105 | (unsigned long long)next->dma); | |
0ebbab37 SS |
106 | } |
107 | ||
108 | /* XXX: Do we need the hcd structure in all these functions? */ | |
f94e0186 | 109 | void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring) |
0ebbab37 SS |
110 | { |
111 | struct xhci_segment *seg; | |
112 | struct xhci_segment *first_seg; | |
113 | ||
114 | if (!ring || !ring->first_seg) | |
115 | return; | |
116 | first_seg = ring->first_seg; | |
117 | seg = first_seg->next; | |
700e2052 | 118 | xhci_dbg(xhci, "Freeing ring at %p\n", ring); |
0ebbab37 SS |
119 | while (seg != first_seg) { |
120 | struct xhci_segment *next = seg->next; | |
121 | xhci_segment_free(xhci, seg); | |
122 | seg = next; | |
123 | } | |
124 | xhci_segment_free(xhci, first_seg); | |
125 | ring->first_seg = NULL; | |
126 | kfree(ring); | |
127 | } | |
128 | ||
74f9fe21 SS |
129 | static void xhci_initialize_ring_info(struct xhci_ring *ring) |
130 | { | |
131 | /* The ring is empty, so the enqueue pointer == dequeue pointer */ | |
132 | ring->enqueue = ring->first_seg->trbs; | |
133 | ring->enq_seg = ring->first_seg; | |
134 | ring->dequeue = ring->enqueue; | |
135 | ring->deq_seg = ring->first_seg; | |
136 | /* The ring is initialized to 0. The producer must write 1 to the cycle | |
137 | * bit to handover ownership of the TRB, so PCS = 1. The consumer must | |
138 | * compare CCS to the cycle bit to check ownership, so CCS = 1. | |
139 | */ | |
140 | ring->cycle_state = 1; | |
141 | /* Not necessary for new rings, but needed for re-initialized rings */ | |
142 | ring->enq_updates = 0; | |
143 | ring->deq_updates = 0; | |
144 | } | |
145 | ||
0ebbab37 SS |
146 | /** |
147 | * Create a new ring with zero or more segments. | |
148 | * | |
149 | * Link each segment together into a ring. | |
150 | * Set the end flag and the cycle toggle bit on the last segment. | |
151 | * See section 4.9.1 and figures 15 and 16. | |
152 | */ | |
153 | static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, | |
154 | unsigned int num_segs, bool link_trbs, gfp_t flags) | |
155 | { | |
156 | struct xhci_ring *ring; | |
157 | struct xhci_segment *prev; | |
158 | ||
159 | ring = kzalloc(sizeof *(ring), flags); | |
700e2052 | 160 | xhci_dbg(xhci, "Allocating ring at %p\n", ring); |
0ebbab37 SS |
161 | if (!ring) |
162 | return 0; | |
163 | ||
d0e96f5a | 164 | INIT_LIST_HEAD(&ring->td_list); |
0ebbab37 SS |
165 | if (num_segs == 0) |
166 | return ring; | |
167 | ||
168 | ring->first_seg = xhci_segment_alloc(xhci, flags); | |
169 | if (!ring->first_seg) | |
170 | goto fail; | |
171 | num_segs--; | |
172 | ||
173 | prev = ring->first_seg; | |
174 | while (num_segs > 0) { | |
175 | struct xhci_segment *next; | |
176 | ||
177 | next = xhci_segment_alloc(xhci, flags); | |
178 | if (!next) | |
179 | goto fail; | |
180 | xhci_link_segments(xhci, prev, next, link_trbs); | |
181 | ||
182 | prev = next; | |
183 | num_segs--; | |
184 | } | |
185 | xhci_link_segments(xhci, prev, ring->first_seg, link_trbs); | |
186 | ||
187 | if (link_trbs) { | |
188 | /* See section 4.9.2.1 and 6.4.4.1 */ | |
189 | prev->trbs[TRBS_PER_SEGMENT-1].link.control |= (LINK_TOGGLE); | |
190 | xhci_dbg(xhci, "Wrote link toggle flag to" | |
700e2052 GKH |
191 | " segment %p (virtual), 0x%llx (DMA)\n", |
192 | prev, (unsigned long long)prev->dma); | |
0ebbab37 | 193 | } |
74f9fe21 | 194 | xhci_initialize_ring_info(ring); |
0ebbab37 SS |
195 | return ring; |
196 | ||
197 | fail: | |
198 | xhci_ring_free(xhci, ring); | |
199 | return 0; | |
200 | } | |
201 | ||
412566bd SS |
202 | void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, |
203 | struct xhci_virt_device *virt_dev, | |
204 | unsigned int ep_index) | |
205 | { | |
206 | int rings_cached; | |
207 | ||
208 | rings_cached = virt_dev->num_rings_cached; | |
209 | if (rings_cached < XHCI_MAX_RINGS_CACHED) { | |
210 | virt_dev->num_rings_cached++; | |
211 | rings_cached = virt_dev->num_rings_cached; | |
212 | virt_dev->ring_cache[rings_cached] = | |
213 | virt_dev->eps[ep_index].ring; | |
214 | xhci_dbg(xhci, "Cached old ring, " | |
215 | "%d ring%s cached\n", | |
216 | rings_cached, | |
217 | (rings_cached > 1) ? "s" : ""); | |
218 | } else { | |
219 | xhci_ring_free(xhci, virt_dev->eps[ep_index].ring); | |
220 | xhci_dbg(xhci, "Ring cache full (%d rings), " | |
221 | "freeing ring\n", | |
222 | virt_dev->num_rings_cached); | |
223 | } | |
224 | virt_dev->eps[ep_index].ring = NULL; | |
225 | } | |
226 | ||
74f9fe21 SS |
227 | /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue |
228 | * pointers to the beginning of the ring. | |
229 | */ | |
230 | static void xhci_reinit_cached_ring(struct xhci_hcd *xhci, | |
231 | struct xhci_ring *ring) | |
232 | { | |
233 | struct xhci_segment *seg = ring->first_seg; | |
234 | do { | |
235 | memset(seg->trbs, 0, | |
236 | sizeof(union xhci_trb)*TRBS_PER_SEGMENT); | |
237 | /* All endpoint rings have link TRBs */ | |
238 | xhci_link_segments(xhci, seg, seg->next, 1); | |
239 | seg = seg->next; | |
240 | } while (seg != ring->first_seg); | |
241 | xhci_initialize_ring_info(ring); | |
242 | /* td list should be empty since all URBs have been cancelled, | |
243 | * but just in case... | |
244 | */ | |
245 | INIT_LIST_HEAD(&ring->td_list); | |
246 | } | |
247 | ||
d115b048 JY |
248 | #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) |
249 | ||
250 | struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, | |
251 | int type, gfp_t flags) | |
252 | { | |
253 | struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags); | |
254 | if (!ctx) | |
255 | return NULL; | |
256 | ||
257 | BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT)); | |
258 | ctx->type = type; | |
259 | ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024; | |
260 | if (type == XHCI_CTX_TYPE_INPUT) | |
261 | ctx->size += CTX_SIZE(xhci->hcc_params); | |
262 | ||
263 | ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma); | |
264 | memset(ctx->bytes, 0, ctx->size); | |
265 | return ctx; | |
266 | } | |
267 | ||
268 | void xhci_free_container_ctx(struct xhci_hcd *xhci, | |
269 | struct xhci_container_ctx *ctx) | |
270 | { | |
a1d78c16 SS |
271 | if (!ctx) |
272 | return; | |
d115b048 JY |
273 | dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma); |
274 | kfree(ctx); | |
275 | } | |
276 | ||
277 | struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, | |
278 | struct xhci_container_ctx *ctx) | |
279 | { | |
280 | BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT); | |
281 | return (struct xhci_input_control_ctx *)ctx->bytes; | |
282 | } | |
283 | ||
284 | struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, | |
285 | struct xhci_container_ctx *ctx) | |
286 | { | |
287 | if (ctx->type == XHCI_CTX_TYPE_DEVICE) | |
288 | return (struct xhci_slot_ctx *)ctx->bytes; | |
289 | ||
290 | return (struct xhci_slot_ctx *) | |
291 | (ctx->bytes + CTX_SIZE(xhci->hcc_params)); | |
292 | } | |
293 | ||
294 | struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, | |
295 | struct xhci_container_ctx *ctx, | |
296 | unsigned int ep_index) | |
297 | { | |
298 | /* increment ep index by offset of start of ep ctx array */ | |
299 | ep_index++; | |
300 | if (ctx->type == XHCI_CTX_TYPE_INPUT) | |
301 | ep_index++; | |
302 | ||
303 | return (struct xhci_ep_ctx *) | |
304 | (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params))); | |
305 | } | |
306 | ||
6f5165cf SS |
307 | static void xhci_init_endpoint_timer(struct xhci_hcd *xhci, |
308 | struct xhci_virt_ep *ep) | |
309 | { | |
310 | init_timer(&ep->stop_cmd_timer); | |
311 | ep->stop_cmd_timer.data = (unsigned long) ep; | |
312 | ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog; | |
313 | ep->xhci = xhci; | |
314 | } | |
315 | ||
d0e96f5a | 316 | /* All the xhci_tds in the ring's TD list should be freed at this point */ |
3ffbba95 SS |
317 | void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id) |
318 | { | |
319 | struct xhci_virt_device *dev; | |
320 | int i; | |
321 | ||
322 | /* Slot ID 0 is reserved */ | |
323 | if (slot_id == 0 || !xhci->devs[slot_id]) | |
324 | return; | |
325 | ||
326 | dev = xhci->devs[slot_id]; | |
8e595a5d | 327 | xhci->dcbaa->dev_context_ptrs[slot_id] = 0; |
3ffbba95 SS |
328 | if (!dev) |
329 | return; | |
330 | ||
331 | for (i = 0; i < 31; ++i) | |
63a0d9ab SS |
332 | if (dev->eps[i].ring) |
333 | xhci_ring_free(xhci, dev->eps[i].ring); | |
3ffbba95 | 334 | |
74f9fe21 SS |
335 | if (dev->ring_cache) { |
336 | for (i = 0; i < dev->num_rings_cached; i++) | |
337 | xhci_ring_free(xhci, dev->ring_cache[i]); | |
338 | kfree(dev->ring_cache); | |
339 | } | |
340 | ||
3ffbba95 | 341 | if (dev->in_ctx) |
d115b048 | 342 | xhci_free_container_ctx(xhci, dev->in_ctx); |
3ffbba95 | 343 | if (dev->out_ctx) |
d115b048 JY |
344 | xhci_free_container_ctx(xhci, dev->out_ctx); |
345 | ||
3ffbba95 SS |
346 | kfree(xhci->devs[slot_id]); |
347 | xhci->devs[slot_id] = 0; | |
348 | } | |
349 | ||
350 | int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, | |
351 | struct usb_device *udev, gfp_t flags) | |
352 | { | |
3ffbba95 | 353 | struct xhci_virt_device *dev; |
63a0d9ab | 354 | int i; |
3ffbba95 SS |
355 | |
356 | /* Slot ID 0 is reserved */ | |
357 | if (slot_id == 0 || xhci->devs[slot_id]) { | |
358 | xhci_warn(xhci, "Bad Slot ID %d\n", slot_id); | |
359 | return 0; | |
360 | } | |
361 | ||
362 | xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags); | |
363 | if (!xhci->devs[slot_id]) | |
364 | return 0; | |
365 | dev = xhci->devs[slot_id]; | |
366 | ||
d115b048 JY |
367 | /* Allocate the (output) device context that will be used in the HC. */ |
368 | dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags); | |
3ffbba95 SS |
369 | if (!dev->out_ctx) |
370 | goto fail; | |
d115b048 | 371 | |
700e2052 | 372 | xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id, |
d115b048 | 373 | (unsigned long long)dev->out_ctx->dma); |
3ffbba95 SS |
374 | |
375 | /* Allocate the (input) device context for address device command */ | |
d115b048 | 376 | dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags); |
3ffbba95 SS |
377 | if (!dev->in_ctx) |
378 | goto fail; | |
d115b048 | 379 | |
700e2052 | 380 | xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id, |
d115b048 | 381 | (unsigned long long)dev->in_ctx->dma); |
3ffbba95 | 382 | |
6f5165cf SS |
383 | /* Initialize the cancellation list and watchdog timers for each ep */ |
384 | for (i = 0; i < 31; i++) { | |
385 | xhci_init_endpoint_timer(xhci, &dev->eps[i]); | |
63a0d9ab | 386 | INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list); |
6f5165cf | 387 | } |
63a0d9ab | 388 | |
3ffbba95 | 389 | /* Allocate endpoint 0 ring */ |
63a0d9ab SS |
390 | dev->eps[0].ring = xhci_ring_alloc(xhci, 1, true, flags); |
391 | if (!dev->eps[0].ring) | |
3ffbba95 SS |
392 | goto fail; |
393 | ||
74f9fe21 SS |
394 | /* Allocate pointers to the ring cache */ |
395 | dev->ring_cache = kzalloc( | |
396 | sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED, | |
397 | flags); | |
398 | if (!dev->ring_cache) | |
399 | goto fail; | |
400 | dev->num_rings_cached = 0; | |
401 | ||
f94e0186 | 402 | init_completion(&dev->cmd_completion); |
913a8a34 | 403 | INIT_LIST_HEAD(&dev->cmd_list); |
f94e0186 | 404 | |
28c2d2ef | 405 | /* Point to output device context in dcbaa. */ |
d115b048 | 406 | xhci->dcbaa->dev_context_ptrs[slot_id] = dev->out_ctx->dma; |
700e2052 | 407 | xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n", |
3ffbba95 | 408 | slot_id, |
8e595a5d | 409 | &xhci->dcbaa->dev_context_ptrs[slot_id], |
28c2d2ef | 410 | (unsigned long long) xhci->dcbaa->dev_context_ptrs[slot_id]); |
3ffbba95 SS |
411 | |
412 | return 1; | |
413 | fail: | |
414 | xhci_free_virt_device(xhci, slot_id); | |
415 | return 0; | |
416 | } | |
417 | ||
418 | /* Setup an xHCI virtual device for a Set Address command */ | |
419 | int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev) | |
420 | { | |
421 | struct xhci_virt_device *dev; | |
422 | struct xhci_ep_ctx *ep0_ctx; | |
423 | struct usb_device *top_dev; | |
d115b048 JY |
424 | struct xhci_slot_ctx *slot_ctx; |
425 | struct xhci_input_control_ctx *ctrl_ctx; | |
3ffbba95 SS |
426 | |
427 | dev = xhci->devs[udev->slot_id]; | |
428 | /* Slot ID 0 is reserved */ | |
429 | if (udev->slot_id == 0 || !dev) { | |
430 | xhci_warn(xhci, "Slot ID %d is not assigned to this device\n", | |
431 | udev->slot_id); | |
432 | return -EINVAL; | |
433 | } | |
d115b048 JY |
434 | ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0); |
435 | ctrl_ctx = xhci_get_input_control_ctx(xhci, dev->in_ctx); | |
436 | slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx); | |
3ffbba95 SS |
437 | |
438 | /* 2) New slot context and endpoint 0 context are valid*/ | |
d115b048 | 439 | ctrl_ctx->add_flags = SLOT_FLAG | EP0_FLAG; |
3ffbba95 SS |
440 | |
441 | /* 3) Only the control endpoint is valid - one endpoint context */ | |
d115b048 | 442 | slot_ctx->dev_info |= LAST_CTX(1); |
3ffbba95 | 443 | |
4a0cd967 | 444 | slot_ctx->dev_info |= (u32) udev->route; |
3ffbba95 SS |
445 | switch (udev->speed) { |
446 | case USB_SPEED_SUPER: | |
d115b048 | 447 | slot_ctx->dev_info |= (u32) SLOT_SPEED_SS; |
3ffbba95 SS |
448 | break; |
449 | case USB_SPEED_HIGH: | |
d115b048 | 450 | slot_ctx->dev_info |= (u32) SLOT_SPEED_HS; |
3ffbba95 SS |
451 | break; |
452 | case USB_SPEED_FULL: | |
d115b048 | 453 | slot_ctx->dev_info |= (u32) SLOT_SPEED_FS; |
3ffbba95 SS |
454 | break; |
455 | case USB_SPEED_LOW: | |
d115b048 | 456 | slot_ctx->dev_info |= (u32) SLOT_SPEED_LS; |
3ffbba95 | 457 | break; |
551cdbbe | 458 | case USB_SPEED_WIRELESS: |
3ffbba95 SS |
459 | xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n"); |
460 | return -EINVAL; | |
461 | break; | |
462 | default: | |
463 | /* Speed was set earlier, this shouldn't happen. */ | |
464 | BUG(); | |
465 | } | |
466 | /* Find the root hub port this device is under */ | |
467 | for (top_dev = udev; top_dev->parent && top_dev->parent->parent; | |
468 | top_dev = top_dev->parent) | |
469 | /* Found device below root hub */; | |
d115b048 | 470 | slot_ctx->dev_info2 |= (u32) ROOT_HUB_PORT(top_dev->portnum); |
3ffbba95 SS |
471 | xhci_dbg(xhci, "Set root hub portnum to %d\n", top_dev->portnum); |
472 | ||
473 | /* Is this a LS/FS device under a HS hub? */ | |
3ffbba95 SS |
474 | if ((udev->speed == USB_SPEED_LOW || udev->speed == USB_SPEED_FULL) && |
475 | udev->tt) { | |
d115b048 JY |
476 | slot_ctx->tt_info = udev->tt->hub->slot_id; |
477 | slot_ctx->tt_info |= udev->ttport << 8; | |
07b6de10 SS |
478 | if (udev->tt->multi) |
479 | slot_ctx->dev_info |= DEV_MTT; | |
3ffbba95 | 480 | } |
700e2052 | 481 | xhci_dbg(xhci, "udev->tt = %p\n", udev->tt); |
3ffbba95 SS |
482 | xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport); |
483 | ||
484 | /* Step 4 - ring already allocated */ | |
485 | /* Step 5 */ | |
486 | ep0_ctx->ep_info2 = EP_TYPE(CTRL_EP); | |
487 | /* | |
3ffbba95 SS |
488 | * XXX: Not sure about wireless USB devices. |
489 | */ | |
47aded8a SS |
490 | switch (udev->speed) { |
491 | case USB_SPEED_SUPER: | |
3ffbba95 | 492 | ep0_ctx->ep_info2 |= MAX_PACKET(512); |
47aded8a SS |
493 | break; |
494 | case USB_SPEED_HIGH: | |
495 | /* USB core guesses at a 64-byte max packet first for FS devices */ | |
496 | case USB_SPEED_FULL: | |
497 | ep0_ctx->ep_info2 |= MAX_PACKET(64); | |
498 | break; | |
499 | case USB_SPEED_LOW: | |
3ffbba95 | 500 | ep0_ctx->ep_info2 |= MAX_PACKET(8); |
47aded8a | 501 | break; |
551cdbbe | 502 | case USB_SPEED_WIRELESS: |
47aded8a SS |
503 | xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n"); |
504 | return -EINVAL; | |
505 | break; | |
506 | default: | |
507 | /* New speed? */ | |
508 | BUG(); | |
509 | } | |
3ffbba95 SS |
510 | /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */ |
511 | ep0_ctx->ep_info2 |= MAX_BURST(0); | |
512 | ep0_ctx->ep_info2 |= ERROR_COUNT(3); | |
513 | ||
8e595a5d | 514 | ep0_ctx->deq = |
63a0d9ab SS |
515 | dev->eps[0].ring->first_seg->dma; |
516 | ep0_ctx->deq |= dev->eps[0].ring->cycle_state; | |
3ffbba95 SS |
517 | |
518 | /* Steps 7 and 8 were done in xhci_alloc_virt_device() */ | |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
f94e0186 SS |
523 | /* Return the polling or NAK interval. |
524 | * | |
525 | * The polling interval is expressed in "microframes". If xHCI's Interval field | |
526 | * is set to N, it will service the endpoint every 2^(Interval)*125us. | |
527 | * | |
528 | * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval | |
529 | * is set to 0. | |
530 | */ | |
531 | static inline unsigned int xhci_get_endpoint_interval(struct usb_device *udev, | |
532 | struct usb_host_endpoint *ep) | |
533 | { | |
534 | unsigned int interval = 0; | |
535 | ||
536 | switch (udev->speed) { | |
537 | case USB_SPEED_HIGH: | |
538 | /* Max NAK rate */ | |
539 | if (usb_endpoint_xfer_control(&ep->desc) || | |
540 | usb_endpoint_xfer_bulk(&ep->desc)) | |
541 | interval = ep->desc.bInterval; | |
542 | /* Fall through - SS and HS isoc/int have same decoding */ | |
543 | case USB_SPEED_SUPER: | |
544 | if (usb_endpoint_xfer_int(&ep->desc) || | |
545 | usb_endpoint_xfer_isoc(&ep->desc)) { | |
546 | if (ep->desc.bInterval == 0) | |
547 | interval = 0; | |
548 | else | |
549 | interval = ep->desc.bInterval - 1; | |
550 | if (interval > 15) | |
551 | interval = 15; | |
552 | if (interval != ep->desc.bInterval + 1) | |
553 | dev_warn(&udev->dev, "ep %#x - rounding interval to %d microframes\n", | |
554 | ep->desc.bEndpointAddress, 1 << interval); | |
555 | } | |
556 | break; | |
557 | /* Convert bInterval (in 1-255 frames) to microframes and round down to | |
558 | * nearest power of 2. | |
559 | */ | |
560 | case USB_SPEED_FULL: | |
561 | case USB_SPEED_LOW: | |
562 | if (usb_endpoint_xfer_int(&ep->desc) || | |
563 | usb_endpoint_xfer_isoc(&ep->desc)) { | |
564 | interval = fls(8*ep->desc.bInterval) - 1; | |
565 | if (interval > 10) | |
566 | interval = 10; | |
567 | if (interval < 3) | |
568 | interval = 3; | |
569 | if ((1 << interval) != 8*ep->desc.bInterval) | |
9ce669a8 SS |
570 | dev_warn(&udev->dev, |
571 | "ep %#x - rounding interval" | |
572 | " to %d microframes, " | |
573 | "ep desc says %d microframes\n", | |
574 | ep->desc.bEndpointAddress, | |
575 | 1 << interval, | |
576 | 8*ep->desc.bInterval); | |
f94e0186 SS |
577 | } |
578 | break; | |
579 | default: | |
580 | BUG(); | |
581 | } | |
582 | return EP_INTERVAL(interval); | |
583 | } | |
584 | ||
1cf62246 SS |
585 | /* The "Mult" field in the endpoint context is only set for SuperSpeed devices. |
586 | * High speed endpoint descriptors can define "the number of additional | |
587 | * transaction opportunities per microframe", but that goes in the Max Burst | |
588 | * endpoint context field. | |
589 | */ | |
590 | static inline u32 xhci_get_endpoint_mult(struct usb_device *udev, | |
591 | struct usb_host_endpoint *ep) | |
592 | { | |
593 | if (udev->speed != USB_SPEED_SUPER || !ep->ss_ep_comp) | |
594 | return 0; | |
595 | return ep->ss_ep_comp->desc.bmAttributes; | |
596 | } | |
597 | ||
f94e0186 SS |
598 | static inline u32 xhci_get_endpoint_type(struct usb_device *udev, |
599 | struct usb_host_endpoint *ep) | |
600 | { | |
601 | int in; | |
602 | u32 type; | |
603 | ||
604 | in = usb_endpoint_dir_in(&ep->desc); | |
605 | if (usb_endpoint_xfer_control(&ep->desc)) { | |
606 | type = EP_TYPE(CTRL_EP); | |
607 | } else if (usb_endpoint_xfer_bulk(&ep->desc)) { | |
608 | if (in) | |
609 | type = EP_TYPE(BULK_IN_EP); | |
610 | else | |
611 | type = EP_TYPE(BULK_OUT_EP); | |
612 | } else if (usb_endpoint_xfer_isoc(&ep->desc)) { | |
613 | if (in) | |
614 | type = EP_TYPE(ISOC_IN_EP); | |
615 | else | |
616 | type = EP_TYPE(ISOC_OUT_EP); | |
617 | } else if (usb_endpoint_xfer_int(&ep->desc)) { | |
618 | if (in) | |
619 | type = EP_TYPE(INT_IN_EP); | |
620 | else | |
621 | type = EP_TYPE(INT_OUT_EP); | |
622 | } else { | |
623 | BUG(); | |
624 | } | |
625 | return type; | |
626 | } | |
627 | ||
628 | int xhci_endpoint_init(struct xhci_hcd *xhci, | |
629 | struct xhci_virt_device *virt_dev, | |
630 | struct usb_device *udev, | |
f88ba78d SS |
631 | struct usb_host_endpoint *ep, |
632 | gfp_t mem_flags) | |
f94e0186 SS |
633 | { |
634 | unsigned int ep_index; | |
635 | struct xhci_ep_ctx *ep_ctx; | |
636 | struct xhci_ring *ep_ring; | |
637 | unsigned int max_packet; | |
638 | unsigned int max_burst; | |
639 | ||
640 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
d115b048 | 641 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); |
f94e0186 SS |
642 | |
643 | /* Set up the endpoint ring */ | |
63a0d9ab SS |
644 | virt_dev->eps[ep_index].new_ring = |
645 | xhci_ring_alloc(xhci, 1, true, mem_flags); | |
74f9fe21 SS |
646 | if (!virt_dev->eps[ep_index].new_ring) { |
647 | /* Attempt to use the ring cache */ | |
648 | if (virt_dev->num_rings_cached == 0) | |
649 | return -ENOMEM; | |
650 | virt_dev->eps[ep_index].new_ring = | |
651 | virt_dev->ring_cache[virt_dev->num_rings_cached]; | |
652 | virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL; | |
653 | virt_dev->num_rings_cached--; | |
654 | xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring); | |
655 | } | |
63a0d9ab | 656 | ep_ring = virt_dev->eps[ep_index].new_ring; |
8e595a5d | 657 | ep_ctx->deq = ep_ring->first_seg->dma | ep_ring->cycle_state; |
f94e0186 SS |
658 | |
659 | ep_ctx->ep_info = xhci_get_endpoint_interval(udev, ep); | |
1cf62246 | 660 | ep_ctx->ep_info |= EP_MULT(xhci_get_endpoint_mult(udev, ep)); |
f94e0186 SS |
661 | |
662 | /* FIXME dig Mult and streams info out of ep companion desc */ | |
663 | ||
47692d17 SS |
664 | /* Allow 3 retries for everything but isoc; |
665 | * error count = 0 means infinite retries. | |
666 | */ | |
f94e0186 SS |
667 | if (!usb_endpoint_xfer_isoc(&ep->desc)) |
668 | ep_ctx->ep_info2 = ERROR_COUNT(3); | |
669 | else | |
47692d17 | 670 | ep_ctx->ep_info2 = ERROR_COUNT(1); |
f94e0186 SS |
671 | |
672 | ep_ctx->ep_info2 |= xhci_get_endpoint_type(udev, ep); | |
673 | ||
674 | /* Set the max packet size and max burst */ | |
675 | switch (udev->speed) { | |
676 | case USB_SPEED_SUPER: | |
677 | max_packet = ep->desc.wMaxPacketSize; | |
678 | ep_ctx->ep_info2 |= MAX_PACKET(max_packet); | |
b10de142 | 679 | /* dig out max burst from ep companion desc */ |
b7d6d998 SS |
680 | if (!ep->ss_ep_comp) { |
681 | xhci_warn(xhci, "WARN no SS endpoint companion descriptor.\n"); | |
682 | max_packet = 0; | |
683 | } else { | |
684 | max_packet = ep->ss_ep_comp->desc.bMaxBurst; | |
685 | } | |
b10de142 | 686 | ep_ctx->ep_info2 |= MAX_BURST(max_packet); |
f94e0186 SS |
687 | break; |
688 | case USB_SPEED_HIGH: | |
689 | /* bits 11:12 specify the number of additional transaction | |
690 | * opportunities per microframe (USB 2.0, section 9.6.6) | |
691 | */ | |
692 | if (usb_endpoint_xfer_isoc(&ep->desc) || | |
693 | usb_endpoint_xfer_int(&ep->desc)) { | |
694 | max_burst = (ep->desc.wMaxPacketSize & 0x1800) >> 11; | |
695 | ep_ctx->ep_info2 |= MAX_BURST(max_burst); | |
696 | } | |
697 | /* Fall through */ | |
698 | case USB_SPEED_FULL: | |
699 | case USB_SPEED_LOW: | |
700 | max_packet = ep->desc.wMaxPacketSize & 0x3ff; | |
701 | ep_ctx->ep_info2 |= MAX_PACKET(max_packet); | |
702 | break; | |
703 | default: | |
704 | BUG(); | |
705 | } | |
706 | /* FIXME Debug endpoint context */ | |
707 | return 0; | |
708 | } | |
709 | ||
710 | void xhci_endpoint_zero(struct xhci_hcd *xhci, | |
711 | struct xhci_virt_device *virt_dev, | |
712 | struct usb_host_endpoint *ep) | |
713 | { | |
714 | unsigned int ep_index; | |
715 | struct xhci_ep_ctx *ep_ctx; | |
716 | ||
717 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
d115b048 | 718 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); |
f94e0186 SS |
719 | |
720 | ep_ctx->ep_info = 0; | |
721 | ep_ctx->ep_info2 = 0; | |
8e595a5d | 722 | ep_ctx->deq = 0; |
f94e0186 SS |
723 | ep_ctx->tx_info = 0; |
724 | /* Don't free the endpoint ring until the set interface or configuration | |
725 | * request succeeds. | |
726 | */ | |
727 | } | |
728 | ||
f2217e8e SS |
729 | /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy. |
730 | * Useful when you want to change one particular aspect of the endpoint and then | |
731 | * issue a configure endpoint command. | |
732 | */ | |
733 | void xhci_endpoint_copy(struct xhci_hcd *xhci, | |
913a8a34 SS |
734 | struct xhci_container_ctx *in_ctx, |
735 | struct xhci_container_ctx *out_ctx, | |
736 | unsigned int ep_index) | |
f2217e8e SS |
737 | { |
738 | struct xhci_ep_ctx *out_ep_ctx; | |
739 | struct xhci_ep_ctx *in_ep_ctx; | |
740 | ||
913a8a34 SS |
741 | out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); |
742 | in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); | |
f2217e8e SS |
743 | |
744 | in_ep_ctx->ep_info = out_ep_ctx->ep_info; | |
745 | in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2; | |
746 | in_ep_ctx->deq = out_ep_ctx->deq; | |
747 | in_ep_ctx->tx_info = out_ep_ctx->tx_info; | |
748 | } | |
749 | ||
750 | /* Copy output xhci_slot_ctx to the input xhci_slot_ctx. | |
751 | * Useful when you want to change one particular aspect of the endpoint and then | |
752 | * issue a configure endpoint command. Only the context entries field matters, | |
753 | * but we'll copy the whole thing anyway. | |
754 | */ | |
913a8a34 SS |
755 | void xhci_slot_copy(struct xhci_hcd *xhci, |
756 | struct xhci_container_ctx *in_ctx, | |
757 | struct xhci_container_ctx *out_ctx) | |
f2217e8e SS |
758 | { |
759 | struct xhci_slot_ctx *in_slot_ctx; | |
760 | struct xhci_slot_ctx *out_slot_ctx; | |
761 | ||
913a8a34 SS |
762 | in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx); |
763 | out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx); | |
f2217e8e SS |
764 | |
765 | in_slot_ctx->dev_info = out_slot_ctx->dev_info; | |
766 | in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2; | |
767 | in_slot_ctx->tt_info = out_slot_ctx->tt_info; | |
768 | in_slot_ctx->dev_state = out_slot_ctx->dev_state; | |
769 | } | |
770 | ||
254c80a3 JY |
771 | /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */ |
772 | static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags) | |
773 | { | |
774 | int i; | |
775 | struct device *dev = xhci_to_hcd(xhci)->self.controller; | |
776 | int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); | |
777 | ||
778 | xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp); | |
779 | ||
780 | if (!num_sp) | |
781 | return 0; | |
782 | ||
783 | xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags); | |
784 | if (!xhci->scratchpad) | |
785 | goto fail_sp; | |
786 | ||
787 | xhci->scratchpad->sp_array = | |
788 | pci_alloc_consistent(to_pci_dev(dev), | |
789 | num_sp * sizeof(u64), | |
790 | &xhci->scratchpad->sp_dma); | |
791 | if (!xhci->scratchpad->sp_array) | |
792 | goto fail_sp2; | |
793 | ||
794 | xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags); | |
795 | if (!xhci->scratchpad->sp_buffers) | |
796 | goto fail_sp3; | |
797 | ||
798 | xhci->scratchpad->sp_dma_buffers = | |
799 | kzalloc(sizeof(dma_addr_t) * num_sp, flags); | |
800 | ||
801 | if (!xhci->scratchpad->sp_dma_buffers) | |
802 | goto fail_sp4; | |
803 | ||
804 | xhci->dcbaa->dev_context_ptrs[0] = xhci->scratchpad->sp_dma; | |
805 | for (i = 0; i < num_sp; i++) { | |
806 | dma_addr_t dma; | |
807 | void *buf = pci_alloc_consistent(to_pci_dev(dev), | |
808 | xhci->page_size, &dma); | |
809 | if (!buf) | |
810 | goto fail_sp5; | |
811 | ||
812 | xhci->scratchpad->sp_array[i] = dma; | |
813 | xhci->scratchpad->sp_buffers[i] = buf; | |
814 | xhci->scratchpad->sp_dma_buffers[i] = dma; | |
815 | } | |
816 | ||
817 | return 0; | |
818 | ||
819 | fail_sp5: | |
820 | for (i = i - 1; i >= 0; i--) { | |
821 | pci_free_consistent(to_pci_dev(dev), xhci->page_size, | |
822 | xhci->scratchpad->sp_buffers[i], | |
823 | xhci->scratchpad->sp_dma_buffers[i]); | |
824 | } | |
825 | kfree(xhci->scratchpad->sp_dma_buffers); | |
826 | ||
827 | fail_sp4: | |
828 | kfree(xhci->scratchpad->sp_buffers); | |
829 | ||
830 | fail_sp3: | |
831 | pci_free_consistent(to_pci_dev(dev), num_sp * sizeof(u64), | |
832 | xhci->scratchpad->sp_array, | |
833 | xhci->scratchpad->sp_dma); | |
834 | ||
835 | fail_sp2: | |
836 | kfree(xhci->scratchpad); | |
837 | xhci->scratchpad = NULL; | |
838 | ||
839 | fail_sp: | |
840 | return -ENOMEM; | |
841 | } | |
842 | ||
843 | static void scratchpad_free(struct xhci_hcd *xhci) | |
844 | { | |
845 | int num_sp; | |
846 | int i; | |
847 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
848 | ||
849 | if (!xhci->scratchpad) | |
850 | return; | |
851 | ||
852 | num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); | |
853 | ||
854 | for (i = 0; i < num_sp; i++) { | |
855 | pci_free_consistent(pdev, xhci->page_size, | |
856 | xhci->scratchpad->sp_buffers[i], | |
857 | xhci->scratchpad->sp_dma_buffers[i]); | |
858 | } | |
859 | kfree(xhci->scratchpad->sp_dma_buffers); | |
860 | kfree(xhci->scratchpad->sp_buffers); | |
861 | pci_free_consistent(pdev, num_sp * sizeof(u64), | |
862 | xhci->scratchpad->sp_array, | |
863 | xhci->scratchpad->sp_dma); | |
864 | kfree(xhci->scratchpad); | |
865 | xhci->scratchpad = NULL; | |
866 | } | |
867 | ||
913a8a34 | 868 | struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, |
a1d78c16 SS |
869 | bool allocate_in_ctx, bool allocate_completion, |
870 | gfp_t mem_flags) | |
913a8a34 SS |
871 | { |
872 | struct xhci_command *command; | |
873 | ||
874 | command = kzalloc(sizeof(*command), mem_flags); | |
875 | if (!command) | |
876 | return NULL; | |
877 | ||
a1d78c16 SS |
878 | if (allocate_in_ctx) { |
879 | command->in_ctx = | |
880 | xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, | |
881 | mem_flags); | |
882 | if (!command->in_ctx) { | |
883 | kfree(command); | |
884 | return NULL; | |
885 | } | |
06e18291 | 886 | } |
913a8a34 SS |
887 | |
888 | if (allocate_completion) { | |
889 | command->completion = | |
890 | kzalloc(sizeof(struct completion), mem_flags); | |
891 | if (!command->completion) { | |
892 | xhci_free_container_ctx(xhci, command->in_ctx); | |
06e18291 | 893 | kfree(command); |
913a8a34 SS |
894 | return NULL; |
895 | } | |
896 | init_completion(command->completion); | |
897 | } | |
898 | ||
899 | command->status = 0; | |
900 | INIT_LIST_HEAD(&command->cmd_list); | |
901 | return command; | |
902 | } | |
903 | ||
904 | void xhci_free_command(struct xhci_hcd *xhci, | |
905 | struct xhci_command *command) | |
906 | { | |
907 | xhci_free_container_ctx(xhci, | |
908 | command->in_ctx); | |
909 | kfree(command->completion); | |
910 | kfree(command); | |
911 | } | |
912 | ||
66d4eadd SS |
913 | void xhci_mem_cleanup(struct xhci_hcd *xhci) |
914 | { | |
0ebbab37 SS |
915 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); |
916 | int size; | |
3ffbba95 | 917 | int i; |
0ebbab37 SS |
918 | |
919 | /* Free the Event Ring Segment Table and the actual Event Ring */ | |
d94c05e3 SS |
920 | if (xhci->ir_set) { |
921 | xhci_writel(xhci, 0, &xhci->ir_set->erst_size); | |
922 | xhci_write_64(xhci, 0, &xhci->ir_set->erst_base); | |
923 | xhci_write_64(xhci, 0, &xhci->ir_set->erst_dequeue); | |
924 | } | |
0ebbab37 SS |
925 | size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries); |
926 | if (xhci->erst.entries) | |
927 | pci_free_consistent(pdev, size, | |
928 | xhci->erst.entries, xhci->erst.erst_dma_addr); | |
929 | xhci->erst.entries = NULL; | |
930 | xhci_dbg(xhci, "Freed ERST\n"); | |
931 | if (xhci->event_ring) | |
932 | xhci_ring_free(xhci, xhci->event_ring); | |
933 | xhci->event_ring = NULL; | |
934 | xhci_dbg(xhci, "Freed event ring\n"); | |
935 | ||
8e595a5d | 936 | xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring); |
0ebbab37 SS |
937 | if (xhci->cmd_ring) |
938 | xhci_ring_free(xhci, xhci->cmd_ring); | |
939 | xhci->cmd_ring = NULL; | |
940 | xhci_dbg(xhci, "Freed command ring\n"); | |
3ffbba95 SS |
941 | |
942 | for (i = 1; i < MAX_HC_SLOTS; ++i) | |
943 | xhci_free_virt_device(xhci, i); | |
944 | ||
0ebbab37 SS |
945 | if (xhci->segment_pool) |
946 | dma_pool_destroy(xhci->segment_pool); | |
947 | xhci->segment_pool = NULL; | |
948 | xhci_dbg(xhci, "Freed segment pool\n"); | |
3ffbba95 SS |
949 | |
950 | if (xhci->device_pool) | |
951 | dma_pool_destroy(xhci->device_pool); | |
952 | xhci->device_pool = NULL; | |
953 | xhci_dbg(xhci, "Freed device context pool\n"); | |
954 | ||
8e595a5d | 955 | xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr); |
a74588f9 SS |
956 | if (xhci->dcbaa) |
957 | pci_free_consistent(pdev, sizeof(*xhci->dcbaa), | |
958 | xhci->dcbaa, xhci->dcbaa->dma); | |
959 | xhci->dcbaa = NULL; | |
3ffbba95 | 960 | |
5294bea4 | 961 | scratchpad_free(xhci); |
66d4eadd SS |
962 | xhci->page_size = 0; |
963 | xhci->page_shift = 0; | |
964 | } | |
965 | ||
6648f29d SS |
966 | static int xhci_test_trb_in_td(struct xhci_hcd *xhci, |
967 | struct xhci_segment *input_seg, | |
968 | union xhci_trb *start_trb, | |
969 | union xhci_trb *end_trb, | |
970 | dma_addr_t input_dma, | |
971 | struct xhci_segment *result_seg, | |
972 | char *test_name, int test_number) | |
973 | { | |
974 | unsigned long long start_dma; | |
975 | unsigned long long end_dma; | |
976 | struct xhci_segment *seg; | |
977 | ||
978 | start_dma = xhci_trb_virt_to_dma(input_seg, start_trb); | |
979 | end_dma = xhci_trb_virt_to_dma(input_seg, end_trb); | |
980 | ||
981 | seg = trb_in_td(input_seg, start_trb, end_trb, input_dma); | |
982 | if (seg != result_seg) { | |
983 | xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n", | |
984 | test_name, test_number); | |
985 | xhci_warn(xhci, "Tested TRB math w/ seg %p and " | |
986 | "input DMA 0x%llx\n", | |
987 | input_seg, | |
988 | (unsigned long long) input_dma); | |
989 | xhci_warn(xhci, "starting TRB %p (0x%llx DMA), " | |
990 | "ending TRB %p (0x%llx DMA)\n", | |
991 | start_trb, start_dma, | |
992 | end_trb, end_dma); | |
993 | xhci_warn(xhci, "Expected seg %p, got seg %p\n", | |
994 | result_seg, seg); | |
995 | return -1; | |
996 | } | |
997 | return 0; | |
998 | } | |
999 | ||
1000 | /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */ | |
1001 | static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags) | |
1002 | { | |
1003 | struct { | |
1004 | dma_addr_t input_dma; | |
1005 | struct xhci_segment *result_seg; | |
1006 | } simple_test_vector [] = { | |
1007 | /* A zeroed DMA field should fail */ | |
1008 | { 0, NULL }, | |
1009 | /* One TRB before the ring start should fail */ | |
1010 | { xhci->event_ring->first_seg->dma - 16, NULL }, | |
1011 | /* One byte before the ring start should fail */ | |
1012 | { xhci->event_ring->first_seg->dma - 1, NULL }, | |
1013 | /* Starting TRB should succeed */ | |
1014 | { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg }, | |
1015 | /* Ending TRB should succeed */ | |
1016 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16, | |
1017 | xhci->event_ring->first_seg }, | |
1018 | /* One byte after the ring end should fail */ | |
1019 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL }, | |
1020 | /* One TRB after the ring end should fail */ | |
1021 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL }, | |
1022 | /* An address of all ones should fail */ | |
1023 | { (dma_addr_t) (~0), NULL }, | |
1024 | }; | |
1025 | struct { | |
1026 | struct xhci_segment *input_seg; | |
1027 | union xhci_trb *start_trb; | |
1028 | union xhci_trb *end_trb; | |
1029 | dma_addr_t input_dma; | |
1030 | struct xhci_segment *result_seg; | |
1031 | } complex_test_vector [] = { | |
1032 | /* Test feeding a valid DMA address from a different ring */ | |
1033 | { .input_seg = xhci->event_ring->first_seg, | |
1034 | .start_trb = xhci->event_ring->first_seg->trbs, | |
1035 | .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
1036 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
1037 | .result_seg = NULL, | |
1038 | }, | |
1039 | /* Test feeding a valid end TRB from a different ring */ | |
1040 | { .input_seg = xhci->event_ring->first_seg, | |
1041 | .start_trb = xhci->event_ring->first_seg->trbs, | |
1042 | .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
1043 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
1044 | .result_seg = NULL, | |
1045 | }, | |
1046 | /* Test feeding a valid start and end TRB from a different ring */ | |
1047 | { .input_seg = xhci->event_ring->first_seg, | |
1048 | .start_trb = xhci->cmd_ring->first_seg->trbs, | |
1049 | .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
1050 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
1051 | .result_seg = NULL, | |
1052 | }, | |
1053 | /* TRB in this ring, but after this TD */ | |
1054 | { .input_seg = xhci->event_ring->first_seg, | |
1055 | .start_trb = &xhci->event_ring->first_seg->trbs[0], | |
1056 | .end_trb = &xhci->event_ring->first_seg->trbs[3], | |
1057 | .input_dma = xhci->event_ring->first_seg->dma + 4*16, | |
1058 | .result_seg = NULL, | |
1059 | }, | |
1060 | /* TRB in this ring, but before this TD */ | |
1061 | { .input_seg = xhci->event_ring->first_seg, | |
1062 | .start_trb = &xhci->event_ring->first_seg->trbs[3], | |
1063 | .end_trb = &xhci->event_ring->first_seg->trbs[6], | |
1064 | .input_dma = xhci->event_ring->first_seg->dma + 2*16, | |
1065 | .result_seg = NULL, | |
1066 | }, | |
1067 | /* TRB in this ring, but after this wrapped TD */ | |
1068 | { .input_seg = xhci->event_ring->first_seg, | |
1069 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
1070 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
1071 | .input_dma = xhci->event_ring->first_seg->dma + 2*16, | |
1072 | .result_seg = NULL, | |
1073 | }, | |
1074 | /* TRB in this ring, but before this wrapped TD */ | |
1075 | { .input_seg = xhci->event_ring->first_seg, | |
1076 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
1077 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
1078 | .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16, | |
1079 | .result_seg = NULL, | |
1080 | }, | |
1081 | /* TRB not in this ring, and we have a wrapped TD */ | |
1082 | { .input_seg = xhci->event_ring->first_seg, | |
1083 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
1084 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
1085 | .input_dma = xhci->cmd_ring->first_seg->dma + 2*16, | |
1086 | .result_seg = NULL, | |
1087 | }, | |
1088 | }; | |
1089 | ||
1090 | unsigned int num_tests; | |
1091 | int i, ret; | |
1092 | ||
1093 | num_tests = sizeof(simple_test_vector) / sizeof(simple_test_vector[0]); | |
1094 | for (i = 0; i < num_tests; i++) { | |
1095 | ret = xhci_test_trb_in_td(xhci, | |
1096 | xhci->event_ring->first_seg, | |
1097 | xhci->event_ring->first_seg->trbs, | |
1098 | &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
1099 | simple_test_vector[i].input_dma, | |
1100 | simple_test_vector[i].result_seg, | |
1101 | "Simple", i); | |
1102 | if (ret < 0) | |
1103 | return ret; | |
1104 | } | |
1105 | ||
1106 | num_tests = sizeof(complex_test_vector) / sizeof(complex_test_vector[0]); | |
1107 | for (i = 0; i < num_tests; i++) { | |
1108 | ret = xhci_test_trb_in_td(xhci, | |
1109 | complex_test_vector[i].input_seg, | |
1110 | complex_test_vector[i].start_trb, | |
1111 | complex_test_vector[i].end_trb, | |
1112 | complex_test_vector[i].input_dma, | |
1113 | complex_test_vector[i].result_seg, | |
1114 | "Complex", i); | |
1115 | if (ret < 0) | |
1116 | return ret; | |
1117 | } | |
1118 | xhci_dbg(xhci, "TRB math tests passed.\n"); | |
1119 | return 0; | |
1120 | } | |
1121 | ||
1122 | ||
66d4eadd SS |
1123 | int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) |
1124 | { | |
0ebbab37 SS |
1125 | dma_addr_t dma; |
1126 | struct device *dev = xhci_to_hcd(xhci)->self.controller; | |
66d4eadd | 1127 | unsigned int val, val2; |
8e595a5d | 1128 | u64 val_64; |
0ebbab37 | 1129 | struct xhci_segment *seg; |
66d4eadd SS |
1130 | u32 page_size; |
1131 | int i; | |
1132 | ||
1133 | page_size = xhci_readl(xhci, &xhci->op_regs->page_size); | |
1134 | xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size); | |
1135 | for (i = 0; i < 16; i++) { | |
1136 | if ((0x1 & page_size) != 0) | |
1137 | break; | |
1138 | page_size = page_size >> 1; | |
1139 | } | |
1140 | if (i < 16) | |
1141 | xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024); | |
1142 | else | |
1143 | xhci_warn(xhci, "WARN: no supported page size\n"); | |
1144 | /* Use 4K pages, since that's common and the minimum the HC supports */ | |
1145 | xhci->page_shift = 12; | |
1146 | xhci->page_size = 1 << xhci->page_shift; | |
1147 | xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024); | |
1148 | ||
1149 | /* | |
1150 | * Program the Number of Device Slots Enabled field in the CONFIG | |
1151 | * register with the max value of slots the HC can handle. | |
1152 | */ | |
1153 | val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1)); | |
1154 | xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n", | |
1155 | (unsigned int) val); | |
1156 | val2 = xhci_readl(xhci, &xhci->op_regs->config_reg); | |
1157 | val |= (val2 & ~HCS_SLOTS_MASK); | |
1158 | xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n", | |
1159 | (unsigned int) val); | |
1160 | xhci_writel(xhci, val, &xhci->op_regs->config_reg); | |
1161 | ||
a74588f9 SS |
1162 | /* |
1163 | * Section 5.4.8 - doorbell array must be | |
1164 | * "physically contiguous and 64-byte (cache line) aligned". | |
1165 | */ | |
1166 | xhci->dcbaa = pci_alloc_consistent(to_pci_dev(dev), | |
1167 | sizeof(*xhci->dcbaa), &dma); | |
1168 | if (!xhci->dcbaa) | |
1169 | goto fail; | |
1170 | memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa)); | |
1171 | xhci->dcbaa->dma = dma; | |
700e2052 GKH |
1172 | xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n", |
1173 | (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa); | |
8e595a5d | 1174 | xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr); |
a74588f9 | 1175 | |
0ebbab37 SS |
1176 | /* |
1177 | * Initialize the ring segment pool. The ring must be a contiguous | |
1178 | * structure comprised of TRBs. The TRBs must be 16 byte aligned, | |
1179 | * however, the command ring segment needs 64-byte aligned segments, | |
1180 | * so we pick the greater alignment need. | |
1181 | */ | |
1182 | xhci->segment_pool = dma_pool_create("xHCI ring segments", dev, | |
1183 | SEGMENT_SIZE, 64, xhci->page_size); | |
d115b048 | 1184 | |
3ffbba95 | 1185 | /* See Table 46 and Note on Figure 55 */ |
3ffbba95 | 1186 | xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev, |
d115b048 | 1187 | 2112, 64, xhci->page_size); |
3ffbba95 | 1188 | if (!xhci->segment_pool || !xhci->device_pool) |
0ebbab37 SS |
1189 | goto fail; |
1190 | ||
1191 | /* Set up the command ring to have one segments for now. */ | |
1192 | xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, flags); | |
1193 | if (!xhci->cmd_ring) | |
1194 | goto fail; | |
700e2052 GKH |
1195 | xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring); |
1196 | xhci_dbg(xhci, "First segment DMA is 0x%llx\n", | |
1197 | (unsigned long long)xhci->cmd_ring->first_seg->dma); | |
0ebbab37 SS |
1198 | |
1199 | /* Set the address in the Command Ring Control register */ | |
8e595a5d SS |
1200 | val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
1201 | val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | | |
1202 | (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) | | |
0ebbab37 | 1203 | xhci->cmd_ring->cycle_state; |
8e595a5d SS |
1204 | xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val); |
1205 | xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); | |
0ebbab37 SS |
1206 | xhci_dbg_cmd_ptrs(xhci); |
1207 | ||
1208 | val = xhci_readl(xhci, &xhci->cap_regs->db_off); | |
1209 | val &= DBOFF_MASK; | |
1210 | xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x" | |
1211 | " from cap regs base addr\n", val); | |
1212 | xhci->dba = (void *) xhci->cap_regs + val; | |
1213 | xhci_dbg_regs(xhci); | |
1214 | xhci_print_run_regs(xhci); | |
1215 | /* Set ir_set to interrupt register set 0 */ | |
1216 | xhci->ir_set = (void *) xhci->run_regs->ir_set; | |
1217 | ||
1218 | /* | |
1219 | * Event ring setup: Allocate a normal ring, but also setup | |
1220 | * the event ring segment table (ERST). Section 4.9.3. | |
1221 | */ | |
1222 | xhci_dbg(xhci, "// Allocating event ring\n"); | |
1223 | xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, flags); | |
1224 | if (!xhci->event_ring) | |
1225 | goto fail; | |
6648f29d SS |
1226 | if (xhci_check_trb_in_td_math(xhci, flags) < 0) |
1227 | goto fail; | |
0ebbab37 SS |
1228 | |
1229 | xhci->erst.entries = pci_alloc_consistent(to_pci_dev(dev), | |
1230 | sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS, &dma); | |
1231 | if (!xhci->erst.entries) | |
1232 | goto fail; | |
700e2052 GKH |
1233 | xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n", |
1234 | (unsigned long long)dma); | |
0ebbab37 SS |
1235 | |
1236 | memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS); | |
1237 | xhci->erst.num_entries = ERST_NUM_SEGS; | |
1238 | xhci->erst.erst_dma_addr = dma; | |
700e2052 | 1239 | xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n", |
0ebbab37 | 1240 | xhci->erst.num_entries, |
700e2052 GKH |
1241 | xhci->erst.entries, |
1242 | (unsigned long long)xhci->erst.erst_dma_addr); | |
0ebbab37 SS |
1243 | |
1244 | /* set ring base address and size for each segment table entry */ | |
1245 | for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) { | |
1246 | struct xhci_erst_entry *entry = &xhci->erst.entries[val]; | |
8e595a5d | 1247 | entry->seg_addr = seg->dma; |
0ebbab37 SS |
1248 | entry->seg_size = TRBS_PER_SEGMENT; |
1249 | entry->rsvd = 0; | |
1250 | seg = seg->next; | |
1251 | } | |
1252 | ||
1253 | /* set ERST count with the number of entries in the segment table */ | |
1254 | val = xhci_readl(xhci, &xhci->ir_set->erst_size); | |
1255 | val &= ERST_SIZE_MASK; | |
1256 | val |= ERST_NUM_SEGS; | |
1257 | xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n", | |
1258 | val); | |
1259 | xhci_writel(xhci, val, &xhci->ir_set->erst_size); | |
1260 | ||
1261 | xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n"); | |
1262 | /* set the segment table base address */ | |
700e2052 GKH |
1263 | xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n", |
1264 | (unsigned long long)xhci->erst.erst_dma_addr); | |
8e595a5d SS |
1265 | val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base); |
1266 | val_64 &= ERST_PTR_MASK; | |
1267 | val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK); | |
1268 | xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base); | |
0ebbab37 SS |
1269 | |
1270 | /* Set the event ring dequeue address */ | |
23e3be11 | 1271 | xhci_set_hc_event_deq(xhci); |
0ebbab37 SS |
1272 | xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n"); |
1273 | xhci_print_ir_set(xhci, xhci->ir_set, 0); | |
1274 | ||
1275 | /* | |
1276 | * XXX: Might need to set the Interrupter Moderation Register to | |
1277 | * something other than the default (~1ms minimum between interrupts). | |
1278 | * See section 5.5.1.2. | |
1279 | */ | |
3ffbba95 SS |
1280 | init_completion(&xhci->addr_dev); |
1281 | for (i = 0; i < MAX_HC_SLOTS; ++i) | |
1282 | xhci->devs[i] = 0; | |
66d4eadd | 1283 | |
254c80a3 JY |
1284 | if (scratchpad_alloc(xhci, flags)) |
1285 | goto fail; | |
1286 | ||
66d4eadd | 1287 | return 0; |
254c80a3 | 1288 | |
66d4eadd SS |
1289 | fail: |
1290 | xhci_warn(xhci, "Couldn't initialize memory\n"); | |
1291 | xhci_mem_cleanup(xhci); | |
1292 | return -ENOMEM; | |
1293 | } |