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1 | /* |
2 | * Copyright (c) 2015 MediaTek Inc. | |
3 | * Author: | |
4 | * Zhigang.Wei <zhigang.wei@mediatek.com> | |
5 | * Chunfeng.Yun <chunfeng.yun@mediatek.com> | |
6 | * | |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | */ | |
17 | ||
18 | #ifndef _XHCI_MTK_H_ | |
19 | #define _XHCI_MTK_H_ | |
20 | ||
21 | #include "xhci.h" | |
22 | ||
23 | /** | |
24 | * To simplify scheduler algorithm, set a upper limit for ESIT, | |
25 | * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT, | |
26 | * round down to the limit value, that means allocating more | |
27 | * bandwidth to it. | |
28 | */ | |
29 | #define XHCI_MTK_MAX_ESIT 64 | |
30 | ||
31 | /** | |
32 | * struct mu3h_sch_bw_info: schedule information for bandwidth domain | |
33 | * | |
34 | * @bus_bw: array to keep track of bandwidth already used at each uframes | |
35 | * @bw_ep_list: eps in the bandwidth domain | |
36 | * | |
37 | * treat a HS root port as a bandwidth domain, but treat a SS root port as | |
38 | * two bandwidth domains, one for IN eps and another for OUT eps. | |
39 | */ | |
40 | struct mu3h_sch_bw_info { | |
41 | u32 bus_bw[XHCI_MTK_MAX_ESIT]; | |
42 | struct list_head bw_ep_list; | |
43 | }; | |
44 | ||
45 | /** | |
46 | * struct mu3h_sch_ep_info: schedule information for endpoint | |
47 | * | |
48 | * @esit: unit is 125us, equal to 2 << Interval field in ep-context | |
49 | * @num_budget_microframes: number of continuous uframes | |
50 | * (@repeat==1) scheduled within the interval | |
51 | * @bw_cost_per_microframe: bandwidth cost per microframe | |
52 | * @endpoint: linked into bandwidth domain which it belongs to | |
53 | * @ep: address of usb_host_endpoint struct | |
54 | * @offset: which uframe of the interval that transfer should be | |
55 | * scheduled first time within the interval | |
56 | * @repeat: the time gap between two uframes that transfers are | |
57 | * scheduled within a interval. in the simple algorithm, only | |
58 | * assign 0 or 1 to it; 0 means using only one uframe in a | |
59 | * interval, and 1 means using @num_budget_microframes | |
60 | * continuous uframes | |
61 | * @pkts: number of packets to be transferred in the scheduled uframes | |
62 | * @cs_count: number of CS that host will trigger | |
63 | * @burst_mode: burst mode for scheduling. 0: normal burst mode, | |
64 | * distribute the bMaxBurst+1 packets for a single burst | |
65 | * according to @pkts and @repeat, repeate the burst multiple | |
66 | * times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets | |
67 | * according to @pkts and @repeat. normal mode is used by | |
68 | * default | |
69 | */ | |
70 | struct mu3h_sch_ep_info { | |
71 | u32 esit; | |
72 | u32 num_budget_microframes; | |
73 | u32 bw_cost_per_microframe; | |
74 | struct list_head endpoint; | |
75 | void *ep; | |
76 | /* | |
77 | * mtk xHCI scheduling information put into reserved DWs | |
78 | * in ep context | |
79 | */ | |
80 | u32 offset; | |
81 | u32 repeat; | |
82 | u32 pkts; | |
83 | u32 cs_count; | |
84 | u32 burst_mode; | |
85 | }; | |
86 | ||
87 | #define MU3C_U3_PORT_MAX 4 | |
88 | #define MU3C_U2_PORT_MAX 5 | |
89 | ||
90 | /** | |
91 | * struct mu3c_ippc_regs: MTK ssusb ip port control registers | |
92 | * @ip_pw_ctr0~3: ip power and clock control registers | |
93 | * @ip_pw_sts1~2: ip power and clock status registers | |
94 | * @ip_xhci_cap: ip xHCI capability register | |
95 | * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used | |
96 | * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used | |
97 | * @u2_phy_pll: usb2 phy pll control register | |
98 | */ | |
99 | struct mu3c_ippc_regs { | |
100 | __le32 ip_pw_ctr0; | |
101 | __le32 ip_pw_ctr1; | |
102 | __le32 ip_pw_ctr2; | |
103 | __le32 ip_pw_ctr3; | |
104 | __le32 ip_pw_sts1; | |
105 | __le32 ip_pw_sts2; | |
106 | __le32 reserved0[3]; | |
107 | __le32 ip_xhci_cap; | |
108 | __le32 reserved1[2]; | |
109 | __le64 u3_ctrl_p[MU3C_U3_PORT_MAX]; | |
110 | __le64 u2_ctrl_p[MU3C_U2_PORT_MAX]; | |
111 | __le32 reserved2; | |
112 | __le32 u2_phy_pll; | |
113 | __le32 reserved3[33]; /* 0x80 ~ 0xff */ | |
114 | }; | |
115 | ||
116 | struct xhci_hcd_mtk { | |
117 | struct device *dev; | |
118 | struct usb_hcd *hcd; | |
119 | struct mu3h_sch_bw_info *sch_array; | |
120 | struct mu3c_ippc_regs __iomem *ippc_regs; | |
121 | int num_u2_ports; | |
122 | int num_u3_ports; | |
123 | struct regulator *vusb33; | |
124 | struct regulator *vbus; | |
125 | struct clk *sys_clk; /* sys and mac clock */ | |
126 | struct clk *wk_deb_p0; /* port0's wakeup debounce clock */ | |
127 | struct clk *wk_deb_p1; | |
128 | struct regmap *pericfg; | |
129 | struct phy **phys; | |
130 | int num_phys; | |
131 | int wakeup_src; | |
132 | bool lpm_support; | |
133 | }; | |
134 | ||
135 | static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd) | |
136 | { | |
137 | return dev_get_drvdata(hcd->self.controller); | |
138 | } | |
139 | ||
140 | #if IS_ENABLED(CONFIG_USB_XHCI_MTK) | |
141 | int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk); | |
142 | void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk); | |
143 | int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev, | |
144 | struct usb_host_endpoint *ep); | |
145 | void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev, | |
146 | struct usb_host_endpoint *ep); | |
147 | ||
148 | #else | |
149 | static inline int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, | |
150 | struct usb_device *udev, struct usb_host_endpoint *ep) | |
151 | { | |
152 | return 0; | |
153 | } | |
154 | ||
155 | static inline void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, | |
156 | struct usb_device *udev, struct usb_host_endpoint *ep) | |
157 | { | |
158 | } | |
159 | ||
160 | #endif | |
161 | ||
162 | #endif /* _XHCI_MTK_H_ */ |