Commit | Line | Data |
---|---|---|
66d4eadd SS |
1 | /* |
2 | * xHCI host controller driver PCI Bus Glue. | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/pci.h> | |
7fc2a616 | 24 | #include <linux/slab.h> |
6eb0de82 | 25 | #include <linux/module.h> |
c3c5819a | 26 | #include <linux/acpi.h> |
66d4eadd SS |
27 | |
28 | #include "xhci.h" | |
4bdfe4c3 | 29 | #include "xhci-trace.h" |
66d4eadd | 30 | |
abce329c RM |
31 | #define PORT2_SSIC_CONFIG_REG2 0x883c |
32 | #define PROG_DONE (1 << 30) | |
33 | #define SSIC_PORT_UNUSED (1 << 31) | |
34 | ||
ac9d8fe7 SS |
35 | /* Device for a quirk */ |
36 | #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 | |
37 | #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 | |
bba18e33 | 38 | #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 |
ac9d8fe7 | 39 | |
c877b3b2 | 40 | #define PCI_VENDOR_ID_ETRON 0x1b6f |
170625e9 | 41 | #define PCI_DEVICE_ID_EJ168 0x7023 |
c877b3b2 | 42 | |
638298dc TI |
43 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 |
44 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 | |
b8cb91e0 MN |
45 | #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 |
46 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f | |
47 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f | |
638298dc | 48 | |
66d4eadd SS |
49 | static const char hcd_name[] = "xhci_hcd"; |
50 | ||
1885d9a3 AB |
51 | static struct hc_driver __read_mostly xhci_pci_hc_driver; |
52 | ||
cd33a321 RQ |
53 | static int xhci_pci_setup(struct usb_hcd *hcd); |
54 | ||
55 | static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { | |
cd33a321 RQ |
56 | .reset = xhci_pci_setup, |
57 | }; | |
58 | ||
66d4eadd SS |
59 | /* called after powerup, by probe or system-pm "wakeup" */ |
60 | static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) | |
61 | { | |
62 | /* | |
63 | * TODO: Implement finding debug ports later. | |
64 | * TODO: see if there are any quirks that need to be added to handle | |
65 | * new extended capabilities. | |
66 | */ | |
67 | ||
68 | /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ | |
69 | if (!pci_set_mwi(pdev)) | |
70 | xhci_dbg(xhci, "MWI active\n"); | |
71 | ||
72 | xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); | |
73 | return 0; | |
74 | } | |
75 | ||
da3c9c4f SAS |
76 | static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) |
77 | { | |
78 | struct pci_dev *pdev = to_pci_dev(dev); | |
79 | ||
ac9d8fe7 SS |
80 | /* Look for vendor-specific quirks */ |
81 | if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && | |
bba18e33 SS |
82 | (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || |
83 | pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { | |
84 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && | |
85 | pdev->revision == 0x0) { | |
ac9d8fe7 | 86 | xhci->quirks |= XHCI_RESET_EP_QUIRK; |
4bdfe4c3 XR |
87 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
88 | "QUIRK: Fresco Logic xHC needs configure" | |
89 | " endpoint cmd after reset endpoint"); | |
f5182b41 | 90 | } |
455f5892 ON |
91 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && |
92 | pdev->revision == 0x4) { | |
93 | xhci->quirks |= XHCI_SLOW_SUSPEND; | |
94 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
95 | "QUIRK: Fresco Logic xHC revision %u" | |
96 | "must be suspended extra slowly", | |
97 | pdev->revision); | |
98 | } | |
7f5c4d63 HG |
99 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) |
100 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
f5182b41 SS |
101 | /* Fresco Logic confirms: all revisions of this chip do not |
102 | * support MSI, even though some of them claim to in their PCI | |
103 | * capabilities. | |
104 | */ | |
105 | xhci->quirks |= XHCI_BROKEN_MSI; | |
4bdfe4c3 XR |
106 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
107 | "QUIRK: Fresco Logic revision %u " | |
108 | "has broken MSI implementation", | |
f5182b41 | 109 | pdev->revision); |
1530bbc6 | 110 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
ac9d8fe7 | 111 | } |
f5182b41 | 112 | |
0238634d SS |
113 | if (pdev->vendor == PCI_VENDOR_ID_NEC) |
114 | xhci->quirks |= XHCI_NEC_HOST; | |
ac9d8fe7 | 115 | |
7e393a83 AX |
116 | if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) |
117 | xhci->quirks |= XHCI_AMD_0x96_HOST; | |
118 | ||
c41136b0 AX |
119 | /* AMD PLL quirk */ |
120 | if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) | |
121 | xhci->quirks |= XHCI_AMD_PLL_FIX; | |
2597fe99 HR |
122 | |
123 | if (pdev->vendor == PCI_VENDOR_ID_AMD) | |
124 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; | |
125 | ||
e3567d2c SS |
126 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
127 | xhci->quirks |= XHCI_LPM_SUPPORT; | |
128 | xhci->quirks |= XHCI_INTEL_HOST; | |
227a4fd8 | 129 | xhci->quirks |= XHCI_AVOID_BEI; |
e3567d2c | 130 | } |
ad808333 SS |
131 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
132 | pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { | |
2cf95c18 SS |
133 | xhci->quirks |= XHCI_EP_LIMIT_QUIRK; |
134 | xhci->limit_active_eps = 64; | |
86cc558e | 135 | xhci->quirks |= XHCI_SW_BW_CHECKING; |
e95829f4 SS |
136 | /* |
137 | * PPT desktop boards DH77EB and DH77DF will power back on after | |
138 | * a few seconds of being shutdown. The fix for this is to | |
139 | * switch the ports from xHCI to EHCI on shutdown. We can't use | |
140 | * DMI information to find those particular boards (since each | |
141 | * vendor will change the board name), so we have to key off all | |
142 | * PPT chipsets. | |
143 | */ | |
144 | xhci->quirks |= XHCI_SPURIOUS_REBOOT; | |
ad808333 | 145 | } |
0a939993 DT |
146 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
147 | pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) { | |
c09ec25d | 148 | xhci->quirks |= XHCI_SPURIOUS_REBOOT; |
fd7cd061 | 149 | xhci->quirks |= XHCI_SPURIOUS_WAKEUP; |
638298dc | 150 | } |
b8cb91e0 MN |
151 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
152 | (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || | |
153 | pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || | |
154 | pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)) { | |
155 | xhci->quirks |= XHCI_PME_STUCK_QUIRK; | |
156 | } | |
c877b3b2 | 157 | if (pdev->vendor == PCI_VENDOR_ID_ETRON && |
170625e9 | 158 | pdev->device == PCI_DEVICE_ID_EJ168) { |
c877b3b2 | 159 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
5cb7df2b | 160 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
8f873c1f | 161 | xhci->quirks |= XHCI_BROKEN_STREAMS; |
c877b3b2 | 162 | } |
1aa9578c | 163 | if (pdev->vendor == PCI_VENDOR_ID_RENESAS && |
6db249eb | 164 | pdev->device == 0x0015) |
1aa9578c | 165 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
457a4f61 EF |
166 | if (pdev->vendor == PCI_VENDOR_ID_VIA) |
167 | xhci->quirks |= XHCI_RESET_ON_RESUME; | |
85f4e45b | 168 | |
e21eba05 HG |
169 | /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ |
170 | if (pdev->vendor == PCI_VENDOR_ID_VIA && | |
171 | pdev->device == 0x3432) | |
172 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
173 | ||
2391eacb HG |
174 | if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && |
175 | pdev->device == 0x1042) | |
176 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
177 | ||
85f4e45b ON |
178 | if (xhci->quirks & XHCI_RESET_ON_RESUME) |
179 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
180 | "QUIRK: Resetting on resume"); | |
da3c9c4f | 181 | } |
c41136b0 | 182 | |
c3c5819a MN |
183 | #ifdef CONFIG_ACPI |
184 | static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) | |
185 | { | |
186 | static const u8 intel_dsm_uuid[] = { | |
187 | 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45, | |
188 | 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23, | |
189 | }; | |
84ed9152 MW |
190 | union acpi_object *obj; |
191 | ||
192 | obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1, | |
193 | NULL); | |
194 | ACPI_FREE(obj); | |
c3c5819a MN |
195 | } |
196 | #else | |
84ed9152 | 197 | static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } |
c3c5819a MN |
198 | #endif /* CONFIG_ACPI */ |
199 | ||
da3c9c4f SAS |
200 | /* called during probe() after chip reset completes */ |
201 | static int xhci_pci_setup(struct usb_hcd *hcd) | |
202 | { | |
203 | struct xhci_hcd *xhci; | |
204 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
205 | int retval; | |
66d4eadd | 206 | |
b50107bb MN |
207 | xhci = hcd_to_xhci(hcd); |
208 | if (!xhci->sbrn) | |
209 | pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); | |
210 | ||
da3c9c4f | 211 | retval = xhci_gen_setup(hcd, xhci_pci_quirks); |
66d4eadd | 212 | if (retval) |
da3c9c4f | 213 | return retval; |
006d5820 | 214 | |
da3c9c4f SAS |
215 | if (!usb_hcd_is_primary_hcd(hcd)) |
216 | return 0; | |
66d4eadd | 217 | |
66d4eadd SS |
218 | xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); |
219 | ||
220 | /* Find any debug ports */ | |
b02d0ed6 SS |
221 | retval = xhci_pci_reinit(xhci, pdev); |
222 | if (!retval) | |
223 | return retval; | |
224 | ||
b02d0ed6 SS |
225 | return retval; |
226 | } | |
227 | ||
f6ff0ac8 SS |
228 | /* |
229 | * We need to register our own PCI probe function (instead of the USB core's | |
230 | * function) in order to create a second roothub under xHCI. | |
231 | */ | |
232 | static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
233 | { | |
234 | int retval; | |
235 | struct xhci_hcd *xhci; | |
236 | struct hc_driver *driver; | |
237 | struct usb_hcd *hcd; | |
238 | ||
239 | driver = (struct hc_driver *)id->driver_data; | |
bcffae77 MN |
240 | |
241 | /* Prevent runtime suspending between USB-2 and USB-3 initialization */ | |
242 | pm_runtime_get_noresume(&dev->dev); | |
243 | ||
f6ff0ac8 SS |
244 | /* Register the USB 2.0 roothub. |
245 | * FIXME: USB core must know to register the USB 2.0 roothub first. | |
246 | * This is sort of silly, because we could just set the HCD driver flags | |
247 | * to say USB 2.0, but I'm not sure what the implications would be in | |
248 | * the other parts of the HCD code. | |
249 | */ | |
250 | retval = usb_hcd_pci_probe(dev, id); | |
251 | ||
252 | if (retval) | |
bcffae77 | 253 | goto put_runtime_pm; |
f6ff0ac8 SS |
254 | |
255 | /* USB 2.0 roothub is stored in the PCI device now. */ | |
256 | hcd = dev_get_drvdata(&dev->dev); | |
257 | xhci = hcd_to_xhci(hcd); | |
258 | xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, | |
259 | pci_name(dev), hcd); | |
260 | if (!xhci->shared_hcd) { | |
261 | retval = -ENOMEM; | |
262 | goto dealloc_usb2_hcd; | |
263 | } | |
264 | ||
f6ff0ac8 | 265 | retval = usb_add_hcd(xhci->shared_hcd, dev->irq, |
b5dd18d8 | 266 | IRQF_SHARED); |
f6ff0ac8 SS |
267 | if (retval) |
268 | goto put_usb3_hcd; | |
269 | /* Roothub already marked as USB 3.0 speed */ | |
3b3db026 | 270 | |
8f873c1f HG |
271 | if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && |
272 | HCC_MAX_PSA(xhci->hcc_params) >= 4) | |
14aec589 ON |
273 | xhci->shared_hcd->can_do_streams = 1; |
274 | ||
c3c5819a MN |
275 | if (xhci->quirks & XHCI_PME_STUCK_QUIRK) |
276 | xhci_pme_acpi_rtd3_enable(dev); | |
277 | ||
bcffae77 MN |
278 | /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ |
279 | pm_runtime_put_noidle(&dev->dev); | |
280 | ||
f6ff0ac8 SS |
281 | return 0; |
282 | ||
283 | put_usb3_hcd: | |
284 | usb_put_hcd(xhci->shared_hcd); | |
285 | dealloc_usb2_hcd: | |
286 | usb_hcd_pci_remove(dev); | |
bcffae77 MN |
287 | put_runtime_pm: |
288 | pm_runtime_put_noidle(&dev->dev); | |
f6ff0ac8 SS |
289 | return retval; |
290 | } | |
291 | ||
b02d0ed6 SS |
292 | static void xhci_pci_remove(struct pci_dev *dev) |
293 | { | |
294 | struct xhci_hcd *xhci; | |
295 | ||
296 | xhci = hcd_to_xhci(pci_get_drvdata(dev)); | |
f6ff0ac8 SS |
297 | if (xhci->shared_hcd) { |
298 | usb_remove_hcd(xhci->shared_hcd); | |
299 | usb_put_hcd(xhci->shared_hcd); | |
300 | } | |
b02d0ed6 | 301 | usb_hcd_pci_remove(dev); |
638298dc TI |
302 | |
303 | /* Workaround for spurious wakeups at shutdown with HSW */ | |
304 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | |
305 | pci_set_power_state(dev, PCI_D3hot); | |
66d4eadd SS |
306 | } |
307 | ||
5535b1d5 | 308 | #ifdef CONFIG_PM |
2b7627b7 TB |
309 | /* |
310 | * In some Intel xHCI controllers, in order to get D3 working, | |
311 | * through a vendor specific SSIC CONFIG register at offset 0x883c, | |
312 | * SSIC PORT need to be marked as "unused" before putting xHCI | |
313 | * into D3. After D3 exit, the SSIC port need to be marked as "used". | |
314 | * Without this change, xHCI might not enter D3 state. | |
315 | * Make sure PME works on some Intel xHCI controllers by writing 1 to clear | |
316 | * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 | |
317 | */ | |
318 | static void xhci_pme_quirk(struct usb_hcd *hcd, bool suspend) | |
319 | { | |
320 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
321 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
322 | u32 val; | |
323 | void __iomem *reg; | |
324 | ||
325 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && | |
326 | pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) { | |
327 | ||
328 | reg = (void __iomem *) xhci->cap_regs + PORT2_SSIC_CONFIG_REG2; | |
329 | ||
330 | /* Notify SSIC that SSIC profile programming is not done */ | |
331 | val = readl(reg) & ~PROG_DONE; | |
332 | writel(val, reg); | |
333 | ||
334 | /* Mark SSIC port as unused(suspend) or used(resume) */ | |
335 | val = readl(reg); | |
336 | if (suspend) | |
337 | val |= SSIC_PORT_UNUSED; | |
338 | else | |
339 | val &= ~SSIC_PORT_UNUSED; | |
340 | writel(val, reg); | |
341 | ||
342 | /* Notify SSIC that SSIC profile programming is done */ | |
343 | val = readl(reg) | PROG_DONE; | |
344 | writel(val, reg); | |
345 | readl(reg); | |
346 | } | |
347 | ||
348 | reg = (void __iomem *) xhci->cap_regs + 0x80a4; | |
349 | val = readl(reg); | |
350 | writel(val | BIT(28), reg); | |
351 | readl(reg); | |
352 | } | |
353 | ||
5535b1d5 AX |
354 | static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) |
355 | { | |
356 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c3897aa5 SS |
357 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
358 | ||
359 | /* | |
360 | * Systems with the TI redriver that loses port status change events | |
361 | * need to have the registers polled during D3, so avoid D3cold. | |
362 | */ | |
e1cd9727 | 363 | if (xhci->quirks & XHCI_COMP_MODE_QUIRK) |
c3897aa5 | 364 | pdev->no_d3cold = true; |
5535b1d5 | 365 | |
b8cb91e0 | 366 | if (xhci->quirks & XHCI_PME_STUCK_QUIRK) |
abce329c | 367 | xhci_pme_quirk(hcd, true); |
b8cb91e0 | 368 | |
a1377e53 | 369 | return xhci_suspend(xhci, do_wakeup); |
5535b1d5 AX |
370 | } |
371 | ||
372 | static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) | |
373 | { | |
374 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
69e848c2 | 375 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
5535b1d5 AX |
376 | int retval = 0; |
377 | ||
69e848c2 SS |
378 | /* The BIOS on systems with the Intel Panther Point chipset may or may |
379 | * not support xHCI natively. That means that during system resume, it | |
380 | * may switch the ports back to EHCI so that users can use their | |
381 | * keyboard to select a kernel from GRUB after resume from hibernate. | |
382 | * | |
383 | * The BIOS is supposed to remember whether the OS had xHCI ports | |
384 | * enabled before resume, and switch the ports back to xHCI when the | |
385 | * BIOS/OS semaphore is written, but we all know we can't trust BIOS | |
386 | * writers. | |
387 | * | |
388 | * Unconditionally switch the ports back to xHCI after a system resume. | |
26b76798 MN |
389 | * It should not matter whether the EHCI or xHCI controller is |
390 | * resumed first. It's enough to do the switchover in xHCI because | |
391 | * USB core won't notice anything as the hub driver doesn't start | |
392 | * running again until after all the devices (including both EHCI and | |
393 | * xHCI host controllers) have been resumed. | |
69e848c2 | 394 | */ |
26b76798 MN |
395 | |
396 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) | |
397 | usb_enable_intel_xhci_ports(pdev); | |
69e848c2 | 398 | |
b8cb91e0 | 399 | if (xhci->quirks & XHCI_PME_STUCK_QUIRK) |
abce329c | 400 | xhci_pme_quirk(hcd, false); |
b8cb91e0 | 401 | |
5535b1d5 AX |
402 | retval = xhci_resume(xhci, hibernated); |
403 | return retval; | |
404 | } | |
405 | #endif /* CONFIG_PM */ | |
406 | ||
66d4eadd SS |
407 | /*-------------------------------------------------------------------------*/ |
408 | ||
409 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
410 | static const struct pci_device_id pci_ids[] = { { | |
411 | /* handle any USB 3.0 xHCI controller */ | |
412 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), | |
413 | .driver_data = (unsigned long) &xhci_pci_hc_driver, | |
414 | }, | |
415 | { /* end: all zeroes */ } | |
416 | }; | |
417 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
418 | ||
419 | /* pci driver glue; this is a "new style" PCI driver module */ | |
420 | static struct pci_driver xhci_pci_driver = { | |
421 | .name = (char *) hcd_name, | |
422 | .id_table = pci_ids, | |
423 | ||
f6ff0ac8 | 424 | .probe = xhci_pci_probe, |
b02d0ed6 | 425 | .remove = xhci_pci_remove, |
66d4eadd SS |
426 | /* suspend and resume implemented later */ |
427 | ||
428 | .shutdown = usb_hcd_pci_shutdown, | |
f875fdbf | 429 | #ifdef CONFIG_PM |
5535b1d5 AX |
430 | .driver = { |
431 | .pm = &usb_hcd_pci_pm_ops | |
432 | }, | |
433 | #endif | |
66d4eadd SS |
434 | }; |
435 | ||
29e409f0 | 436 | static int __init xhci_pci_init(void) |
66d4eadd | 437 | { |
cd33a321 | 438 | xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); |
1885d9a3 AB |
439 | #ifdef CONFIG_PM |
440 | xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; | |
441 | xhci_pci_hc_driver.pci_resume = xhci_pci_resume; | |
442 | #endif | |
66d4eadd SS |
443 | return pci_register_driver(&xhci_pci_driver); |
444 | } | |
29e409f0 | 445 | module_init(xhci_pci_init); |
66d4eadd | 446 | |
29e409f0 | 447 | static void __exit xhci_pci_exit(void) |
66d4eadd SS |
448 | { |
449 | pci_unregister_driver(&xhci_pci_driver); | |
450 | } | |
29e409f0 AB |
451 | module_exit(xhci_pci_exit); |
452 | ||
453 | MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); | |
454 | MODULE_LICENSE("GPL"); |