Commit | Line | Data |
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7f84eef0 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Ring initialization rules: | |
25 | * 1. Each segment is initialized to zero, except for link TRBs. | |
26 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or | |
27 | * Consumer Cycle State (CCS), depending on ring function. | |
28 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. | |
29 | * | |
30 | * Ring behavior rules: | |
31 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at | |
32 | * least one free TRB in the ring. This is useful if you want to turn that | |
33 | * into a link TRB and expand the ring. | |
34 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a | |
35 | * link TRB, then load the pointer with the address in the link TRB. If the | |
36 | * link TRB had its toggle bit set, you may need to update the ring cycle | |
37 | * state (see cycle bit rules). You may have to do this multiple times | |
38 | * until you reach a non-link TRB. | |
39 | * 3. A ring is full if enqueue++ (for the definition of increment above) | |
40 | * equals the dequeue pointer. | |
41 | * | |
42 | * Cycle bit rules: | |
43 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit | |
44 | * in a link TRB, it must toggle the ring cycle state. | |
45 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit | |
46 | * in a link TRB, it must toggle the ring cycle state. | |
47 | * | |
48 | * Producer rules: | |
49 | * 1. Check if ring is full before you enqueue. | |
50 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. | |
51 | * Update enqueue pointer between each write (which may update the ring | |
52 | * cycle state). | |
53 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command | |
54 | * and endpoint rings. If HC is the producer for the event ring, | |
55 | * and it generates an interrupt according to interrupt modulation rules. | |
56 | * | |
57 | * Consumer rules: | |
58 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, | |
59 | * the TRB is owned by the consumer. | |
60 | * 2. Update dequeue pointer (which may update the ring cycle state) and | |
61 | * continue processing TRBs until you reach a TRB which is not owned by you. | |
62 | * 3. Notify the producer. SW is the consumer for the event ring, and it | |
63 | * updates event ring dequeue pointer. HC is the consumer for the command and | |
64 | * endpoint rings; it generates events on the event ring for these. | |
65 | */ | |
66 | ||
8a96c052 | 67 | #include <linux/scatterlist.h> |
7f84eef0 SS |
68 | #include "xhci.h" |
69 | ||
70 | /* | |
71 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | |
72 | * address of the TRB. | |
73 | */ | |
23e3be11 | 74 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
7f84eef0 SS |
75 | union xhci_trb *trb) |
76 | { | |
6071d836 | 77 | unsigned long segment_offset; |
7f84eef0 | 78 | |
6071d836 | 79 | if (!seg || !trb || trb < seg->trbs) |
7f84eef0 | 80 | return 0; |
6071d836 SS |
81 | /* offset in TRBs */ |
82 | segment_offset = trb - seg->trbs; | |
83 | if (segment_offset > TRBS_PER_SEGMENT) | |
7f84eef0 | 84 | return 0; |
6071d836 | 85 | return seg->dma + (segment_offset * sizeof(*trb)); |
7f84eef0 SS |
86 | } |
87 | ||
88 | /* Does this link TRB point to the first segment in a ring, | |
89 | * or was the previous TRB the last TRB on the last segment in the ERST? | |
90 | */ | |
91 | static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
92 | struct xhci_segment *seg, union xhci_trb *trb) | |
93 | { | |
94 | if (ring == xhci->event_ring) | |
95 | return (trb == &seg->trbs[TRBS_PER_SEGMENT]) && | |
96 | (seg->next == xhci->event_ring->first_seg); | |
97 | else | |
98 | return trb->link.control & LINK_TOGGLE; | |
99 | } | |
100 | ||
101 | /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring | |
102 | * segment? I.e. would the updated event TRB pointer step off the end of the | |
103 | * event seg? | |
104 | */ | |
105 | static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
106 | struct xhci_segment *seg, union xhci_trb *trb) | |
107 | { | |
108 | if (ring == xhci->event_ring) | |
109 | return trb == &seg->trbs[TRBS_PER_SEGMENT]; | |
110 | else | |
111 | return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK); | |
112 | } | |
113 | ||
ae636747 SS |
114 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
115 | * TRB is in a new segment. This does not skip over link TRBs, and it does not | |
116 | * effect the ring dequeue or enqueue pointers. | |
117 | */ | |
118 | static void next_trb(struct xhci_hcd *xhci, | |
119 | struct xhci_ring *ring, | |
120 | struct xhci_segment **seg, | |
121 | union xhci_trb **trb) | |
122 | { | |
123 | if (last_trb(xhci, ring, *seg, *trb)) { | |
124 | *seg = (*seg)->next; | |
125 | *trb = ((*seg)->trbs); | |
126 | } else { | |
127 | *trb = (*trb)++; | |
128 | } | |
129 | } | |
130 | ||
7f84eef0 SS |
131 | /* |
132 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
133 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
134 | */ | |
135 | static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer) | |
136 | { | |
137 | union xhci_trb *next = ++(ring->dequeue); | |
66e49d87 | 138 | unsigned long long addr; |
7f84eef0 SS |
139 | |
140 | ring->deq_updates++; | |
141 | /* Update the dequeue pointer further if that was a link TRB or we're at | |
142 | * the end of an event ring segment (which doesn't have link TRBS) | |
143 | */ | |
144 | while (last_trb(xhci, ring, ring->deq_seg, next)) { | |
145 | if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) { | |
146 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
147 | if (!in_interrupt()) | |
700e2052 GKH |
148 | xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n", |
149 | ring, | |
7f84eef0 SS |
150 | (unsigned int) ring->cycle_state); |
151 | } | |
152 | ring->deq_seg = ring->deq_seg->next; | |
153 | ring->dequeue = ring->deq_seg->trbs; | |
154 | next = ring->dequeue; | |
155 | } | |
66e49d87 SS |
156 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue); |
157 | if (ring == xhci->event_ring) | |
158 | xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr); | |
159 | else if (ring == xhci->cmd_ring) | |
160 | xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr); | |
161 | else | |
162 | xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr); | |
7f84eef0 SS |
163 | } |
164 | ||
165 | /* | |
166 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
167 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
168 | * | |
169 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the | |
170 | * chain bit is set), then set the chain bit in all the following link TRBs. | |
171 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs | |
172 | * have their chain bit cleared (so that each Link TRB is a separate TD). | |
173 | * | |
174 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit | |
b0567b3f SS |
175 | * set, but other sections talk about dealing with the chain bit set. This was |
176 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 | |
177 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. | |
7f84eef0 SS |
178 | */ |
179 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer) | |
180 | { | |
181 | u32 chain; | |
182 | union xhci_trb *next; | |
66e49d87 | 183 | unsigned long long addr; |
7f84eef0 SS |
184 | |
185 | chain = ring->enqueue->generic.field[3] & TRB_CHAIN; | |
186 | next = ++(ring->enqueue); | |
187 | ||
188 | ring->enq_updates++; | |
189 | /* Update the dequeue pointer further if that was a link TRB or we're at | |
190 | * the end of an event ring segment (which doesn't have link TRBS) | |
191 | */ | |
192 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | |
193 | if (!consumer) { | |
194 | if (ring != xhci->event_ring) { | |
b0567b3f SS |
195 | /* If we're not dealing with 0.95 hardware, |
196 | * carry over the chain bit of the previous TRB | |
197 | * (which may mean the chain bit is cleared). | |
198 | */ | |
199 | if (!xhci_link_trb_quirk(xhci)) { | |
200 | next->link.control &= ~TRB_CHAIN; | |
201 | next->link.control |= chain; | |
202 | } | |
7f84eef0 | 203 | /* Give this link TRB to the hardware */ |
b7116ebc | 204 | wmb(); |
7f84eef0 SS |
205 | if (next->link.control & TRB_CYCLE) |
206 | next->link.control &= (u32) ~TRB_CYCLE; | |
207 | else | |
208 | next->link.control |= (u32) TRB_CYCLE; | |
7f84eef0 SS |
209 | } |
210 | /* Toggle the cycle bit after the last ring segment. */ | |
211 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | |
212 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
213 | if (!in_interrupt()) | |
700e2052 GKH |
214 | xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n", |
215 | ring, | |
7f84eef0 SS |
216 | (unsigned int) ring->cycle_state); |
217 | } | |
218 | } | |
219 | ring->enq_seg = ring->enq_seg->next; | |
220 | ring->enqueue = ring->enq_seg->trbs; | |
221 | next = ring->enqueue; | |
222 | } | |
66e49d87 SS |
223 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue); |
224 | if (ring == xhci->event_ring) | |
225 | xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr); | |
226 | else if (ring == xhci->cmd_ring) | |
227 | xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr); | |
228 | else | |
229 | xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr); | |
7f84eef0 SS |
230 | } |
231 | ||
232 | /* | |
233 | * Check to see if there's room to enqueue num_trbs on the ring. See rules | |
234 | * above. | |
235 | * FIXME: this would be simpler and faster if we just kept track of the number | |
236 | * of free TRBs in a ring. | |
237 | */ | |
238 | static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
239 | unsigned int num_trbs) | |
240 | { | |
241 | int i; | |
242 | union xhci_trb *enq = ring->enqueue; | |
243 | struct xhci_segment *enq_seg = ring->enq_seg; | |
244 | ||
245 | /* Check if ring is empty */ | |
246 | if (enq == ring->dequeue) | |
247 | return 1; | |
248 | /* Make sure there's an extra empty TRB available */ | |
249 | for (i = 0; i <= num_trbs; ++i) { | |
250 | if (enq == ring->dequeue) | |
251 | return 0; | |
252 | enq++; | |
253 | while (last_trb(xhci, ring, enq_seg, enq)) { | |
254 | enq_seg = enq_seg->next; | |
255 | enq = enq_seg->trbs; | |
256 | } | |
257 | } | |
258 | return 1; | |
259 | } | |
260 | ||
23e3be11 | 261 | void xhci_set_hc_event_deq(struct xhci_hcd *xhci) |
7f84eef0 | 262 | { |
8e595a5d | 263 | u64 temp; |
7f84eef0 SS |
264 | dma_addr_t deq; |
265 | ||
23e3be11 | 266 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, |
7f84eef0 SS |
267 | xhci->event_ring->dequeue); |
268 | if (deq == 0 && !in_interrupt()) | |
269 | xhci_warn(xhci, "WARN something wrong with SW event ring " | |
270 | "dequeue ptr.\n"); | |
271 | /* Update HC event ring dequeue pointer */ | |
8e595a5d | 272 | temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
7f84eef0 | 273 | temp &= ERST_PTR_MASK; |
2d83109b SS |
274 | /* Don't clear the EHB bit (which is RW1C) because |
275 | * there might be more events to service. | |
276 | */ | |
277 | temp &= ~ERST_EHB; | |
66e49d87 | 278 | xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n"); |
8e595a5d SS |
279 | xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp, |
280 | &xhci->ir_set->erst_dequeue); | |
7f84eef0 SS |
281 | } |
282 | ||
283 | /* Ring the host controller doorbell after placing a command on the ring */ | |
23e3be11 | 284 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
7f84eef0 SS |
285 | { |
286 | u32 temp; | |
287 | ||
288 | xhci_dbg(xhci, "// Ding dong!\n"); | |
289 | temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK; | |
290 | xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]); | |
291 | /* Flush PCI posted writes */ | |
292 | xhci_readl(xhci, &xhci->dba->doorbell[0]); | |
293 | } | |
294 | ||
ae636747 SS |
295 | static void ring_ep_doorbell(struct xhci_hcd *xhci, |
296 | unsigned int slot_id, | |
297 | unsigned int ep_index) | |
298 | { | |
63a0d9ab SS |
299 | struct xhci_virt_ep *ep; |
300 | unsigned int ep_state; | |
ae636747 SS |
301 | u32 field; |
302 | __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; | |
303 | ||
63a0d9ab SS |
304 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
305 | ep_state = ep->ep_state; | |
ae636747 SS |
306 | /* Don't ring the doorbell for this endpoint if there are pending |
307 | * cancellations because the we don't want to interrupt processing. | |
308 | */ | |
678539cf | 309 | if (!(ep_state & EP_HALT_PENDING) && !(ep_state & SET_DEQ_PENDING) |
63a0d9ab | 310 | && !(ep_state & EP_HALTED)) { |
ae636747 SS |
311 | field = xhci_readl(xhci, db_addr) & DB_MASK; |
312 | xhci_writel(xhci, field | EPI_TO_DB(ep_index), db_addr); | |
313 | /* Flush PCI posted writes - FIXME Matthew Wilcox says this | |
314 | * isn't time-critical and we shouldn't make the CPU wait for | |
315 | * the flush. | |
316 | */ | |
317 | xhci_readl(xhci, db_addr); | |
318 | } | |
319 | } | |
320 | ||
321 | /* | |
322 | * Find the segment that trb is in. Start searching in start_seg. | |
323 | * If we must move past a segment that has a link TRB with a toggle cycle state | |
324 | * bit set, then we will toggle the value pointed at by cycle_state. | |
325 | */ | |
326 | static struct xhci_segment *find_trb_seg( | |
327 | struct xhci_segment *start_seg, | |
328 | union xhci_trb *trb, int *cycle_state) | |
329 | { | |
330 | struct xhci_segment *cur_seg = start_seg; | |
331 | struct xhci_generic_trb *generic_trb; | |
332 | ||
333 | while (cur_seg->trbs > trb || | |
334 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) { | |
335 | generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic; | |
336 | if (TRB_TYPE(generic_trb->field[3]) == TRB_LINK && | |
337 | (generic_trb->field[3] & LINK_TOGGLE)) | |
338 | *cycle_state = ~(*cycle_state) & 0x1; | |
339 | cur_seg = cur_seg->next; | |
340 | if (cur_seg == start_seg) | |
341 | /* Looped over the entire list. Oops! */ | |
342 | return 0; | |
343 | } | |
344 | return cur_seg; | |
345 | } | |
346 | ||
ae636747 SS |
347 | /* |
348 | * Move the xHC's endpoint ring dequeue pointer past cur_td. | |
349 | * Record the new state of the xHC's endpoint ring dequeue segment, | |
350 | * dequeue pointer, and new consumer cycle state in state. | |
351 | * Update our internal representation of the ring's dequeue pointer. | |
352 | * | |
353 | * We do this in three jumps: | |
354 | * - First we update our new ring state to be the same as when the xHC stopped. | |
355 | * - Then we traverse the ring to find the segment that contains | |
356 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass | |
357 | * any link TRBs with the toggle cycle bit set. | |
358 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit | |
359 | * if we've moved it past a link TRB with the toggle cycle bit set. | |
360 | */ | |
c92bcfa7 | 361 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
ae636747 | 362 | unsigned int slot_id, unsigned int ep_index, |
c92bcfa7 | 363 | struct xhci_td *cur_td, struct xhci_dequeue_state *state) |
ae636747 SS |
364 | { |
365 | struct xhci_virt_device *dev = xhci->devs[slot_id]; | |
63a0d9ab | 366 | struct xhci_ring *ep_ring = dev->eps[ep_index].ring; |
ae636747 | 367 | struct xhci_generic_trb *trb; |
d115b048 | 368 | struct xhci_ep_ctx *ep_ctx; |
c92bcfa7 | 369 | dma_addr_t addr; |
ae636747 SS |
370 | |
371 | state->new_cycle_state = 0; | |
c92bcfa7 | 372 | xhci_dbg(xhci, "Finding segment containing stopped TRB.\n"); |
ae636747 | 373 | state->new_deq_seg = find_trb_seg(cur_td->start_seg, |
63a0d9ab | 374 | dev->eps[ep_index].stopped_trb, |
ae636747 SS |
375 | &state->new_cycle_state); |
376 | if (!state->new_deq_seg) | |
377 | BUG(); | |
378 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ | |
c92bcfa7 | 379 | xhci_dbg(xhci, "Finding endpoint context\n"); |
d115b048 JY |
380 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
381 | state->new_cycle_state = 0x1 & ep_ctx->deq; | |
ae636747 SS |
382 | |
383 | state->new_deq_ptr = cur_td->last_trb; | |
c92bcfa7 | 384 | xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n"); |
ae636747 SS |
385 | state->new_deq_seg = find_trb_seg(state->new_deq_seg, |
386 | state->new_deq_ptr, | |
387 | &state->new_cycle_state); | |
388 | if (!state->new_deq_seg) | |
389 | BUG(); | |
390 | ||
391 | trb = &state->new_deq_ptr->generic; | |
392 | if (TRB_TYPE(trb->field[3]) == TRB_LINK && | |
393 | (trb->field[3] & LINK_TOGGLE)) | |
394 | state->new_cycle_state = ~(state->new_cycle_state) & 0x1; | |
395 | next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr); | |
396 | ||
397 | /* Don't update the ring cycle state for the producer (us). */ | |
c92bcfa7 SS |
398 | xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n", |
399 | state->new_deq_seg); | |
400 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); | |
401 | xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n", | |
402 | (unsigned long long) addr); | |
403 | xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n"); | |
ae636747 SS |
404 | ep_ring->dequeue = state->new_deq_ptr; |
405 | ep_ring->deq_seg = state->new_deq_seg; | |
406 | } | |
407 | ||
23e3be11 | 408 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
ae636747 SS |
409 | struct xhci_td *cur_td) |
410 | { | |
411 | struct xhci_segment *cur_seg; | |
412 | union xhci_trb *cur_trb; | |
413 | ||
414 | for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; | |
415 | true; | |
416 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
417 | if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) == | |
418 | TRB_TYPE(TRB_LINK)) { | |
419 | /* Unchain any chained Link TRBs, but | |
420 | * leave the pointers intact. | |
421 | */ | |
422 | cur_trb->generic.field[3] &= ~TRB_CHAIN; | |
423 | xhci_dbg(xhci, "Cancel (unchain) link TRB\n"); | |
700e2052 GKH |
424 | xhci_dbg(xhci, "Address = %p (0x%llx dma); " |
425 | "in seg %p (0x%llx dma)\n", | |
426 | cur_trb, | |
23e3be11 | 427 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
700e2052 GKH |
428 | cur_seg, |
429 | (unsigned long long)cur_seg->dma); | |
ae636747 SS |
430 | } else { |
431 | cur_trb->generic.field[0] = 0; | |
432 | cur_trb->generic.field[1] = 0; | |
433 | cur_trb->generic.field[2] = 0; | |
434 | /* Preserve only the cycle bit of this TRB */ | |
435 | cur_trb->generic.field[3] &= TRB_CYCLE; | |
436 | cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP); | |
700e2052 GKH |
437 | xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) " |
438 | "in seg %p (0x%llx dma)\n", | |
439 | cur_trb, | |
23e3be11 | 440 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
700e2052 GKH |
441 | cur_seg, |
442 | (unsigned long long)cur_seg->dma); | |
ae636747 SS |
443 | } |
444 | if (cur_trb == cur_td->last_trb) | |
445 | break; | |
446 | } | |
447 | } | |
448 | ||
449 | static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, | |
450 | unsigned int ep_index, struct xhci_segment *deq_seg, | |
451 | union xhci_trb *deq_ptr, u32 cycle_state); | |
452 | ||
c92bcfa7 | 453 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, |
63a0d9ab SS |
454 | unsigned int slot_id, unsigned int ep_index, |
455 | struct xhci_dequeue_state *deq_state) | |
c92bcfa7 | 456 | { |
63a0d9ab SS |
457 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
458 | ||
c92bcfa7 SS |
459 | xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), " |
460 | "new deq ptr = %p (0x%llx dma), new cycle = %u\n", | |
461 | deq_state->new_deq_seg, | |
462 | (unsigned long long)deq_state->new_deq_seg->dma, | |
463 | deq_state->new_deq_ptr, | |
464 | (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr), | |
465 | deq_state->new_cycle_state); | |
466 | queue_set_tr_deq(xhci, slot_id, ep_index, | |
467 | deq_state->new_deq_seg, | |
468 | deq_state->new_deq_ptr, | |
469 | (u32) deq_state->new_cycle_state); | |
470 | /* Stop the TD queueing code from ringing the doorbell until | |
471 | * this command completes. The HC won't set the dequeue pointer | |
472 | * if the ring is running, and ringing the doorbell starts the | |
473 | * ring running. | |
474 | */ | |
63a0d9ab | 475 | ep->ep_state |= SET_DEQ_PENDING; |
c92bcfa7 SS |
476 | } |
477 | ||
6f5165cf SS |
478 | static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
479 | struct xhci_virt_ep *ep) | |
480 | { | |
481 | ep->ep_state &= ~EP_HALT_PENDING; | |
482 | /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the | |
483 | * timer is running on another CPU, we don't decrement stop_cmds_pending | |
484 | * (since we didn't successfully stop the watchdog timer). | |
485 | */ | |
486 | if (del_timer(&ep->stop_cmd_timer)) | |
487 | ep->stop_cmds_pending--; | |
488 | } | |
489 | ||
490 | /* Must be called with xhci->lock held in interrupt context */ | |
491 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, | |
492 | struct xhci_td *cur_td, int status, char *adjective) | |
493 | { | |
494 | struct usb_hcd *hcd = xhci_to_hcd(xhci); | |
495 | ||
496 | cur_td->urb->hcpriv = NULL; | |
497 | usb_hcd_unlink_urb_from_ep(hcd, cur_td->urb); | |
498 | xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, cur_td->urb); | |
499 | ||
500 | spin_unlock(&xhci->lock); | |
501 | usb_hcd_giveback_urb(hcd, cur_td->urb, status); | |
502 | kfree(cur_td); | |
503 | spin_lock(&xhci->lock); | |
504 | xhci_dbg(xhci, "%s URB given back\n", adjective); | |
505 | } | |
506 | ||
ae636747 SS |
507 | /* |
508 | * When we get a command completion for a Stop Endpoint Command, we need to | |
509 | * unlink any cancelled TDs from the ring. There are two ways to do that: | |
510 | * | |
511 | * 1. If the HW was in the middle of processing the TD that needs to be | |
512 | * cancelled, then we must move the ring's dequeue pointer past the last TRB | |
513 | * in the TD with a Set Dequeue Pointer Command. | |
514 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain | |
515 | * bit cleared) so that the HW will skip over them. | |
516 | */ | |
517 | static void handle_stopped_endpoint(struct xhci_hcd *xhci, | |
518 | union xhci_trb *trb) | |
519 | { | |
520 | unsigned int slot_id; | |
521 | unsigned int ep_index; | |
522 | struct xhci_ring *ep_ring; | |
63a0d9ab | 523 | struct xhci_virt_ep *ep; |
ae636747 SS |
524 | struct list_head *entry; |
525 | struct xhci_td *cur_td = 0; | |
526 | struct xhci_td *last_unlinked_td; | |
527 | ||
c92bcfa7 | 528 | struct xhci_dequeue_state deq_state; |
ae636747 SS |
529 | |
530 | memset(&deq_state, 0, sizeof(deq_state)); | |
531 | slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); | |
532 | ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); | |
63a0d9ab SS |
533 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
534 | ep_ring = ep->ring; | |
ae636747 | 535 | |
678539cf | 536 | if (list_empty(&ep->cancelled_td_list)) { |
6f5165cf | 537 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
678539cf | 538 | ring_ep_doorbell(xhci, slot_id, ep_index); |
ae636747 | 539 | return; |
678539cf | 540 | } |
ae636747 SS |
541 | |
542 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. | |
543 | * We have the xHCI lock, so nothing can modify this list until we drop | |
544 | * it. We're also in the event handler, so we can't get re-interrupted | |
545 | * if another Stop Endpoint command completes | |
546 | */ | |
63a0d9ab | 547 | list_for_each(entry, &ep->cancelled_td_list) { |
ae636747 | 548 | cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); |
700e2052 GKH |
549 | xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n", |
550 | cur_td->first_trb, | |
23e3be11 | 551 | (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb)); |
ae636747 SS |
552 | /* |
553 | * If we stopped on the TD we need to cancel, then we have to | |
554 | * move the xHC endpoint ring dequeue pointer past this TD. | |
555 | */ | |
63a0d9ab | 556 | if (cur_td == ep->stopped_td) |
c92bcfa7 | 557 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, cur_td, |
ae636747 SS |
558 | &deq_state); |
559 | else | |
560 | td_to_noop(xhci, ep_ring, cur_td); | |
561 | /* | |
562 | * The event handler won't see a completion for this TD anymore, | |
563 | * so remove it from the endpoint ring's TD list. Keep it in | |
564 | * the cancelled TD list for URB completion later. | |
565 | */ | |
566 | list_del(&cur_td->td_list); | |
ae636747 SS |
567 | } |
568 | last_unlinked_td = cur_td; | |
6f5165cf | 569 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
ae636747 SS |
570 | |
571 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ | |
572 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { | |
63a0d9ab | 573 | xhci_queue_new_dequeue_state(xhci, |
c92bcfa7 | 574 | slot_id, ep_index, &deq_state); |
ac9d8fe7 | 575 | xhci_ring_cmd_db(xhci); |
ae636747 SS |
576 | } else { |
577 | /* Otherwise just ring the doorbell to restart the ring */ | |
578 | ring_ep_doorbell(xhci, slot_id, ep_index); | |
579 | } | |
580 | ||
581 | /* | |
582 | * Drop the lock and complete the URBs in the cancelled TD list. | |
583 | * New TDs to be cancelled might be added to the end of the list before | |
584 | * we can complete all the URBs for the TDs we already unlinked. | |
585 | * So stop when we've completed the URB for the last TD we unlinked. | |
586 | */ | |
587 | do { | |
63a0d9ab | 588 | cur_td = list_entry(ep->cancelled_td_list.next, |
ae636747 SS |
589 | struct xhci_td, cancelled_td_list); |
590 | list_del(&cur_td->cancelled_td_list); | |
591 | ||
592 | /* Clean up the cancelled URB */ | |
ae636747 SS |
593 | /* Doesn't matter what we pass for status, since the core will |
594 | * just overwrite it (because the URB has been unlinked). | |
595 | */ | |
6f5165cf | 596 | xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled"); |
ae636747 | 597 | |
6f5165cf SS |
598 | /* Stop processing the cancelled list if the watchdog timer is |
599 | * running. | |
600 | */ | |
601 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
602 | return; | |
ae636747 SS |
603 | } while (cur_td != last_unlinked_td); |
604 | ||
605 | /* Return to the event handler with xhci->lock re-acquired */ | |
606 | } | |
607 | ||
6f5165cf SS |
608 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
609 | * In this case, we assume the host controller is broken or dying or dead. The | |
610 | * host may still be completing some other events, so we have to be careful to | |
611 | * let the event ring handler and the URB dequeueing/enqueueing functions know | |
612 | * through xhci->state. | |
613 | * | |
614 | * The timer may also fire if the host takes a very long time to respond to the | |
615 | * command, and the stop endpoint command completion handler cannot delete the | |
616 | * timer before the timer function is called. Another endpoint cancellation may | |
617 | * sneak in before the timer function can grab the lock, and that may queue | |
618 | * another stop endpoint command and add the timer back. So we cannot use a | |
619 | * simple flag to say whether there is a pending stop endpoint command for a | |
620 | * particular endpoint. | |
621 | * | |
622 | * Instead we use a combination of that flag and a counter for the number of | |
623 | * pending stop endpoint commands. If the timer is the tail end of the last | |
624 | * stop endpoint command, and the endpoint's command is still pending, we assume | |
625 | * the host is dying. | |
626 | */ | |
627 | void xhci_stop_endpoint_command_watchdog(unsigned long arg) | |
628 | { | |
629 | struct xhci_hcd *xhci; | |
630 | struct xhci_virt_ep *ep; | |
631 | struct xhci_virt_ep *temp_ep; | |
632 | struct xhci_ring *ring; | |
633 | struct xhci_td *cur_td; | |
634 | int ret, i, j; | |
635 | ||
636 | ep = (struct xhci_virt_ep *) arg; | |
637 | xhci = ep->xhci; | |
638 | ||
639 | spin_lock(&xhci->lock); | |
640 | ||
641 | ep->stop_cmds_pending--; | |
642 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
643 | xhci_dbg(xhci, "Stop EP timer ran, but another timer marked " | |
644 | "xHCI as DYING, exiting.\n"); | |
645 | spin_unlock(&xhci->lock); | |
646 | return; | |
647 | } | |
648 | if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { | |
649 | xhci_dbg(xhci, "Stop EP timer ran, but no command pending, " | |
650 | "exiting.\n"); | |
651 | spin_unlock(&xhci->lock); | |
652 | return; | |
653 | } | |
654 | ||
655 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); | |
656 | xhci_warn(xhci, "Assuming host is dying, halting host.\n"); | |
657 | /* Oops, HC is dead or dying or at least not responding to the stop | |
658 | * endpoint command. | |
659 | */ | |
660 | xhci->xhc_state |= XHCI_STATE_DYING; | |
661 | /* Disable interrupts from the host controller and start halting it */ | |
662 | xhci_quiesce(xhci); | |
663 | spin_unlock(&xhci->lock); | |
664 | ||
665 | ret = xhci_halt(xhci); | |
666 | ||
667 | spin_lock(&xhci->lock); | |
668 | if (ret < 0) { | |
669 | /* This is bad; the host is not responding to commands and it's | |
670 | * not allowing itself to be halted. At least interrupts are | |
671 | * disabled, so we can set HC_STATE_HALT and notify the | |
672 | * USB core. But if we call usb_hc_died(), it will attempt to | |
673 | * disconnect all device drivers under this host. Those | |
674 | * disconnect() methods will wait for all URBs to be unlinked, | |
675 | * so we must complete them. | |
676 | */ | |
677 | xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); | |
678 | xhci_warn(xhci, "Completing active URBs anyway.\n"); | |
679 | /* We could turn all TDs on the rings to no-ops. This won't | |
680 | * help if the host has cached part of the ring, and is slow if | |
681 | * we want to preserve the cycle bit. Skip it and hope the host | |
682 | * doesn't touch the memory. | |
683 | */ | |
684 | } | |
685 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
686 | if (!xhci->devs[i]) | |
687 | continue; | |
688 | for (j = 0; j < 31; j++) { | |
689 | temp_ep = &xhci->devs[i]->eps[j]; | |
690 | ring = temp_ep->ring; | |
691 | if (!ring) | |
692 | continue; | |
693 | xhci_dbg(xhci, "Killing URBs for slot ID %u, " | |
694 | "ep index %u\n", i, j); | |
695 | while (!list_empty(&ring->td_list)) { | |
696 | cur_td = list_first_entry(&ring->td_list, | |
697 | struct xhci_td, | |
698 | td_list); | |
699 | list_del(&cur_td->td_list); | |
700 | if (!list_empty(&cur_td->cancelled_td_list)) | |
701 | list_del(&cur_td->cancelled_td_list); | |
702 | xhci_giveback_urb_in_irq(xhci, cur_td, | |
703 | -ESHUTDOWN, "killed"); | |
704 | } | |
705 | while (!list_empty(&temp_ep->cancelled_td_list)) { | |
706 | cur_td = list_first_entry( | |
707 | &temp_ep->cancelled_td_list, | |
708 | struct xhci_td, | |
709 | cancelled_td_list); | |
710 | list_del(&cur_td->cancelled_td_list); | |
711 | xhci_giveback_urb_in_irq(xhci, cur_td, | |
712 | -ESHUTDOWN, "killed"); | |
713 | } | |
714 | } | |
715 | } | |
716 | spin_unlock(&xhci->lock); | |
717 | xhci_to_hcd(xhci)->state = HC_STATE_HALT; | |
718 | xhci_dbg(xhci, "Calling usb_hc_died()\n"); | |
719 | usb_hc_died(xhci_to_hcd(xhci)); | |
720 | xhci_dbg(xhci, "xHCI host controller is dead.\n"); | |
721 | } | |
722 | ||
ae636747 SS |
723 | /* |
724 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, | |
725 | * we need to clear the set deq pending flag in the endpoint ring state, so that | |
726 | * the TD queueing code can ring the doorbell again. We also need to ring the | |
727 | * endpoint doorbell to restart the ring, but only if there aren't more | |
728 | * cancellations pending. | |
729 | */ | |
730 | static void handle_set_deq_completion(struct xhci_hcd *xhci, | |
731 | struct xhci_event_cmd *event, | |
732 | union xhci_trb *trb) | |
733 | { | |
734 | unsigned int slot_id; | |
735 | unsigned int ep_index; | |
736 | struct xhci_ring *ep_ring; | |
737 | struct xhci_virt_device *dev; | |
d115b048 JY |
738 | struct xhci_ep_ctx *ep_ctx; |
739 | struct xhci_slot_ctx *slot_ctx; | |
ae636747 SS |
740 | |
741 | slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); | |
742 | ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); | |
743 | dev = xhci->devs[slot_id]; | |
63a0d9ab | 744 | ep_ring = dev->eps[ep_index].ring; |
d115b048 JY |
745 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
746 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); | |
ae636747 SS |
747 | |
748 | if (GET_COMP_CODE(event->status) != COMP_SUCCESS) { | |
749 | unsigned int ep_state; | |
750 | unsigned int slot_state; | |
751 | ||
752 | switch (GET_COMP_CODE(event->status)) { | |
753 | case COMP_TRB_ERR: | |
754 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because " | |
755 | "of stream ID configuration\n"); | |
756 | break; | |
757 | case COMP_CTX_STATE: | |
758 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due " | |
759 | "to incorrect slot or ep state.\n"); | |
d115b048 | 760 | ep_state = ep_ctx->ep_info; |
ae636747 | 761 | ep_state &= EP_STATE_MASK; |
d115b048 | 762 | slot_state = slot_ctx->dev_state; |
ae636747 SS |
763 | slot_state = GET_SLOT_STATE(slot_state); |
764 | xhci_dbg(xhci, "Slot state = %u, EP state = %u\n", | |
765 | slot_state, ep_state); | |
766 | break; | |
767 | case COMP_EBADSLT: | |
768 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because " | |
769 | "slot %u was not enabled.\n", slot_id); | |
770 | break; | |
771 | default: | |
772 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown " | |
773 | "completion code of %u.\n", | |
774 | GET_COMP_CODE(event->status)); | |
775 | break; | |
776 | } | |
777 | /* OK what do we do now? The endpoint state is hosed, and we | |
778 | * should never get to this point if the synchronization between | |
779 | * queueing, and endpoint state are correct. This might happen | |
780 | * if the device gets disconnected after we've finished | |
781 | * cancelling URBs, which might not be an error... | |
782 | */ | |
783 | } else { | |
8e595a5d | 784 | xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n", |
d115b048 | 785 | ep_ctx->deq); |
ae636747 SS |
786 | } |
787 | ||
63a0d9ab | 788 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
ae636747 SS |
789 | ring_ep_doorbell(xhci, slot_id, ep_index); |
790 | } | |
791 | ||
a1587d97 SS |
792 | static void handle_reset_ep_completion(struct xhci_hcd *xhci, |
793 | struct xhci_event_cmd *event, | |
794 | union xhci_trb *trb) | |
795 | { | |
796 | int slot_id; | |
797 | unsigned int ep_index; | |
ac9d8fe7 | 798 | struct xhci_ring *ep_ring; |
a1587d97 SS |
799 | |
800 | slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); | |
801 | ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); | |
63a0d9ab | 802 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
a1587d97 SS |
803 | /* This command will only fail if the endpoint wasn't halted, |
804 | * but we don't care. | |
805 | */ | |
806 | xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n", | |
807 | (unsigned int) GET_COMP_CODE(event->status)); | |
808 | ||
ac9d8fe7 SS |
809 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
810 | * command complete before the endpoint can be used. Queue that here | |
811 | * because the HW can't handle two commands being queued in a row. | |
812 | */ | |
813 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { | |
814 | xhci_dbg(xhci, "Queueing configure endpoint command\n"); | |
815 | xhci_queue_configure_endpoint(xhci, | |
913a8a34 SS |
816 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
817 | false); | |
ac9d8fe7 SS |
818 | xhci_ring_cmd_db(xhci); |
819 | } else { | |
820 | /* Clear our internal halted state and restart the ring */ | |
63a0d9ab | 821 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
ac9d8fe7 SS |
822 | ring_ep_doorbell(xhci, slot_id, ep_index); |
823 | } | |
a1587d97 | 824 | } |
ae636747 | 825 | |
a50c8aa9 SS |
826 | /* Check to see if a command in the device's command queue matches this one. |
827 | * Signal the completion or free the command, and return 1. Return 0 if the | |
828 | * completed command isn't at the head of the command list. | |
829 | */ | |
830 | static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, | |
831 | struct xhci_virt_device *virt_dev, | |
832 | struct xhci_event_cmd *event) | |
833 | { | |
834 | struct xhci_command *command; | |
835 | ||
836 | if (list_empty(&virt_dev->cmd_list)) | |
837 | return 0; | |
838 | ||
839 | command = list_entry(virt_dev->cmd_list.next, | |
840 | struct xhci_command, cmd_list); | |
841 | if (xhci->cmd_ring->dequeue != command->command_trb) | |
842 | return 0; | |
843 | ||
844 | command->status = | |
845 | GET_COMP_CODE(event->status); | |
846 | list_del(&command->cmd_list); | |
847 | if (command->completion) | |
848 | complete(command->completion); | |
849 | else | |
850 | xhci_free_command(xhci, command); | |
851 | return 1; | |
852 | } | |
853 | ||
7f84eef0 SS |
854 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
855 | struct xhci_event_cmd *event) | |
856 | { | |
3ffbba95 | 857 | int slot_id = TRB_TO_SLOT_ID(event->flags); |
7f84eef0 SS |
858 | u64 cmd_dma; |
859 | dma_addr_t cmd_dequeue_dma; | |
ac9d8fe7 | 860 | struct xhci_input_control_ctx *ctrl_ctx; |
913a8a34 | 861 | struct xhci_virt_device *virt_dev; |
ac9d8fe7 SS |
862 | unsigned int ep_index; |
863 | struct xhci_ring *ep_ring; | |
864 | unsigned int ep_state; | |
7f84eef0 | 865 | |
8e595a5d | 866 | cmd_dma = event->cmd_trb; |
23e3be11 | 867 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
7f84eef0 SS |
868 | xhci->cmd_ring->dequeue); |
869 | /* Is the command ring deq ptr out of sync with the deq seg ptr? */ | |
870 | if (cmd_dequeue_dma == 0) { | |
871 | xhci->error_bitmask |= 1 << 4; | |
872 | return; | |
873 | } | |
874 | /* Does the DMA address match our internal dequeue pointer address? */ | |
875 | if (cmd_dma != (u64) cmd_dequeue_dma) { | |
876 | xhci->error_bitmask |= 1 << 5; | |
877 | return; | |
878 | } | |
879 | switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) { | |
3ffbba95 SS |
880 | case TRB_TYPE(TRB_ENABLE_SLOT): |
881 | if (GET_COMP_CODE(event->status) == COMP_SUCCESS) | |
882 | xhci->slot_id = slot_id; | |
883 | else | |
884 | xhci->slot_id = 0; | |
885 | complete(&xhci->addr_dev); | |
886 | break; | |
887 | case TRB_TYPE(TRB_DISABLE_SLOT): | |
888 | if (xhci->devs[slot_id]) | |
889 | xhci_free_virt_device(xhci, slot_id); | |
890 | break; | |
f94e0186 | 891 | case TRB_TYPE(TRB_CONFIG_EP): |
913a8a34 | 892 | virt_dev = xhci->devs[slot_id]; |
a50c8aa9 | 893 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) |
913a8a34 | 894 | break; |
ac9d8fe7 SS |
895 | /* |
896 | * Configure endpoint commands can come from the USB core | |
897 | * configuration or alt setting changes, or because the HW | |
898 | * needed an extra configure endpoint command after a reset | |
899 | * endpoint command. In the latter case, the xHCI driver is | |
900 | * not waiting on the configure endpoint command. | |
901 | */ | |
902 | ctrl_ctx = xhci_get_input_control_ctx(xhci, | |
913a8a34 | 903 | virt_dev->in_ctx); |
ac9d8fe7 SS |
904 | /* Input ctx add_flags are the endpoint index plus one */ |
905 | ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1; | |
63a0d9ab | 906 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
ac9d8fe7 SS |
907 | if (!ep_ring) { |
908 | /* This must have been an initial configure endpoint */ | |
909 | xhci->devs[slot_id]->cmd_status = | |
910 | GET_COMP_CODE(event->status); | |
911 | complete(&xhci->devs[slot_id]->cmd_completion); | |
912 | break; | |
913 | } | |
63a0d9ab | 914 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; |
ac9d8fe7 SS |
915 | xhci_dbg(xhci, "Completed config ep cmd - last ep index = %d, " |
916 | "state = %d\n", ep_index, ep_state); | |
917 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && | |
918 | ep_state & EP_HALTED) { | |
919 | /* Clear our internal halted state and restart ring */ | |
63a0d9ab | 920 | xhci->devs[slot_id]->eps[ep_index].ep_state &= |
ac9d8fe7 SS |
921 | ~EP_HALTED; |
922 | ring_ep_doorbell(xhci, slot_id, ep_index); | |
923 | } else { | |
924 | xhci->devs[slot_id]->cmd_status = | |
925 | GET_COMP_CODE(event->status); | |
926 | complete(&xhci->devs[slot_id]->cmd_completion); | |
927 | } | |
f94e0186 | 928 | break; |
2d3f1fac | 929 | case TRB_TYPE(TRB_EVAL_CONTEXT): |
ac1c1b7f SS |
930 | virt_dev = xhci->devs[slot_id]; |
931 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) | |
932 | break; | |
2d3f1fac SS |
933 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status); |
934 | complete(&xhci->devs[slot_id]->cmd_completion); | |
935 | break; | |
3ffbba95 SS |
936 | case TRB_TYPE(TRB_ADDR_DEV): |
937 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status); | |
938 | complete(&xhci->addr_dev); | |
939 | break; | |
ae636747 SS |
940 | case TRB_TYPE(TRB_STOP_RING): |
941 | handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue); | |
942 | break; | |
943 | case TRB_TYPE(TRB_SET_DEQ): | |
944 | handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue); | |
945 | break; | |
7f84eef0 SS |
946 | case TRB_TYPE(TRB_CMD_NOOP): |
947 | ++xhci->noops_handled; | |
948 | break; | |
a1587d97 SS |
949 | case TRB_TYPE(TRB_RESET_EP): |
950 | handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue); | |
951 | break; | |
7f84eef0 SS |
952 | default: |
953 | /* Skip over unknown commands on the event ring */ | |
954 | xhci->error_bitmask |= 1 << 6; | |
955 | break; | |
956 | } | |
957 | inc_deq(xhci, xhci->cmd_ring, false); | |
958 | } | |
959 | ||
0f2a7930 SS |
960 | static void handle_port_status(struct xhci_hcd *xhci, |
961 | union xhci_trb *event) | |
962 | { | |
963 | u32 port_id; | |
964 | ||
965 | /* Port status change events always have a successful completion code */ | |
966 | if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) { | |
967 | xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); | |
968 | xhci->error_bitmask |= 1 << 8; | |
969 | } | |
970 | /* FIXME: core doesn't care about all port link state changes yet */ | |
971 | port_id = GET_PORT_ID(event->generic.field[0]); | |
972 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); | |
973 | ||
974 | /* Update event ring dequeue pointer before dropping the lock */ | |
975 | inc_deq(xhci, xhci->event_ring, true); | |
23e3be11 | 976 | xhci_set_hc_event_deq(xhci); |
0f2a7930 SS |
977 | |
978 | spin_unlock(&xhci->lock); | |
979 | /* Pass this up to the core */ | |
980 | usb_hcd_poll_rh_status(xhci_to_hcd(xhci)); | |
981 | spin_lock(&xhci->lock); | |
982 | } | |
983 | ||
d0e96f5a SS |
984 | /* |
985 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending | |
986 | * at end_trb, which may be in another segment. If the suspect DMA address is a | |
987 | * TRB in this TD, this function returns that TRB's segment. Otherwise it | |
988 | * returns 0. | |
989 | */ | |
6648f29d | 990 | struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, |
d0e96f5a SS |
991 | union xhci_trb *start_trb, |
992 | union xhci_trb *end_trb, | |
993 | dma_addr_t suspect_dma) | |
994 | { | |
995 | dma_addr_t start_dma; | |
996 | dma_addr_t end_seg_dma; | |
997 | dma_addr_t end_trb_dma; | |
998 | struct xhci_segment *cur_seg; | |
999 | ||
23e3be11 | 1000 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
d0e96f5a SS |
1001 | cur_seg = start_seg; |
1002 | ||
1003 | do { | |
2fa88daa SS |
1004 | if (start_dma == 0) |
1005 | return 0; | |
ae636747 | 1006 | /* We may get an event for a Link TRB in the middle of a TD */ |
23e3be11 | 1007 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
2fa88daa | 1008 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
d0e96f5a | 1009 | /* If the end TRB isn't in this segment, this is set to 0 */ |
23e3be11 | 1010 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
d0e96f5a SS |
1011 | |
1012 | if (end_trb_dma > 0) { | |
1013 | /* The end TRB is in this segment, so suspect should be here */ | |
1014 | if (start_dma <= end_trb_dma) { | |
1015 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) | |
1016 | return cur_seg; | |
1017 | } else { | |
1018 | /* Case for one segment with | |
1019 | * a TD wrapped around to the top | |
1020 | */ | |
1021 | if ((suspect_dma >= start_dma && | |
1022 | suspect_dma <= end_seg_dma) || | |
1023 | (suspect_dma >= cur_seg->dma && | |
1024 | suspect_dma <= end_trb_dma)) | |
1025 | return cur_seg; | |
1026 | } | |
1027 | return 0; | |
1028 | } else { | |
1029 | /* Might still be somewhere in this segment */ | |
1030 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) | |
1031 | return cur_seg; | |
1032 | } | |
1033 | cur_seg = cur_seg->next; | |
23e3be11 | 1034 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
2fa88daa | 1035 | } while (cur_seg != start_seg); |
d0e96f5a | 1036 | |
2fa88daa | 1037 | return 0; |
d0e96f5a SS |
1038 | } |
1039 | ||
1040 | /* | |
1041 | * If this function returns an error condition, it means it got a Transfer | |
1042 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. | |
1043 | * At this point, the host controller is probably hosed and should be reset. | |
1044 | */ | |
1045 | static int handle_tx_event(struct xhci_hcd *xhci, | |
1046 | struct xhci_transfer_event *event) | |
1047 | { | |
1048 | struct xhci_virt_device *xdev; | |
63a0d9ab | 1049 | struct xhci_virt_ep *ep; |
d0e96f5a | 1050 | struct xhci_ring *ep_ring; |
82d1009f | 1051 | unsigned int slot_id; |
d0e96f5a SS |
1052 | int ep_index; |
1053 | struct xhci_td *td = 0; | |
1054 | dma_addr_t event_dma; | |
1055 | struct xhci_segment *event_seg; | |
1056 | union xhci_trb *event_trb; | |
ae636747 | 1057 | struct urb *urb = 0; |
d0e96f5a | 1058 | int status = -EINPROGRESS; |
d115b048 | 1059 | struct xhci_ep_ctx *ep_ctx; |
66d1eebc | 1060 | u32 trb_comp_code; |
d0e96f5a | 1061 | |
66e49d87 | 1062 | xhci_dbg(xhci, "In %s\n", __func__); |
82d1009f SS |
1063 | slot_id = TRB_TO_SLOT_ID(event->flags); |
1064 | xdev = xhci->devs[slot_id]; | |
d0e96f5a SS |
1065 | if (!xdev) { |
1066 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); | |
1067 | return -ENODEV; | |
1068 | } | |
1069 | ||
1070 | /* Endpoint ID is 1 based, our index is zero based */ | |
1071 | ep_index = TRB_TO_EP_ID(event->flags) - 1; | |
66e49d87 | 1072 | xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index); |
63a0d9ab SS |
1073 | ep = &xdev->eps[ep_index]; |
1074 | ep_ring = ep->ring; | |
d115b048 JY |
1075 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
1076 | if (!ep_ring || (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) { | |
d0e96f5a SS |
1077 | xhci_err(xhci, "ERROR Transfer event pointed to disabled endpoint\n"); |
1078 | return -ENODEV; | |
1079 | } | |
1080 | ||
8e595a5d | 1081 | event_dma = event->buffer; |
d0e96f5a | 1082 | /* This TRB should be in the TD at the head of this ring's TD list */ |
66e49d87 | 1083 | xhci_dbg(xhci, "%s - checking for list empty\n", __func__); |
d0e96f5a SS |
1084 | if (list_empty(&ep_ring->td_list)) { |
1085 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", | |
1086 | TRB_TO_SLOT_ID(event->flags), ep_index); | |
1087 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", | |
1088 | (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10); | |
1089 | xhci_print_trb_offsets(xhci, (union xhci_trb *) event); | |
1090 | urb = NULL; | |
1091 | goto cleanup; | |
1092 | } | |
66e49d87 | 1093 | xhci_dbg(xhci, "%s - getting list entry\n", __func__); |
d0e96f5a SS |
1094 | td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); |
1095 | ||
1096 | /* Is this a TRB in the currently executing TD? */ | |
66e49d87 | 1097 | xhci_dbg(xhci, "%s - looking for TD\n", __func__); |
d0e96f5a SS |
1098 | event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue, |
1099 | td->last_trb, event_dma); | |
66e49d87 | 1100 | xhci_dbg(xhci, "%s - found event_seg = %p\n", __func__, event_seg); |
d0e96f5a SS |
1101 | if (!event_seg) { |
1102 | /* HC is busted, give up! */ | |
1103 | xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not part of current TD\n"); | |
1104 | return -ESHUTDOWN; | |
1105 | } | |
1106 | event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / sizeof(*event_trb)]; | |
b10de142 SS |
1107 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", |
1108 | (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10); | |
8e595a5d SS |
1109 | xhci_dbg(xhci, "Offset 0x00 (buffer lo) = 0x%x\n", |
1110 | lower_32_bits(event->buffer)); | |
1111 | xhci_dbg(xhci, "Offset 0x04 (buffer hi) = 0x%x\n", | |
1112 | upper_32_bits(event->buffer)); | |
b10de142 SS |
1113 | xhci_dbg(xhci, "Offset 0x08 (transfer length) = 0x%x\n", |
1114 | (unsigned int) event->transfer_len); | |
1115 | xhci_dbg(xhci, "Offset 0x0C (flags) = 0x%x\n", | |
1116 | (unsigned int) event->flags); | |
1117 | ||
1118 | /* Look for common error cases */ | |
66d1eebc SS |
1119 | trb_comp_code = GET_COMP_CODE(event->transfer_len); |
1120 | switch (trb_comp_code) { | |
b10de142 SS |
1121 | /* Skip codes that require special handling depending on |
1122 | * transfer type | |
1123 | */ | |
1124 | case COMP_SUCCESS: | |
1125 | case COMP_SHORT_TX: | |
1126 | break; | |
ae636747 SS |
1127 | case COMP_STOP: |
1128 | xhci_dbg(xhci, "Stopped on Transfer TRB\n"); | |
1129 | break; | |
1130 | case COMP_STOP_INVAL: | |
1131 | xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); | |
1132 | break; | |
b10de142 SS |
1133 | case COMP_STALL: |
1134 | xhci_warn(xhci, "WARN: Stalled endpoint\n"); | |
63a0d9ab | 1135 | ep->ep_state |= EP_HALTED; |
b10de142 SS |
1136 | status = -EPIPE; |
1137 | break; | |
1138 | case COMP_TRB_ERR: | |
1139 | xhci_warn(xhci, "WARN: TRB error on endpoint\n"); | |
1140 | status = -EILSEQ; | |
1141 | break; | |
1142 | case COMP_TX_ERR: | |
1143 | xhci_warn(xhci, "WARN: transfer error on endpoint\n"); | |
1144 | status = -EPROTO; | |
1145 | break; | |
4a73143c SS |
1146 | case COMP_BABBLE: |
1147 | xhci_warn(xhci, "WARN: babble error on endpoint\n"); | |
1148 | status = -EOVERFLOW; | |
1149 | break; | |
b10de142 SS |
1150 | case COMP_DB_ERR: |
1151 | xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); | |
1152 | status = -ENOSR; | |
1153 | break; | |
1154 | default: | |
1155 | xhci_warn(xhci, "ERROR Unknown event condition, HC probably busted\n"); | |
1156 | urb = NULL; | |
1157 | goto cleanup; | |
1158 | } | |
d0e96f5a SS |
1159 | /* Now update the urb's actual_length and give back to the core */ |
1160 | /* Was this a control transfer? */ | |
1161 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) { | |
1162 | xhci_debug_trb(xhci, xhci->event_ring->dequeue); | |
66d1eebc | 1163 | switch (trb_comp_code) { |
d0e96f5a SS |
1164 | case COMP_SUCCESS: |
1165 | if (event_trb == ep_ring->dequeue) { | |
1166 | xhci_warn(xhci, "WARN: Success on ctrl setup TRB without IOC set??\n"); | |
1167 | status = -ESHUTDOWN; | |
1168 | } else if (event_trb != td->last_trb) { | |
1169 | xhci_warn(xhci, "WARN: Success on ctrl data TRB without IOC set??\n"); | |
1170 | status = -ESHUTDOWN; | |
1171 | } else { | |
1172 | xhci_dbg(xhci, "Successful control transfer!\n"); | |
1173 | status = 0; | |
1174 | } | |
1175 | break; | |
1176 | case COMP_SHORT_TX: | |
1177 | xhci_warn(xhci, "WARN: short transfer on control ep\n"); | |
204970a4 SS |
1178 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
1179 | status = -EREMOTEIO; | |
1180 | else | |
1181 | status = 0; | |
d0e96f5a | 1182 | break; |
83fbcdcc SS |
1183 | case COMP_BABBLE: |
1184 | /* The 0.96 spec says a babbling control endpoint | |
1185 | * is not halted. The 0.96 spec says it is. Some HW | |
1186 | * claims to be 0.95 compliant, but it halts the control | |
1187 | * endpoint anyway. Check if a babble halted the | |
1188 | * endpoint. | |
1189 | */ | |
1190 | if (ep_ctx->ep_info != EP_STATE_HALTED) | |
1191 | break; | |
1192 | /* else fall through */ | |
82d1009f SS |
1193 | case COMP_STALL: |
1194 | /* Did we transfer part of the data (middle) phase? */ | |
1195 | if (event_trb != ep_ring->dequeue && | |
1196 | event_trb != td->last_trb) | |
1197 | td->urb->actual_length = | |
1198 | td->urb->transfer_buffer_length | |
1199 | - TRB_LEN(event->transfer_len); | |
1200 | else | |
1201 | td->urb->actual_length = 0; | |
1202 | ||
63a0d9ab SS |
1203 | ep->stopped_td = td; |
1204 | ep->stopped_trb = event_trb; | |
82d1009f | 1205 | xhci_queue_reset_ep(xhci, slot_id, ep_index); |
63a0d9ab | 1206 | xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index); |
82d1009f SS |
1207 | xhci_ring_cmd_db(xhci); |
1208 | goto td_cleanup; | |
d0e96f5a | 1209 | default: |
b10de142 SS |
1210 | /* Others already handled above */ |
1211 | break; | |
d0e96f5a SS |
1212 | } |
1213 | /* | |
1214 | * Did we transfer any data, despite the errors that might have | |
1215 | * happened? I.e. did we get past the setup stage? | |
1216 | */ | |
1217 | if (event_trb != ep_ring->dequeue) { | |
1218 | /* The event was for the status stage */ | |
1219 | if (event_trb == td->last_trb) { | |
c92bcfa7 SS |
1220 | if (td->urb->actual_length != 0) { |
1221 | /* Don't overwrite a previously set error code */ | |
204970a4 SS |
1222 | if ((status == -EINPROGRESS || |
1223 | status == 0) && | |
1224 | (td->urb->transfer_flags | |
1225 | & URB_SHORT_NOT_OK)) | |
c92bcfa7 SS |
1226 | /* Did we already see a short data stage? */ |
1227 | status = -EREMOTEIO; | |
1228 | } else { | |
62889610 SS |
1229 | td->urb->actual_length = |
1230 | td->urb->transfer_buffer_length; | |
c92bcfa7 | 1231 | } |
d0e96f5a | 1232 | } else { |
ae636747 | 1233 | /* Maybe the event was for the data stage? */ |
66d1eebc | 1234 | if (trb_comp_code != COMP_STOP_INVAL) { |
ae636747 SS |
1235 | /* We didn't stop on a link TRB in the middle */ |
1236 | td->urb->actual_length = | |
1237 | td->urb->transfer_buffer_length - | |
1238 | TRB_LEN(event->transfer_len); | |
62889610 SS |
1239 | xhci_dbg(xhci, "Waiting for status stage event\n"); |
1240 | urb = NULL; | |
1241 | goto cleanup; | |
1242 | } | |
d0e96f5a SS |
1243 | } |
1244 | } | |
d0e96f5a | 1245 | } else { |
66d1eebc | 1246 | switch (trb_comp_code) { |
b10de142 SS |
1247 | case COMP_SUCCESS: |
1248 | /* Double check that the HW transferred everything. */ | |
1249 | if (event_trb != td->last_trb) { | |
1250 | xhci_warn(xhci, "WARN Successful completion " | |
1251 | "on short TX\n"); | |
1252 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1253 | status = -EREMOTEIO; | |
1254 | else | |
1255 | status = 0; | |
1256 | } else { | |
624defa1 SS |
1257 | if (usb_endpoint_xfer_bulk(&td->urb->ep->desc)) |
1258 | xhci_dbg(xhci, "Successful bulk " | |
1259 | "transfer!\n"); | |
1260 | else | |
1261 | xhci_dbg(xhci, "Successful interrupt " | |
1262 | "transfer!\n"); | |
b10de142 SS |
1263 | status = 0; |
1264 | } | |
1265 | break; | |
1266 | case COMP_SHORT_TX: | |
1267 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1268 | status = -EREMOTEIO; | |
1269 | else | |
1270 | status = 0; | |
1271 | break; | |
1272 | default: | |
1273 | /* Others already handled above */ | |
1274 | break; | |
1275 | } | |
1276 | dev_dbg(&td->urb->dev->dev, | |
1277 | "ep %#x - asked for %d bytes, " | |
1278 | "%d bytes untransferred\n", | |
1279 | td->urb->ep->desc.bEndpointAddress, | |
1280 | td->urb->transfer_buffer_length, | |
1281 | TRB_LEN(event->transfer_len)); | |
1282 | /* Fast path - was this the last TRB in the TD for this URB? */ | |
1283 | if (event_trb == td->last_trb) { | |
1284 | if (TRB_LEN(event->transfer_len) != 0) { | |
1285 | td->urb->actual_length = | |
1286 | td->urb->transfer_buffer_length - | |
1287 | TRB_LEN(event->transfer_len); | |
99eb32db SS |
1288 | if (td->urb->transfer_buffer_length < |
1289 | td->urb->actual_length) { | |
b10de142 SS |
1290 | xhci_warn(xhci, "HC gave bad length " |
1291 | "of %d bytes left\n", | |
1292 | TRB_LEN(event->transfer_len)); | |
1293 | td->urb->actual_length = 0; | |
2f697f6c SS |
1294 | if (td->urb->transfer_flags & |
1295 | URB_SHORT_NOT_OK) | |
1296 | status = -EREMOTEIO; | |
1297 | else | |
1298 | status = 0; | |
b10de142 | 1299 | } |
c92bcfa7 SS |
1300 | /* Don't overwrite a previously set error code */ |
1301 | if (status == -EINPROGRESS) { | |
1302 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1303 | status = -EREMOTEIO; | |
1304 | else | |
1305 | status = 0; | |
1306 | } | |
b10de142 SS |
1307 | } else { |
1308 | td->urb->actual_length = td->urb->transfer_buffer_length; | |
1309 | /* Ignore a short packet completion if the | |
1310 | * untransferred length was zero. | |
1311 | */ | |
c92bcfa7 SS |
1312 | if (status == -EREMOTEIO) |
1313 | status = 0; | |
b10de142 SS |
1314 | } |
1315 | } else { | |
ae636747 SS |
1316 | /* Slow path - walk the list, starting from the dequeue |
1317 | * pointer, to get the actual length transferred. | |
b10de142 | 1318 | */ |
ae636747 SS |
1319 | union xhci_trb *cur_trb; |
1320 | struct xhci_segment *cur_seg; | |
1321 | ||
b10de142 | 1322 | td->urb->actual_length = 0; |
ae636747 SS |
1323 | for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; |
1324 | cur_trb != event_trb; | |
1325 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
1326 | if (TRB_TYPE(cur_trb->generic.field[3]) != TRB_TR_NOOP && | |
1327 | TRB_TYPE(cur_trb->generic.field[3]) != TRB_LINK) | |
1328 | td->urb->actual_length += | |
1329 | TRB_LEN(cur_trb->generic.field[2]); | |
b10de142 | 1330 | } |
ae636747 SS |
1331 | /* If the ring didn't stop on a Link or No-op TRB, add |
1332 | * in the actual bytes transferred from the Normal TRB | |
1333 | */ | |
66d1eebc | 1334 | if (trb_comp_code != COMP_STOP_INVAL) |
ae636747 SS |
1335 | td->urb->actual_length += |
1336 | TRB_LEN(cur_trb->generic.field[2]) - | |
1337 | TRB_LEN(event->transfer_len); | |
b10de142 | 1338 | } |
d0e96f5a | 1339 | } |
66d1eebc SS |
1340 | if (trb_comp_code == COMP_STOP_INVAL || |
1341 | trb_comp_code == COMP_STOP) { | |
c92bcfa7 SS |
1342 | /* The Endpoint Stop Command completion will take care of any |
1343 | * stopped TDs. A stopped TD may be restarted, so don't update | |
1344 | * the ring dequeue pointer or take this TD off any lists yet. | |
1345 | */ | |
63a0d9ab SS |
1346 | ep->stopped_td = td; |
1347 | ep->stopped_trb = event_trb; | |
ae636747 | 1348 | } else { |
83fbcdcc SS |
1349 | if (trb_comp_code == COMP_STALL || |
1350 | trb_comp_code == COMP_BABBLE) { | |
c92bcfa7 SS |
1351 | /* The transfer is completed from the driver's |
1352 | * perspective, but we need to issue a set dequeue | |
1353 | * command for this stalled endpoint to move the dequeue | |
1354 | * pointer past the TD. We can't do that here because | |
1355 | * the halt condition must be cleared first. | |
1356 | */ | |
63a0d9ab SS |
1357 | ep->stopped_td = td; |
1358 | ep->stopped_trb = event_trb; | |
c92bcfa7 SS |
1359 | } else { |
1360 | /* Update ring dequeue pointer */ | |
1361 | while (ep_ring->dequeue != td->last_trb) | |
1362 | inc_deq(xhci, ep_ring, false); | |
ae636747 | 1363 | inc_deq(xhci, ep_ring, false); |
c92bcfa7 | 1364 | } |
b10de142 | 1365 | |
82d1009f | 1366 | td_cleanup: |
ae636747 SS |
1367 | /* Clean up the endpoint's TD list */ |
1368 | urb = td->urb; | |
99eb32db SS |
1369 | /* Do one last check of the actual transfer length. |
1370 | * If the host controller said we transferred more data than | |
1371 | * the buffer length, urb->actual_length will be a very big | |
1372 | * number (since it's unsigned). Play it safe and say we didn't | |
1373 | * transfer anything. | |
1374 | */ | |
1375 | if (urb->actual_length > urb->transfer_buffer_length) { | |
1376 | xhci_warn(xhci, "URB transfer length is wrong, " | |
1377 | "xHC issue? req. len = %u, " | |
1378 | "act. len = %u\n", | |
1379 | urb->transfer_buffer_length, | |
1380 | urb->actual_length); | |
1381 | urb->actual_length = 0; | |
2f697f6c SS |
1382 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
1383 | status = -EREMOTEIO; | |
1384 | else | |
1385 | status = 0; | |
99eb32db | 1386 | } |
ae636747 SS |
1387 | list_del(&td->td_list); |
1388 | /* Was this TD slated to be cancelled but completed anyway? */ | |
678539cf | 1389 | if (!list_empty(&td->cancelled_td_list)) |
ae636747 | 1390 | list_del(&td->cancelled_td_list); |
678539cf | 1391 | |
82d1009f SS |
1392 | /* Leave the TD around for the reset endpoint function to use |
1393 | * (but only if it's not a control endpoint, since we already | |
1394 | * queued the Set TR dequeue pointer command for stalled | |
1395 | * control endpoints). | |
1396 | */ | |
1397 | if (usb_endpoint_xfer_control(&urb->ep->desc) || | |
83fbcdcc SS |
1398 | (trb_comp_code != COMP_STALL && |
1399 | trb_comp_code != COMP_BABBLE)) { | |
c92bcfa7 SS |
1400 | kfree(td); |
1401 | } | |
ae636747 SS |
1402 | urb->hcpriv = NULL; |
1403 | } | |
d0e96f5a SS |
1404 | cleanup: |
1405 | inc_deq(xhci, xhci->event_ring, true); | |
23e3be11 | 1406 | xhci_set_hc_event_deq(xhci); |
d0e96f5a | 1407 | |
b10de142 | 1408 | /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */ |
d0e96f5a SS |
1409 | if (urb) { |
1410 | usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb); | |
66e49d87 | 1411 | xhci_dbg(xhci, "Giveback URB %p, len = %d, status = %d\n", |
9191eee7 | 1412 | urb, urb->actual_length, status); |
d0e96f5a SS |
1413 | spin_unlock(&xhci->lock); |
1414 | usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status); | |
1415 | spin_lock(&xhci->lock); | |
1416 | } | |
1417 | return 0; | |
1418 | } | |
1419 | ||
0f2a7930 SS |
1420 | /* |
1421 | * This function handles all OS-owned events on the event ring. It may drop | |
1422 | * xhci->lock between event processing (e.g. to pass up port status changes). | |
1423 | */ | |
b7258a4a | 1424 | void xhci_handle_event(struct xhci_hcd *xhci) |
7f84eef0 SS |
1425 | { |
1426 | union xhci_trb *event; | |
0f2a7930 | 1427 | int update_ptrs = 1; |
d0e96f5a | 1428 | int ret; |
7f84eef0 | 1429 | |
66e49d87 | 1430 | xhci_dbg(xhci, "In %s\n", __func__); |
7f84eef0 SS |
1431 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { |
1432 | xhci->error_bitmask |= 1 << 1; | |
1433 | return; | |
1434 | } | |
1435 | ||
1436 | event = xhci->event_ring->dequeue; | |
1437 | /* Does the HC or OS own the TRB? */ | |
1438 | if ((event->event_cmd.flags & TRB_CYCLE) != | |
1439 | xhci->event_ring->cycle_state) { | |
1440 | xhci->error_bitmask |= 1 << 2; | |
1441 | return; | |
1442 | } | |
66e49d87 | 1443 | xhci_dbg(xhci, "%s - OS owns TRB\n", __func__); |
7f84eef0 | 1444 | |
0f2a7930 | 1445 | /* FIXME: Handle more event types. */ |
7f84eef0 SS |
1446 | switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) { |
1447 | case TRB_TYPE(TRB_COMPLETION): | |
66e49d87 | 1448 | xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__); |
7f84eef0 | 1449 | handle_cmd_completion(xhci, &event->event_cmd); |
66e49d87 | 1450 | xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__); |
7f84eef0 | 1451 | break; |
0f2a7930 | 1452 | case TRB_TYPE(TRB_PORT_STATUS): |
66e49d87 | 1453 | xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__); |
0f2a7930 | 1454 | handle_port_status(xhci, event); |
66e49d87 | 1455 | xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__); |
0f2a7930 SS |
1456 | update_ptrs = 0; |
1457 | break; | |
d0e96f5a | 1458 | case TRB_TYPE(TRB_TRANSFER): |
66e49d87 | 1459 | xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__); |
d0e96f5a | 1460 | ret = handle_tx_event(xhci, &event->trans_event); |
66e49d87 | 1461 | xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__); |
d0e96f5a SS |
1462 | if (ret < 0) |
1463 | xhci->error_bitmask |= 1 << 9; | |
1464 | else | |
1465 | update_ptrs = 0; | |
1466 | break; | |
7f84eef0 SS |
1467 | default: |
1468 | xhci->error_bitmask |= 1 << 3; | |
1469 | } | |
6f5165cf SS |
1470 | /* Any of the above functions may drop and re-acquire the lock, so check |
1471 | * to make sure a watchdog timer didn't mark the host as non-responsive. | |
1472 | */ | |
1473 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
1474 | xhci_dbg(xhci, "xHCI host dying, returning from " | |
1475 | "event handler.\n"); | |
1476 | return; | |
1477 | } | |
7f84eef0 | 1478 | |
0f2a7930 SS |
1479 | if (update_ptrs) { |
1480 | /* Update SW and HC event ring dequeue pointer */ | |
1481 | inc_deq(xhci, xhci->event_ring, true); | |
23e3be11 | 1482 | xhci_set_hc_event_deq(xhci); |
0f2a7930 | 1483 | } |
7f84eef0 | 1484 | /* Are there more items on the event ring? */ |
b7258a4a | 1485 | xhci_handle_event(xhci); |
7f84eef0 SS |
1486 | } |
1487 | ||
d0e96f5a SS |
1488 | /**** Endpoint Ring Operations ****/ |
1489 | ||
7f84eef0 SS |
1490 | /* |
1491 | * Generic function for queueing a TRB on a ring. | |
1492 | * The caller must have checked to make sure there's room on the ring. | |
1493 | */ | |
1494 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
1495 | bool consumer, | |
1496 | u32 field1, u32 field2, u32 field3, u32 field4) | |
1497 | { | |
1498 | struct xhci_generic_trb *trb; | |
1499 | ||
1500 | trb = &ring->enqueue->generic; | |
1501 | trb->field[0] = field1; | |
1502 | trb->field[1] = field2; | |
1503 | trb->field[2] = field3; | |
1504 | trb->field[3] = field4; | |
1505 | inc_enq(xhci, ring, consumer); | |
1506 | } | |
1507 | ||
d0e96f5a SS |
1508 | /* |
1509 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. | |
1510 | * FIXME allocate segments if the ring is full. | |
1511 | */ | |
1512 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |
1513 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) | |
1514 | { | |
1515 | /* Make sure the endpoint has been added to xHC schedule */ | |
1516 | xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state); | |
1517 | switch (ep_state) { | |
1518 | case EP_STATE_DISABLED: | |
1519 | /* | |
1520 | * USB core changed config/interfaces without notifying us, | |
1521 | * or hardware is reporting the wrong state. | |
1522 | */ | |
1523 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); | |
1524 | return -ENOENT; | |
d0e96f5a | 1525 | case EP_STATE_ERROR: |
c92bcfa7 | 1526 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
d0e96f5a SS |
1527 | /* FIXME event handling code for error needs to clear it */ |
1528 | /* XXX not sure if this should be -ENOENT or not */ | |
1529 | return -EINVAL; | |
c92bcfa7 SS |
1530 | case EP_STATE_HALTED: |
1531 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); | |
d0e96f5a SS |
1532 | case EP_STATE_STOPPED: |
1533 | case EP_STATE_RUNNING: | |
1534 | break; | |
1535 | default: | |
1536 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); | |
1537 | /* | |
1538 | * FIXME issue Configure Endpoint command to try to get the HC | |
1539 | * back into a known state. | |
1540 | */ | |
1541 | return -EINVAL; | |
1542 | } | |
1543 | if (!room_on_ring(xhci, ep_ring, num_trbs)) { | |
1544 | /* FIXME allocate more room */ | |
1545 | xhci_err(xhci, "ERROR no room on ep ring\n"); | |
1546 | return -ENOMEM; | |
1547 | } | |
1548 | return 0; | |
1549 | } | |
1550 | ||
23e3be11 | 1551 | static int prepare_transfer(struct xhci_hcd *xhci, |
d0e96f5a SS |
1552 | struct xhci_virt_device *xdev, |
1553 | unsigned int ep_index, | |
1554 | unsigned int num_trbs, | |
1555 | struct urb *urb, | |
1556 | struct xhci_td **td, | |
1557 | gfp_t mem_flags) | |
1558 | { | |
1559 | int ret; | |
d115b048 | 1560 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
63a0d9ab | 1561 | ret = prepare_ring(xhci, xdev->eps[ep_index].ring, |
d115b048 | 1562 | ep_ctx->ep_info & EP_STATE_MASK, |
d0e96f5a SS |
1563 | num_trbs, mem_flags); |
1564 | if (ret) | |
1565 | return ret; | |
1566 | *td = kzalloc(sizeof(struct xhci_td), mem_flags); | |
1567 | if (!*td) | |
1568 | return -ENOMEM; | |
1569 | INIT_LIST_HEAD(&(*td)->td_list); | |
ae636747 | 1570 | INIT_LIST_HEAD(&(*td)->cancelled_td_list); |
d0e96f5a SS |
1571 | |
1572 | ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb); | |
1573 | if (unlikely(ret)) { | |
1574 | kfree(*td); | |
1575 | return ret; | |
1576 | } | |
1577 | ||
1578 | (*td)->urb = urb; | |
1579 | urb->hcpriv = (void *) (*td); | |
1580 | /* Add this TD to the tail of the endpoint ring's TD list */ | |
63a0d9ab SS |
1581 | list_add_tail(&(*td)->td_list, &xdev->eps[ep_index].ring->td_list); |
1582 | (*td)->start_seg = xdev->eps[ep_index].ring->enq_seg; | |
1583 | (*td)->first_trb = xdev->eps[ep_index].ring->enqueue; | |
d0e96f5a SS |
1584 | |
1585 | return 0; | |
1586 | } | |
1587 | ||
23e3be11 | 1588 | static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb) |
8a96c052 SS |
1589 | { |
1590 | int num_sgs, num_trbs, running_total, temp, i; | |
1591 | struct scatterlist *sg; | |
1592 | ||
1593 | sg = NULL; | |
1594 | num_sgs = urb->num_sgs; | |
1595 | temp = urb->transfer_buffer_length; | |
1596 | ||
1597 | xhci_dbg(xhci, "count sg list trbs: \n"); | |
1598 | num_trbs = 0; | |
1599 | for_each_sg(urb->sg->sg, sg, num_sgs, i) { | |
1600 | unsigned int previous_total_trbs = num_trbs; | |
1601 | unsigned int len = sg_dma_len(sg); | |
1602 | ||
1603 | /* Scatter gather list entries may cross 64KB boundaries */ | |
1604 | running_total = TRB_MAX_BUFF_SIZE - | |
1605 | (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
1606 | if (running_total != 0) | |
1607 | num_trbs++; | |
1608 | ||
1609 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
1610 | while (running_total < sg_dma_len(sg)) { | |
1611 | num_trbs++; | |
1612 | running_total += TRB_MAX_BUFF_SIZE; | |
1613 | } | |
700e2052 GKH |
1614 | xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n", |
1615 | i, (unsigned long long)sg_dma_address(sg), | |
1616 | len, len, num_trbs - previous_total_trbs); | |
8a96c052 SS |
1617 | |
1618 | len = min_t(int, len, temp); | |
1619 | temp -= len; | |
1620 | if (temp == 0) | |
1621 | break; | |
1622 | } | |
1623 | xhci_dbg(xhci, "\n"); | |
1624 | if (!in_interrupt()) | |
1625 | dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n", | |
1626 | urb->ep->desc.bEndpointAddress, | |
1627 | urb->transfer_buffer_length, | |
1628 | num_trbs); | |
1629 | return num_trbs; | |
1630 | } | |
1631 | ||
23e3be11 | 1632 | static void check_trb_math(struct urb *urb, int num_trbs, int running_total) |
8a96c052 SS |
1633 | { |
1634 | if (num_trbs != 0) | |
1635 | dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of " | |
1636 | "TRBs, %d left\n", __func__, | |
1637 | urb->ep->desc.bEndpointAddress, num_trbs); | |
1638 | if (running_total != urb->transfer_buffer_length) | |
1639 | dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " | |
1640 | "queued %#x (%d), asked for %#x (%d)\n", | |
1641 | __func__, | |
1642 | urb->ep->desc.bEndpointAddress, | |
1643 | running_total, running_total, | |
1644 | urb->transfer_buffer_length, | |
1645 | urb->transfer_buffer_length); | |
1646 | } | |
1647 | ||
23e3be11 | 1648 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
8a96c052 SS |
1649 | unsigned int ep_index, int start_cycle, |
1650 | struct xhci_generic_trb *start_trb, struct xhci_td *td) | |
1651 | { | |
8a96c052 SS |
1652 | /* |
1653 | * Pass all the TRBs to the hardware at once and make sure this write | |
1654 | * isn't reordered. | |
1655 | */ | |
1656 | wmb(); | |
1657 | start_trb->field[3] |= start_cycle; | |
ae636747 | 1658 | ring_ep_doorbell(xhci, slot_id, ep_index); |
8a96c052 SS |
1659 | } |
1660 | ||
624defa1 SS |
1661 | /* |
1662 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt | |
1663 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD | |
1664 | * (comprised of sg list entries) can take several service intervals to | |
1665 | * transmit. | |
1666 | */ | |
1667 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
1668 | struct urb *urb, int slot_id, unsigned int ep_index) | |
1669 | { | |
1670 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, | |
1671 | xhci->devs[slot_id]->out_ctx, ep_index); | |
1672 | int xhci_interval; | |
1673 | int ep_interval; | |
1674 | ||
1675 | xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info); | |
1676 | ep_interval = urb->interval; | |
1677 | /* Convert to microframes */ | |
1678 | if (urb->dev->speed == USB_SPEED_LOW || | |
1679 | urb->dev->speed == USB_SPEED_FULL) | |
1680 | ep_interval *= 8; | |
1681 | /* FIXME change this to a warning and a suggestion to use the new API | |
1682 | * to set the polling interval (once the API is added). | |
1683 | */ | |
1684 | if (xhci_interval != ep_interval) { | |
1685 | if (!printk_ratelimit()) | |
1686 | dev_dbg(&urb->dev->dev, "Driver uses different interval" | |
1687 | " (%d microframe%s) than xHCI " | |
1688 | "(%d microframe%s)\n", | |
1689 | ep_interval, | |
1690 | ep_interval == 1 ? "" : "s", | |
1691 | xhci_interval, | |
1692 | xhci_interval == 1 ? "" : "s"); | |
1693 | urb->interval = xhci_interval; | |
1694 | /* Convert back to frames for LS/FS devices */ | |
1695 | if (urb->dev->speed == USB_SPEED_LOW || | |
1696 | urb->dev->speed == USB_SPEED_FULL) | |
1697 | urb->interval /= 8; | |
1698 | } | |
1699 | return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index); | |
1700 | } | |
1701 | ||
23e3be11 | 1702 | static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
8a96c052 SS |
1703 | struct urb *urb, int slot_id, unsigned int ep_index) |
1704 | { | |
1705 | struct xhci_ring *ep_ring; | |
1706 | unsigned int num_trbs; | |
1707 | struct xhci_td *td; | |
1708 | struct scatterlist *sg; | |
1709 | int num_sgs; | |
1710 | int trb_buff_len, this_sg_len, running_total; | |
1711 | bool first_trb; | |
1712 | u64 addr; | |
1713 | ||
1714 | struct xhci_generic_trb *start_trb; | |
1715 | int start_cycle; | |
1716 | ||
63a0d9ab | 1717 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
8a96c052 SS |
1718 | num_trbs = count_sg_trbs_needed(xhci, urb); |
1719 | num_sgs = urb->num_sgs; | |
1720 | ||
23e3be11 | 1721 | trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id], |
8a96c052 SS |
1722 | ep_index, num_trbs, urb, &td, mem_flags); |
1723 | if (trb_buff_len < 0) | |
1724 | return trb_buff_len; | |
1725 | /* | |
1726 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
1727 | * until we've finished creating all the other TRBs. The ring's cycle | |
1728 | * state may change as we enqueue the other TRBs, so save it too. | |
1729 | */ | |
1730 | start_trb = &ep_ring->enqueue->generic; | |
1731 | start_cycle = ep_ring->cycle_state; | |
1732 | ||
1733 | running_total = 0; | |
1734 | /* | |
1735 | * How much data is in the first TRB? | |
1736 | * | |
1737 | * There are three forces at work for TRB buffer pointers and lengths: | |
1738 | * 1. We don't want to walk off the end of this sg-list entry buffer. | |
1739 | * 2. The transfer length that the driver requested may be smaller than | |
1740 | * the amount of memory allocated for this scatter-gather list. | |
1741 | * 3. TRBs buffers can't cross 64KB boundaries. | |
1742 | */ | |
1743 | sg = urb->sg->sg; | |
1744 | addr = (u64) sg_dma_address(sg); | |
1745 | this_sg_len = sg_dma_len(sg); | |
1746 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
1747 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
1748 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); | |
1749 | if (trb_buff_len > urb->transfer_buffer_length) | |
1750 | trb_buff_len = urb->transfer_buffer_length; | |
1751 | xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n", | |
1752 | trb_buff_len); | |
1753 | ||
1754 | first_trb = true; | |
1755 | /* Queue the first TRB, even if it's zero-length */ | |
1756 | do { | |
1757 | u32 field = 0; | |
f9dc68fe | 1758 | u32 length_field = 0; |
8a96c052 SS |
1759 | |
1760 | /* Don't change the cycle bit of the first TRB until later */ | |
1761 | if (first_trb) | |
1762 | first_trb = false; | |
1763 | else | |
1764 | field |= ep_ring->cycle_state; | |
1765 | ||
1766 | /* Chain all the TRBs together; clear the chain bit in the last | |
1767 | * TRB to indicate it's the last TRB in the chain. | |
1768 | */ | |
1769 | if (num_trbs > 1) { | |
1770 | field |= TRB_CHAIN; | |
1771 | } else { | |
1772 | /* FIXME - add check for ZERO_PACKET flag before this */ | |
1773 | td->last_trb = ep_ring->enqueue; | |
1774 | field |= TRB_IOC; | |
1775 | } | |
1776 | xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), " | |
1777 | "64KB boundary at %#x, end dma = %#x\n", | |
1778 | (unsigned int) addr, trb_buff_len, trb_buff_len, | |
1779 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), | |
1780 | (unsigned int) addr + trb_buff_len); | |
1781 | if (TRB_MAX_BUFF_SIZE - | |
1782 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) { | |
1783 | xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n"); | |
1784 | xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n", | |
1785 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), | |
1786 | (unsigned int) addr + trb_buff_len); | |
1787 | } | |
f9dc68fe SS |
1788 | length_field = TRB_LEN(trb_buff_len) | |
1789 | TD_REMAINDER(urb->transfer_buffer_length - running_total) | | |
1790 | TRB_INTR_TARGET(0); | |
8a96c052 | 1791 | queue_trb(xhci, ep_ring, false, |
8e595a5d SS |
1792 | lower_32_bits(addr), |
1793 | upper_32_bits(addr), | |
f9dc68fe | 1794 | length_field, |
8a96c052 SS |
1795 | /* We always want to know if the TRB was short, |
1796 | * or we won't get an event when it completes. | |
1797 | * (Unless we use event data TRBs, which are a | |
1798 | * waste of space and HC resources.) | |
1799 | */ | |
1800 | field | TRB_ISP | TRB_TYPE(TRB_NORMAL)); | |
1801 | --num_trbs; | |
1802 | running_total += trb_buff_len; | |
1803 | ||
1804 | /* Calculate length for next transfer -- | |
1805 | * Are we done queueing all the TRBs for this sg entry? | |
1806 | */ | |
1807 | this_sg_len -= trb_buff_len; | |
1808 | if (this_sg_len == 0) { | |
1809 | --num_sgs; | |
1810 | if (num_sgs == 0) | |
1811 | break; | |
1812 | sg = sg_next(sg); | |
1813 | addr = (u64) sg_dma_address(sg); | |
1814 | this_sg_len = sg_dma_len(sg); | |
1815 | } else { | |
1816 | addr += trb_buff_len; | |
1817 | } | |
1818 | ||
1819 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
1820 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
1821 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); | |
1822 | if (running_total + trb_buff_len > urb->transfer_buffer_length) | |
1823 | trb_buff_len = | |
1824 | urb->transfer_buffer_length - running_total; | |
1825 | } while (running_total < urb->transfer_buffer_length); | |
1826 | ||
1827 | check_trb_math(urb, num_trbs, running_total); | |
1828 | giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td); | |
1829 | return 0; | |
1830 | } | |
1831 | ||
b10de142 | 1832 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
23e3be11 | 1833 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
b10de142 SS |
1834 | struct urb *urb, int slot_id, unsigned int ep_index) |
1835 | { | |
1836 | struct xhci_ring *ep_ring; | |
1837 | struct xhci_td *td; | |
1838 | int num_trbs; | |
1839 | struct xhci_generic_trb *start_trb; | |
1840 | bool first_trb; | |
1841 | int start_cycle; | |
f9dc68fe | 1842 | u32 field, length_field; |
b10de142 SS |
1843 | |
1844 | int running_total, trb_buff_len, ret; | |
1845 | u64 addr; | |
1846 | ||
8a96c052 SS |
1847 | if (urb->sg) |
1848 | return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index); | |
1849 | ||
63a0d9ab | 1850 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
b10de142 SS |
1851 | |
1852 | num_trbs = 0; | |
1853 | /* How much data is (potentially) left before the 64KB boundary? */ | |
1854 | running_total = TRB_MAX_BUFF_SIZE - | |
1855 | (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
1856 | ||
1857 | /* If there's some data on this 64KB chunk, or we have to send a | |
1858 | * zero-length transfer, we need at least one TRB | |
1859 | */ | |
1860 | if (running_total != 0 || urb->transfer_buffer_length == 0) | |
1861 | num_trbs++; | |
1862 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
1863 | while (running_total < urb->transfer_buffer_length) { | |
1864 | num_trbs++; | |
1865 | running_total += TRB_MAX_BUFF_SIZE; | |
1866 | } | |
1867 | /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */ | |
1868 | ||
1869 | if (!in_interrupt()) | |
700e2052 | 1870 | dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n", |
b10de142 | 1871 | urb->ep->desc.bEndpointAddress, |
8a96c052 SS |
1872 | urb->transfer_buffer_length, |
1873 | urb->transfer_buffer_length, | |
700e2052 | 1874 | (unsigned long long)urb->transfer_dma, |
b10de142 | 1875 | num_trbs); |
8a96c052 | 1876 | |
23e3be11 | 1877 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, |
b10de142 SS |
1878 | num_trbs, urb, &td, mem_flags); |
1879 | if (ret < 0) | |
1880 | return ret; | |
1881 | ||
1882 | /* | |
1883 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
1884 | * until we've finished creating all the other TRBs. The ring's cycle | |
1885 | * state may change as we enqueue the other TRBs, so save it too. | |
1886 | */ | |
1887 | start_trb = &ep_ring->enqueue->generic; | |
1888 | start_cycle = ep_ring->cycle_state; | |
1889 | ||
1890 | running_total = 0; | |
1891 | /* How much data is in the first TRB? */ | |
1892 | addr = (u64) urb->transfer_dma; | |
1893 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
1894 | (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
1895 | if (urb->transfer_buffer_length < trb_buff_len) | |
1896 | trb_buff_len = urb->transfer_buffer_length; | |
1897 | ||
1898 | first_trb = true; | |
1899 | ||
1900 | /* Queue the first TRB, even if it's zero-length */ | |
1901 | do { | |
1902 | field = 0; | |
1903 | ||
1904 | /* Don't change the cycle bit of the first TRB until later */ | |
1905 | if (first_trb) | |
1906 | first_trb = false; | |
1907 | else | |
1908 | field |= ep_ring->cycle_state; | |
1909 | ||
1910 | /* Chain all the TRBs together; clear the chain bit in the last | |
1911 | * TRB to indicate it's the last TRB in the chain. | |
1912 | */ | |
1913 | if (num_trbs > 1) { | |
1914 | field |= TRB_CHAIN; | |
1915 | } else { | |
1916 | /* FIXME - add check for ZERO_PACKET flag before this */ | |
1917 | td->last_trb = ep_ring->enqueue; | |
1918 | field |= TRB_IOC; | |
1919 | } | |
f9dc68fe SS |
1920 | length_field = TRB_LEN(trb_buff_len) | |
1921 | TD_REMAINDER(urb->transfer_buffer_length - running_total) | | |
1922 | TRB_INTR_TARGET(0); | |
b10de142 | 1923 | queue_trb(xhci, ep_ring, false, |
8e595a5d SS |
1924 | lower_32_bits(addr), |
1925 | upper_32_bits(addr), | |
f9dc68fe | 1926 | length_field, |
b10de142 SS |
1927 | /* We always want to know if the TRB was short, |
1928 | * or we won't get an event when it completes. | |
1929 | * (Unless we use event data TRBs, which are a | |
1930 | * waste of space and HC resources.) | |
1931 | */ | |
1932 | field | TRB_ISP | TRB_TYPE(TRB_NORMAL)); | |
1933 | --num_trbs; | |
1934 | running_total += trb_buff_len; | |
1935 | ||
1936 | /* Calculate length for next transfer */ | |
1937 | addr += trb_buff_len; | |
1938 | trb_buff_len = urb->transfer_buffer_length - running_total; | |
1939 | if (trb_buff_len > TRB_MAX_BUFF_SIZE) | |
1940 | trb_buff_len = TRB_MAX_BUFF_SIZE; | |
1941 | } while (running_total < urb->transfer_buffer_length); | |
1942 | ||
8a96c052 SS |
1943 | check_trb_math(urb, num_trbs, running_total); |
1944 | giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td); | |
b10de142 SS |
1945 | return 0; |
1946 | } | |
1947 | ||
d0e96f5a | 1948 | /* Caller must have locked xhci->lock */ |
23e3be11 | 1949 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
d0e96f5a SS |
1950 | struct urb *urb, int slot_id, unsigned int ep_index) |
1951 | { | |
1952 | struct xhci_ring *ep_ring; | |
1953 | int num_trbs; | |
1954 | int ret; | |
1955 | struct usb_ctrlrequest *setup; | |
1956 | struct xhci_generic_trb *start_trb; | |
1957 | int start_cycle; | |
f9dc68fe | 1958 | u32 field, length_field; |
d0e96f5a SS |
1959 | struct xhci_td *td; |
1960 | ||
63a0d9ab | 1961 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
d0e96f5a SS |
1962 | |
1963 | /* | |
1964 | * Need to copy setup packet into setup TRB, so we can't use the setup | |
1965 | * DMA address. | |
1966 | */ | |
1967 | if (!urb->setup_packet) | |
1968 | return -EINVAL; | |
1969 | ||
1970 | if (!in_interrupt()) | |
1971 | xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n", | |
1972 | slot_id, ep_index); | |
1973 | /* 1 TRB for setup, 1 for status */ | |
1974 | num_trbs = 2; | |
1975 | /* | |
1976 | * Don't need to check if we need additional event data and normal TRBs, | |
1977 | * since data in control transfers will never get bigger than 16MB | |
1978 | * XXX: can we get a buffer that crosses 64KB boundaries? | |
1979 | */ | |
1980 | if (urb->transfer_buffer_length > 0) | |
1981 | num_trbs++; | |
23e3be11 | 1982 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, num_trbs, |
d0e96f5a SS |
1983 | urb, &td, mem_flags); |
1984 | if (ret < 0) | |
1985 | return ret; | |
1986 | ||
1987 | /* | |
1988 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
1989 | * until we've finished creating all the other TRBs. The ring's cycle | |
1990 | * state may change as we enqueue the other TRBs, so save it too. | |
1991 | */ | |
1992 | start_trb = &ep_ring->enqueue->generic; | |
1993 | start_cycle = ep_ring->cycle_state; | |
1994 | ||
1995 | /* Queue setup TRB - see section 6.4.1.2.1 */ | |
1996 | /* FIXME better way to translate setup_packet into two u32 fields? */ | |
1997 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | |
1998 | queue_trb(xhci, ep_ring, false, | |
1999 | /* FIXME endianness is probably going to bite my ass here. */ | |
2000 | setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16, | |
2001 | setup->wIndex | setup->wLength << 16, | |
2002 | TRB_LEN(8) | TRB_INTR_TARGET(0), | |
2003 | /* Immediate data in pointer */ | |
2004 | TRB_IDT | TRB_TYPE(TRB_SETUP)); | |
2005 | ||
2006 | /* If there's data, queue data TRBs */ | |
2007 | field = 0; | |
f9dc68fe SS |
2008 | length_field = TRB_LEN(urb->transfer_buffer_length) | |
2009 | TD_REMAINDER(urb->transfer_buffer_length) | | |
2010 | TRB_INTR_TARGET(0); | |
d0e96f5a SS |
2011 | if (urb->transfer_buffer_length > 0) { |
2012 | if (setup->bRequestType & USB_DIR_IN) | |
2013 | field |= TRB_DIR_IN; | |
2014 | queue_trb(xhci, ep_ring, false, | |
2015 | lower_32_bits(urb->transfer_dma), | |
2016 | upper_32_bits(urb->transfer_dma), | |
f9dc68fe | 2017 | length_field, |
d0e96f5a SS |
2018 | /* Event on short tx */ |
2019 | field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state); | |
2020 | } | |
2021 | ||
2022 | /* Save the DMA address of the last TRB in the TD */ | |
2023 | td->last_trb = ep_ring->enqueue; | |
2024 | ||
2025 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ | |
2026 | /* If the device sent data, the status stage is an OUT transfer */ | |
2027 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) | |
2028 | field = 0; | |
2029 | else | |
2030 | field = TRB_DIR_IN; | |
2031 | queue_trb(xhci, ep_ring, false, | |
2032 | 0, | |
2033 | 0, | |
2034 | TRB_INTR_TARGET(0), | |
2035 | /* Event on completion */ | |
2036 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | |
2037 | ||
8a96c052 | 2038 | giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td); |
d0e96f5a SS |
2039 | return 0; |
2040 | } | |
2041 | ||
2042 | /**** Command Ring Operations ****/ | |
2043 | ||
913a8a34 SS |
2044 | /* Generic function for queueing a command TRB on the command ring. |
2045 | * Check to make sure there's room on the command ring for one command TRB. | |
2046 | * Also check that there's room reserved for commands that must not fail. | |
2047 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, | |
2048 | * then only check for the number of reserved spots. | |
2049 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB | |
2050 | * because the command event handler may want to resubmit a failed command. | |
2051 | */ | |
2052 | static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2, | |
2053 | u32 field3, u32 field4, bool command_must_succeed) | |
7f84eef0 | 2054 | { |
913a8a34 SS |
2055 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
2056 | if (!command_must_succeed) | |
2057 | reserved_trbs++; | |
2058 | ||
2059 | if (!room_on_ring(xhci, xhci->cmd_ring, reserved_trbs)) { | |
7f84eef0 SS |
2060 | if (!in_interrupt()) |
2061 | xhci_err(xhci, "ERR: No room for command on command ring\n"); | |
913a8a34 SS |
2062 | if (command_must_succeed) |
2063 | xhci_err(xhci, "ERR: Reserved TRB counting for " | |
2064 | "unfailable commands failed.\n"); | |
7f84eef0 SS |
2065 | return -ENOMEM; |
2066 | } | |
2067 | queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, | |
2068 | field4 | xhci->cmd_ring->cycle_state); | |
2069 | return 0; | |
2070 | } | |
2071 | ||
2072 | /* Queue a no-op command on the command ring */ | |
2073 | static int queue_cmd_noop(struct xhci_hcd *xhci) | |
2074 | { | |
913a8a34 | 2075 | return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false); |
7f84eef0 SS |
2076 | } |
2077 | ||
2078 | /* | |
2079 | * Place a no-op command on the command ring to test the command and | |
2080 | * event ring. | |
2081 | */ | |
23e3be11 | 2082 | void *xhci_setup_one_noop(struct xhci_hcd *xhci) |
7f84eef0 SS |
2083 | { |
2084 | if (queue_cmd_noop(xhci) < 0) | |
2085 | return NULL; | |
2086 | xhci->noops_submitted++; | |
23e3be11 | 2087 | return xhci_ring_cmd_db; |
7f84eef0 | 2088 | } |
3ffbba95 SS |
2089 | |
2090 | /* Queue a slot enable or disable request on the command ring */ | |
23e3be11 | 2091 | int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id) |
3ffbba95 SS |
2092 | { |
2093 | return queue_command(xhci, 0, 0, 0, | |
913a8a34 | 2094 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
3ffbba95 SS |
2095 | } |
2096 | ||
2097 | /* Queue an address device command TRB */ | |
23e3be11 SS |
2098 | int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
2099 | u32 slot_id) | |
3ffbba95 | 2100 | { |
8e595a5d SS |
2101 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
2102 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 SS |
2103 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id), |
2104 | false); | |
3ffbba95 | 2105 | } |
f94e0186 SS |
2106 | |
2107 | /* Queue a configure endpoint command TRB */ | |
23e3be11 | 2108 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
913a8a34 | 2109 | u32 slot_id, bool command_must_succeed) |
f94e0186 | 2110 | { |
8e595a5d SS |
2111 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
2112 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 SS |
2113 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
2114 | command_must_succeed); | |
f94e0186 | 2115 | } |
ae636747 | 2116 | |
f2217e8e SS |
2117 | /* Queue an evaluate context command TRB */ |
2118 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, | |
2119 | u32 slot_id) | |
2120 | { | |
2121 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), | |
2122 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 SS |
2123 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
2124 | false); | |
f2217e8e SS |
2125 | } |
2126 | ||
23e3be11 | 2127 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, |
ae636747 SS |
2128 | unsigned int ep_index) |
2129 | { | |
2130 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
2131 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
2132 | u32 type = TRB_TYPE(TRB_STOP_RING); | |
2133 | ||
2134 | return queue_command(xhci, 0, 0, 0, | |
913a8a34 | 2135 | trb_slot_id | trb_ep_index | type, false); |
ae636747 SS |
2136 | } |
2137 | ||
2138 | /* Set Transfer Ring Dequeue Pointer command. | |
2139 | * This should not be used for endpoints that have streams enabled. | |
2140 | */ | |
2141 | static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, | |
2142 | unsigned int ep_index, struct xhci_segment *deq_seg, | |
2143 | union xhci_trb *deq_ptr, u32 cycle_state) | |
2144 | { | |
2145 | dma_addr_t addr; | |
2146 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
2147 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
2148 | u32 type = TRB_TYPE(TRB_SET_DEQ); | |
2149 | ||
23e3be11 | 2150 | addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr); |
c92bcfa7 | 2151 | if (addr == 0) { |
ae636747 | 2152 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
700e2052 GKH |
2153 | xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", |
2154 | deq_seg, deq_ptr); | |
c92bcfa7 SS |
2155 | return 0; |
2156 | } | |
8e595a5d SS |
2157 | return queue_command(xhci, lower_32_bits(addr) | cycle_state, |
2158 | upper_32_bits(addr), 0, | |
913a8a34 | 2159 | trb_slot_id | trb_ep_index | type, false); |
ae636747 | 2160 | } |
a1587d97 SS |
2161 | |
2162 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, | |
2163 | unsigned int ep_index) | |
2164 | { | |
2165 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
2166 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
2167 | u32 type = TRB_TYPE(TRB_RESET_EP); | |
2168 | ||
913a8a34 SS |
2169 | return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type, |
2170 | false); | |
a1587d97 | 2171 | } |