Commit | Line | Data |
---|---|---|
66d4eadd SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
43b86af8 | 23 | #include <linux/pci.h> |
66d4eadd | 24 | #include <linux/irq.h> |
8df75f42 | 25 | #include <linux/log2.h> |
66d4eadd | 26 | #include <linux/module.h> |
b0567b3f | 27 | #include <linux/moduleparam.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
71c731a2 | 29 | #include <linux/dmi.h> |
008eb957 | 30 | #include <linux/dma-mapping.h> |
66d4eadd SS |
31 | |
32 | #include "xhci.h" | |
84a99f6f | 33 | #include "xhci-trace.h" |
66d4eadd SS |
34 | |
35 | #define DRIVER_AUTHOR "Sarah Sharp" | |
36 | #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver" | |
37 | ||
b0567b3f SS |
38 | /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */ |
39 | static int link_quirk; | |
40 | module_param(link_quirk, int, S_IRUGO | S_IWUSR); | |
41 | MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB"); | |
42 | ||
4e6a1ee7 TI |
43 | static unsigned int quirks; |
44 | module_param(quirks, uint, S_IRUGO); | |
45 | MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default"); | |
46 | ||
66d4eadd SS |
47 | /* TODO: copied from ehci-hcd.c - can this be refactored? */ |
48 | /* | |
2611bd18 | 49 | * xhci_handshake - spin reading hc until handshake completes or fails |
66d4eadd SS |
50 | * @ptr: address of hc register to be read |
51 | * @mask: bits to look at in result of read | |
52 | * @done: value of those bits when handshake succeeds | |
53 | * @usec: timeout in microseconds | |
54 | * | |
55 | * Returns negative errno, or zero on success | |
56 | * | |
57 | * Success happens when the "mask" bits have the specified value (hardware | |
58 | * handshake done). There are two failure modes: "usec" have passed (major | |
59 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
60 | */ | |
2611bd18 | 61 | int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr, |
66d4eadd SS |
62 | u32 mask, u32 done, int usec) |
63 | { | |
64 | u32 result; | |
65 | ||
66 | do { | |
b0ba9720 | 67 | result = readl(ptr); |
66d4eadd SS |
68 | if (result == ~(u32)0) /* card removed */ |
69 | return -ENODEV; | |
70 | result &= mask; | |
71 | if (result == done) | |
72 | return 0; | |
73 | udelay(1); | |
74 | usec--; | |
75 | } while (usec > 0); | |
76 | return -ETIMEDOUT; | |
77 | } | |
78 | ||
79 | /* | |
4f0f0bae | 80 | * Disable interrupts and begin the xHCI halting process. |
66d4eadd | 81 | */ |
4f0f0bae | 82 | void xhci_quiesce(struct xhci_hcd *xhci) |
66d4eadd SS |
83 | { |
84 | u32 halted; | |
85 | u32 cmd; | |
86 | u32 mask; | |
87 | ||
66d4eadd | 88 | mask = ~(XHCI_IRQS); |
b0ba9720 | 89 | halted = readl(&xhci->op_regs->status) & STS_HALT; |
66d4eadd SS |
90 | if (!halted) |
91 | mask &= ~CMD_RUN; | |
92 | ||
b0ba9720 | 93 | cmd = readl(&xhci->op_regs->command); |
66d4eadd | 94 | cmd &= mask; |
204b7793 | 95 | writel(cmd, &xhci->op_regs->command); |
4f0f0bae SS |
96 | } |
97 | ||
98 | /* | |
99 | * Force HC into halt state. | |
100 | * | |
101 | * Disable any IRQs and clear the run/stop bit. | |
102 | * HC will complete any current and actively pipelined transactions, and | |
bdfca502 | 103 | * should halt within 16 ms of the run/stop bit being cleared. |
4f0f0bae | 104 | * Read HC Halted bit in the status register to see when the HC is finished. |
4f0f0bae SS |
105 | */ |
106 | int xhci_halt(struct xhci_hcd *xhci) | |
107 | { | |
c6cc27c7 | 108 | int ret; |
d195fcff | 109 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC"); |
4f0f0bae | 110 | xhci_quiesce(xhci); |
66d4eadd | 111 | |
2611bd18 | 112 | ret = xhci_handshake(xhci, &xhci->op_regs->status, |
66d4eadd | 113 | STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); |
c181bc5b | 114 | if (!ret) { |
c6cc27c7 | 115 | xhci->xhc_state |= XHCI_STATE_HALTED; |
c181bc5b EF |
116 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; |
117 | } else | |
5af98bb0 SS |
118 | xhci_warn(xhci, "Host not halted after %u microseconds.\n", |
119 | XHCI_MAX_HALT_USEC); | |
c6cc27c7 | 120 | return ret; |
66d4eadd SS |
121 | } |
122 | ||
ed07453f SS |
123 | /* |
124 | * Set the run bit and wait for the host to be running. | |
125 | */ | |
8212a49d | 126 | static int xhci_start(struct xhci_hcd *xhci) |
ed07453f SS |
127 | { |
128 | u32 temp; | |
129 | int ret; | |
130 | ||
b0ba9720 | 131 | temp = readl(&xhci->op_regs->command); |
ed07453f | 132 | temp |= (CMD_RUN); |
d195fcff | 133 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.", |
ed07453f | 134 | temp); |
204b7793 | 135 | writel(temp, &xhci->op_regs->command); |
ed07453f SS |
136 | |
137 | /* | |
138 | * Wait for the HCHalted Status bit to be 0 to indicate the host is | |
139 | * running. | |
140 | */ | |
2611bd18 | 141 | ret = xhci_handshake(xhci, &xhci->op_regs->status, |
ed07453f SS |
142 | STS_HALT, 0, XHCI_MAX_HALT_USEC); |
143 | if (ret == -ETIMEDOUT) | |
144 | xhci_err(xhci, "Host took too long to start, " | |
145 | "waited %u microseconds.\n", | |
146 | XHCI_MAX_HALT_USEC); | |
c6cc27c7 SS |
147 | if (!ret) |
148 | xhci->xhc_state &= ~XHCI_STATE_HALTED; | |
ed07453f SS |
149 | return ret; |
150 | } | |
151 | ||
66d4eadd | 152 | /* |
ac04e6ff | 153 | * Reset a halted HC. |
66d4eadd SS |
154 | * |
155 | * This resets pipelines, timers, counters, state machines, etc. | |
156 | * Transactions will be terminated immediately, and operational registers | |
157 | * will be set to their defaults. | |
158 | */ | |
159 | int xhci_reset(struct xhci_hcd *xhci) | |
160 | { | |
161 | u32 command; | |
162 | u32 state; | |
f370b996 | 163 | int ret, i; |
66d4eadd | 164 | |
b0ba9720 | 165 | state = readl(&xhci->op_regs->status); |
d3512f63 SS |
166 | if ((state & STS_HALT) == 0) { |
167 | xhci_warn(xhci, "Host controller not halted, aborting reset.\n"); | |
168 | return 0; | |
169 | } | |
66d4eadd | 170 | |
d195fcff | 171 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC"); |
b0ba9720 | 172 | command = readl(&xhci->op_regs->command); |
66d4eadd | 173 | command |= CMD_RESET; |
204b7793 | 174 | writel(command, &xhci->op_regs->command); |
66d4eadd | 175 | |
2611bd18 | 176 | ret = xhci_handshake(xhci, &xhci->op_regs->command, |
22ceac19 | 177 | CMD_RESET, 0, 10 * 1000 * 1000); |
2d62f3ee SS |
178 | if (ret) |
179 | return ret; | |
180 | ||
d195fcff XR |
181 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
182 | "Wait for controller to be ready for doorbell rings"); | |
2d62f3ee SS |
183 | /* |
184 | * xHCI cannot write to any doorbells or operational registers other | |
185 | * than status until the "Controller Not Ready" flag is cleared. | |
186 | */ | |
2611bd18 | 187 | ret = xhci_handshake(xhci, &xhci->op_regs->status, |
22ceac19 | 188 | STS_CNR, 0, 10 * 1000 * 1000); |
f370b996 AX |
189 | |
190 | for (i = 0; i < 2; ++i) { | |
191 | xhci->bus_state[i].port_c_suspend = 0; | |
192 | xhci->bus_state[i].suspended_ports = 0; | |
193 | xhci->bus_state[i].resuming_ports = 0; | |
194 | } | |
195 | ||
196 | return ret; | |
66d4eadd SS |
197 | } |
198 | ||
421aa841 SAS |
199 | #ifdef CONFIG_PCI |
200 | static int xhci_free_msi(struct xhci_hcd *xhci) | |
43b86af8 DN |
201 | { |
202 | int i; | |
43b86af8 | 203 | |
421aa841 SAS |
204 | if (!xhci->msix_entries) |
205 | return -EINVAL; | |
43b86af8 | 206 | |
421aa841 SAS |
207 | for (i = 0; i < xhci->msix_count; i++) |
208 | if (xhci->msix_entries[i].vector) | |
209 | free_irq(xhci->msix_entries[i].vector, | |
210 | xhci_to_hcd(xhci)); | |
211 | return 0; | |
43b86af8 DN |
212 | } |
213 | ||
214 | /* | |
215 | * Set up MSI | |
216 | */ | |
217 | static int xhci_setup_msi(struct xhci_hcd *xhci) | |
66d4eadd SS |
218 | { |
219 | int ret; | |
43b86af8 DN |
220 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); |
221 | ||
222 | ret = pci_enable_msi(pdev); | |
223 | if (ret) { | |
d195fcff XR |
224 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
225 | "failed to allocate MSI entry"); | |
43b86af8 DN |
226 | return ret; |
227 | } | |
228 | ||
851ec164 | 229 | ret = request_irq(pdev->irq, xhci_msi_irq, |
43b86af8 DN |
230 | 0, "xhci_hcd", xhci_to_hcd(xhci)); |
231 | if (ret) { | |
d195fcff XR |
232 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
233 | "disable MSI interrupt"); | |
43b86af8 DN |
234 | pci_disable_msi(pdev); |
235 | } | |
236 | ||
237 | return ret; | |
238 | } | |
239 | ||
421aa841 SAS |
240 | /* |
241 | * Free IRQs | |
242 | * free all IRQs request | |
243 | */ | |
244 | static void xhci_free_irq(struct xhci_hcd *xhci) | |
245 | { | |
246 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
247 | int ret; | |
248 | ||
249 | /* return if using legacy interrupt */ | |
cd70469d | 250 | if (xhci_to_hcd(xhci)->irq > 0) |
421aa841 SAS |
251 | return; |
252 | ||
253 | ret = xhci_free_msi(xhci); | |
254 | if (!ret) | |
255 | return; | |
cd70469d | 256 | if (pdev->irq > 0) |
421aa841 SAS |
257 | free_irq(pdev->irq, xhci_to_hcd(xhci)); |
258 | ||
259 | return; | |
260 | } | |
261 | ||
43b86af8 DN |
262 | /* |
263 | * Set up MSI-X | |
264 | */ | |
265 | static int xhci_setup_msix(struct xhci_hcd *xhci) | |
266 | { | |
267 | int i, ret = 0; | |
0029227f AX |
268 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
269 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
66d4eadd | 270 | |
43b86af8 DN |
271 | /* |
272 | * calculate number of msi-x vectors supported. | |
273 | * - HCS_MAX_INTRS: the max number of interrupts the host can handle, | |
274 | * with max number of interrupters based on the xhci HCSPARAMS1. | |
275 | * - num_online_cpus: maximum msi-x vectors per CPUs core. | |
276 | * Add additional 1 vector to ensure always available interrupt. | |
277 | */ | |
278 | xhci->msix_count = min(num_online_cpus() + 1, | |
279 | HCS_MAX_INTRS(xhci->hcs_params1)); | |
280 | ||
281 | xhci->msix_entries = | |
282 | kmalloc((sizeof(struct msix_entry))*xhci->msix_count, | |
86871975 | 283 | GFP_KERNEL); |
66d4eadd SS |
284 | if (!xhci->msix_entries) { |
285 | xhci_err(xhci, "Failed to allocate MSI-X entries\n"); | |
286 | return -ENOMEM; | |
287 | } | |
43b86af8 DN |
288 | |
289 | for (i = 0; i < xhci->msix_count; i++) { | |
290 | xhci->msix_entries[i].entry = i; | |
291 | xhci->msix_entries[i].vector = 0; | |
292 | } | |
66d4eadd SS |
293 | |
294 | ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count); | |
295 | if (ret) { | |
d195fcff XR |
296 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
297 | "Failed to enable MSI-X"); | |
66d4eadd SS |
298 | goto free_entries; |
299 | } | |
300 | ||
43b86af8 DN |
301 | for (i = 0; i < xhci->msix_count; i++) { |
302 | ret = request_irq(xhci->msix_entries[i].vector, | |
851ec164 | 303 | xhci_msi_irq, |
43b86af8 DN |
304 | 0, "xhci_hcd", xhci_to_hcd(xhci)); |
305 | if (ret) | |
306 | goto disable_msix; | |
66d4eadd | 307 | } |
43b86af8 | 308 | |
0029227f | 309 | hcd->msix_enabled = 1; |
43b86af8 | 310 | return ret; |
66d4eadd SS |
311 | |
312 | disable_msix: | |
d195fcff | 313 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt"); |
43b86af8 | 314 | xhci_free_irq(xhci); |
66d4eadd SS |
315 | pci_disable_msix(pdev); |
316 | free_entries: | |
317 | kfree(xhci->msix_entries); | |
318 | xhci->msix_entries = NULL; | |
319 | return ret; | |
320 | } | |
321 | ||
66d4eadd SS |
322 | /* Free any IRQs and disable MSI-X */ |
323 | static void xhci_cleanup_msix(struct xhci_hcd *xhci) | |
324 | { | |
0029227f AX |
325 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
326 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
66d4eadd | 327 | |
9005355a JP |
328 | if (xhci->quirks & XHCI_PLAT) |
329 | return; | |
330 | ||
43b86af8 DN |
331 | xhci_free_irq(xhci); |
332 | ||
333 | if (xhci->msix_entries) { | |
334 | pci_disable_msix(pdev); | |
335 | kfree(xhci->msix_entries); | |
336 | xhci->msix_entries = NULL; | |
337 | } else { | |
338 | pci_disable_msi(pdev); | |
339 | } | |
340 | ||
0029227f | 341 | hcd->msix_enabled = 0; |
43b86af8 | 342 | return; |
66d4eadd | 343 | } |
66d4eadd | 344 | |
d5c82feb | 345 | static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci) |
421aa841 SAS |
346 | { |
347 | int i; | |
348 | ||
349 | if (xhci->msix_entries) { | |
350 | for (i = 0; i < xhci->msix_count; i++) | |
351 | synchronize_irq(xhci->msix_entries[i].vector); | |
352 | } | |
353 | } | |
354 | ||
355 | static int xhci_try_enable_msi(struct usb_hcd *hcd) | |
356 | { | |
357 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
52fb6125 | 358 | struct pci_dev *pdev; |
421aa841 SAS |
359 | int ret; |
360 | ||
52fb6125 SS |
361 | /* The xhci platform device has set up IRQs through usb_add_hcd. */ |
362 | if (xhci->quirks & XHCI_PLAT) | |
363 | return 0; | |
364 | ||
365 | pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
421aa841 SAS |
366 | /* |
367 | * Some Fresco Logic host controllers advertise MSI, but fail to | |
368 | * generate interrupts. Don't even try to enable MSI. | |
369 | */ | |
370 | if (xhci->quirks & XHCI_BROKEN_MSI) | |
00eed9c8 | 371 | goto legacy_irq; |
421aa841 SAS |
372 | |
373 | /* unregister the legacy interrupt */ | |
374 | if (hcd->irq) | |
375 | free_irq(hcd->irq, hcd); | |
cd70469d | 376 | hcd->irq = 0; |
421aa841 SAS |
377 | |
378 | ret = xhci_setup_msix(xhci); | |
379 | if (ret) | |
380 | /* fall back to msi*/ | |
381 | ret = xhci_setup_msi(xhci); | |
382 | ||
383 | if (!ret) | |
cd70469d | 384 | /* hcd->irq is 0, we have MSI */ |
421aa841 SAS |
385 | return 0; |
386 | ||
68d07f64 SS |
387 | if (!pdev->irq) { |
388 | xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); | |
389 | return -EINVAL; | |
390 | } | |
391 | ||
00eed9c8 | 392 | legacy_irq: |
421aa841 SAS |
393 | /* fall back to legacy interrupt*/ |
394 | ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, | |
395 | hcd->irq_descr, hcd); | |
396 | if (ret) { | |
397 | xhci_err(xhci, "request interrupt %d failed\n", | |
398 | pdev->irq); | |
399 | return ret; | |
400 | } | |
401 | hcd->irq = pdev->irq; | |
402 | return 0; | |
403 | } | |
404 | ||
405 | #else | |
406 | ||
407 | static int xhci_try_enable_msi(struct usb_hcd *hcd) | |
408 | { | |
409 | return 0; | |
410 | } | |
411 | ||
412 | static void xhci_cleanup_msix(struct xhci_hcd *xhci) | |
413 | { | |
414 | } | |
415 | ||
416 | static void xhci_msix_sync_irqs(struct xhci_hcd *xhci) | |
417 | { | |
418 | } | |
419 | ||
420 | #endif | |
421 | ||
71c731a2 AC |
422 | static void compliance_mode_recovery(unsigned long arg) |
423 | { | |
424 | struct xhci_hcd *xhci; | |
425 | struct usb_hcd *hcd; | |
426 | u32 temp; | |
427 | int i; | |
428 | ||
429 | xhci = (struct xhci_hcd *)arg; | |
430 | ||
431 | for (i = 0; i < xhci->num_usb3_ports; i++) { | |
b0ba9720 | 432 | temp = readl(xhci->usb3_ports[i]); |
71c731a2 AC |
433 | if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) { |
434 | /* | |
435 | * Compliance Mode Detected. Letting USB Core | |
436 | * handle the Warm Reset | |
437 | */ | |
4bdfe4c3 XR |
438 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
439 | "Compliance mode detected->port %d", | |
71c731a2 | 440 | i + 1); |
4bdfe4c3 XR |
441 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
442 | "Attempting compliance mode recovery"); | |
71c731a2 AC |
443 | hcd = xhci->shared_hcd; |
444 | ||
445 | if (hcd->state == HC_STATE_SUSPENDED) | |
446 | usb_hcd_resume_root_hub(hcd); | |
447 | ||
448 | usb_hcd_poll_rh_status(hcd); | |
449 | } | |
450 | } | |
451 | ||
452 | if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1)) | |
453 | mod_timer(&xhci->comp_mode_recovery_timer, | |
454 | jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS)); | |
455 | } | |
456 | ||
457 | /* | |
458 | * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver | |
459 | * that causes ports behind that hardware to enter compliance mode sometimes. | |
460 | * The quirk creates a timer that polls every 2 seconds the link state of | |
461 | * each host controller's port and recovers it by issuing a Warm reset | |
462 | * if Compliance mode is detected, otherwise the port will become "dead" (no | |
463 | * device connections or disconnections will be detected anymore). Becasue no | |
464 | * status event is generated when entering compliance mode (per xhci spec), | |
465 | * this quirk is needed on systems that have the failing hardware installed. | |
466 | */ | |
467 | static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci) | |
468 | { | |
469 | xhci->port_status_u0 = 0; | |
470 | init_timer(&xhci->comp_mode_recovery_timer); | |
471 | ||
472 | xhci->comp_mode_recovery_timer.data = (unsigned long) xhci; | |
473 | xhci->comp_mode_recovery_timer.function = compliance_mode_recovery; | |
474 | xhci->comp_mode_recovery_timer.expires = jiffies + | |
475 | msecs_to_jiffies(COMP_MODE_RCVRY_MSECS); | |
476 | ||
477 | set_timer_slack(&xhci->comp_mode_recovery_timer, | |
478 | msecs_to_jiffies(COMP_MODE_RCVRY_MSECS)); | |
479 | add_timer(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
480 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
481 | "Compliance mode recovery timer initialized"); | |
71c731a2 AC |
482 | } |
483 | ||
484 | /* | |
485 | * This function identifies the systems that have installed the SN65LVPE502CP | |
486 | * USB3.0 re-driver and that need the Compliance Mode Quirk. | |
487 | * Systems: | |
488 | * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820 | |
489 | */ | |
c3897aa5 | 490 | bool xhci_compliance_mode_recovery_timer_quirk_check(void) |
71c731a2 AC |
491 | { |
492 | const char *dmi_product_name, *dmi_sys_vendor; | |
493 | ||
494 | dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); | |
495 | dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR); | |
457a73d3 VG |
496 | if (!dmi_product_name || !dmi_sys_vendor) |
497 | return false; | |
71c731a2 AC |
498 | |
499 | if (!(strstr(dmi_sys_vendor, "Hewlett-Packard"))) | |
500 | return false; | |
501 | ||
502 | if (strstr(dmi_product_name, "Z420") || | |
503 | strstr(dmi_product_name, "Z620") || | |
47080974 | 504 | strstr(dmi_product_name, "Z820") || |
b0e4e606 | 505 | strstr(dmi_product_name, "Z1 Workstation")) |
71c731a2 AC |
506 | return true; |
507 | ||
508 | return false; | |
509 | } | |
510 | ||
511 | static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci) | |
512 | { | |
513 | return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1)); | |
514 | } | |
515 | ||
516 | ||
66d4eadd SS |
517 | /* |
518 | * Initialize memory for HCD and xHC (one-time init). | |
519 | * | |
520 | * Program the PAGESIZE register, initialize the device context array, create | |
521 | * device contexts (?), set up a command ring segment (or two?), create event | |
522 | * ring (one for now). | |
523 | */ | |
524 | int xhci_init(struct usb_hcd *hcd) | |
525 | { | |
526 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
527 | int retval = 0; | |
528 | ||
d195fcff | 529 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init"); |
66d4eadd | 530 | spin_lock_init(&xhci->lock); |
d7826599 | 531 | if (xhci->hci_version == 0x95 && link_quirk) { |
4bdfe4c3 XR |
532 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
533 | "QUIRK: Not clearing Link TRB chain bits."); | |
b0567b3f SS |
534 | xhci->quirks |= XHCI_LINK_TRB_QUIRK; |
535 | } else { | |
d195fcff XR |
536 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
537 | "xHCI doesn't need link TRB QUIRK"); | |
b0567b3f | 538 | } |
66d4eadd | 539 | retval = xhci_mem_init(xhci, GFP_KERNEL); |
d195fcff | 540 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init"); |
66d4eadd | 541 | |
71c731a2 | 542 | /* Initializing Compliance Mode Recovery Data If Needed */ |
c3897aa5 | 543 | if (xhci_compliance_mode_recovery_timer_quirk_check()) { |
71c731a2 AC |
544 | xhci->quirks |= XHCI_COMP_MODE_QUIRK; |
545 | compliance_mode_recovery_timer_init(xhci); | |
546 | } | |
547 | ||
66d4eadd SS |
548 | return retval; |
549 | } | |
550 | ||
7f84eef0 SS |
551 | /*-------------------------------------------------------------------------*/ |
552 | ||
7f84eef0 | 553 | |
f6ff0ac8 SS |
554 | static int xhci_run_finished(struct xhci_hcd *xhci) |
555 | { | |
556 | if (xhci_start(xhci)) { | |
557 | xhci_halt(xhci); | |
558 | return -ENODEV; | |
559 | } | |
560 | xhci->shared_hcd->state = HC_STATE_RUNNING; | |
c181bc5b | 561 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; |
f6ff0ac8 SS |
562 | |
563 | if (xhci->quirks & XHCI_NEC_HOST) | |
564 | xhci_ring_cmd_db(xhci); | |
565 | ||
d195fcff XR |
566 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
567 | "Finished xhci_run for USB3 roothub"); | |
f6ff0ac8 SS |
568 | return 0; |
569 | } | |
570 | ||
66d4eadd SS |
571 | /* |
572 | * Start the HC after it was halted. | |
573 | * | |
574 | * This function is called by the USB core when the HC driver is added. | |
575 | * Its opposite is xhci_stop(). | |
576 | * | |
577 | * xhci_init() must be called once before this function can be called. | |
578 | * Reset the HC, enable device slot contexts, program DCBAAP, and | |
579 | * set command ring pointer and event ring pointer. | |
580 | * | |
581 | * Setup MSI-X vectors and enable interrupts. | |
582 | */ | |
583 | int xhci_run(struct usb_hcd *hcd) | |
584 | { | |
585 | u32 temp; | |
8e595a5d | 586 | u64 temp_64; |
3fd1ec58 | 587 | int ret; |
66d4eadd | 588 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
66d4eadd | 589 | |
f6ff0ac8 SS |
590 | /* Start the xHCI host controller running only after the USB 2.0 roothub |
591 | * is setup. | |
592 | */ | |
66d4eadd | 593 | |
0f2a7930 | 594 | hcd->uses_new_polling = 1; |
f6ff0ac8 SS |
595 | if (!usb_hcd_is_primary_hcd(hcd)) |
596 | return xhci_run_finished(xhci); | |
0f2a7930 | 597 | |
d195fcff | 598 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run"); |
43b86af8 | 599 | |
3fd1ec58 | 600 | ret = xhci_try_enable_msi(hcd); |
43b86af8 | 601 | if (ret) |
3fd1ec58 | 602 | return ret; |
66d4eadd | 603 | |
66e49d87 SS |
604 | xhci_dbg(xhci, "Command ring memory map follows:\n"); |
605 | xhci_debug_ring(xhci, xhci->cmd_ring); | |
606 | xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring); | |
607 | xhci_dbg_cmd_ptrs(xhci); | |
608 | ||
609 | xhci_dbg(xhci, "ERST memory map follows:\n"); | |
610 | xhci_dbg_erst(xhci, &xhci->erst); | |
611 | xhci_dbg(xhci, "Event ring:\n"); | |
612 | xhci_debug_ring(xhci, xhci->event_ring); | |
613 | xhci_dbg_ring_ptrs(xhci, xhci->event_ring); | |
e8b37332 | 614 | temp_64 = readq(&xhci->ir_set->erst_dequeue); |
66e49d87 | 615 | temp_64 &= ~ERST_PTR_MASK; |
d195fcff XR |
616 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
617 | "ERST deq = 64'h%0lx", (long unsigned int) temp_64); | |
66e49d87 | 618 | |
d195fcff XR |
619 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
620 | "// Set the interrupt modulation register"); | |
b0ba9720 | 621 | temp = readl(&xhci->ir_set->irq_control); |
a4d88302 | 622 | temp &= ~ER_IRQ_INTERVAL_MASK; |
66d4eadd | 623 | temp |= (u32) 160; |
204b7793 | 624 | writel(temp, &xhci->ir_set->irq_control); |
66d4eadd SS |
625 | |
626 | /* Set the HCD state before we enable the irqs */ | |
b0ba9720 | 627 | temp = readl(&xhci->op_regs->command); |
66d4eadd | 628 | temp |= (CMD_EIE); |
d195fcff XR |
629 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
630 | "// Enable interrupts, cmd = 0x%x.", temp); | |
204b7793 | 631 | writel(temp, &xhci->op_regs->command); |
66d4eadd | 632 | |
b0ba9720 | 633 | temp = readl(&xhci->ir_set->irq_pending); |
d195fcff XR |
634 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
635 | "// Enabling event ring interrupter %p by writing 0x%x to irq_pending", | |
700e2052 | 636 | xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp)); |
204b7793 | 637 | writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending); |
09ece30e | 638 | xhci_print_ir_set(xhci, 0); |
66d4eadd | 639 | |
0238634d SS |
640 | if (xhci->quirks & XHCI_NEC_HOST) |
641 | xhci_queue_vendor_command(xhci, 0, 0, 0, | |
642 | TRB_TYPE(TRB_NEC_GET_FW)); | |
7f84eef0 | 643 | |
d195fcff XR |
644 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
645 | "Finished xhci_run for USB2 roothub"); | |
f6ff0ac8 SS |
646 | return 0; |
647 | } | |
ed07453f | 648 | |
f6ff0ac8 SS |
649 | static void xhci_only_stop_hcd(struct usb_hcd *hcd) |
650 | { | |
651 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
66d4eadd | 652 | |
f6ff0ac8 SS |
653 | spin_lock_irq(&xhci->lock); |
654 | xhci_halt(xhci); | |
655 | ||
656 | /* The shared_hcd is going to be deallocated shortly (the USB core only | |
657 | * calls this function when allocation fails in usb_add_hcd(), or | |
658 | * usb_remove_hcd() is called). So we need to unset xHCI's pointer. | |
659 | */ | |
660 | xhci->shared_hcd = NULL; | |
661 | spin_unlock_irq(&xhci->lock); | |
66d4eadd SS |
662 | } |
663 | ||
664 | /* | |
665 | * Stop xHCI driver. | |
666 | * | |
667 | * This function is called by the USB core when the HC driver is removed. | |
668 | * Its opposite is xhci_run(). | |
669 | * | |
670 | * Disable device contexts, disable IRQs, and quiesce the HC. | |
671 | * Reset the HC, finish any completed transactions, and cleanup memory. | |
672 | */ | |
673 | void xhci_stop(struct usb_hcd *hcd) | |
674 | { | |
675 | u32 temp; | |
676 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
677 | ||
f6ff0ac8 SS |
678 | if (!usb_hcd_is_primary_hcd(hcd)) { |
679 | xhci_only_stop_hcd(xhci->shared_hcd); | |
680 | return; | |
681 | } | |
682 | ||
66d4eadd | 683 | spin_lock_irq(&xhci->lock); |
f6ff0ac8 SS |
684 | /* Make sure the xHC is halted for a USB3 roothub |
685 | * (xhci_stop() could be called as part of failed init). | |
686 | */ | |
66d4eadd SS |
687 | xhci_halt(xhci); |
688 | xhci_reset(xhci); | |
689 | spin_unlock_irq(&xhci->lock); | |
690 | ||
40a9fb17 ZR |
691 | xhci_cleanup_msix(xhci); |
692 | ||
71c731a2 AC |
693 | /* Deleting Compliance Mode Recovery Timer */ |
694 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
58b1d799 | 695 | (!(xhci_all_ports_seen_u0(xhci)))) { |
71c731a2 | 696 | del_timer_sync(&xhci->comp_mode_recovery_timer); |
4bdfe4c3 XR |
697 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
698 | "%s: compliance mode recovery timer deleted", | |
58b1d799 TC |
699 | __func__); |
700 | } | |
71c731a2 | 701 | |
c41136b0 AX |
702 | if (xhci->quirks & XHCI_AMD_PLL_FIX) |
703 | usb_amd_dev_put(); | |
704 | ||
d195fcff XR |
705 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
706 | "// Disabling event ring interrupts"); | |
b0ba9720 | 707 | temp = readl(&xhci->op_regs->status); |
204b7793 | 708 | writel(temp & ~STS_EINT, &xhci->op_regs->status); |
b0ba9720 | 709 | temp = readl(&xhci->ir_set->irq_pending); |
204b7793 | 710 | writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending); |
09ece30e | 711 | xhci_print_ir_set(xhci, 0); |
66d4eadd | 712 | |
d195fcff | 713 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory"); |
66d4eadd | 714 | xhci_mem_cleanup(xhci); |
d195fcff XR |
715 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
716 | "xhci_stop completed - status = %x", | |
b0ba9720 | 717 | readl(&xhci->op_regs->status)); |
66d4eadd SS |
718 | } |
719 | ||
720 | /* | |
721 | * Shutdown HC (not bus-specific) | |
722 | * | |
723 | * This is called when the machine is rebooting or halting. We assume that the | |
724 | * machine will be powered off, and the HC's internal state will be reset. | |
725 | * Don't bother to free memory. | |
f6ff0ac8 SS |
726 | * |
727 | * This will only ever be called with the main usb_hcd (the USB3 roothub). | |
66d4eadd SS |
728 | */ |
729 | void xhci_shutdown(struct usb_hcd *hcd) | |
730 | { | |
731 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
732 | ||
052c7f9f | 733 | if (xhci->quirks & XHCI_SPURIOUS_REBOOT) |
e95829f4 SS |
734 | usb_disable_xhci_ports(to_pci_dev(hcd->self.controller)); |
735 | ||
66d4eadd SS |
736 | spin_lock_irq(&xhci->lock); |
737 | xhci_halt(xhci); | |
638298dc TI |
738 | /* Workaround for spurious wakeups at shutdown with HSW */ |
739 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | |
740 | xhci_reset(xhci); | |
43b86af8 | 741 | spin_unlock_irq(&xhci->lock); |
66d4eadd | 742 | |
40a9fb17 ZR |
743 | xhci_cleanup_msix(xhci); |
744 | ||
d195fcff XR |
745 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
746 | "xhci_shutdown completed - status = %x", | |
b0ba9720 | 747 | readl(&xhci->op_regs->status)); |
638298dc TI |
748 | |
749 | /* Yet another workaround for spurious wakeups at shutdown with HSW */ | |
750 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | |
751 | pci_set_power_state(to_pci_dev(hcd->self.controller), PCI_D3hot); | |
66d4eadd SS |
752 | } |
753 | ||
b5b5c3ac | 754 | #ifdef CONFIG_PM |
5535b1d5 AX |
755 | static void xhci_save_registers(struct xhci_hcd *xhci) |
756 | { | |
b0ba9720 XR |
757 | xhci->s3.command = readl(&xhci->op_regs->command); |
758 | xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification); | |
e8b37332 | 759 | xhci->s3.dcbaa_ptr = readq(&xhci->op_regs->dcbaa_ptr); |
b0ba9720 XR |
760 | xhci->s3.config_reg = readl(&xhci->op_regs->config_reg); |
761 | xhci->s3.erst_size = readl(&xhci->ir_set->erst_size); | |
e8b37332 XR |
762 | xhci->s3.erst_base = readq(&xhci->ir_set->erst_base); |
763 | xhci->s3.erst_dequeue = readq(&xhci->ir_set->erst_dequeue); | |
b0ba9720 XR |
764 | xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending); |
765 | xhci->s3.irq_control = readl(&xhci->ir_set->irq_control); | |
5535b1d5 AX |
766 | } |
767 | ||
768 | static void xhci_restore_registers(struct xhci_hcd *xhci) | |
769 | { | |
204b7793 XR |
770 | writel(xhci->s3.command, &xhci->op_regs->command); |
771 | writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification); | |
7dd09a1a | 772 | writeq(xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr); |
204b7793 XR |
773 | writel(xhci->s3.config_reg, &xhci->op_regs->config_reg); |
774 | writel(xhci->s3.erst_size, &xhci->ir_set->erst_size); | |
7dd09a1a XR |
775 | writeq(xhci->s3.erst_base, &xhci->ir_set->erst_base); |
776 | writeq(xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue); | |
204b7793 XR |
777 | writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending); |
778 | writel(xhci->s3.irq_control, &xhci->ir_set->irq_control); | |
5535b1d5 AX |
779 | } |
780 | ||
89821320 SS |
781 | static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci) |
782 | { | |
783 | u64 val_64; | |
784 | ||
785 | /* step 2: initialize command ring buffer */ | |
e8b37332 | 786 | val_64 = readq(&xhci->op_regs->cmd_ring); |
89821320 SS |
787 | val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | |
788 | (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, | |
789 | xhci->cmd_ring->dequeue) & | |
790 | (u64) ~CMD_RING_RSVD_BITS) | | |
791 | xhci->cmd_ring->cycle_state; | |
d195fcff XR |
792 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
793 | "// Setting command ring address to 0x%llx", | |
89821320 | 794 | (long unsigned long) val_64); |
7dd09a1a | 795 | writeq(val_64, &xhci->op_regs->cmd_ring); |
89821320 SS |
796 | } |
797 | ||
798 | /* | |
799 | * The whole command ring must be cleared to zero when we suspend the host. | |
800 | * | |
801 | * The host doesn't save the command ring pointer in the suspend well, so we | |
802 | * need to re-program it on resume. Unfortunately, the pointer must be 64-byte | |
803 | * aligned, because of the reserved bits in the command ring dequeue pointer | |
804 | * register. Therefore, we can't just set the dequeue pointer back in the | |
805 | * middle of the ring (TRBs are 16-byte aligned). | |
806 | */ | |
807 | static void xhci_clear_command_ring(struct xhci_hcd *xhci) | |
808 | { | |
809 | struct xhci_ring *ring; | |
810 | struct xhci_segment *seg; | |
811 | ||
812 | ring = xhci->cmd_ring; | |
813 | seg = ring->deq_seg; | |
814 | do { | |
158886cd AX |
815 | memset(seg->trbs, 0, |
816 | sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1)); | |
817 | seg->trbs[TRBS_PER_SEGMENT - 1].link.control &= | |
818 | cpu_to_le32(~TRB_CYCLE); | |
89821320 SS |
819 | seg = seg->next; |
820 | } while (seg != ring->deq_seg); | |
821 | ||
822 | /* Reset the software enqueue and dequeue pointers */ | |
823 | ring->deq_seg = ring->first_seg; | |
824 | ring->dequeue = ring->first_seg->trbs; | |
825 | ring->enq_seg = ring->deq_seg; | |
826 | ring->enqueue = ring->dequeue; | |
827 | ||
b008df60 | 828 | ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1; |
89821320 SS |
829 | /* |
830 | * Ring is now zeroed, so the HW should look for change of ownership | |
831 | * when the cycle bit is set to 1. | |
832 | */ | |
833 | ring->cycle_state = 1; | |
834 | ||
835 | /* | |
836 | * Reset the hardware dequeue pointer. | |
837 | * Yes, this will need to be re-written after resume, but we're paranoid | |
838 | * and want to make sure the hardware doesn't access bogus memory | |
839 | * because, say, the BIOS or an SMI started the host without changing | |
840 | * the command ring pointers. | |
841 | */ | |
842 | xhci_set_cmd_ring_deq(xhci); | |
843 | } | |
844 | ||
5535b1d5 AX |
845 | /* |
846 | * Stop HC (not bus-specific) | |
847 | * | |
848 | * This is called when the machine transition into S3/S4 mode. | |
849 | * | |
850 | */ | |
851 | int xhci_suspend(struct xhci_hcd *xhci) | |
852 | { | |
853 | int rc = 0; | |
455f5892 | 854 | unsigned int delay = XHCI_MAX_HALT_USEC; |
5535b1d5 AX |
855 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
856 | u32 command; | |
857 | ||
77b84767 FB |
858 | if (hcd->state != HC_STATE_SUSPENDED || |
859 | xhci->shared_hcd->state != HC_STATE_SUSPENDED) | |
860 | return -EINVAL; | |
861 | ||
c52804a4 SS |
862 | /* Don't poll the roothubs on bus suspend. */ |
863 | xhci_dbg(xhci, "%s: stopping port polling.\n", __func__); | |
864 | clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
865 | del_timer_sync(&hcd->rh_timer); | |
866 | ||
5535b1d5 AX |
867 | spin_lock_irq(&xhci->lock); |
868 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
b3209379 | 869 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags); |
5535b1d5 AX |
870 | /* step 1: stop endpoint */ |
871 | /* skipped assuming that port suspend has done */ | |
872 | ||
873 | /* step 2: clear Run/Stop bit */ | |
b0ba9720 | 874 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 875 | command &= ~CMD_RUN; |
204b7793 | 876 | writel(command, &xhci->op_regs->command); |
455f5892 ON |
877 | |
878 | /* Some chips from Fresco Logic need an extraordinary delay */ | |
879 | delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1; | |
880 | ||
2611bd18 | 881 | if (xhci_handshake(xhci, &xhci->op_regs->status, |
455f5892 | 882 | STS_HALT, STS_HALT, delay)) { |
5535b1d5 AX |
883 | xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n"); |
884 | spin_unlock_irq(&xhci->lock); | |
885 | return -ETIMEDOUT; | |
886 | } | |
89821320 | 887 | xhci_clear_command_ring(xhci); |
5535b1d5 AX |
888 | |
889 | /* step 3: save registers */ | |
890 | xhci_save_registers(xhci); | |
891 | ||
892 | /* step 4: set CSS flag */ | |
b0ba9720 | 893 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 894 | command |= CMD_CSS; |
204b7793 | 895 | writel(command, &xhci->op_regs->command); |
2611bd18 SS |
896 | if (xhci_handshake(xhci, &xhci->op_regs->status, |
897 | STS_SAVE, 0, 10 * 1000)) { | |
622eb783 | 898 | xhci_warn(xhci, "WARN: xHC save state timeout\n"); |
5535b1d5 AX |
899 | spin_unlock_irq(&xhci->lock); |
900 | return -ETIMEDOUT; | |
901 | } | |
5535b1d5 AX |
902 | spin_unlock_irq(&xhci->lock); |
903 | ||
71c731a2 AC |
904 | /* |
905 | * Deleting Compliance Mode Recovery Timer because the xHCI Host | |
906 | * is about to be suspended. | |
907 | */ | |
908 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
909 | (!(xhci_all_ports_seen_u0(xhci)))) { | |
910 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
911 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
912 | "%s: compliance mode recovery timer deleted", | |
58b1d799 | 913 | __func__); |
71c731a2 AC |
914 | } |
915 | ||
0029227f AX |
916 | /* step 5: remove core well power */ |
917 | /* synchronize irq when using MSI-X */ | |
421aa841 | 918 | xhci_msix_sync_irqs(xhci); |
0029227f | 919 | |
5535b1d5 AX |
920 | return rc; |
921 | } | |
922 | ||
923 | /* | |
924 | * start xHC (not bus-specific) | |
925 | * | |
926 | * This is called when the machine transition from S3/S4 mode. | |
927 | * | |
928 | */ | |
929 | int xhci_resume(struct xhci_hcd *xhci, bool hibernated) | |
930 | { | |
931 | u32 command, temp = 0; | |
932 | struct usb_hcd *hcd = xhci_to_hcd(xhci); | |
65b22f93 | 933 | struct usb_hcd *secondary_hcd; |
f69e3120 | 934 | int retval = 0; |
77df9e0b | 935 | bool comp_timer_running = false; |
5535b1d5 | 936 | |
f6ff0ac8 | 937 | /* Wait a bit if either of the roothubs need to settle from the |
25985edc | 938 | * transition into bus suspend. |
20b67cf5 | 939 | */ |
f6ff0ac8 SS |
940 | if (time_before(jiffies, xhci->bus_state[0].next_statechange) || |
941 | time_before(jiffies, | |
942 | xhci->bus_state[1].next_statechange)) | |
5535b1d5 AX |
943 | msleep(100); |
944 | ||
f69e3120 AS |
945 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
946 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags); | |
947 | ||
5535b1d5 | 948 | spin_lock_irq(&xhci->lock); |
c877b3b2 ML |
949 | if (xhci->quirks & XHCI_RESET_ON_RESUME) |
950 | hibernated = true; | |
5535b1d5 AX |
951 | |
952 | if (!hibernated) { | |
953 | /* step 1: restore register */ | |
954 | xhci_restore_registers(xhci); | |
955 | /* step 2: initialize command ring buffer */ | |
89821320 | 956 | xhci_set_cmd_ring_deq(xhci); |
5535b1d5 AX |
957 | /* step 3: restore state and start state*/ |
958 | /* step 3: set CRS flag */ | |
b0ba9720 | 959 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 960 | command |= CMD_CRS; |
204b7793 | 961 | writel(command, &xhci->op_regs->command); |
2611bd18 | 962 | if (xhci_handshake(xhci, &xhci->op_regs->status, |
622eb783 AX |
963 | STS_RESTORE, 0, 10 * 1000)) { |
964 | xhci_warn(xhci, "WARN: xHC restore state timeout\n"); | |
5535b1d5 AX |
965 | spin_unlock_irq(&xhci->lock); |
966 | return -ETIMEDOUT; | |
967 | } | |
b0ba9720 | 968 | temp = readl(&xhci->op_regs->status); |
5535b1d5 AX |
969 | } |
970 | ||
971 | /* If restore operation fails, re-initialize the HC during resume */ | |
972 | if ((temp & STS_SRE) || hibernated) { | |
77df9e0b TC |
973 | |
974 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
975 | !(xhci_all_ports_seen_u0(xhci))) { | |
976 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
977 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
978 | "Compliance Mode Recovery Timer deleted!"); | |
77df9e0b TC |
979 | } |
980 | ||
fedd383e SS |
981 | /* Let the USB core know _both_ roothubs lost power. */ |
982 | usb_root_hub_lost_power(xhci->main_hcd->self.root_hub); | |
983 | usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub); | |
5535b1d5 AX |
984 | |
985 | xhci_dbg(xhci, "Stop HCD\n"); | |
986 | xhci_halt(xhci); | |
987 | xhci_reset(xhci); | |
5535b1d5 | 988 | spin_unlock_irq(&xhci->lock); |
0029227f | 989 | xhci_cleanup_msix(xhci); |
5535b1d5 | 990 | |
5535b1d5 | 991 | xhci_dbg(xhci, "// Disabling event ring interrupts\n"); |
b0ba9720 | 992 | temp = readl(&xhci->op_regs->status); |
204b7793 | 993 | writel(temp & ~STS_EINT, &xhci->op_regs->status); |
b0ba9720 | 994 | temp = readl(&xhci->ir_set->irq_pending); |
204b7793 | 995 | writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending); |
09ece30e | 996 | xhci_print_ir_set(xhci, 0); |
5535b1d5 AX |
997 | |
998 | xhci_dbg(xhci, "cleaning up memory\n"); | |
999 | xhci_mem_cleanup(xhci); | |
1000 | xhci_dbg(xhci, "xhci_stop completed - status = %x\n", | |
b0ba9720 | 1001 | readl(&xhci->op_regs->status)); |
5535b1d5 | 1002 | |
65b22f93 SS |
1003 | /* USB core calls the PCI reinit and start functions twice: |
1004 | * first with the primary HCD, and then with the secondary HCD. | |
1005 | * If we don't do the same, the host will never be started. | |
1006 | */ | |
1007 | if (!usb_hcd_is_primary_hcd(hcd)) | |
1008 | secondary_hcd = hcd; | |
1009 | else | |
1010 | secondary_hcd = xhci->shared_hcd; | |
1011 | ||
1012 | xhci_dbg(xhci, "Initialize the xhci_hcd\n"); | |
1013 | retval = xhci_init(hcd->primary_hcd); | |
5535b1d5 AX |
1014 | if (retval) |
1015 | return retval; | |
77df9e0b TC |
1016 | comp_timer_running = true; |
1017 | ||
65b22f93 SS |
1018 | xhci_dbg(xhci, "Start the primary HCD\n"); |
1019 | retval = xhci_run(hcd->primary_hcd); | |
b3209379 | 1020 | if (!retval) { |
f69e3120 AS |
1021 | xhci_dbg(xhci, "Start the secondary HCD\n"); |
1022 | retval = xhci_run(secondary_hcd); | |
b3209379 | 1023 | } |
5535b1d5 | 1024 | hcd->state = HC_STATE_SUSPENDED; |
b3209379 | 1025 | xhci->shared_hcd->state = HC_STATE_SUSPENDED; |
f69e3120 | 1026 | goto done; |
5535b1d5 AX |
1027 | } |
1028 | ||
5535b1d5 | 1029 | /* step 4: set Run/Stop bit */ |
b0ba9720 | 1030 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 1031 | command |= CMD_RUN; |
204b7793 | 1032 | writel(command, &xhci->op_regs->command); |
2611bd18 | 1033 | xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT, |
5535b1d5 AX |
1034 | 0, 250 * 1000); |
1035 | ||
1036 | /* step 5: walk topology and initialize portsc, | |
1037 | * portpmsc and portli | |
1038 | */ | |
1039 | /* this is done in bus_resume */ | |
1040 | ||
1041 | /* step 6: restart each of the previously | |
1042 | * Running endpoints by ringing their doorbells | |
1043 | */ | |
1044 | ||
5535b1d5 | 1045 | spin_unlock_irq(&xhci->lock); |
f69e3120 AS |
1046 | |
1047 | done: | |
1048 | if (retval == 0) { | |
1049 | usb_hcd_resume_root_hub(hcd); | |
1050 | usb_hcd_resume_root_hub(xhci->shared_hcd); | |
1051 | } | |
71c731a2 AC |
1052 | |
1053 | /* | |
1054 | * If system is subject to the Quirk, Compliance Mode Timer needs to | |
1055 | * be re-initialized Always after a system resume. Ports are subject | |
1056 | * to suffer the Compliance Mode issue again. It doesn't matter if | |
1057 | * ports have entered previously to U0 before system's suspension. | |
1058 | */ | |
77df9e0b | 1059 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running) |
71c731a2 AC |
1060 | compliance_mode_recovery_timer_init(xhci); |
1061 | ||
c52804a4 SS |
1062 | /* Re-enable port polling. */ |
1063 | xhci_dbg(xhci, "%s: starting port polling.\n", __func__); | |
1064 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
1065 | usb_hcd_poll_rh_status(hcd); | |
1066 | ||
f69e3120 | 1067 | return retval; |
5535b1d5 | 1068 | } |
b5b5c3ac SS |
1069 | #endif /* CONFIG_PM */ |
1070 | ||
7f84eef0 SS |
1071 | /*-------------------------------------------------------------------------*/ |
1072 | ||
d0e96f5a SS |
1073 | /** |
1074 | * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and | |
1075 | * HCDs. Find the index for an endpoint given its descriptor. Use the return | |
1076 | * value to right shift 1 for the bitmask. | |
1077 | * | |
1078 | * Index = (epnum * 2) + direction - 1, | |
1079 | * where direction = 0 for OUT, 1 for IN. | |
1080 | * For control endpoints, the IN index is used (OUT index is unused), so | |
1081 | * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2) | |
1082 | */ | |
1083 | unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc) | |
1084 | { | |
1085 | unsigned int index; | |
1086 | if (usb_endpoint_xfer_control(desc)) | |
1087 | index = (unsigned int) (usb_endpoint_num(desc)*2); | |
1088 | else | |
1089 | index = (unsigned int) (usb_endpoint_num(desc)*2) + | |
1090 | (usb_endpoint_dir_in(desc) ? 1 : 0) - 1; | |
1091 | return index; | |
1092 | } | |
1093 | ||
01c5f447 JW |
1094 | /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint |
1095 | * address from the XHCI endpoint index. | |
1096 | */ | |
1097 | unsigned int xhci_get_endpoint_address(unsigned int ep_index) | |
1098 | { | |
1099 | unsigned int number = DIV_ROUND_UP(ep_index, 2); | |
1100 | unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN; | |
1101 | return direction | number; | |
1102 | } | |
1103 | ||
f94e0186 SS |
1104 | /* Find the flag for this endpoint (for use in the control context). Use the |
1105 | * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is | |
1106 | * bit 1, etc. | |
1107 | */ | |
1108 | unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc) | |
1109 | { | |
1110 | return 1 << (xhci_get_endpoint_index(desc) + 1); | |
1111 | } | |
1112 | ||
ac9d8fe7 SS |
1113 | /* Find the flag for this endpoint (for use in the control context). Use the |
1114 | * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is | |
1115 | * bit 1, etc. | |
1116 | */ | |
1117 | unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index) | |
1118 | { | |
1119 | return 1 << (ep_index + 1); | |
1120 | } | |
1121 | ||
f94e0186 SS |
1122 | /* Compute the last valid endpoint context index. Basically, this is the |
1123 | * endpoint index plus one. For slot contexts with more than valid endpoint, | |
1124 | * we find the most significant bit set in the added contexts flags. | |
1125 | * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000 | |
1126 | * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one. | |
1127 | */ | |
ac9d8fe7 | 1128 | unsigned int xhci_last_valid_endpoint(u32 added_ctxs) |
f94e0186 SS |
1129 | { |
1130 | return fls(added_ctxs) - 1; | |
1131 | } | |
1132 | ||
d0e96f5a SS |
1133 | /* Returns 1 if the arguments are OK; |
1134 | * returns 0 this is a root hub; returns -EINVAL for NULL pointers. | |
1135 | */ | |
8212a49d | 1136 | static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev, |
64927730 AX |
1137 | struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev, |
1138 | const char *func) { | |
1139 | struct xhci_hcd *xhci; | |
1140 | struct xhci_virt_device *virt_dev; | |
1141 | ||
d0e96f5a | 1142 | if (!hcd || (check_ep && !ep) || !udev) { |
5c1127d3 | 1143 | pr_debug("xHCI %s called with invalid args\n", func); |
d0e96f5a SS |
1144 | return -EINVAL; |
1145 | } | |
1146 | if (!udev->parent) { | |
5c1127d3 | 1147 | pr_debug("xHCI %s called for root hub\n", func); |
d0e96f5a SS |
1148 | return 0; |
1149 | } | |
64927730 | 1150 | |
7bd89b40 | 1151 | xhci = hcd_to_xhci(hcd); |
64927730 | 1152 | if (check_virt_dev) { |
73ddc247 | 1153 | if (!udev->slot_id || !xhci->devs[udev->slot_id]) { |
5c1127d3 XR |
1154 | xhci_dbg(xhci, "xHCI %s called with unaddressed device\n", |
1155 | func); | |
64927730 AX |
1156 | return -EINVAL; |
1157 | } | |
1158 | ||
1159 | virt_dev = xhci->devs[udev->slot_id]; | |
1160 | if (virt_dev->udev != udev) { | |
5c1127d3 | 1161 | xhci_dbg(xhci, "xHCI %s called with udev and " |
64927730 AX |
1162 | "virt_dev does not match\n", func); |
1163 | return -EINVAL; | |
1164 | } | |
d0e96f5a | 1165 | } |
64927730 | 1166 | |
203a8661 SS |
1167 | if (xhci->xhc_state & XHCI_STATE_HALTED) |
1168 | return -ENODEV; | |
1169 | ||
d0e96f5a SS |
1170 | return 1; |
1171 | } | |
1172 | ||
2d3f1fac | 1173 | static int xhci_configure_endpoint(struct xhci_hcd *xhci, |
913a8a34 SS |
1174 | struct usb_device *udev, struct xhci_command *command, |
1175 | bool ctx_change, bool must_succeed); | |
2d3f1fac SS |
1176 | |
1177 | /* | |
1178 | * Full speed devices may have a max packet size greater than 8 bytes, but the | |
1179 | * USB core doesn't know that until it reads the first 8 bytes of the | |
1180 | * descriptor. If the usb_device's max packet size changes after that point, | |
1181 | * we need to issue an evaluate context command and wait on it. | |
1182 | */ | |
1183 | static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id, | |
1184 | unsigned int ep_index, struct urb *urb) | |
1185 | { | |
1186 | struct xhci_container_ctx *in_ctx; | |
1187 | struct xhci_container_ctx *out_ctx; | |
1188 | struct xhci_input_control_ctx *ctrl_ctx; | |
1189 | struct xhci_ep_ctx *ep_ctx; | |
1190 | int max_packet_size; | |
1191 | int hw_max_packet_size; | |
1192 | int ret = 0; | |
1193 | ||
1194 | out_ctx = xhci->devs[slot_id]->out_ctx; | |
1195 | ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); | |
28ccd296 | 1196 | hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2)); |
29cc8897 | 1197 | max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc); |
2d3f1fac | 1198 | if (hw_max_packet_size != max_packet_size) { |
3a7fa5be XR |
1199 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1200 | "Max Packet Size for ep 0 changed."); | |
1201 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, | |
1202 | "Max packet size in usb_device = %d", | |
2d3f1fac | 1203 | max_packet_size); |
3a7fa5be XR |
1204 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1205 | "Max packet size in xHCI HW = %d", | |
2d3f1fac | 1206 | hw_max_packet_size); |
3a7fa5be XR |
1207 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1208 | "Issuing evaluate context command."); | |
2d3f1fac | 1209 | |
92f8e767 SS |
1210 | /* Set up the input context flags for the command */ |
1211 | /* FIXME: This won't work if a non-default control endpoint | |
1212 | * changes max packet sizes. | |
1213 | */ | |
1214 | in_ctx = xhci->devs[slot_id]->in_ctx; | |
1215 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); | |
1216 | if (!ctrl_ctx) { | |
1217 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1218 | __func__); | |
1219 | return -ENOMEM; | |
1220 | } | |
2d3f1fac | 1221 | /* Set up the modified control endpoint 0 */ |
913a8a34 SS |
1222 | xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx, |
1223 | xhci->devs[slot_id]->out_ctx, ep_index); | |
92f8e767 | 1224 | |
2d3f1fac | 1225 | ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); |
28ccd296 ME |
1226 | ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK); |
1227 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size)); | |
2d3f1fac | 1228 | |
28ccd296 | 1229 | ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG); |
2d3f1fac SS |
1230 | ctrl_ctx->drop_flags = 0; |
1231 | ||
1232 | xhci_dbg(xhci, "Slot %d input context\n", slot_id); | |
1233 | xhci_dbg_ctx(xhci, in_ctx, ep_index); | |
1234 | xhci_dbg(xhci, "Slot %d output context\n", slot_id); | |
1235 | xhci_dbg_ctx(xhci, out_ctx, ep_index); | |
1236 | ||
913a8a34 SS |
1237 | ret = xhci_configure_endpoint(xhci, urb->dev, NULL, |
1238 | true, false); | |
2d3f1fac SS |
1239 | |
1240 | /* Clean up the input context for later use by bandwidth | |
1241 | * functions. | |
1242 | */ | |
28ccd296 | 1243 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG); |
2d3f1fac SS |
1244 | } |
1245 | return ret; | |
1246 | } | |
1247 | ||
d0e96f5a SS |
1248 | /* |
1249 | * non-error returns are a promise to giveback() the urb later | |
1250 | * we drop ownership so next owner (or urb unlink) can get it | |
1251 | */ | |
1252 | int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) | |
1253 | { | |
1254 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
2ffdea25 | 1255 | struct xhci_td *buffer; |
d0e96f5a SS |
1256 | unsigned long flags; |
1257 | int ret = 0; | |
1258 | unsigned int slot_id, ep_index; | |
8e51adcc AX |
1259 | struct urb_priv *urb_priv; |
1260 | int size, i; | |
2d3f1fac | 1261 | |
64927730 AX |
1262 | if (!urb || xhci_check_args(hcd, urb->dev, urb->ep, |
1263 | true, true, __func__) <= 0) | |
d0e96f5a SS |
1264 | return -EINVAL; |
1265 | ||
1266 | slot_id = urb->dev->slot_id; | |
1267 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); | |
d0e96f5a | 1268 | |
541c7d43 | 1269 | if (!HCD_HW_ACCESSIBLE(hcd)) { |
d0e96f5a SS |
1270 | if (!in_interrupt()) |
1271 | xhci_dbg(xhci, "urb submitted during PCI suspend\n"); | |
1272 | ret = -ESHUTDOWN; | |
1273 | goto exit; | |
1274 | } | |
8e51adcc AX |
1275 | |
1276 | if (usb_endpoint_xfer_isoc(&urb->ep->desc)) | |
1277 | size = urb->number_of_packets; | |
1278 | else | |
1279 | size = 1; | |
1280 | ||
1281 | urb_priv = kzalloc(sizeof(struct urb_priv) + | |
1282 | size * sizeof(struct xhci_td *), mem_flags); | |
1283 | if (!urb_priv) | |
1284 | return -ENOMEM; | |
1285 | ||
2ffdea25 AX |
1286 | buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags); |
1287 | if (!buffer) { | |
1288 | kfree(urb_priv); | |
1289 | return -ENOMEM; | |
1290 | } | |
1291 | ||
8e51adcc | 1292 | for (i = 0; i < size; i++) { |
2ffdea25 AX |
1293 | urb_priv->td[i] = buffer; |
1294 | buffer++; | |
8e51adcc AX |
1295 | } |
1296 | ||
1297 | urb_priv->length = size; | |
1298 | urb_priv->td_cnt = 0; | |
1299 | urb->hcpriv = urb_priv; | |
1300 | ||
2d3f1fac SS |
1301 | if (usb_endpoint_xfer_control(&urb->ep->desc)) { |
1302 | /* Check to see if the max packet size for the default control | |
1303 | * endpoint changed during FS device enumeration | |
1304 | */ | |
1305 | if (urb->dev->speed == USB_SPEED_FULL) { | |
1306 | ret = xhci_check_maxpacket(xhci, slot_id, | |
1307 | ep_index, urb); | |
d13565c1 SS |
1308 | if (ret < 0) { |
1309 | xhci_urb_free_priv(xhci, urb_priv); | |
1310 | urb->hcpriv = NULL; | |
2d3f1fac | 1311 | return ret; |
d13565c1 | 1312 | } |
2d3f1fac SS |
1313 | } |
1314 | ||
b11069f5 SS |
1315 | /* We have a spinlock and interrupts disabled, so we must pass |
1316 | * atomic context to this function, which may allocate memory. | |
1317 | */ | |
2d3f1fac | 1318 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf SS |
1319 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1320 | goto dying; | |
b11069f5 | 1321 | ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb, |
23e3be11 | 1322 | slot_id, ep_index); |
d13565c1 SS |
1323 | if (ret) |
1324 | goto free_priv; | |
2d3f1fac SS |
1325 | spin_unlock_irqrestore(&xhci->lock, flags); |
1326 | } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) { | |
1327 | spin_lock_irqsave(&xhci->lock, flags); | |
6f5165cf SS |
1328 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1329 | goto dying; | |
8df75f42 SS |
1330 | if (xhci->devs[slot_id]->eps[ep_index].ep_state & |
1331 | EP_GETTING_STREAMS) { | |
1332 | xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep " | |
1333 | "is transitioning to using streams.\n"); | |
1334 | ret = -EINVAL; | |
1335 | } else if (xhci->devs[slot_id]->eps[ep_index].ep_state & | |
1336 | EP_GETTING_NO_STREAMS) { | |
1337 | xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep " | |
1338 | "is transitioning to " | |
1339 | "not having streams.\n"); | |
1340 | ret = -EINVAL; | |
1341 | } else { | |
1342 | ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, | |
1343 | slot_id, ep_index); | |
1344 | } | |
d13565c1 SS |
1345 | if (ret) |
1346 | goto free_priv; | |
2d3f1fac | 1347 | spin_unlock_irqrestore(&xhci->lock, flags); |
624defa1 SS |
1348 | } else if (usb_endpoint_xfer_int(&urb->ep->desc)) { |
1349 | spin_lock_irqsave(&xhci->lock, flags); | |
6f5165cf SS |
1350 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1351 | goto dying; | |
624defa1 SS |
1352 | ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb, |
1353 | slot_id, ep_index); | |
d13565c1 SS |
1354 | if (ret) |
1355 | goto free_priv; | |
624defa1 | 1356 | spin_unlock_irqrestore(&xhci->lock, flags); |
2d3f1fac | 1357 | } else { |
787f4e5a AX |
1358 | spin_lock_irqsave(&xhci->lock, flags); |
1359 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
1360 | goto dying; | |
1361 | ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb, | |
1362 | slot_id, ep_index); | |
d13565c1 SS |
1363 | if (ret) |
1364 | goto free_priv; | |
787f4e5a | 1365 | spin_unlock_irqrestore(&xhci->lock, flags); |
2d3f1fac | 1366 | } |
d0e96f5a | 1367 | exit: |
d0e96f5a | 1368 | return ret; |
6f5165cf SS |
1369 | dying: |
1370 | xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for " | |
1371 | "non-responsive xHCI host.\n", | |
1372 | urb->ep->desc.bEndpointAddress, urb); | |
d13565c1 SS |
1373 | ret = -ESHUTDOWN; |
1374 | free_priv: | |
1375 | xhci_urb_free_priv(xhci, urb_priv); | |
1376 | urb->hcpriv = NULL; | |
6f5165cf | 1377 | spin_unlock_irqrestore(&xhci->lock, flags); |
d13565c1 | 1378 | return ret; |
d0e96f5a SS |
1379 | } |
1380 | ||
021bff91 SS |
1381 | /* Get the right ring for the given URB. |
1382 | * If the endpoint supports streams, boundary check the URB's stream ID. | |
1383 | * If the endpoint doesn't support streams, return the singular endpoint ring. | |
1384 | */ | |
1385 | static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, | |
1386 | struct urb *urb) | |
1387 | { | |
1388 | unsigned int slot_id; | |
1389 | unsigned int ep_index; | |
1390 | unsigned int stream_id; | |
1391 | struct xhci_virt_ep *ep; | |
1392 | ||
1393 | slot_id = urb->dev->slot_id; | |
1394 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); | |
1395 | stream_id = urb->stream_id; | |
1396 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
1397 | /* Common case: no streams */ | |
1398 | if (!(ep->ep_state & EP_HAS_STREAMS)) | |
1399 | return ep->ring; | |
1400 | ||
1401 | if (stream_id == 0) { | |
1402 | xhci_warn(xhci, | |
1403 | "WARN: Slot ID %u, ep index %u has streams, " | |
1404 | "but URB has no stream ID.\n", | |
1405 | slot_id, ep_index); | |
1406 | return NULL; | |
1407 | } | |
1408 | ||
1409 | if (stream_id < ep->stream_info->num_streams) | |
1410 | return ep->stream_info->stream_rings[stream_id]; | |
1411 | ||
1412 | xhci_warn(xhci, | |
1413 | "WARN: Slot ID %u, ep index %u has " | |
1414 | "stream IDs 1 to %u allocated, " | |
1415 | "but stream ID %u is requested.\n", | |
1416 | slot_id, ep_index, | |
1417 | ep->stream_info->num_streams - 1, | |
1418 | stream_id); | |
1419 | return NULL; | |
1420 | } | |
1421 | ||
ae636747 SS |
1422 | /* |
1423 | * Remove the URB's TD from the endpoint ring. This may cause the HC to stop | |
1424 | * USB transfers, potentially stopping in the middle of a TRB buffer. The HC | |
1425 | * should pick up where it left off in the TD, unless a Set Transfer Ring | |
1426 | * Dequeue Pointer is issued. | |
1427 | * | |
1428 | * The TRBs that make up the buffers for the canceled URB will be "removed" from | |
1429 | * the ring. Since the ring is a contiguous structure, they can't be physically | |
1430 | * removed. Instead, there are two options: | |
1431 | * | |
1432 | * 1) If the HC is in the middle of processing the URB to be canceled, we | |
1433 | * simply move the ring's dequeue pointer past those TRBs using the Set | |
1434 | * Transfer Ring Dequeue Pointer command. This will be the common case, | |
1435 | * when drivers timeout on the last submitted URB and attempt to cancel. | |
1436 | * | |
1437 | * 2) If the HC is in the middle of a different TD, we turn the TRBs into a | |
1438 | * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The | |
1439 | * HC will need to invalidate the any TRBs it has cached after the stop | |
1440 | * endpoint command, as noted in the xHCI 0.95 errata. | |
1441 | * | |
1442 | * 3) The TD may have completed by the time the Stop Endpoint Command | |
1443 | * completes, so software needs to handle that case too. | |
1444 | * | |
1445 | * This function should protect against the TD enqueueing code ringing the | |
1446 | * doorbell while this code is waiting for a Stop Endpoint command to complete. | |
1447 | * It also needs to account for multiple cancellations on happening at the same | |
1448 | * time for the same endpoint. | |
1449 | * | |
1450 | * Note that this function can be called in any context, or so says | |
1451 | * usb_hcd_unlink_urb() | |
d0e96f5a SS |
1452 | */ |
1453 | int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) | |
1454 | { | |
ae636747 | 1455 | unsigned long flags; |
8e51adcc | 1456 | int ret, i; |
e34b2fbf | 1457 | u32 temp; |
ae636747 | 1458 | struct xhci_hcd *xhci; |
8e51adcc | 1459 | struct urb_priv *urb_priv; |
ae636747 SS |
1460 | struct xhci_td *td; |
1461 | unsigned int ep_index; | |
1462 | struct xhci_ring *ep_ring; | |
63a0d9ab | 1463 | struct xhci_virt_ep *ep; |
ae636747 SS |
1464 | |
1465 | xhci = hcd_to_xhci(hcd); | |
1466 | spin_lock_irqsave(&xhci->lock, flags); | |
1467 | /* Make sure the URB hasn't completed or been unlinked already */ | |
1468 | ret = usb_hcd_check_unlink_urb(hcd, urb, status); | |
1469 | if (ret || !urb->hcpriv) | |
1470 | goto done; | |
b0ba9720 | 1471 | temp = readl(&xhci->op_regs->status); |
c6cc27c7 | 1472 | if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) { |
aa50b290 XR |
1473 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1474 | "HW died, freeing TD."); | |
8e51adcc | 1475 | urb_priv = urb->hcpriv; |
585df1d9 SS |
1476 | for (i = urb_priv->td_cnt; i < urb_priv->length; i++) { |
1477 | td = urb_priv->td[i]; | |
1478 | if (!list_empty(&td->td_list)) | |
1479 | list_del_init(&td->td_list); | |
1480 | if (!list_empty(&td->cancelled_td_list)) | |
1481 | list_del_init(&td->cancelled_td_list); | |
1482 | } | |
e34b2fbf SS |
1483 | |
1484 | usb_hcd_unlink_urb_from_ep(hcd, urb); | |
1485 | spin_unlock_irqrestore(&xhci->lock, flags); | |
214f76f7 | 1486 | usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN); |
8e51adcc | 1487 | xhci_urb_free_priv(xhci, urb_priv); |
e34b2fbf SS |
1488 | return ret; |
1489 | } | |
7bd89b40 SS |
1490 | if ((xhci->xhc_state & XHCI_STATE_DYING) || |
1491 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | |
aa50b290 XR |
1492 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1493 | "Ep 0x%x: URB %p to be canceled on " | |
1494 | "non-responsive xHCI host.", | |
6f5165cf SS |
1495 | urb->ep->desc.bEndpointAddress, urb); |
1496 | /* Let the stop endpoint command watchdog timer (which set this | |
1497 | * state) finish cleaning up the endpoint TD lists. We must | |
1498 | * have caught it in the middle of dropping a lock and giving | |
1499 | * back an URB. | |
1500 | */ | |
1501 | goto done; | |
1502 | } | |
ae636747 | 1503 | |
ae636747 | 1504 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); |
63a0d9ab | 1505 | ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index]; |
e9df17eb SS |
1506 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
1507 | if (!ep_ring) { | |
1508 | ret = -EINVAL; | |
1509 | goto done; | |
1510 | } | |
1511 | ||
8e51adcc | 1512 | urb_priv = urb->hcpriv; |
79688acf SS |
1513 | i = urb_priv->td_cnt; |
1514 | if (i < urb_priv->length) | |
aa50b290 XR |
1515 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1516 | "Cancel URB %p, dev %s, ep 0x%x, " | |
1517 | "starting at offset 0x%llx", | |
79688acf SS |
1518 | urb, urb->dev->devpath, |
1519 | urb->ep->desc.bEndpointAddress, | |
1520 | (unsigned long long) xhci_trb_virt_to_dma( | |
1521 | urb_priv->td[i]->start_seg, | |
1522 | urb_priv->td[i]->first_trb)); | |
1523 | ||
1524 | for (; i < urb_priv->length; i++) { | |
8e51adcc AX |
1525 | td = urb_priv->td[i]; |
1526 | list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list); | |
1527 | } | |
1528 | ||
ae636747 SS |
1529 | /* Queue a stop endpoint command, but only if this is |
1530 | * the first cancellation to be handled. | |
1531 | */ | |
678539cf SS |
1532 | if (!(ep->ep_state & EP_HALT_PENDING)) { |
1533 | ep->ep_state |= EP_HALT_PENDING; | |
6f5165cf SS |
1534 | ep->stop_cmds_pending++; |
1535 | ep->stop_cmd_timer.expires = jiffies + | |
1536 | XHCI_STOP_EP_CMD_TIMEOUT * HZ; | |
1537 | add_timer(&ep->stop_cmd_timer); | |
be88fe4f | 1538 | xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index, 0); |
23e3be11 | 1539 | xhci_ring_cmd_db(xhci); |
ae636747 SS |
1540 | } |
1541 | done: | |
1542 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1543 | return ret; | |
d0e96f5a SS |
1544 | } |
1545 | ||
f94e0186 SS |
1546 | /* Drop an endpoint from a new bandwidth configuration for this device. |
1547 | * Only one call to this function is allowed per endpoint before | |
1548 | * check_bandwidth() or reset_bandwidth() must be called. | |
1549 | * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will | |
1550 | * add the endpoint to the schedule with possibly new parameters denoted by a | |
1551 | * different endpoint descriptor in usb_host_endpoint. | |
1552 | * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is | |
1553 | * not allowed. | |
f88ba78d SS |
1554 | * |
1555 | * The USB core will not allow URBs to be queued to an endpoint that is being | |
1556 | * disabled, so there's no need for mutual exclusion to protect | |
1557 | * the xhci->devs[slot_id] structure. | |
f94e0186 SS |
1558 | */ |
1559 | int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, | |
1560 | struct usb_host_endpoint *ep) | |
1561 | { | |
f94e0186 | 1562 | struct xhci_hcd *xhci; |
d115b048 JY |
1563 | struct xhci_container_ctx *in_ctx, *out_ctx; |
1564 | struct xhci_input_control_ctx *ctrl_ctx; | |
1565 | struct xhci_slot_ctx *slot_ctx; | |
f94e0186 SS |
1566 | unsigned int last_ctx; |
1567 | unsigned int ep_index; | |
1568 | struct xhci_ep_ctx *ep_ctx; | |
1569 | u32 drop_flag; | |
1570 | u32 new_add_flags, new_drop_flags, new_slot_info; | |
1571 | int ret; | |
1572 | ||
64927730 | 1573 | ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); |
f94e0186 SS |
1574 | if (ret <= 0) |
1575 | return ret; | |
1576 | xhci = hcd_to_xhci(hcd); | |
fe6c6c13 SS |
1577 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1578 | return -ENODEV; | |
f94e0186 | 1579 | |
fe6c6c13 | 1580 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
1581 | drop_flag = xhci_get_endpoint_flag(&ep->desc); |
1582 | if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) { | |
1583 | xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n", | |
1584 | __func__, drop_flag); | |
1585 | return 0; | |
1586 | } | |
1587 | ||
f94e0186 | 1588 | in_ctx = xhci->devs[udev->slot_id]->in_ctx; |
d115b048 JY |
1589 | out_ctx = xhci->devs[udev->slot_id]->out_ctx; |
1590 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); | |
92f8e767 SS |
1591 | if (!ctrl_ctx) { |
1592 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1593 | __func__); | |
1594 | return 0; | |
1595 | } | |
1596 | ||
f94e0186 | 1597 | ep_index = xhci_get_endpoint_index(&ep->desc); |
d115b048 | 1598 | ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); |
f94e0186 SS |
1599 | /* If the HC already knows the endpoint is disabled, |
1600 | * or the HCD has noted it is disabled, ignore this request | |
1601 | */ | |
f5960b69 ME |
1602 | if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) == |
1603 | cpu_to_le32(EP_STATE_DISABLED)) || | |
28ccd296 ME |
1604 | le32_to_cpu(ctrl_ctx->drop_flags) & |
1605 | xhci_get_endpoint_flag(&ep->desc)) { | |
700e2052 GKH |
1606 | xhci_warn(xhci, "xHCI %s called with disabled ep %p\n", |
1607 | __func__, ep); | |
f94e0186 SS |
1608 | return 0; |
1609 | } | |
1610 | ||
28ccd296 ME |
1611 | ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag); |
1612 | new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
f94e0186 | 1613 | |
28ccd296 ME |
1614 | ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag); |
1615 | new_add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
f94e0186 | 1616 | |
28ccd296 | 1617 | last_ctx = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)); |
d115b048 | 1618 | slot_ctx = xhci_get_slot_ctx(xhci, in_ctx); |
f94e0186 | 1619 | /* Update the last valid endpoint context, if we deleted the last one */ |
28ccd296 ME |
1620 | if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) > |
1621 | LAST_CTX(last_ctx)) { | |
1622 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); | |
1623 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx)); | |
f94e0186 | 1624 | } |
28ccd296 | 1625 | new_slot_info = le32_to_cpu(slot_ctx->dev_info); |
f94e0186 SS |
1626 | |
1627 | xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep); | |
1628 | ||
f94e0186 SS |
1629 | xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n", |
1630 | (unsigned int) ep->desc.bEndpointAddress, | |
1631 | udev->slot_id, | |
1632 | (unsigned int) new_drop_flags, | |
1633 | (unsigned int) new_add_flags, | |
1634 | (unsigned int) new_slot_info); | |
1635 | return 0; | |
1636 | } | |
1637 | ||
1638 | /* Add an endpoint to a new possible bandwidth configuration for this device. | |
1639 | * Only one call to this function is allowed per endpoint before | |
1640 | * check_bandwidth() or reset_bandwidth() must be called. | |
1641 | * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will | |
1642 | * add the endpoint to the schedule with possibly new parameters denoted by a | |
1643 | * different endpoint descriptor in usb_host_endpoint. | |
1644 | * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is | |
1645 | * not allowed. | |
f88ba78d SS |
1646 | * |
1647 | * The USB core will not allow URBs to be queued to an endpoint until the | |
1648 | * configuration or alt setting is installed in the device, so there's no need | |
1649 | * for mutual exclusion to protect the xhci->devs[slot_id] structure. | |
f94e0186 SS |
1650 | */ |
1651 | int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, | |
1652 | struct usb_host_endpoint *ep) | |
1653 | { | |
f94e0186 | 1654 | struct xhci_hcd *xhci; |
d115b048 | 1655 | struct xhci_container_ctx *in_ctx, *out_ctx; |
f94e0186 | 1656 | unsigned int ep_index; |
d115b048 JY |
1657 | struct xhci_slot_ctx *slot_ctx; |
1658 | struct xhci_input_control_ctx *ctrl_ctx; | |
f94e0186 SS |
1659 | u32 added_ctxs; |
1660 | unsigned int last_ctx; | |
1661 | u32 new_add_flags, new_drop_flags, new_slot_info; | |
fa75ac37 | 1662 | struct xhci_virt_device *virt_dev; |
f94e0186 SS |
1663 | int ret = 0; |
1664 | ||
64927730 | 1665 | ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); |
a1587d97 SS |
1666 | if (ret <= 0) { |
1667 | /* So we won't queue a reset ep command for a root hub */ | |
1668 | ep->hcpriv = NULL; | |
f94e0186 | 1669 | return ret; |
a1587d97 | 1670 | } |
f94e0186 | 1671 | xhci = hcd_to_xhci(hcd); |
fe6c6c13 SS |
1672 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1673 | return -ENODEV; | |
f94e0186 SS |
1674 | |
1675 | added_ctxs = xhci_get_endpoint_flag(&ep->desc); | |
1676 | last_ctx = xhci_last_valid_endpoint(added_ctxs); | |
1677 | if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) { | |
1678 | /* FIXME when we have to issue an evaluate endpoint command to | |
1679 | * deal with ep0 max packet size changing once we get the | |
1680 | * descriptors | |
1681 | */ | |
1682 | xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n", | |
1683 | __func__, added_ctxs); | |
1684 | return 0; | |
1685 | } | |
1686 | ||
fa75ac37 SS |
1687 | virt_dev = xhci->devs[udev->slot_id]; |
1688 | in_ctx = virt_dev->in_ctx; | |
1689 | out_ctx = virt_dev->out_ctx; | |
d115b048 | 1690 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); |
92f8e767 SS |
1691 | if (!ctrl_ctx) { |
1692 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1693 | __func__); | |
1694 | return 0; | |
1695 | } | |
fa75ac37 | 1696 | |
92f8e767 | 1697 | ep_index = xhci_get_endpoint_index(&ep->desc); |
fa75ac37 SS |
1698 | /* If this endpoint is already in use, and the upper layers are trying |
1699 | * to add it again without dropping it, reject the addition. | |
1700 | */ | |
1701 | if (virt_dev->eps[ep_index].ring && | |
1702 | !(le32_to_cpu(ctrl_ctx->drop_flags) & | |
1703 | xhci_get_endpoint_flag(&ep->desc))) { | |
1704 | xhci_warn(xhci, "Trying to add endpoint 0x%x " | |
1705 | "without dropping it.\n", | |
1706 | (unsigned int) ep->desc.bEndpointAddress); | |
1707 | return -EINVAL; | |
1708 | } | |
1709 | ||
f94e0186 SS |
1710 | /* If the HCD has already noted the endpoint is enabled, |
1711 | * ignore this request. | |
1712 | */ | |
28ccd296 ME |
1713 | if (le32_to_cpu(ctrl_ctx->add_flags) & |
1714 | xhci_get_endpoint_flag(&ep->desc)) { | |
700e2052 GKH |
1715 | xhci_warn(xhci, "xHCI %s called with enabled ep %p\n", |
1716 | __func__, ep); | |
f94e0186 SS |
1717 | return 0; |
1718 | } | |
1719 | ||
f88ba78d SS |
1720 | /* |
1721 | * Configuration and alternate setting changes must be done in | |
1722 | * process context, not interrupt context (or so documenation | |
1723 | * for usb_set_interface() and usb_set_configuration() claim). | |
1724 | */ | |
fa75ac37 | 1725 | if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) { |
f94e0186 SS |
1726 | dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n", |
1727 | __func__, ep->desc.bEndpointAddress); | |
f94e0186 SS |
1728 | return -ENOMEM; |
1729 | } | |
1730 | ||
28ccd296 ME |
1731 | ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs); |
1732 | new_add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
f94e0186 SS |
1733 | |
1734 | /* If xhci_endpoint_disable() was called for this endpoint, but the | |
1735 | * xHC hasn't been notified yet through the check_bandwidth() call, | |
1736 | * this re-adds a new state for the endpoint from the new endpoint | |
1737 | * descriptors. We must drop and re-add this endpoint, so we leave the | |
1738 | * drop flags alone. | |
1739 | */ | |
28ccd296 | 1740 | new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); |
f94e0186 | 1741 | |
d115b048 | 1742 | slot_ctx = xhci_get_slot_ctx(xhci, in_ctx); |
f94e0186 | 1743 | /* Update the last valid endpoint context, if we just added one past */ |
28ccd296 ME |
1744 | if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) < |
1745 | LAST_CTX(last_ctx)) { | |
1746 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); | |
1747 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx)); | |
f94e0186 | 1748 | } |
28ccd296 | 1749 | new_slot_info = le32_to_cpu(slot_ctx->dev_info); |
f94e0186 | 1750 | |
a1587d97 SS |
1751 | /* Store the usb_device pointer for later use */ |
1752 | ep->hcpriv = udev; | |
1753 | ||
f94e0186 SS |
1754 | xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n", |
1755 | (unsigned int) ep->desc.bEndpointAddress, | |
1756 | udev->slot_id, | |
1757 | (unsigned int) new_drop_flags, | |
1758 | (unsigned int) new_add_flags, | |
1759 | (unsigned int) new_slot_info); | |
1760 | return 0; | |
1761 | } | |
1762 | ||
d115b048 | 1763 | static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev) |
f94e0186 | 1764 | { |
d115b048 | 1765 | struct xhci_input_control_ctx *ctrl_ctx; |
f94e0186 | 1766 | struct xhci_ep_ctx *ep_ctx; |
d115b048 | 1767 | struct xhci_slot_ctx *slot_ctx; |
f94e0186 SS |
1768 | int i; |
1769 | ||
92f8e767 SS |
1770 | ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx); |
1771 | if (!ctrl_ctx) { | |
1772 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1773 | __func__); | |
1774 | return; | |
1775 | } | |
1776 | ||
f94e0186 SS |
1777 | /* When a device's add flag and drop flag are zero, any subsequent |
1778 | * configure endpoint command will leave that endpoint's state | |
1779 | * untouched. Make sure we don't leave any old state in the input | |
1780 | * endpoint contexts. | |
1781 | */ | |
d115b048 JY |
1782 | ctrl_ctx->drop_flags = 0; |
1783 | ctrl_ctx->add_flags = 0; | |
1784 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); | |
28ccd296 | 1785 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); |
f94e0186 | 1786 | /* Endpoint 0 is always valid */ |
28ccd296 | 1787 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1)); |
f94e0186 | 1788 | for (i = 1; i < 31; ++i) { |
d115b048 | 1789 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i); |
f94e0186 SS |
1790 | ep_ctx->ep_info = 0; |
1791 | ep_ctx->ep_info2 = 0; | |
8e595a5d | 1792 | ep_ctx->deq = 0; |
f94e0186 SS |
1793 | ep_ctx->tx_info = 0; |
1794 | } | |
1795 | } | |
1796 | ||
f2217e8e | 1797 | static int xhci_configure_endpoint_result(struct xhci_hcd *xhci, |
00161f7d | 1798 | struct usb_device *udev, u32 *cmd_status) |
f2217e8e SS |
1799 | { |
1800 | int ret; | |
1801 | ||
913a8a34 | 1802 | switch (*cmd_status) { |
f2217e8e SS |
1803 | case COMP_ENOMEM: |
1804 | dev_warn(&udev->dev, "Not enough host controller resources " | |
1805 | "for new device state.\n"); | |
1806 | ret = -ENOMEM; | |
1807 | /* FIXME: can we allocate more resources for the HC? */ | |
1808 | break; | |
1809 | case COMP_BW_ERR: | |
71d85724 | 1810 | case COMP_2ND_BW_ERR: |
f2217e8e SS |
1811 | dev_warn(&udev->dev, "Not enough bandwidth " |
1812 | "for new device state.\n"); | |
1813 | ret = -ENOSPC; | |
1814 | /* FIXME: can we go back to the old state? */ | |
1815 | break; | |
1816 | case COMP_TRB_ERR: | |
1817 | /* the HCD set up something wrong */ | |
1818 | dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, " | |
1819 | "add flag = 1, " | |
1820 | "and endpoint is not disabled.\n"); | |
1821 | ret = -EINVAL; | |
1822 | break; | |
f6ba6fe2 AH |
1823 | case COMP_DEV_ERR: |
1824 | dev_warn(&udev->dev, "ERROR: Incompatible device for endpoint " | |
1825 | "configure command.\n"); | |
1826 | ret = -ENODEV; | |
1827 | break; | |
f2217e8e | 1828 | case COMP_SUCCESS: |
3a7fa5be XR |
1829 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1830 | "Successful Endpoint Configure command"); | |
f2217e8e SS |
1831 | ret = 0; |
1832 | break; | |
1833 | default: | |
1834 | xhci_err(xhci, "ERROR: unexpected command completion " | |
913a8a34 | 1835 | "code 0x%x.\n", *cmd_status); |
f2217e8e SS |
1836 | ret = -EINVAL; |
1837 | break; | |
1838 | } | |
1839 | return ret; | |
1840 | } | |
1841 | ||
1842 | static int xhci_evaluate_context_result(struct xhci_hcd *xhci, | |
00161f7d | 1843 | struct usb_device *udev, u32 *cmd_status) |
f2217e8e SS |
1844 | { |
1845 | int ret; | |
913a8a34 | 1846 | struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id]; |
f2217e8e | 1847 | |
913a8a34 | 1848 | switch (*cmd_status) { |
f2217e8e SS |
1849 | case COMP_EINVAL: |
1850 | dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate " | |
1851 | "context command.\n"); | |
1852 | ret = -EINVAL; | |
1853 | break; | |
1854 | case COMP_EBADSLT: | |
1855 | dev_warn(&udev->dev, "WARN: slot not enabled for" | |
1856 | "evaluate context command.\n"); | |
b8031342 SS |
1857 | ret = -EINVAL; |
1858 | break; | |
f2217e8e SS |
1859 | case COMP_CTX_STATE: |
1860 | dev_warn(&udev->dev, "WARN: invalid context state for " | |
1861 | "evaluate context command.\n"); | |
1862 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1); | |
1863 | ret = -EINVAL; | |
1864 | break; | |
f6ba6fe2 AH |
1865 | case COMP_DEV_ERR: |
1866 | dev_warn(&udev->dev, "ERROR: Incompatible device for evaluate " | |
1867 | "context command.\n"); | |
1868 | ret = -ENODEV; | |
1869 | break; | |
1bb73a88 AH |
1870 | case COMP_MEL_ERR: |
1871 | /* Max Exit Latency too large error */ | |
1872 | dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n"); | |
1873 | ret = -EINVAL; | |
1874 | break; | |
f2217e8e | 1875 | case COMP_SUCCESS: |
3a7fa5be XR |
1876 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1877 | "Successful evaluate context command"); | |
f2217e8e SS |
1878 | ret = 0; |
1879 | break; | |
1880 | default: | |
1881 | xhci_err(xhci, "ERROR: unexpected command completion " | |
913a8a34 | 1882 | "code 0x%x.\n", *cmd_status); |
f2217e8e SS |
1883 | ret = -EINVAL; |
1884 | break; | |
1885 | } | |
1886 | return ret; | |
1887 | } | |
1888 | ||
2cf95c18 | 1889 | static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci, |
92f8e767 | 1890 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 | 1891 | { |
2cf95c18 SS |
1892 | u32 valid_add_flags; |
1893 | u32 valid_drop_flags; | |
1894 | ||
2cf95c18 SS |
1895 | /* Ignore the slot flag (bit 0), and the default control endpoint flag |
1896 | * (bit 1). The default control endpoint is added during the Address | |
1897 | * Device command and is never removed until the slot is disabled. | |
1898 | */ | |
ef73400c XR |
1899 | valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2; |
1900 | valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2; | |
2cf95c18 SS |
1901 | |
1902 | /* Use hweight32 to count the number of ones in the add flags, or | |
1903 | * number of endpoints added. Don't count endpoints that are changed | |
1904 | * (both added and dropped). | |
1905 | */ | |
1906 | return hweight32(valid_add_flags) - | |
1907 | hweight32(valid_add_flags & valid_drop_flags); | |
1908 | } | |
1909 | ||
1910 | static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci, | |
92f8e767 | 1911 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 | 1912 | { |
2cf95c18 SS |
1913 | u32 valid_add_flags; |
1914 | u32 valid_drop_flags; | |
1915 | ||
78d1ff02 XR |
1916 | valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2; |
1917 | valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2; | |
2cf95c18 SS |
1918 | |
1919 | return hweight32(valid_drop_flags) - | |
1920 | hweight32(valid_add_flags & valid_drop_flags); | |
1921 | } | |
1922 | ||
1923 | /* | |
1924 | * We need to reserve the new number of endpoints before the configure endpoint | |
1925 | * command completes. We can't subtract the dropped endpoints from the number | |
1926 | * of active endpoints until the command completes because we can oversubscribe | |
1927 | * the host in this case: | |
1928 | * | |
1929 | * - the first configure endpoint command drops more endpoints than it adds | |
1930 | * - a second configure endpoint command that adds more endpoints is queued | |
1931 | * - the first configure endpoint command fails, so the config is unchanged | |
1932 | * - the second command may succeed, even though there isn't enough resources | |
1933 | * | |
1934 | * Must be called with xhci->lock held. | |
1935 | */ | |
1936 | static int xhci_reserve_host_resources(struct xhci_hcd *xhci, | |
92f8e767 | 1937 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
1938 | { |
1939 | u32 added_eps; | |
1940 | ||
92f8e767 | 1941 | added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx); |
2cf95c18 | 1942 | if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) { |
4bdfe4c3 XR |
1943 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1944 | "Not enough ep ctxs: " | |
1945 | "%u active, need to add %u, limit is %u.", | |
2cf95c18 SS |
1946 | xhci->num_active_eps, added_eps, |
1947 | xhci->limit_active_eps); | |
1948 | return -ENOMEM; | |
1949 | } | |
1950 | xhci->num_active_eps += added_eps; | |
4bdfe4c3 XR |
1951 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1952 | "Adding %u ep ctxs, %u now active.", added_eps, | |
2cf95c18 SS |
1953 | xhci->num_active_eps); |
1954 | return 0; | |
1955 | } | |
1956 | ||
1957 | /* | |
1958 | * The configure endpoint was failed by the xHC for some other reason, so we | |
1959 | * need to revert the resources that failed configuration would have used. | |
1960 | * | |
1961 | * Must be called with xhci->lock held. | |
1962 | */ | |
1963 | static void xhci_free_host_resources(struct xhci_hcd *xhci, | |
92f8e767 | 1964 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
1965 | { |
1966 | u32 num_failed_eps; | |
1967 | ||
92f8e767 | 1968 | num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx); |
2cf95c18 | 1969 | xhci->num_active_eps -= num_failed_eps; |
4bdfe4c3 XR |
1970 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1971 | "Removing %u failed ep ctxs, %u now active.", | |
2cf95c18 SS |
1972 | num_failed_eps, |
1973 | xhci->num_active_eps); | |
1974 | } | |
1975 | ||
1976 | /* | |
1977 | * Now that the command has completed, clean up the active endpoint count by | |
1978 | * subtracting out the endpoints that were dropped (but not changed). | |
1979 | * | |
1980 | * Must be called with xhci->lock held. | |
1981 | */ | |
1982 | static void xhci_finish_resource_reservation(struct xhci_hcd *xhci, | |
92f8e767 | 1983 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
1984 | { |
1985 | u32 num_dropped_eps; | |
1986 | ||
92f8e767 | 1987 | num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx); |
2cf95c18 SS |
1988 | xhci->num_active_eps -= num_dropped_eps; |
1989 | if (num_dropped_eps) | |
4bdfe4c3 XR |
1990 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1991 | "Removing %u dropped ep ctxs, %u now active.", | |
2cf95c18 SS |
1992 | num_dropped_eps, |
1993 | xhci->num_active_eps); | |
1994 | } | |
1995 | ||
ed384bd3 | 1996 | static unsigned int xhci_get_block_size(struct usb_device *udev) |
c29eea62 SS |
1997 | { |
1998 | switch (udev->speed) { | |
1999 | case USB_SPEED_LOW: | |
2000 | case USB_SPEED_FULL: | |
2001 | return FS_BLOCK; | |
2002 | case USB_SPEED_HIGH: | |
2003 | return HS_BLOCK; | |
2004 | case USB_SPEED_SUPER: | |
2005 | return SS_BLOCK; | |
2006 | case USB_SPEED_UNKNOWN: | |
2007 | case USB_SPEED_WIRELESS: | |
2008 | default: | |
2009 | /* Should never happen */ | |
2010 | return 1; | |
2011 | } | |
2012 | } | |
2013 | ||
ed384bd3 FB |
2014 | static unsigned int |
2015 | xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw) | |
c29eea62 SS |
2016 | { |
2017 | if (interval_bw->overhead[LS_OVERHEAD_TYPE]) | |
2018 | return LS_OVERHEAD; | |
2019 | if (interval_bw->overhead[FS_OVERHEAD_TYPE]) | |
2020 | return FS_OVERHEAD; | |
2021 | return HS_OVERHEAD; | |
2022 | } | |
2023 | ||
2024 | /* If we are changing a LS/FS device under a HS hub, | |
2025 | * make sure (if we are activating a new TT) that the HS bus has enough | |
2026 | * bandwidth for this new TT. | |
2027 | */ | |
2028 | static int xhci_check_tt_bw_table(struct xhci_hcd *xhci, | |
2029 | struct xhci_virt_device *virt_dev, | |
2030 | int old_active_eps) | |
2031 | { | |
2032 | struct xhci_interval_bw_table *bw_table; | |
2033 | struct xhci_tt_bw_info *tt_info; | |
2034 | ||
2035 | /* Find the bandwidth table for the root port this TT is attached to. */ | |
2036 | bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table; | |
2037 | tt_info = virt_dev->tt_info; | |
2038 | /* If this TT already had active endpoints, the bandwidth for this TT | |
2039 | * has already been added. Removing all periodic endpoints (and thus | |
2040 | * making the TT enactive) will only decrease the bandwidth used. | |
2041 | */ | |
2042 | if (old_active_eps) | |
2043 | return 0; | |
2044 | if (old_active_eps == 0 && tt_info->active_eps != 0) { | |
2045 | if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT) | |
2046 | return -ENOMEM; | |
2047 | return 0; | |
2048 | } | |
2049 | /* Not sure why we would have no new active endpoints... | |
2050 | * | |
2051 | * Maybe because of an Evaluate Context change for a hub update or a | |
2052 | * control endpoint 0 max packet size change? | |
2053 | * FIXME: skip the bandwidth calculation in that case. | |
2054 | */ | |
2055 | return 0; | |
2056 | } | |
2057 | ||
2b698999 SS |
2058 | static int xhci_check_ss_bw(struct xhci_hcd *xhci, |
2059 | struct xhci_virt_device *virt_dev) | |
2060 | { | |
2061 | unsigned int bw_reserved; | |
2062 | ||
2063 | bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100); | |
2064 | if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved)) | |
2065 | return -ENOMEM; | |
2066 | ||
2067 | bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100); | |
2068 | if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved)) | |
2069 | return -ENOMEM; | |
2070 | ||
2071 | return 0; | |
2072 | } | |
2073 | ||
c29eea62 SS |
2074 | /* |
2075 | * This algorithm is a very conservative estimate of the worst-case scheduling | |
2076 | * scenario for any one interval. The hardware dynamically schedules the | |
2077 | * packets, so we can't tell which microframe could be the limiting factor in | |
2078 | * the bandwidth scheduling. This only takes into account periodic endpoints. | |
2079 | * | |
2080 | * Obviously, we can't solve an NP complete problem to find the minimum worst | |
2081 | * case scenario. Instead, we come up with an estimate that is no less than | |
2082 | * the worst case bandwidth used for any one microframe, but may be an | |
2083 | * over-estimate. | |
2084 | * | |
2085 | * We walk the requirements for each endpoint by interval, starting with the | |
2086 | * smallest interval, and place packets in the schedule where there is only one | |
2087 | * possible way to schedule packets for that interval. In order to simplify | |
2088 | * this algorithm, we record the largest max packet size for each interval, and | |
2089 | * assume all packets will be that size. | |
2090 | * | |
2091 | * For interval 0, we obviously must schedule all packets for each interval. | |
2092 | * The bandwidth for interval 0 is just the amount of data to be transmitted | |
2093 | * (the sum of all max ESIT payload sizes, plus any overhead per packet times | |
2094 | * the number of packets). | |
2095 | * | |
2096 | * For interval 1, we have two possible microframes to schedule those packets | |
2097 | * in. For this algorithm, if we can schedule the same number of packets for | |
2098 | * each possible scheduling opportunity (each microframe), we will do so. The | |
2099 | * remaining number of packets will be saved to be transmitted in the gaps in | |
2100 | * the next interval's scheduling sequence. | |
2101 | * | |
2102 | * As we move those remaining packets to be scheduled with interval 2 packets, | |
2103 | * we have to double the number of remaining packets to transmit. This is | |
2104 | * because the intervals are actually powers of 2, and we would be transmitting | |
2105 | * the previous interval's packets twice in this interval. We also have to be | |
2106 | * sure that when we look at the largest max packet size for this interval, we | |
2107 | * also look at the largest max packet size for the remaining packets and take | |
2108 | * the greater of the two. | |
2109 | * | |
2110 | * The algorithm continues to evenly distribute packets in each scheduling | |
2111 | * opportunity, and push the remaining packets out, until we get to the last | |
2112 | * interval. Then those packets and their associated overhead are just added | |
2113 | * to the bandwidth used. | |
2e27980e SS |
2114 | */ |
2115 | static int xhci_check_bw_table(struct xhci_hcd *xhci, | |
2116 | struct xhci_virt_device *virt_dev, | |
2117 | int old_active_eps) | |
2118 | { | |
c29eea62 SS |
2119 | unsigned int bw_reserved; |
2120 | unsigned int max_bandwidth; | |
2121 | unsigned int bw_used; | |
2122 | unsigned int block_size; | |
2123 | struct xhci_interval_bw_table *bw_table; | |
2124 | unsigned int packet_size = 0; | |
2125 | unsigned int overhead = 0; | |
2126 | unsigned int packets_transmitted = 0; | |
2127 | unsigned int packets_remaining = 0; | |
2128 | unsigned int i; | |
2129 | ||
2b698999 SS |
2130 | if (virt_dev->udev->speed == USB_SPEED_SUPER) |
2131 | return xhci_check_ss_bw(xhci, virt_dev); | |
2132 | ||
c29eea62 SS |
2133 | if (virt_dev->udev->speed == USB_SPEED_HIGH) { |
2134 | max_bandwidth = HS_BW_LIMIT; | |
2135 | /* Convert percent of bus BW reserved to blocks reserved */ | |
2136 | bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100); | |
2137 | } else { | |
2138 | max_bandwidth = FS_BW_LIMIT; | |
2139 | bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100); | |
2140 | } | |
2141 | ||
2142 | bw_table = virt_dev->bw_table; | |
2143 | /* We need to translate the max packet size and max ESIT payloads into | |
2144 | * the units the hardware uses. | |
2145 | */ | |
2146 | block_size = xhci_get_block_size(virt_dev->udev); | |
2147 | ||
2148 | /* If we are manipulating a LS/FS device under a HS hub, double check | |
2149 | * that the HS bus has enough bandwidth if we are activing a new TT. | |
2150 | */ | |
2151 | if (virt_dev->tt_info) { | |
4bdfe4c3 XR |
2152 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2153 | "Recalculating BW for rootport %u", | |
c29eea62 SS |
2154 | virt_dev->real_port); |
2155 | if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) { | |
2156 | xhci_warn(xhci, "Not enough bandwidth on HS bus for " | |
2157 | "newly activated TT.\n"); | |
2158 | return -ENOMEM; | |
2159 | } | |
4bdfe4c3 XR |
2160 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2161 | "Recalculating BW for TT slot %u port %u", | |
c29eea62 SS |
2162 | virt_dev->tt_info->slot_id, |
2163 | virt_dev->tt_info->ttport); | |
2164 | } else { | |
4bdfe4c3 XR |
2165 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2166 | "Recalculating BW for rootport %u", | |
c29eea62 SS |
2167 | virt_dev->real_port); |
2168 | } | |
2169 | ||
2170 | /* Add in how much bandwidth will be used for interval zero, or the | |
2171 | * rounded max ESIT payload + number of packets * largest overhead. | |
2172 | */ | |
2173 | bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) + | |
2174 | bw_table->interval_bw[0].num_packets * | |
2175 | xhci_get_largest_overhead(&bw_table->interval_bw[0]); | |
2176 | ||
2177 | for (i = 1; i < XHCI_MAX_INTERVAL; i++) { | |
2178 | unsigned int bw_added; | |
2179 | unsigned int largest_mps; | |
2180 | unsigned int interval_overhead; | |
2181 | ||
2182 | /* | |
2183 | * How many packets could we transmit in this interval? | |
2184 | * If packets didn't fit in the previous interval, we will need | |
2185 | * to transmit that many packets twice within this interval. | |
2186 | */ | |
2187 | packets_remaining = 2 * packets_remaining + | |
2188 | bw_table->interval_bw[i].num_packets; | |
2189 | ||
2190 | /* Find the largest max packet size of this or the previous | |
2191 | * interval. | |
2192 | */ | |
2193 | if (list_empty(&bw_table->interval_bw[i].endpoints)) | |
2194 | largest_mps = 0; | |
2195 | else { | |
2196 | struct xhci_virt_ep *virt_ep; | |
2197 | struct list_head *ep_entry; | |
2198 | ||
2199 | ep_entry = bw_table->interval_bw[i].endpoints.next; | |
2200 | virt_ep = list_entry(ep_entry, | |
2201 | struct xhci_virt_ep, bw_endpoint_list); | |
2202 | /* Convert to blocks, rounding up */ | |
2203 | largest_mps = DIV_ROUND_UP( | |
2204 | virt_ep->bw_info.max_packet_size, | |
2205 | block_size); | |
2206 | } | |
2207 | if (largest_mps > packet_size) | |
2208 | packet_size = largest_mps; | |
2209 | ||
2210 | /* Use the larger overhead of this or the previous interval. */ | |
2211 | interval_overhead = xhci_get_largest_overhead( | |
2212 | &bw_table->interval_bw[i]); | |
2213 | if (interval_overhead > overhead) | |
2214 | overhead = interval_overhead; | |
2215 | ||
2216 | /* How many packets can we evenly distribute across | |
2217 | * (1 << (i + 1)) possible scheduling opportunities? | |
2218 | */ | |
2219 | packets_transmitted = packets_remaining >> (i + 1); | |
2220 | ||
2221 | /* Add in the bandwidth used for those scheduled packets */ | |
2222 | bw_added = packets_transmitted * (overhead + packet_size); | |
2223 | ||
2224 | /* How many packets do we have remaining to transmit? */ | |
2225 | packets_remaining = packets_remaining % (1 << (i + 1)); | |
2226 | ||
2227 | /* What largest max packet size should those packets have? */ | |
2228 | /* If we've transmitted all packets, don't carry over the | |
2229 | * largest packet size. | |
2230 | */ | |
2231 | if (packets_remaining == 0) { | |
2232 | packet_size = 0; | |
2233 | overhead = 0; | |
2234 | } else if (packets_transmitted > 0) { | |
2235 | /* Otherwise if we do have remaining packets, and we've | |
2236 | * scheduled some packets in this interval, take the | |
2237 | * largest max packet size from endpoints with this | |
2238 | * interval. | |
2239 | */ | |
2240 | packet_size = largest_mps; | |
2241 | overhead = interval_overhead; | |
2242 | } | |
2243 | /* Otherwise carry over packet_size and overhead from the last | |
2244 | * time we had a remainder. | |
2245 | */ | |
2246 | bw_used += bw_added; | |
2247 | if (bw_used > max_bandwidth) { | |
2248 | xhci_warn(xhci, "Not enough bandwidth. " | |
2249 | "Proposed: %u, Max: %u\n", | |
2250 | bw_used, max_bandwidth); | |
2251 | return -ENOMEM; | |
2252 | } | |
2253 | } | |
2254 | /* | |
2255 | * Ok, we know we have some packets left over after even-handedly | |
2256 | * scheduling interval 15. We don't know which microframes they will | |
2257 | * fit into, so we over-schedule and say they will be scheduled every | |
2258 | * microframe. | |
2259 | */ | |
2260 | if (packets_remaining > 0) | |
2261 | bw_used += overhead + packet_size; | |
2262 | ||
2263 | if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) { | |
2264 | unsigned int port_index = virt_dev->real_port - 1; | |
2265 | ||
2266 | /* OK, we're manipulating a HS device attached to a | |
2267 | * root port bandwidth domain. Include the number of active TTs | |
2268 | * in the bandwidth used. | |
2269 | */ | |
2270 | bw_used += TT_HS_OVERHEAD * | |
2271 | xhci->rh_bw[port_index].num_active_tts; | |
2272 | } | |
2273 | ||
4bdfe4c3 XR |
2274 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2275 | "Final bandwidth: %u, Limit: %u, Reserved: %u, " | |
2276 | "Available: %u " "percent", | |
c29eea62 SS |
2277 | bw_used, max_bandwidth, bw_reserved, |
2278 | (max_bandwidth - bw_used - bw_reserved) * 100 / | |
2279 | max_bandwidth); | |
2280 | ||
2281 | bw_used += bw_reserved; | |
2282 | if (bw_used > max_bandwidth) { | |
2283 | xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n", | |
2284 | bw_used, max_bandwidth); | |
2285 | return -ENOMEM; | |
2286 | } | |
2287 | ||
2288 | bw_table->bw_used = bw_used; | |
2e27980e SS |
2289 | return 0; |
2290 | } | |
2291 | ||
2292 | static bool xhci_is_async_ep(unsigned int ep_type) | |
2293 | { | |
2294 | return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP && | |
2295 | ep_type != ISOC_IN_EP && | |
2296 | ep_type != INT_IN_EP); | |
2297 | } | |
2298 | ||
2b698999 SS |
2299 | static bool xhci_is_sync_in_ep(unsigned int ep_type) |
2300 | { | |
392a07ae | 2301 | return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP); |
2b698999 SS |
2302 | } |
2303 | ||
2304 | static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw) | |
2305 | { | |
2306 | unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK); | |
2307 | ||
2308 | if (ep_bw->ep_interval == 0) | |
2309 | return SS_OVERHEAD_BURST + | |
2310 | (ep_bw->mult * ep_bw->num_packets * | |
2311 | (SS_OVERHEAD + mps)); | |
2312 | return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets * | |
2313 | (SS_OVERHEAD + mps + SS_OVERHEAD_BURST), | |
2314 | 1 << ep_bw->ep_interval); | |
2315 | ||
2316 | } | |
2317 | ||
2e27980e SS |
2318 | void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, |
2319 | struct xhci_bw_info *ep_bw, | |
2320 | struct xhci_interval_bw_table *bw_table, | |
2321 | struct usb_device *udev, | |
2322 | struct xhci_virt_ep *virt_ep, | |
2323 | struct xhci_tt_bw_info *tt_info) | |
2324 | { | |
2325 | struct xhci_interval_bw *interval_bw; | |
2326 | int normalized_interval; | |
2327 | ||
2b698999 | 2328 | if (xhci_is_async_ep(ep_bw->type)) |
2e27980e SS |
2329 | return; |
2330 | ||
2b698999 SS |
2331 | if (udev->speed == USB_SPEED_SUPER) { |
2332 | if (xhci_is_sync_in_ep(ep_bw->type)) | |
2333 | xhci->devs[udev->slot_id]->bw_table->ss_bw_in -= | |
2334 | xhci_get_ss_bw_consumed(ep_bw); | |
2335 | else | |
2336 | xhci->devs[udev->slot_id]->bw_table->ss_bw_out -= | |
2337 | xhci_get_ss_bw_consumed(ep_bw); | |
2338 | return; | |
2339 | } | |
2340 | ||
2341 | /* SuperSpeed endpoints never get added to intervals in the table, so | |
2342 | * this check is only valid for HS/FS/LS devices. | |
2343 | */ | |
2344 | if (list_empty(&virt_ep->bw_endpoint_list)) | |
2345 | return; | |
2e27980e SS |
2346 | /* For LS/FS devices, we need to translate the interval expressed in |
2347 | * microframes to frames. | |
2348 | */ | |
2349 | if (udev->speed == USB_SPEED_HIGH) | |
2350 | normalized_interval = ep_bw->ep_interval; | |
2351 | else | |
2352 | normalized_interval = ep_bw->ep_interval - 3; | |
2353 | ||
2354 | if (normalized_interval == 0) | |
2355 | bw_table->interval0_esit_payload -= ep_bw->max_esit_payload; | |
2356 | interval_bw = &bw_table->interval_bw[normalized_interval]; | |
2357 | interval_bw->num_packets -= ep_bw->num_packets; | |
2358 | switch (udev->speed) { | |
2359 | case USB_SPEED_LOW: | |
2360 | interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1; | |
2361 | break; | |
2362 | case USB_SPEED_FULL: | |
2363 | interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1; | |
2364 | break; | |
2365 | case USB_SPEED_HIGH: | |
2366 | interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1; | |
2367 | break; | |
2368 | case USB_SPEED_SUPER: | |
2369 | case USB_SPEED_UNKNOWN: | |
2370 | case USB_SPEED_WIRELESS: | |
2371 | /* Should never happen because only LS/FS/HS endpoints will get | |
2372 | * added to the endpoint list. | |
2373 | */ | |
2374 | return; | |
2375 | } | |
2376 | if (tt_info) | |
2377 | tt_info->active_eps -= 1; | |
2378 | list_del_init(&virt_ep->bw_endpoint_list); | |
2379 | } | |
2380 | ||
2381 | static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci, | |
2382 | struct xhci_bw_info *ep_bw, | |
2383 | struct xhci_interval_bw_table *bw_table, | |
2384 | struct usb_device *udev, | |
2385 | struct xhci_virt_ep *virt_ep, | |
2386 | struct xhci_tt_bw_info *tt_info) | |
2387 | { | |
2388 | struct xhci_interval_bw *interval_bw; | |
2389 | struct xhci_virt_ep *smaller_ep; | |
2390 | int normalized_interval; | |
2391 | ||
2392 | if (xhci_is_async_ep(ep_bw->type)) | |
2393 | return; | |
2394 | ||
2b698999 SS |
2395 | if (udev->speed == USB_SPEED_SUPER) { |
2396 | if (xhci_is_sync_in_ep(ep_bw->type)) | |
2397 | xhci->devs[udev->slot_id]->bw_table->ss_bw_in += | |
2398 | xhci_get_ss_bw_consumed(ep_bw); | |
2399 | else | |
2400 | xhci->devs[udev->slot_id]->bw_table->ss_bw_out += | |
2401 | xhci_get_ss_bw_consumed(ep_bw); | |
2402 | return; | |
2403 | } | |
2404 | ||
2e27980e SS |
2405 | /* For LS/FS devices, we need to translate the interval expressed in |
2406 | * microframes to frames. | |
2407 | */ | |
2408 | if (udev->speed == USB_SPEED_HIGH) | |
2409 | normalized_interval = ep_bw->ep_interval; | |
2410 | else | |
2411 | normalized_interval = ep_bw->ep_interval - 3; | |
2412 | ||
2413 | if (normalized_interval == 0) | |
2414 | bw_table->interval0_esit_payload += ep_bw->max_esit_payload; | |
2415 | interval_bw = &bw_table->interval_bw[normalized_interval]; | |
2416 | interval_bw->num_packets += ep_bw->num_packets; | |
2417 | switch (udev->speed) { | |
2418 | case USB_SPEED_LOW: | |
2419 | interval_bw->overhead[LS_OVERHEAD_TYPE] += 1; | |
2420 | break; | |
2421 | case USB_SPEED_FULL: | |
2422 | interval_bw->overhead[FS_OVERHEAD_TYPE] += 1; | |
2423 | break; | |
2424 | case USB_SPEED_HIGH: | |
2425 | interval_bw->overhead[HS_OVERHEAD_TYPE] += 1; | |
2426 | break; | |
2427 | case USB_SPEED_SUPER: | |
2428 | case USB_SPEED_UNKNOWN: | |
2429 | case USB_SPEED_WIRELESS: | |
2430 | /* Should never happen because only LS/FS/HS endpoints will get | |
2431 | * added to the endpoint list. | |
2432 | */ | |
2433 | return; | |
2434 | } | |
2435 | ||
2436 | if (tt_info) | |
2437 | tt_info->active_eps += 1; | |
2438 | /* Insert the endpoint into the list, largest max packet size first. */ | |
2439 | list_for_each_entry(smaller_ep, &interval_bw->endpoints, | |
2440 | bw_endpoint_list) { | |
2441 | if (ep_bw->max_packet_size >= | |
2442 | smaller_ep->bw_info.max_packet_size) { | |
2443 | /* Add the new ep before the smaller endpoint */ | |
2444 | list_add_tail(&virt_ep->bw_endpoint_list, | |
2445 | &smaller_ep->bw_endpoint_list); | |
2446 | return; | |
2447 | } | |
2448 | } | |
2449 | /* Add the new endpoint at the end of the list. */ | |
2450 | list_add_tail(&virt_ep->bw_endpoint_list, | |
2451 | &interval_bw->endpoints); | |
2452 | } | |
2453 | ||
2454 | void xhci_update_tt_active_eps(struct xhci_hcd *xhci, | |
2455 | struct xhci_virt_device *virt_dev, | |
2456 | int old_active_eps) | |
2457 | { | |
2458 | struct xhci_root_port_bw_info *rh_bw_info; | |
2459 | if (!virt_dev->tt_info) | |
2460 | return; | |
2461 | ||
2462 | rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1]; | |
2463 | if (old_active_eps == 0 && | |
2464 | virt_dev->tt_info->active_eps != 0) { | |
2465 | rh_bw_info->num_active_tts += 1; | |
c29eea62 | 2466 | rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD; |
2e27980e SS |
2467 | } else if (old_active_eps != 0 && |
2468 | virt_dev->tt_info->active_eps == 0) { | |
2469 | rh_bw_info->num_active_tts -= 1; | |
c29eea62 | 2470 | rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD; |
2e27980e SS |
2471 | } |
2472 | } | |
2473 | ||
2474 | static int xhci_reserve_bandwidth(struct xhci_hcd *xhci, | |
2475 | struct xhci_virt_device *virt_dev, | |
2476 | struct xhci_container_ctx *in_ctx) | |
2477 | { | |
2478 | struct xhci_bw_info ep_bw_info[31]; | |
2479 | int i; | |
2480 | struct xhci_input_control_ctx *ctrl_ctx; | |
2481 | int old_active_eps = 0; | |
2482 | ||
2e27980e SS |
2483 | if (virt_dev->tt_info) |
2484 | old_active_eps = virt_dev->tt_info->active_eps; | |
2485 | ||
2486 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); | |
92f8e767 SS |
2487 | if (!ctrl_ctx) { |
2488 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2489 | __func__); | |
2490 | return -ENOMEM; | |
2491 | } | |
2e27980e SS |
2492 | |
2493 | for (i = 0; i < 31; i++) { | |
2494 | if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i)) | |
2495 | continue; | |
2496 | ||
2497 | /* Make a copy of the BW info in case we need to revert this */ | |
2498 | memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info, | |
2499 | sizeof(ep_bw_info[i])); | |
2500 | /* Drop the endpoint from the interval table if the endpoint is | |
2501 | * being dropped or changed. | |
2502 | */ | |
2503 | if (EP_IS_DROPPED(ctrl_ctx, i)) | |
2504 | xhci_drop_ep_from_interval_table(xhci, | |
2505 | &virt_dev->eps[i].bw_info, | |
2506 | virt_dev->bw_table, | |
2507 | virt_dev->udev, | |
2508 | &virt_dev->eps[i], | |
2509 | virt_dev->tt_info); | |
2510 | } | |
2511 | /* Overwrite the information stored in the endpoints' bw_info */ | |
2512 | xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev); | |
2513 | for (i = 0; i < 31; i++) { | |
2514 | /* Add any changed or added endpoints to the interval table */ | |
2515 | if (EP_IS_ADDED(ctrl_ctx, i)) | |
2516 | xhci_add_ep_to_interval_table(xhci, | |
2517 | &virt_dev->eps[i].bw_info, | |
2518 | virt_dev->bw_table, | |
2519 | virt_dev->udev, | |
2520 | &virt_dev->eps[i], | |
2521 | virt_dev->tt_info); | |
2522 | } | |
2523 | ||
2524 | if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) { | |
2525 | /* Ok, this fits in the bandwidth we have. | |
2526 | * Update the number of active TTs. | |
2527 | */ | |
2528 | xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps); | |
2529 | return 0; | |
2530 | } | |
2531 | ||
2532 | /* We don't have enough bandwidth for this, revert the stored info. */ | |
2533 | for (i = 0; i < 31; i++) { | |
2534 | if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i)) | |
2535 | continue; | |
2536 | ||
2537 | /* Drop the new copies of any added or changed endpoints from | |
2538 | * the interval table. | |
2539 | */ | |
2540 | if (EP_IS_ADDED(ctrl_ctx, i)) { | |
2541 | xhci_drop_ep_from_interval_table(xhci, | |
2542 | &virt_dev->eps[i].bw_info, | |
2543 | virt_dev->bw_table, | |
2544 | virt_dev->udev, | |
2545 | &virt_dev->eps[i], | |
2546 | virt_dev->tt_info); | |
2547 | } | |
2548 | /* Revert the endpoint back to its old information */ | |
2549 | memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i], | |
2550 | sizeof(ep_bw_info[i])); | |
2551 | /* Add any changed or dropped endpoints back into the table */ | |
2552 | if (EP_IS_DROPPED(ctrl_ctx, i)) | |
2553 | xhci_add_ep_to_interval_table(xhci, | |
2554 | &virt_dev->eps[i].bw_info, | |
2555 | virt_dev->bw_table, | |
2556 | virt_dev->udev, | |
2557 | &virt_dev->eps[i], | |
2558 | virt_dev->tt_info); | |
2559 | } | |
2560 | return -ENOMEM; | |
2561 | } | |
2562 | ||
2563 | ||
f2217e8e SS |
2564 | /* Issue a configure endpoint command or evaluate context command |
2565 | * and wait for it to finish. | |
2566 | */ | |
2567 | static int xhci_configure_endpoint(struct xhci_hcd *xhci, | |
913a8a34 SS |
2568 | struct usb_device *udev, |
2569 | struct xhci_command *command, | |
2570 | bool ctx_change, bool must_succeed) | |
f2217e8e SS |
2571 | { |
2572 | int ret; | |
2573 | int timeleft; | |
2574 | unsigned long flags; | |
913a8a34 | 2575 | struct xhci_container_ctx *in_ctx; |
92f8e767 | 2576 | struct xhci_input_control_ctx *ctrl_ctx; |
913a8a34 | 2577 | struct completion *cmd_completion; |
28ccd296 | 2578 | u32 *cmd_status; |
913a8a34 | 2579 | struct xhci_virt_device *virt_dev; |
6e4468b9 | 2580 | union xhci_trb *cmd_trb; |
f2217e8e SS |
2581 | |
2582 | spin_lock_irqsave(&xhci->lock, flags); | |
913a8a34 | 2583 | virt_dev = xhci->devs[udev->slot_id]; |
750645f8 SS |
2584 | |
2585 | if (command) | |
913a8a34 | 2586 | in_ctx = command->in_ctx; |
750645f8 SS |
2587 | else |
2588 | in_ctx = virt_dev->in_ctx; | |
92f8e767 SS |
2589 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); |
2590 | if (!ctrl_ctx) { | |
1f21569c | 2591 | spin_unlock_irqrestore(&xhci->lock, flags); |
92f8e767 SS |
2592 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", |
2593 | __func__); | |
2594 | return -ENOMEM; | |
2595 | } | |
2cf95c18 | 2596 | |
750645f8 | 2597 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) && |
92f8e767 | 2598 | xhci_reserve_host_resources(xhci, ctrl_ctx)) { |
750645f8 SS |
2599 | spin_unlock_irqrestore(&xhci->lock, flags); |
2600 | xhci_warn(xhci, "Not enough host resources, " | |
2601 | "active endpoint contexts = %u\n", | |
2602 | xhci->num_active_eps); | |
2603 | return -ENOMEM; | |
2604 | } | |
2e27980e SS |
2605 | if ((xhci->quirks & XHCI_SW_BW_CHECKING) && |
2606 | xhci_reserve_bandwidth(xhci, virt_dev, in_ctx)) { | |
2607 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) | |
92f8e767 | 2608 | xhci_free_host_resources(xhci, ctrl_ctx); |
2e27980e SS |
2609 | spin_unlock_irqrestore(&xhci->lock, flags); |
2610 | xhci_warn(xhci, "Not enough bandwidth\n"); | |
2611 | return -ENOMEM; | |
2612 | } | |
750645f8 SS |
2613 | |
2614 | if (command) { | |
913a8a34 SS |
2615 | cmd_completion = command->completion; |
2616 | cmd_status = &command->status; | |
ec7e43e2 | 2617 | command->command_trb = xhci_find_next_enqueue(xhci->cmd_ring); |
913a8a34 SS |
2618 | list_add_tail(&command->cmd_list, &virt_dev->cmd_list); |
2619 | } else { | |
913a8a34 SS |
2620 | cmd_completion = &virt_dev->cmd_completion; |
2621 | cmd_status = &virt_dev->cmd_status; | |
2622 | } | |
1d68064a | 2623 | init_completion(cmd_completion); |
913a8a34 | 2624 | |
ec7e43e2 | 2625 | cmd_trb = xhci_find_next_enqueue(xhci->cmd_ring); |
f2217e8e | 2626 | if (!ctx_change) |
913a8a34 SS |
2627 | ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma, |
2628 | udev->slot_id, must_succeed); | |
f2217e8e | 2629 | else |
913a8a34 | 2630 | ret = xhci_queue_evaluate_context(xhci, in_ctx->dma, |
4b266541 | 2631 | udev->slot_id, must_succeed); |
f2217e8e | 2632 | if (ret < 0) { |
c01591bd SS |
2633 | if (command) |
2634 | list_del(&command->cmd_list); | |
2cf95c18 | 2635 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) |
92f8e767 | 2636 | xhci_free_host_resources(xhci, ctrl_ctx); |
f2217e8e | 2637 | spin_unlock_irqrestore(&xhci->lock, flags); |
3a7fa5be XR |
2638 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
2639 | "FIXME allocate a new ring segment"); | |
f2217e8e SS |
2640 | return -ENOMEM; |
2641 | } | |
2642 | xhci_ring_cmd_db(xhci); | |
2643 | spin_unlock_irqrestore(&xhci->lock, flags); | |
2644 | ||
2645 | /* Wait for the configure endpoint command to complete */ | |
2646 | timeleft = wait_for_completion_interruptible_timeout( | |
913a8a34 | 2647 | cmd_completion, |
6e4468b9 | 2648 | XHCI_CMD_DEFAULT_TIMEOUT); |
f2217e8e SS |
2649 | if (timeleft <= 0) { |
2650 | xhci_warn(xhci, "%s while waiting for %s command\n", | |
2651 | timeleft == 0 ? "Timeout" : "Signal", | |
2652 | ctx_change == 0 ? | |
2653 | "configure endpoint" : | |
2654 | "evaluate context"); | |
6e4468b9 EF |
2655 | /* cancel the configure endpoint command */ |
2656 | ret = xhci_cancel_cmd(xhci, command, cmd_trb); | |
2657 | if (ret < 0) | |
2658 | return ret; | |
f2217e8e SS |
2659 | return -ETIME; |
2660 | } | |
2661 | ||
2662 | if (!ctx_change) | |
2cf95c18 SS |
2663 | ret = xhci_configure_endpoint_result(xhci, udev, cmd_status); |
2664 | else | |
2665 | ret = xhci_evaluate_context_result(xhci, udev, cmd_status); | |
2666 | ||
2667 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | |
2668 | spin_lock_irqsave(&xhci->lock, flags); | |
2669 | /* If the command failed, remove the reserved resources. | |
2670 | * Otherwise, clean up the estimate to include dropped eps. | |
2671 | */ | |
2672 | if (ret) | |
92f8e767 | 2673 | xhci_free_host_resources(xhci, ctrl_ctx); |
2cf95c18 | 2674 | else |
92f8e767 | 2675 | xhci_finish_resource_reservation(xhci, ctrl_ctx); |
2cf95c18 SS |
2676 | spin_unlock_irqrestore(&xhci->lock, flags); |
2677 | } | |
2678 | return ret; | |
f2217e8e SS |
2679 | } |
2680 | ||
f88ba78d SS |
2681 | /* Called after one or more calls to xhci_add_endpoint() or |
2682 | * xhci_drop_endpoint(). If this call fails, the USB core is expected | |
2683 | * to call xhci_reset_bandwidth(). | |
2684 | * | |
2685 | * Since we are in the middle of changing either configuration or | |
2686 | * installing a new alt setting, the USB core won't allow URBs to be | |
2687 | * enqueued for any endpoint on the old config or interface. Nothing | |
2688 | * else should be touching the xhci->devs[slot_id] structure, so we | |
2689 | * don't need to take the xhci->lock for manipulating that. | |
2690 | */ | |
f94e0186 SS |
2691 | int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) |
2692 | { | |
2693 | int i; | |
2694 | int ret = 0; | |
f94e0186 SS |
2695 | struct xhci_hcd *xhci; |
2696 | struct xhci_virt_device *virt_dev; | |
d115b048 JY |
2697 | struct xhci_input_control_ctx *ctrl_ctx; |
2698 | struct xhci_slot_ctx *slot_ctx; | |
f94e0186 | 2699 | |
64927730 | 2700 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
f94e0186 SS |
2701 | if (ret <= 0) |
2702 | return ret; | |
2703 | xhci = hcd_to_xhci(hcd); | |
fe6c6c13 SS |
2704 | if (xhci->xhc_state & XHCI_STATE_DYING) |
2705 | return -ENODEV; | |
f94e0186 | 2706 | |
700e2052 | 2707 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
2708 | virt_dev = xhci->devs[udev->slot_id]; |
2709 | ||
2710 | /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */ | |
d115b048 | 2711 | ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx); |
92f8e767 SS |
2712 | if (!ctrl_ctx) { |
2713 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2714 | __func__); | |
2715 | return -ENOMEM; | |
2716 | } | |
28ccd296 ME |
2717 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
2718 | ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG); | |
2719 | ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG)); | |
2dc37539 SS |
2720 | |
2721 | /* Don't issue the command if there's no endpoints to update. */ | |
2722 | if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) && | |
2723 | ctrl_ctx->drop_flags == 0) | |
2724 | return 0; | |
2725 | ||
f94e0186 | 2726 | xhci_dbg(xhci, "New Input Control Context:\n"); |
d115b048 JY |
2727 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); |
2728 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, | |
28ccd296 | 2729 | LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info))); |
f94e0186 | 2730 | |
913a8a34 SS |
2731 | ret = xhci_configure_endpoint(xhci, udev, NULL, |
2732 | false, false); | |
f94e0186 SS |
2733 | if (ret) { |
2734 | /* Callee should call reset_bandwidth() */ | |
f94e0186 SS |
2735 | return ret; |
2736 | } | |
2737 | ||
2738 | xhci_dbg(xhci, "Output context after successful config ep cmd:\n"); | |
d115b048 | 2739 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, |
28ccd296 | 2740 | LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info))); |
f94e0186 | 2741 | |
834cb0fc SS |
2742 | /* Free any rings that were dropped, but not changed. */ |
2743 | for (i = 1; i < 31; ++i) { | |
4819fef5 ME |
2744 | if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) && |
2745 | !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) | |
834cb0fc SS |
2746 | xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i); |
2747 | } | |
d115b048 | 2748 | xhci_zero_in_ctx(xhci, virt_dev); |
834cb0fc SS |
2749 | /* |
2750 | * Install any rings for completely new endpoints or changed endpoints, | |
2751 | * and free or cache any old rings from changed endpoints. | |
2752 | */ | |
f94e0186 | 2753 | for (i = 1; i < 31; ++i) { |
74f9fe21 SS |
2754 | if (!virt_dev->eps[i].new_ring) |
2755 | continue; | |
2756 | /* Only cache or free the old ring if it exists. | |
2757 | * It may not if this is the first add of an endpoint. | |
2758 | */ | |
2759 | if (virt_dev->eps[i].ring) { | |
412566bd | 2760 | xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i); |
f94e0186 | 2761 | } |
74f9fe21 SS |
2762 | virt_dev->eps[i].ring = virt_dev->eps[i].new_ring; |
2763 | virt_dev->eps[i].new_ring = NULL; | |
f94e0186 SS |
2764 | } |
2765 | ||
f94e0186 SS |
2766 | return ret; |
2767 | } | |
2768 | ||
2769 | void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) | |
2770 | { | |
f94e0186 SS |
2771 | struct xhci_hcd *xhci; |
2772 | struct xhci_virt_device *virt_dev; | |
2773 | int i, ret; | |
2774 | ||
64927730 | 2775 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
f94e0186 SS |
2776 | if (ret <= 0) |
2777 | return; | |
2778 | xhci = hcd_to_xhci(hcd); | |
2779 | ||
700e2052 | 2780 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
2781 | virt_dev = xhci->devs[udev->slot_id]; |
2782 | /* Free any rings allocated for added endpoints */ | |
2783 | for (i = 0; i < 31; ++i) { | |
63a0d9ab SS |
2784 | if (virt_dev->eps[i].new_ring) { |
2785 | xhci_ring_free(xhci, virt_dev->eps[i].new_ring); | |
2786 | virt_dev->eps[i].new_ring = NULL; | |
f94e0186 SS |
2787 | } |
2788 | } | |
d115b048 | 2789 | xhci_zero_in_ctx(xhci, virt_dev); |
f94e0186 SS |
2790 | } |
2791 | ||
5270b951 | 2792 | static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci, |
913a8a34 SS |
2793 | struct xhci_container_ctx *in_ctx, |
2794 | struct xhci_container_ctx *out_ctx, | |
92f8e767 | 2795 | struct xhci_input_control_ctx *ctrl_ctx, |
913a8a34 | 2796 | u32 add_flags, u32 drop_flags) |
5270b951 | 2797 | { |
28ccd296 ME |
2798 | ctrl_ctx->add_flags = cpu_to_le32(add_flags); |
2799 | ctrl_ctx->drop_flags = cpu_to_le32(drop_flags); | |
913a8a34 | 2800 | xhci_slot_copy(xhci, in_ctx, out_ctx); |
28ccd296 | 2801 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
5270b951 | 2802 | |
913a8a34 SS |
2803 | xhci_dbg(xhci, "Input Context:\n"); |
2804 | xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags)); | |
5270b951 SS |
2805 | } |
2806 | ||
8212a49d | 2807 | static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci, |
ac9d8fe7 SS |
2808 | unsigned int slot_id, unsigned int ep_index, |
2809 | struct xhci_dequeue_state *deq_state) | |
2810 | { | |
92f8e767 | 2811 | struct xhci_input_control_ctx *ctrl_ctx; |
ac9d8fe7 | 2812 | struct xhci_container_ctx *in_ctx; |
ac9d8fe7 SS |
2813 | struct xhci_ep_ctx *ep_ctx; |
2814 | u32 added_ctxs; | |
2815 | dma_addr_t addr; | |
2816 | ||
92f8e767 SS |
2817 | in_ctx = xhci->devs[slot_id]->in_ctx; |
2818 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); | |
2819 | if (!ctrl_ctx) { | |
2820 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2821 | __func__); | |
2822 | return; | |
2823 | } | |
2824 | ||
913a8a34 SS |
2825 | xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx, |
2826 | xhci->devs[slot_id]->out_ctx, ep_index); | |
ac9d8fe7 SS |
2827 | ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); |
2828 | addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, | |
2829 | deq_state->new_deq_ptr); | |
2830 | if (addr == 0) { | |
2831 | xhci_warn(xhci, "WARN Cannot submit config ep after " | |
2832 | "reset ep command\n"); | |
2833 | xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n", | |
2834 | deq_state->new_deq_seg, | |
2835 | deq_state->new_deq_ptr); | |
2836 | return; | |
2837 | } | |
28ccd296 | 2838 | ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state); |
ac9d8fe7 | 2839 | |
ac9d8fe7 | 2840 | added_ctxs = xhci_get_endpoint_flag_from_index(ep_index); |
913a8a34 | 2841 | xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx, |
92f8e767 SS |
2842 | xhci->devs[slot_id]->out_ctx, ctrl_ctx, |
2843 | added_ctxs, added_ctxs); | |
ac9d8fe7 SS |
2844 | } |
2845 | ||
82d1009f | 2846 | void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, |
63a0d9ab | 2847 | struct usb_device *udev, unsigned int ep_index) |
82d1009f SS |
2848 | { |
2849 | struct xhci_dequeue_state deq_state; | |
63a0d9ab | 2850 | struct xhci_virt_ep *ep; |
82d1009f | 2851 | |
a0254324 XR |
2852 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2853 | "Cleaning up stalled endpoint ring"); | |
63a0d9ab | 2854 | ep = &xhci->devs[udev->slot_id]->eps[ep_index]; |
82d1009f SS |
2855 | /* We need to move the HW's dequeue pointer past this TD, |
2856 | * or it will attempt to resend it on the next doorbell ring. | |
2857 | */ | |
2858 | xhci_find_new_dequeue_state(xhci, udev->slot_id, | |
e9df17eb | 2859 | ep_index, ep->stopped_stream, ep->stopped_td, |
ac9d8fe7 | 2860 | &deq_state); |
82d1009f | 2861 | |
ac9d8fe7 SS |
2862 | /* HW with the reset endpoint quirk will use the saved dequeue state to |
2863 | * issue a configure endpoint command later. | |
2864 | */ | |
2865 | if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) { | |
a0254324 XR |
2866 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2867 | "Queueing new dequeue state"); | |
63a0d9ab | 2868 | xhci_queue_new_dequeue_state(xhci, udev->slot_id, |
e9df17eb | 2869 | ep_index, ep->stopped_stream, &deq_state); |
ac9d8fe7 SS |
2870 | } else { |
2871 | /* Better hope no one uses the input context between now and the | |
2872 | * reset endpoint completion! | |
e9df17eb SS |
2873 | * XXX: No idea how this hardware will react when stream rings |
2874 | * are enabled. | |
ac9d8fe7 | 2875 | */ |
4bdfe4c3 XR |
2876 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2877 | "Setting up input context for " | |
2878 | "configure endpoint command"); | |
ac9d8fe7 SS |
2879 | xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id, |
2880 | ep_index, &deq_state); | |
2881 | } | |
82d1009f SS |
2882 | } |
2883 | ||
a1587d97 SS |
2884 | /* Deal with stalled endpoints. The core should have sent the control message |
2885 | * to clear the halt condition. However, we need to make the xHCI hardware | |
2886 | * reset its sequence number, since a device will expect a sequence number of | |
2887 | * zero after the halt condition is cleared. | |
2888 | * Context: in_interrupt | |
2889 | */ | |
2890 | void xhci_endpoint_reset(struct usb_hcd *hcd, | |
2891 | struct usb_host_endpoint *ep) | |
2892 | { | |
2893 | struct xhci_hcd *xhci; | |
2894 | struct usb_device *udev; | |
2895 | unsigned int ep_index; | |
2896 | unsigned long flags; | |
2897 | int ret; | |
63a0d9ab | 2898 | struct xhci_virt_ep *virt_ep; |
a1587d97 SS |
2899 | |
2900 | xhci = hcd_to_xhci(hcd); | |
2901 | udev = (struct usb_device *) ep->hcpriv; | |
2902 | /* Called with a root hub endpoint (or an endpoint that wasn't added | |
2903 | * with xhci_add_endpoint() | |
2904 | */ | |
2905 | if (!ep->hcpriv) | |
2906 | return; | |
2907 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
63a0d9ab SS |
2908 | virt_ep = &xhci->devs[udev->slot_id]->eps[ep_index]; |
2909 | if (!virt_ep->stopped_td) { | |
a0254324 XR |
2910 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2911 | "Endpoint 0x%x not halted, refusing to reset.", | |
2912 | ep->desc.bEndpointAddress); | |
c92bcfa7 SS |
2913 | return; |
2914 | } | |
82d1009f | 2915 | if (usb_endpoint_xfer_control(&ep->desc)) { |
a0254324 XR |
2916 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2917 | "Control endpoint stall already handled."); | |
82d1009f SS |
2918 | return; |
2919 | } | |
a1587d97 | 2920 | |
a0254324 XR |
2921 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2922 | "Queueing reset endpoint command"); | |
a1587d97 SS |
2923 | spin_lock_irqsave(&xhci->lock, flags); |
2924 | ret = xhci_queue_reset_ep(xhci, udev->slot_id, ep_index); | |
c92bcfa7 SS |
2925 | /* |
2926 | * Can't change the ring dequeue pointer until it's transitioned to the | |
2927 | * stopped state, which is only upon a successful reset endpoint | |
2928 | * command. Better hope that last command worked! | |
2929 | */ | |
a1587d97 | 2930 | if (!ret) { |
63a0d9ab SS |
2931 | xhci_cleanup_stalled_ring(xhci, udev, ep_index); |
2932 | kfree(virt_ep->stopped_td); | |
a1587d97 SS |
2933 | xhci_ring_cmd_db(xhci); |
2934 | } | |
1624ae1c SS |
2935 | virt_ep->stopped_td = NULL; |
2936 | virt_ep->stopped_trb = NULL; | |
5e5cf6fc | 2937 | virt_ep->stopped_stream = 0; |
a1587d97 SS |
2938 | spin_unlock_irqrestore(&xhci->lock, flags); |
2939 | ||
2940 | if (ret) | |
2941 | xhci_warn(xhci, "FIXME allocate a new ring segment\n"); | |
2942 | } | |
2943 | ||
8df75f42 SS |
2944 | static int xhci_check_streams_endpoint(struct xhci_hcd *xhci, |
2945 | struct usb_device *udev, struct usb_host_endpoint *ep, | |
2946 | unsigned int slot_id) | |
2947 | { | |
2948 | int ret; | |
2949 | unsigned int ep_index; | |
2950 | unsigned int ep_state; | |
2951 | ||
2952 | if (!ep) | |
2953 | return -EINVAL; | |
64927730 | 2954 | ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__); |
8df75f42 SS |
2955 | if (ret <= 0) |
2956 | return -EINVAL; | |
842f1690 | 2957 | if (ep->ss_ep_comp.bmAttributes == 0) { |
8df75f42 SS |
2958 | xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion" |
2959 | " descriptor for ep 0x%x does not support streams\n", | |
2960 | ep->desc.bEndpointAddress); | |
2961 | return -EINVAL; | |
2962 | } | |
2963 | ||
2964 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
2965 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
2966 | if (ep_state & EP_HAS_STREAMS || | |
2967 | ep_state & EP_GETTING_STREAMS) { | |
2968 | xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x " | |
2969 | "already has streams set up.\n", | |
2970 | ep->desc.bEndpointAddress); | |
2971 | xhci_warn(xhci, "Send email to xHCI maintainer and ask for " | |
2972 | "dynamic stream context array reallocation.\n"); | |
2973 | return -EINVAL; | |
2974 | } | |
2975 | if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) { | |
2976 | xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk " | |
2977 | "endpoint 0x%x; URBs are pending.\n", | |
2978 | ep->desc.bEndpointAddress); | |
2979 | return -EINVAL; | |
2980 | } | |
2981 | return 0; | |
2982 | } | |
2983 | ||
2984 | static void xhci_calculate_streams_entries(struct xhci_hcd *xhci, | |
2985 | unsigned int *num_streams, unsigned int *num_stream_ctxs) | |
2986 | { | |
2987 | unsigned int max_streams; | |
2988 | ||
2989 | /* The stream context array size must be a power of two */ | |
2990 | *num_stream_ctxs = roundup_pow_of_two(*num_streams); | |
2991 | /* | |
2992 | * Find out how many primary stream array entries the host controller | |
2993 | * supports. Later we may use secondary stream arrays (similar to 2nd | |
2994 | * level page entries), but that's an optional feature for xHCI host | |
2995 | * controllers. xHCs must support at least 4 stream IDs. | |
2996 | */ | |
2997 | max_streams = HCC_MAX_PSA(xhci->hcc_params); | |
2998 | if (*num_stream_ctxs > max_streams) { | |
2999 | xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n", | |
3000 | max_streams); | |
3001 | *num_stream_ctxs = max_streams; | |
3002 | *num_streams = max_streams; | |
3003 | } | |
3004 | } | |
3005 | ||
3006 | /* Returns an error code if one of the endpoint already has streams. | |
3007 | * This does not change any data structures, it only checks and gathers | |
3008 | * information. | |
3009 | */ | |
3010 | static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci, | |
3011 | struct usb_device *udev, | |
3012 | struct usb_host_endpoint **eps, unsigned int num_eps, | |
3013 | unsigned int *num_streams, u32 *changed_ep_bitmask) | |
3014 | { | |
8df75f42 SS |
3015 | unsigned int max_streams; |
3016 | unsigned int endpoint_flag; | |
3017 | int i; | |
3018 | int ret; | |
3019 | ||
3020 | for (i = 0; i < num_eps; i++) { | |
3021 | ret = xhci_check_streams_endpoint(xhci, udev, | |
3022 | eps[i], udev->slot_id); | |
3023 | if (ret < 0) | |
3024 | return ret; | |
3025 | ||
18b7ede5 | 3026 | max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp); |
8df75f42 SS |
3027 | if (max_streams < (*num_streams - 1)) { |
3028 | xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n", | |
3029 | eps[i]->desc.bEndpointAddress, | |
3030 | max_streams); | |
3031 | *num_streams = max_streams+1; | |
3032 | } | |
3033 | ||
3034 | endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc); | |
3035 | if (*changed_ep_bitmask & endpoint_flag) | |
3036 | return -EINVAL; | |
3037 | *changed_ep_bitmask |= endpoint_flag; | |
3038 | } | |
3039 | return 0; | |
3040 | } | |
3041 | ||
3042 | static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci, | |
3043 | struct usb_device *udev, | |
3044 | struct usb_host_endpoint **eps, unsigned int num_eps) | |
3045 | { | |
3046 | u32 changed_ep_bitmask = 0; | |
3047 | unsigned int slot_id; | |
3048 | unsigned int ep_index; | |
3049 | unsigned int ep_state; | |
3050 | int i; | |
3051 | ||
3052 | slot_id = udev->slot_id; | |
3053 | if (!xhci->devs[slot_id]) | |
3054 | return 0; | |
3055 | ||
3056 | for (i = 0; i < num_eps; i++) { | |
3057 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3058 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
3059 | /* Are streams already being freed for the endpoint? */ | |
3060 | if (ep_state & EP_GETTING_NO_STREAMS) { | |
3061 | xhci_warn(xhci, "WARN Can't disable streams for " | |
03e64e96 JP |
3062 | "endpoint 0x%x, " |
3063 | "streams are being disabled already\n", | |
8df75f42 SS |
3064 | eps[i]->desc.bEndpointAddress); |
3065 | return 0; | |
3066 | } | |
3067 | /* Are there actually any streams to free? */ | |
3068 | if (!(ep_state & EP_HAS_STREAMS) && | |
3069 | !(ep_state & EP_GETTING_STREAMS)) { | |
3070 | xhci_warn(xhci, "WARN Can't disable streams for " | |
03e64e96 JP |
3071 | "endpoint 0x%x, " |
3072 | "streams are already disabled!\n", | |
8df75f42 SS |
3073 | eps[i]->desc.bEndpointAddress); |
3074 | xhci_warn(xhci, "WARN xhci_free_streams() called " | |
3075 | "with non-streams endpoint\n"); | |
3076 | return 0; | |
3077 | } | |
3078 | changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc); | |
3079 | } | |
3080 | return changed_ep_bitmask; | |
3081 | } | |
3082 | ||
3083 | /* | |
3084 | * The USB device drivers use this function (though the HCD interface in USB | |
3085 | * core) to prepare a set of bulk endpoints to use streams. Streams are used to | |
3086 | * coordinate mass storage command queueing across multiple endpoints (basically | |
3087 | * a stream ID == a task ID). | |
3088 | * | |
3089 | * Setting up streams involves allocating the same size stream context array | |
3090 | * for each endpoint and issuing a configure endpoint command for all endpoints. | |
3091 | * | |
3092 | * Don't allow the call to succeed if one endpoint only supports one stream | |
3093 | * (which means it doesn't support streams at all). | |
3094 | * | |
3095 | * Drivers may get less stream IDs than they asked for, if the host controller | |
3096 | * hardware or endpoints claim they can't support the number of requested | |
3097 | * stream IDs. | |
3098 | */ | |
3099 | int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, | |
3100 | struct usb_host_endpoint **eps, unsigned int num_eps, | |
3101 | unsigned int num_streams, gfp_t mem_flags) | |
3102 | { | |
3103 | int i, ret; | |
3104 | struct xhci_hcd *xhci; | |
3105 | struct xhci_virt_device *vdev; | |
3106 | struct xhci_command *config_cmd; | |
92f8e767 | 3107 | struct xhci_input_control_ctx *ctrl_ctx; |
8df75f42 SS |
3108 | unsigned int ep_index; |
3109 | unsigned int num_stream_ctxs; | |
3110 | unsigned long flags; | |
3111 | u32 changed_ep_bitmask = 0; | |
3112 | ||
3113 | if (!eps) | |
3114 | return -EINVAL; | |
3115 | ||
3116 | /* Add one to the number of streams requested to account for | |
3117 | * stream 0 that is reserved for xHCI usage. | |
3118 | */ | |
3119 | num_streams += 1; | |
3120 | xhci = hcd_to_xhci(hcd); | |
3121 | xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n", | |
3122 | num_streams); | |
3123 | ||
3124 | config_cmd = xhci_alloc_command(xhci, true, true, mem_flags); | |
3125 | if (!config_cmd) { | |
3126 | xhci_dbg(xhci, "Could not allocate xHCI command structure.\n"); | |
3127 | return -ENOMEM; | |
3128 | } | |
92f8e767 SS |
3129 | ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx); |
3130 | if (!ctrl_ctx) { | |
3131 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
3132 | __func__); | |
3133 | xhci_free_command(xhci, config_cmd); | |
3134 | return -ENOMEM; | |
3135 | } | |
8df75f42 SS |
3136 | |
3137 | /* Check to make sure all endpoints are not already configured for | |
3138 | * streams. While we're at it, find the maximum number of streams that | |
3139 | * all the endpoints will support and check for duplicate endpoints. | |
3140 | */ | |
3141 | spin_lock_irqsave(&xhci->lock, flags); | |
3142 | ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps, | |
3143 | num_eps, &num_streams, &changed_ep_bitmask); | |
3144 | if (ret < 0) { | |
3145 | xhci_free_command(xhci, config_cmd); | |
3146 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3147 | return ret; | |
3148 | } | |
3149 | if (num_streams <= 1) { | |
3150 | xhci_warn(xhci, "WARN: endpoints can't handle " | |
3151 | "more than one stream.\n"); | |
3152 | xhci_free_command(xhci, config_cmd); | |
3153 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3154 | return -EINVAL; | |
3155 | } | |
3156 | vdev = xhci->devs[udev->slot_id]; | |
25985edc | 3157 | /* Mark each endpoint as being in transition, so |
8df75f42 SS |
3158 | * xhci_urb_enqueue() will reject all URBs. |
3159 | */ | |
3160 | for (i = 0; i < num_eps; i++) { | |
3161 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3162 | vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS; | |
3163 | } | |
3164 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3165 | ||
3166 | /* Setup internal data structures and allocate HW data structures for | |
3167 | * streams (but don't install the HW structures in the input context | |
3168 | * until we're sure all memory allocation succeeded). | |
3169 | */ | |
3170 | xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs); | |
3171 | xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n", | |
3172 | num_stream_ctxs, num_streams); | |
3173 | ||
3174 | for (i = 0; i < num_eps; i++) { | |
3175 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3176 | vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci, | |
3177 | num_stream_ctxs, | |
3178 | num_streams, mem_flags); | |
3179 | if (!vdev->eps[ep_index].stream_info) | |
3180 | goto cleanup; | |
3181 | /* Set maxPstreams in endpoint context and update deq ptr to | |
3182 | * point to stream context array. FIXME | |
3183 | */ | |
3184 | } | |
3185 | ||
3186 | /* Set up the input context for a configure endpoint command. */ | |
3187 | for (i = 0; i < num_eps; i++) { | |
3188 | struct xhci_ep_ctx *ep_ctx; | |
3189 | ||
3190 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3191 | ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index); | |
3192 | ||
3193 | xhci_endpoint_copy(xhci, config_cmd->in_ctx, | |
3194 | vdev->out_ctx, ep_index); | |
3195 | xhci_setup_streams_ep_input_ctx(xhci, ep_ctx, | |
3196 | vdev->eps[ep_index].stream_info); | |
3197 | } | |
3198 | /* Tell the HW to drop its old copy of the endpoint context info | |
3199 | * and add the updated copy from the input context. | |
3200 | */ | |
3201 | xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx, | |
92f8e767 SS |
3202 | vdev->out_ctx, ctrl_ctx, |
3203 | changed_ep_bitmask, changed_ep_bitmask); | |
8df75f42 SS |
3204 | |
3205 | /* Issue and wait for the configure endpoint command */ | |
3206 | ret = xhci_configure_endpoint(xhci, udev, config_cmd, | |
3207 | false, false); | |
3208 | ||
3209 | /* xHC rejected the configure endpoint command for some reason, so we | |
3210 | * leave the old ring intact and free our internal streams data | |
3211 | * structure. | |
3212 | */ | |
3213 | if (ret < 0) | |
3214 | goto cleanup; | |
3215 | ||
3216 | spin_lock_irqsave(&xhci->lock, flags); | |
3217 | for (i = 0; i < num_eps; i++) { | |
3218 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3219 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS; | |
3220 | xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n", | |
3221 | udev->slot_id, ep_index); | |
3222 | vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS; | |
3223 | } | |
3224 | xhci_free_command(xhci, config_cmd); | |
3225 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3226 | ||
3227 | /* Subtract 1 for stream 0, which drivers can't use */ | |
3228 | return num_streams - 1; | |
3229 | ||
3230 | cleanup: | |
3231 | /* If it didn't work, free the streams! */ | |
3232 | for (i = 0; i < num_eps; i++) { | |
3233 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3234 | xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info); | |
8a007748 | 3235 | vdev->eps[ep_index].stream_info = NULL; |
8df75f42 SS |
3236 | /* FIXME Unset maxPstreams in endpoint context and |
3237 | * update deq ptr to point to normal string ring. | |
3238 | */ | |
3239 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS; | |
3240 | vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS; | |
3241 | xhci_endpoint_zero(xhci, vdev, eps[i]); | |
3242 | } | |
3243 | xhci_free_command(xhci, config_cmd); | |
3244 | return -ENOMEM; | |
3245 | } | |
3246 | ||
3247 | /* Transition the endpoint from using streams to being a "normal" endpoint | |
3248 | * without streams. | |
3249 | * | |
3250 | * Modify the endpoint context state, submit a configure endpoint command, | |
3251 | * and free all endpoint rings for streams if that completes successfully. | |
3252 | */ | |
3253 | int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, | |
3254 | struct usb_host_endpoint **eps, unsigned int num_eps, | |
3255 | gfp_t mem_flags) | |
3256 | { | |
3257 | int i, ret; | |
3258 | struct xhci_hcd *xhci; | |
3259 | struct xhci_virt_device *vdev; | |
3260 | struct xhci_command *command; | |
92f8e767 | 3261 | struct xhci_input_control_ctx *ctrl_ctx; |
8df75f42 SS |
3262 | unsigned int ep_index; |
3263 | unsigned long flags; | |
3264 | u32 changed_ep_bitmask; | |
3265 | ||
3266 | xhci = hcd_to_xhci(hcd); | |
3267 | vdev = xhci->devs[udev->slot_id]; | |
3268 | ||
3269 | /* Set up a configure endpoint command to remove the streams rings */ | |
3270 | spin_lock_irqsave(&xhci->lock, flags); | |
3271 | changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci, | |
3272 | udev, eps, num_eps); | |
3273 | if (changed_ep_bitmask == 0) { | |
3274 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3275 | return -EINVAL; | |
3276 | } | |
3277 | ||
3278 | /* Use the xhci_command structure from the first endpoint. We may have | |
3279 | * allocated too many, but the driver may call xhci_free_streams() for | |
3280 | * each endpoint it grouped into one call to xhci_alloc_streams(). | |
3281 | */ | |
3282 | ep_index = xhci_get_endpoint_index(&eps[0]->desc); | |
3283 | command = vdev->eps[ep_index].stream_info->free_streams_command; | |
92f8e767 SS |
3284 | ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx); |
3285 | if (!ctrl_ctx) { | |
1f21569c | 3286 | spin_unlock_irqrestore(&xhci->lock, flags); |
92f8e767 SS |
3287 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", |
3288 | __func__); | |
3289 | return -EINVAL; | |
3290 | } | |
3291 | ||
8df75f42 SS |
3292 | for (i = 0; i < num_eps; i++) { |
3293 | struct xhci_ep_ctx *ep_ctx; | |
3294 | ||
3295 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3296 | ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index); | |
3297 | xhci->devs[udev->slot_id]->eps[ep_index].ep_state |= | |
3298 | EP_GETTING_NO_STREAMS; | |
3299 | ||
3300 | xhci_endpoint_copy(xhci, command->in_ctx, | |
3301 | vdev->out_ctx, ep_index); | |
3302 | xhci_setup_no_streams_ep_input_ctx(xhci, ep_ctx, | |
3303 | &vdev->eps[ep_index]); | |
3304 | } | |
3305 | xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx, | |
92f8e767 SS |
3306 | vdev->out_ctx, ctrl_ctx, |
3307 | changed_ep_bitmask, changed_ep_bitmask); | |
8df75f42 SS |
3308 | spin_unlock_irqrestore(&xhci->lock, flags); |
3309 | ||
3310 | /* Issue and wait for the configure endpoint command, | |
3311 | * which must succeed. | |
3312 | */ | |
3313 | ret = xhci_configure_endpoint(xhci, udev, command, | |
3314 | false, true); | |
3315 | ||
3316 | /* xHC rejected the configure endpoint command for some reason, so we | |
3317 | * leave the streams rings intact. | |
3318 | */ | |
3319 | if (ret < 0) | |
3320 | return ret; | |
3321 | ||
3322 | spin_lock_irqsave(&xhci->lock, flags); | |
3323 | for (i = 0; i < num_eps; i++) { | |
3324 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3325 | xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info); | |
8a007748 | 3326 | vdev->eps[ep_index].stream_info = NULL; |
8df75f42 SS |
3327 | /* FIXME Unset maxPstreams in endpoint context and |
3328 | * update deq ptr to point to normal string ring. | |
3329 | */ | |
3330 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS; | |
3331 | vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS; | |
3332 | } | |
3333 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3334 | ||
3335 | return 0; | |
3336 | } | |
3337 | ||
2cf95c18 SS |
3338 | /* |
3339 | * Deletes endpoint resources for endpoints that were active before a Reset | |
3340 | * Device command, or a Disable Slot command. The Reset Device command leaves | |
3341 | * the control endpoint intact, whereas the Disable Slot command deletes it. | |
3342 | * | |
3343 | * Must be called with xhci->lock held. | |
3344 | */ | |
3345 | void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, | |
3346 | struct xhci_virt_device *virt_dev, bool drop_control_ep) | |
3347 | { | |
3348 | int i; | |
3349 | unsigned int num_dropped_eps = 0; | |
3350 | unsigned int drop_flags = 0; | |
3351 | ||
3352 | for (i = (drop_control_ep ? 0 : 1); i < 31; i++) { | |
3353 | if (virt_dev->eps[i].ring) { | |
3354 | drop_flags |= 1 << i; | |
3355 | num_dropped_eps++; | |
3356 | } | |
3357 | } | |
3358 | xhci->num_active_eps -= num_dropped_eps; | |
3359 | if (num_dropped_eps) | |
4bdfe4c3 XR |
3360 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3361 | "Dropped %u ep ctxs, flags = 0x%x, " | |
3362 | "%u now active.", | |
2cf95c18 SS |
3363 | num_dropped_eps, drop_flags, |
3364 | xhci->num_active_eps); | |
3365 | } | |
3366 | ||
2a8f82c4 SS |
3367 | /* |
3368 | * This submits a Reset Device Command, which will set the device state to 0, | |
3369 | * set the device address to 0, and disable all the endpoints except the default | |
3370 | * control endpoint. The USB core should come back and call | |
3371 | * xhci_address_device(), and then re-set up the configuration. If this is | |
3372 | * called because of a usb_reset_and_verify_device(), then the old alternate | |
3373 | * settings will be re-installed through the normal bandwidth allocation | |
3374 | * functions. | |
3375 | * | |
3376 | * Wait for the Reset Device command to finish. Remove all structures | |
3377 | * associated with the endpoints that were disabled. Clear the input device | |
3378 | * structure? Cache the rings? Reset the control endpoint 0 max packet size? | |
f0615c45 AX |
3379 | * |
3380 | * If the virt_dev to be reset does not exist or does not match the udev, | |
3381 | * it means the device is lost, possibly due to the xHC restore error and | |
3382 | * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to | |
3383 | * re-allocate the device. | |
2a8f82c4 | 3384 | */ |
f0615c45 | 3385 | int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev) |
2a8f82c4 SS |
3386 | { |
3387 | int ret, i; | |
3388 | unsigned long flags; | |
3389 | struct xhci_hcd *xhci; | |
3390 | unsigned int slot_id; | |
3391 | struct xhci_virt_device *virt_dev; | |
3392 | struct xhci_command *reset_device_cmd; | |
3393 | int timeleft; | |
3394 | int last_freed_endpoint; | |
001fd382 | 3395 | struct xhci_slot_ctx *slot_ctx; |
2e27980e | 3396 | int old_active_eps = 0; |
2a8f82c4 | 3397 | |
f0615c45 | 3398 | ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__); |
2a8f82c4 SS |
3399 | if (ret <= 0) |
3400 | return ret; | |
3401 | xhci = hcd_to_xhci(hcd); | |
3402 | slot_id = udev->slot_id; | |
3403 | virt_dev = xhci->devs[slot_id]; | |
f0615c45 AX |
3404 | if (!virt_dev) { |
3405 | xhci_dbg(xhci, "The device to be reset with slot ID %u does " | |
3406 | "not exist. Re-allocate the device\n", slot_id); | |
3407 | ret = xhci_alloc_dev(hcd, udev); | |
3408 | if (ret == 1) | |
3409 | return 0; | |
3410 | else | |
3411 | return -EINVAL; | |
3412 | } | |
3413 | ||
3414 | if (virt_dev->udev != udev) { | |
3415 | /* If the virt_dev and the udev does not match, this virt_dev | |
3416 | * may belong to another udev. | |
3417 | * Re-allocate the device. | |
3418 | */ | |
3419 | xhci_dbg(xhci, "The device to be reset with slot ID %u does " | |
3420 | "not match the udev. Re-allocate the device\n", | |
3421 | slot_id); | |
3422 | ret = xhci_alloc_dev(hcd, udev); | |
3423 | if (ret == 1) | |
3424 | return 0; | |
3425 | else | |
3426 | return -EINVAL; | |
3427 | } | |
2a8f82c4 | 3428 | |
001fd382 ML |
3429 | /* If device is not setup, there is no point in resetting it */ |
3430 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); | |
3431 | if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) == | |
3432 | SLOT_STATE_DISABLED) | |
3433 | return 0; | |
3434 | ||
2a8f82c4 SS |
3435 | xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id); |
3436 | /* Allocate the command structure that holds the struct completion. | |
3437 | * Assume we're in process context, since the normal device reset | |
3438 | * process has to wait for the device anyway. Storage devices are | |
3439 | * reset as part of error handling, so use GFP_NOIO instead of | |
3440 | * GFP_KERNEL. | |
3441 | */ | |
3442 | reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); | |
3443 | if (!reset_device_cmd) { | |
3444 | xhci_dbg(xhci, "Couldn't allocate command structure.\n"); | |
3445 | return -ENOMEM; | |
3446 | } | |
3447 | ||
3448 | /* Attempt to submit the Reset Device command to the command ring */ | |
3449 | spin_lock_irqsave(&xhci->lock, flags); | |
ec7e43e2 | 3450 | reset_device_cmd->command_trb = xhci_find_next_enqueue(xhci->cmd_ring); |
7a3783ef | 3451 | |
2a8f82c4 SS |
3452 | list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list); |
3453 | ret = xhci_queue_reset_device(xhci, slot_id); | |
3454 | if (ret) { | |
3455 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
3456 | list_del(&reset_device_cmd->cmd_list); | |
3457 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3458 | goto command_cleanup; | |
3459 | } | |
3460 | xhci_ring_cmd_db(xhci); | |
3461 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3462 | ||
3463 | /* Wait for the Reset Device command to finish */ | |
3464 | timeleft = wait_for_completion_interruptible_timeout( | |
3465 | reset_device_cmd->completion, | |
d194c031 | 3466 | XHCI_CMD_DEFAULT_TIMEOUT); |
2a8f82c4 SS |
3467 | if (timeleft <= 0) { |
3468 | xhci_warn(xhci, "%s while waiting for reset device command\n", | |
3469 | timeleft == 0 ? "Timeout" : "Signal"); | |
3470 | spin_lock_irqsave(&xhci->lock, flags); | |
3471 | /* The timeout might have raced with the event ring handler, so | |
3472 | * only delete from the list if the item isn't poisoned. | |
3473 | */ | |
3474 | if (reset_device_cmd->cmd_list.next != LIST_POISON1) | |
3475 | list_del(&reset_device_cmd->cmd_list); | |
3476 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3477 | ret = -ETIME; | |
3478 | goto command_cleanup; | |
3479 | } | |
3480 | ||
3481 | /* The Reset Device command can't fail, according to the 0.95/0.96 spec, | |
3482 | * unless we tried to reset a slot ID that wasn't enabled, | |
3483 | * or the device wasn't in the addressed or configured state. | |
3484 | */ | |
3485 | ret = reset_device_cmd->status; | |
3486 | switch (ret) { | |
3487 | case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */ | |
3488 | case COMP_CTX_STATE: /* 0.96 completion code for same thing */ | |
38a532a6 | 3489 | xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n", |
2a8f82c4 SS |
3490 | slot_id, |
3491 | xhci_get_slot_state(xhci, virt_dev->out_ctx)); | |
38a532a6 | 3492 | xhci_dbg(xhci, "Not freeing device rings.\n"); |
2a8f82c4 SS |
3493 | /* Don't treat this as an error. May change my mind later. */ |
3494 | ret = 0; | |
3495 | goto command_cleanup; | |
3496 | case COMP_SUCCESS: | |
3497 | xhci_dbg(xhci, "Successful reset device command.\n"); | |
3498 | break; | |
3499 | default: | |
3500 | if (xhci_is_vendor_info_code(xhci, ret)) | |
3501 | break; | |
3502 | xhci_warn(xhci, "Unknown completion code %u for " | |
3503 | "reset device command.\n", ret); | |
3504 | ret = -EINVAL; | |
3505 | goto command_cleanup; | |
3506 | } | |
3507 | ||
2cf95c18 SS |
3508 | /* Free up host controller endpoint resources */ |
3509 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | |
3510 | spin_lock_irqsave(&xhci->lock, flags); | |
3511 | /* Don't delete the default control endpoint resources */ | |
3512 | xhci_free_device_endpoint_resources(xhci, virt_dev, false); | |
3513 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3514 | } | |
3515 | ||
2a8f82c4 SS |
3516 | /* Everything but endpoint 0 is disabled, so free or cache the rings. */ |
3517 | last_freed_endpoint = 1; | |
3518 | for (i = 1; i < 31; ++i) { | |
2dea75d9 DT |
3519 | struct xhci_virt_ep *ep = &virt_dev->eps[i]; |
3520 | ||
3521 | if (ep->ep_state & EP_HAS_STREAMS) { | |
3522 | xhci_free_stream_info(xhci, ep->stream_info); | |
3523 | ep->stream_info = NULL; | |
3524 | ep->ep_state &= ~EP_HAS_STREAMS; | |
3525 | } | |
3526 | ||
3527 | if (ep->ring) { | |
3528 | xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i); | |
3529 | last_freed_endpoint = i; | |
3530 | } | |
2e27980e SS |
3531 | if (!list_empty(&virt_dev->eps[i].bw_endpoint_list)) |
3532 | xhci_drop_ep_from_interval_table(xhci, | |
3533 | &virt_dev->eps[i].bw_info, | |
3534 | virt_dev->bw_table, | |
3535 | udev, | |
3536 | &virt_dev->eps[i], | |
3537 | virt_dev->tt_info); | |
9af5d71d | 3538 | xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info); |
2a8f82c4 | 3539 | } |
2e27980e SS |
3540 | /* If necessary, update the number of active TTs on this root port */ |
3541 | xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps); | |
3542 | ||
2a8f82c4 SS |
3543 | xhci_dbg(xhci, "Output context after successful reset device cmd:\n"); |
3544 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint); | |
3545 | ret = 0; | |
3546 | ||
3547 | command_cleanup: | |
3548 | xhci_free_command(xhci, reset_device_cmd); | |
3549 | return ret; | |
3550 | } | |
3551 | ||
3ffbba95 SS |
3552 | /* |
3553 | * At this point, the struct usb_device is about to go away, the device has | |
3554 | * disconnected, and all traffic has been stopped and the endpoints have been | |
3555 | * disabled. Free any HC data structures associated with that device. | |
3556 | */ | |
3557 | void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev) | |
3558 | { | |
3559 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
6f5165cf | 3560 | struct xhci_virt_device *virt_dev; |
3ffbba95 | 3561 | unsigned long flags; |
c526d0d4 | 3562 | u32 state; |
64927730 | 3563 | int i, ret; |
3ffbba95 | 3564 | |
c8476fb8 SN |
3565 | #ifndef CONFIG_USB_DEFAULT_PERSIST |
3566 | /* | |
3567 | * We called pm_runtime_get_noresume when the device was attached. | |
3568 | * Decrement the counter here to allow controller to runtime suspend | |
3569 | * if no devices remain. | |
3570 | */ | |
3571 | if (xhci->quirks & XHCI_RESET_ON_RESUME) | |
e7ecf069 | 3572 | pm_runtime_put_noidle(hcd->self.controller); |
c8476fb8 SN |
3573 | #endif |
3574 | ||
64927730 | 3575 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
7bd89b40 SS |
3576 | /* If the host is halted due to driver unload, we still need to free the |
3577 | * device. | |
3578 | */ | |
3579 | if (ret <= 0 && ret != -ENODEV) | |
3ffbba95 | 3580 | return; |
64927730 | 3581 | |
6f5165cf | 3582 | virt_dev = xhci->devs[udev->slot_id]; |
6f5165cf SS |
3583 | |
3584 | /* Stop any wayward timer functions (which may grab the lock) */ | |
3585 | for (i = 0; i < 31; ++i) { | |
3586 | virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING; | |
3587 | del_timer_sync(&virt_dev->eps[i].stop_cmd_timer); | |
3588 | } | |
3ffbba95 SS |
3589 | |
3590 | spin_lock_irqsave(&xhci->lock, flags); | |
c526d0d4 | 3591 | /* Don't disable the slot if the host controller is dead. */ |
b0ba9720 | 3592 | state = readl(&xhci->op_regs->status); |
7bd89b40 SS |
3593 | if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) || |
3594 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | |
c526d0d4 SS |
3595 | xhci_free_virt_device(xhci, udev->slot_id); |
3596 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3597 | return; | |
3598 | } | |
3599 | ||
23e3be11 | 3600 | if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) { |
3ffbba95 SS |
3601 | spin_unlock_irqrestore(&xhci->lock, flags); |
3602 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
3603 | return; | |
3604 | } | |
23e3be11 | 3605 | xhci_ring_cmd_db(xhci); |
3ffbba95 SS |
3606 | spin_unlock_irqrestore(&xhci->lock, flags); |
3607 | /* | |
3608 | * Event command completion handler will free any data structures | |
f88ba78d | 3609 | * associated with the slot. XXX Can free sleep? |
3ffbba95 SS |
3610 | */ |
3611 | } | |
3612 | ||
2cf95c18 SS |
3613 | /* |
3614 | * Checks if we have enough host controller resources for the default control | |
3615 | * endpoint. | |
3616 | * | |
3617 | * Must be called with xhci->lock held. | |
3618 | */ | |
3619 | static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci) | |
3620 | { | |
3621 | if (xhci->num_active_eps + 1 > xhci->limit_active_eps) { | |
4bdfe4c3 XR |
3622 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3623 | "Not enough ep ctxs: " | |
3624 | "%u active, need to add 1, limit is %u.", | |
2cf95c18 SS |
3625 | xhci->num_active_eps, xhci->limit_active_eps); |
3626 | return -ENOMEM; | |
3627 | } | |
3628 | xhci->num_active_eps += 1; | |
4bdfe4c3 XR |
3629 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3630 | "Adding 1 ep ctx, %u now active.", | |
2cf95c18 SS |
3631 | xhci->num_active_eps); |
3632 | return 0; | |
3633 | } | |
3634 | ||
3635 | ||
3ffbba95 SS |
3636 | /* |
3637 | * Returns 0 if the xHC ran out of device slots, the Enable Slot command | |
3638 | * timed out, or allocating memory failed. Returns 1 on success. | |
3639 | */ | |
3640 | int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev) | |
3641 | { | |
3642 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
3643 | unsigned long flags; | |
3644 | int timeleft; | |
3645 | int ret; | |
6e4468b9 | 3646 | union xhci_trb *cmd_trb; |
3ffbba95 SS |
3647 | |
3648 | spin_lock_irqsave(&xhci->lock, flags); | |
ec7e43e2 | 3649 | cmd_trb = xhci_find_next_enqueue(xhci->cmd_ring); |
23e3be11 | 3650 | ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0); |
3ffbba95 SS |
3651 | if (ret) { |
3652 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3653 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
3654 | return 0; | |
3655 | } | |
23e3be11 | 3656 | xhci_ring_cmd_db(xhci); |
3ffbba95 SS |
3657 | spin_unlock_irqrestore(&xhci->lock, flags); |
3658 | ||
3659 | /* XXX: how much time for xHC slot assignment? */ | |
3660 | timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev, | |
6e4468b9 | 3661 | XHCI_CMD_DEFAULT_TIMEOUT); |
3ffbba95 SS |
3662 | if (timeleft <= 0) { |
3663 | xhci_warn(xhci, "%s while waiting for a slot\n", | |
3664 | timeleft == 0 ? "Timeout" : "Signal"); | |
6e4468b9 EF |
3665 | /* cancel the enable slot request */ |
3666 | return xhci_cancel_cmd(xhci, NULL, cmd_trb); | |
3ffbba95 SS |
3667 | } |
3668 | ||
3ffbba95 SS |
3669 | if (!xhci->slot_id) { |
3670 | xhci_err(xhci, "Error while assigning device slot ID\n"); | |
3ffbba95 SS |
3671 | return 0; |
3672 | } | |
2cf95c18 SS |
3673 | |
3674 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | |
3675 | spin_lock_irqsave(&xhci->lock, flags); | |
3676 | ret = xhci_reserve_host_control_ep_resources(xhci); | |
3677 | if (ret) { | |
3678 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3679 | xhci_warn(xhci, "Not enough host resources, " | |
3680 | "active endpoint contexts = %u\n", | |
3681 | xhci->num_active_eps); | |
3682 | goto disable_slot; | |
3683 | } | |
3684 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3685 | } | |
3686 | /* Use GFP_NOIO, since this function can be called from | |
a6d940dd SS |
3687 | * xhci_discover_or_reset_device(), which may be called as part of |
3688 | * mass storage driver error handling. | |
3689 | */ | |
3690 | if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_NOIO)) { | |
3ffbba95 | 3691 | xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); |
2cf95c18 | 3692 | goto disable_slot; |
3ffbba95 SS |
3693 | } |
3694 | udev->slot_id = xhci->slot_id; | |
c8476fb8 SN |
3695 | |
3696 | #ifndef CONFIG_USB_DEFAULT_PERSIST | |
3697 | /* | |
3698 | * If resetting upon resume, we can't put the controller into runtime | |
3699 | * suspend if there is a device attached. | |
3700 | */ | |
3701 | if (xhci->quirks & XHCI_RESET_ON_RESUME) | |
e7ecf069 | 3702 | pm_runtime_get_noresume(hcd->self.controller); |
c8476fb8 SN |
3703 | #endif |
3704 | ||
3ffbba95 SS |
3705 | /* Is this a LS or FS device under a HS hub? */ |
3706 | /* Hub or peripherial? */ | |
3ffbba95 | 3707 | return 1; |
2cf95c18 SS |
3708 | |
3709 | disable_slot: | |
3710 | /* Disable slot, if we can do it without mem alloc */ | |
3711 | spin_lock_irqsave(&xhci->lock, flags); | |
3712 | if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) | |
3713 | xhci_ring_cmd_db(xhci); | |
3714 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3715 | return 0; | |
3ffbba95 SS |
3716 | } |
3717 | ||
3718 | /* | |
48fc7dbd DW |
3719 | * Issue an Address Device command and optionally send a corresponding |
3720 | * SetAddress request to the device. | |
3ffbba95 SS |
3721 | * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so |
3722 | * we should only issue and wait on one address command at the same time. | |
3ffbba95 | 3723 | */ |
48fc7dbd DW |
3724 | static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev, |
3725 | enum xhci_setup_dev setup) | |
3ffbba95 | 3726 | { |
6f8ffc0b | 3727 | const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address"; |
3ffbba95 SS |
3728 | unsigned long flags; |
3729 | int timeleft; | |
3730 | struct xhci_virt_device *virt_dev; | |
3731 | int ret = 0; | |
3732 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
d115b048 JY |
3733 | struct xhci_slot_ctx *slot_ctx; |
3734 | struct xhci_input_control_ctx *ctrl_ctx; | |
8e595a5d | 3735 | u64 temp_64; |
6e4468b9 | 3736 | union xhci_trb *cmd_trb; |
3ffbba95 SS |
3737 | |
3738 | if (!udev->slot_id) { | |
84a99f6f XR |
3739 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3740 | "Bad Slot ID %d", udev->slot_id); | |
3ffbba95 SS |
3741 | return -EINVAL; |
3742 | } | |
3743 | ||
3ffbba95 SS |
3744 | virt_dev = xhci->devs[udev->slot_id]; |
3745 | ||
7ed603ec ME |
3746 | if (WARN_ON(!virt_dev)) { |
3747 | /* | |
3748 | * In plug/unplug torture test with an NEC controller, | |
3749 | * a zero-dereference was observed once due to virt_dev = 0. | |
3750 | * Print useful debug rather than crash if it is observed again! | |
3751 | */ | |
3752 | xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n", | |
3753 | udev->slot_id); | |
3754 | return -EINVAL; | |
3755 | } | |
3756 | ||
f0615c45 | 3757 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); |
92f8e767 SS |
3758 | ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx); |
3759 | if (!ctrl_ctx) { | |
3760 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
3761 | __func__); | |
3762 | return -EINVAL; | |
3763 | } | |
f0615c45 AX |
3764 | /* |
3765 | * If this is the first Set Address since device plug-in or | |
3766 | * virt_device realloaction after a resume with an xHCI power loss, | |
3767 | * then set up the slot context. | |
3768 | */ | |
3769 | if (!slot_ctx->dev_info) | |
3ffbba95 | 3770 | xhci_setup_addressable_virt_dev(xhci, udev); |
f0615c45 | 3771 | /* Otherwise, update the control endpoint ring enqueue pointer. */ |
2d1ee590 SS |
3772 | else |
3773 | xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev); | |
d31c285b SS |
3774 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG); |
3775 | ctrl_ctx->drop_flags = 0; | |
3776 | ||
66e49d87 | 3777 | xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); |
d115b048 | 3778 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2); |
1d27fabe | 3779 | trace_xhci_address_ctx(xhci, virt_dev->in_ctx, |
0c052aab | 3780 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
3ffbba95 | 3781 | |
f88ba78d | 3782 | spin_lock_irqsave(&xhci->lock, flags); |
ec7e43e2 | 3783 | cmd_trb = xhci_find_next_enqueue(xhci->cmd_ring); |
d115b048 | 3784 | ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma, |
48fc7dbd | 3785 | udev->slot_id, setup); |
3ffbba95 SS |
3786 | if (ret) { |
3787 | spin_unlock_irqrestore(&xhci->lock, flags); | |
84a99f6f XR |
3788 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3789 | "FIXME: allocate a command ring segment"); | |
3ffbba95 SS |
3790 | return ret; |
3791 | } | |
23e3be11 | 3792 | xhci_ring_cmd_db(xhci); |
3ffbba95 SS |
3793 | spin_unlock_irqrestore(&xhci->lock, flags); |
3794 | ||
3795 | /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */ | |
3796 | timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev, | |
6e4468b9 | 3797 | XHCI_CMD_DEFAULT_TIMEOUT); |
3ffbba95 SS |
3798 | /* FIXME: From section 4.3.4: "Software shall be responsible for timing |
3799 | * the SetAddress() "recovery interval" required by USB and aborting the | |
3800 | * command on a timeout. | |
3801 | */ | |
3802 | if (timeleft <= 0) { | |
6f8ffc0b DW |
3803 | xhci_warn(xhci, "%s while waiting for setup %s command\n", |
3804 | timeleft == 0 ? "Timeout" : "Signal", act); | |
6e4468b9 EF |
3805 | /* cancel the address device command */ |
3806 | ret = xhci_cancel_cmd(xhci, NULL, cmd_trb); | |
3807 | if (ret < 0) | |
3808 | return ret; | |
3ffbba95 SS |
3809 | return -ETIME; |
3810 | } | |
3811 | ||
3ffbba95 SS |
3812 | switch (virt_dev->cmd_status) { |
3813 | case COMP_CTX_STATE: | |
3814 | case COMP_EBADSLT: | |
6f8ffc0b DW |
3815 | xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n", |
3816 | act, udev->slot_id); | |
3ffbba95 SS |
3817 | ret = -EINVAL; |
3818 | break; | |
3819 | case COMP_TX_ERR: | |
6f8ffc0b | 3820 | dev_warn(&udev->dev, "Device not responding to setup %s.\n", act); |
3ffbba95 SS |
3821 | ret = -EPROTO; |
3822 | break; | |
f6ba6fe2 | 3823 | case COMP_DEV_ERR: |
6f8ffc0b DW |
3824 | dev_warn(&udev->dev, |
3825 | "ERROR: Incompatible device for setup %s command\n", act); | |
f6ba6fe2 AH |
3826 | ret = -ENODEV; |
3827 | break; | |
3ffbba95 | 3828 | case COMP_SUCCESS: |
84a99f6f | 3829 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
6f8ffc0b | 3830 | "Successful setup %s command", act); |
3ffbba95 SS |
3831 | break; |
3832 | default: | |
6f8ffc0b DW |
3833 | xhci_err(xhci, |
3834 | "ERROR: unexpected setup %s command completion code 0x%x.\n", | |
3835 | act, virt_dev->cmd_status); | |
66e49d87 | 3836 | xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id); |
d115b048 | 3837 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2); |
1d27fabe | 3838 | trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1); |
3ffbba95 SS |
3839 | ret = -EINVAL; |
3840 | break; | |
3841 | } | |
3842 | if (ret) { | |
3ffbba95 SS |
3843 | return ret; |
3844 | } | |
e8b37332 | 3845 | temp_64 = readq(&xhci->op_regs->dcbaa_ptr); |
84a99f6f XR |
3846 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3847 | "Op regs DCBAA ptr = %#016llx", temp_64); | |
3848 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, | |
3849 | "Slot ID %d dcbaa entry @%p = %#016llx", | |
3850 | udev->slot_id, | |
3851 | &xhci->dcbaa->dev_context_ptrs[udev->slot_id], | |
3852 | (unsigned long long) | |
3853 | le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id])); | |
3854 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, | |
3855 | "Output Context DMA address = %#08llx", | |
d115b048 | 3856 | (unsigned long long)virt_dev->out_ctx->dma); |
3ffbba95 | 3857 | xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); |
d115b048 | 3858 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2); |
1d27fabe | 3859 | trace_xhci_address_ctx(xhci, virt_dev->in_ctx, |
0c052aab | 3860 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
3ffbba95 | 3861 | xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id); |
d115b048 | 3862 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2); |
3ffbba95 SS |
3863 | /* |
3864 | * USB core uses address 1 for the roothubs, so we add one to the | |
3865 | * address given back to us by the HC. | |
3866 | */ | |
d115b048 | 3867 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); |
1d27fabe | 3868 | trace_xhci_address_ctx(xhci, virt_dev->out_ctx, |
0c052aab | 3869 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
f94e0186 | 3870 | /* Zero the input context control for later use */ |
d115b048 JY |
3871 | ctrl_ctx->add_flags = 0; |
3872 | ctrl_ctx->drop_flags = 0; | |
3ffbba95 | 3873 | |
84a99f6f | 3874 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
a2cdc343 DW |
3875 | "Internal device address = %d", |
3876 | le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK); | |
3ffbba95 SS |
3877 | |
3878 | return 0; | |
3879 | } | |
3880 | ||
48fc7dbd DW |
3881 | int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) |
3882 | { | |
3883 | return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS); | |
3884 | } | |
3885 | ||
3886 | int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev) | |
3887 | { | |
3888 | return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY); | |
3889 | } | |
3890 | ||
3f5eb141 LT |
3891 | /* |
3892 | * Transfer the port index into real index in the HW port status | |
3893 | * registers. Caculate offset between the port's PORTSC register | |
3894 | * and port status base. Divide the number of per port register | |
3895 | * to get the real index. The raw port number bases 1. | |
3896 | */ | |
3897 | int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1) | |
3898 | { | |
3899 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
3900 | __le32 __iomem *base_addr = &xhci->op_regs->port_status_base; | |
3901 | __le32 __iomem *addr; | |
3902 | int raw_port; | |
3903 | ||
3904 | if (hcd->speed != HCD_USB3) | |
3905 | addr = xhci->usb2_ports[port1 - 1]; | |
3906 | else | |
3907 | addr = xhci->usb3_ports[port1 - 1]; | |
3908 | ||
3909 | raw_port = (addr - base_addr)/NUM_PORT_REGS + 1; | |
3910 | return raw_port; | |
3911 | } | |
3912 | ||
a558ccdc MN |
3913 | /* |
3914 | * Issue an Evaluate Context command to change the Maximum Exit Latency in the | |
3915 | * slot context. If that succeeds, store the new MEL in the xhci_virt_device. | |
3916 | */ | |
d5c82feb | 3917 | static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci, |
a558ccdc MN |
3918 | struct usb_device *udev, u16 max_exit_latency) |
3919 | { | |
3920 | struct xhci_virt_device *virt_dev; | |
3921 | struct xhci_command *command; | |
3922 | struct xhci_input_control_ctx *ctrl_ctx; | |
3923 | struct xhci_slot_ctx *slot_ctx; | |
3924 | unsigned long flags; | |
3925 | int ret; | |
3926 | ||
3927 | spin_lock_irqsave(&xhci->lock, flags); | |
3928 | if (max_exit_latency == xhci->devs[udev->slot_id]->current_mel) { | |
3929 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3930 | return 0; | |
3931 | } | |
3932 | ||
3933 | /* Attempt to issue an Evaluate Context command to change the MEL. */ | |
3934 | virt_dev = xhci->devs[udev->slot_id]; | |
3935 | command = xhci->lpm_command; | |
92f8e767 SS |
3936 | ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx); |
3937 | if (!ctrl_ctx) { | |
3938 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3939 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
3940 | __func__); | |
3941 | return -ENOMEM; | |
3942 | } | |
3943 | ||
a558ccdc MN |
3944 | xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx); |
3945 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3946 | ||
a558ccdc MN |
3947 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
3948 | slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx); | |
3949 | slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT)); | |
3950 | slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency); | |
3951 | ||
3a7fa5be XR |
3952 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
3953 | "Set up evaluate context for LPM MEL change."); | |
a558ccdc MN |
3954 | xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id); |
3955 | xhci_dbg_ctx(xhci, command->in_ctx, 0); | |
3956 | ||
3957 | /* Issue and wait for the evaluate context command. */ | |
3958 | ret = xhci_configure_endpoint(xhci, udev, command, | |
3959 | true, true); | |
3960 | xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id); | |
3961 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0); | |
3962 | ||
3963 | if (!ret) { | |
3964 | spin_lock_irqsave(&xhci->lock, flags); | |
3965 | virt_dev->current_mel = max_exit_latency; | |
3966 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3967 | } | |
3968 | return ret; | |
3969 | } | |
3970 | ||
84ebc102 | 3971 | #ifdef CONFIG_PM_RUNTIME |
9574323c AX |
3972 | |
3973 | /* BESL to HIRD Encoding array for USB2 LPM */ | |
3974 | static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000, | |
3975 | 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000}; | |
3976 | ||
3977 | /* Calculate HIRD/BESL for USB2 PORTPMSC*/ | |
f99298bf AX |
3978 | static int xhci_calculate_hird_besl(struct xhci_hcd *xhci, |
3979 | struct usb_device *udev) | |
9574323c | 3980 | { |
f99298bf AX |
3981 | int u2del, besl, besl_host; |
3982 | int besl_device = 0; | |
3983 | u32 field; | |
3984 | ||
3985 | u2del = HCS_U2_LATENCY(xhci->hcs_params3); | |
3986 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
9574323c | 3987 | |
f99298bf AX |
3988 | if (field & USB_BESL_SUPPORT) { |
3989 | for (besl_host = 0; besl_host < 16; besl_host++) { | |
3990 | if (xhci_besl_encoding[besl_host] >= u2del) | |
9574323c AX |
3991 | break; |
3992 | } | |
f99298bf AX |
3993 | /* Use baseline BESL value as default */ |
3994 | if (field & USB_BESL_BASELINE_VALID) | |
3995 | besl_device = USB_GET_BESL_BASELINE(field); | |
3996 | else if (field & USB_BESL_DEEP_VALID) | |
3997 | besl_device = USB_GET_BESL_DEEP(field); | |
9574323c AX |
3998 | } else { |
3999 | if (u2del <= 50) | |
f99298bf | 4000 | besl_host = 0; |
9574323c | 4001 | else |
f99298bf | 4002 | besl_host = (u2del - 51) / 75 + 1; |
9574323c AX |
4003 | } |
4004 | ||
f99298bf AX |
4005 | besl = besl_host + besl_device; |
4006 | if (besl > 15) | |
4007 | besl = 15; | |
4008 | ||
4009 | return besl; | |
9574323c AX |
4010 | } |
4011 | ||
a558ccdc MN |
4012 | /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */ |
4013 | static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev) | |
4014 | { | |
4015 | u32 field; | |
4016 | int l1; | |
4017 | int besld = 0; | |
4018 | int hirdm = 0; | |
4019 | ||
4020 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
4021 | ||
4022 | /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */ | |
17f34867 | 4023 | l1 = udev->l1_params.timeout / 256; |
a558ccdc MN |
4024 | |
4025 | /* device has preferred BESLD */ | |
4026 | if (field & USB_BESL_DEEP_VALID) { | |
4027 | besld = USB_GET_BESL_DEEP(field); | |
4028 | hirdm = 1; | |
4029 | } | |
4030 | ||
4031 | return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm); | |
4032 | } | |
4033 | ||
65580b43 AX |
4034 | int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, |
4035 | struct usb_device *udev, int enable) | |
4036 | { | |
4037 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4038 | __le32 __iomem **port_array; | |
a558ccdc MN |
4039 | __le32 __iomem *pm_addr, *hlpm_addr; |
4040 | u32 pm_val, hlpm_val, field; | |
65580b43 AX |
4041 | unsigned int port_num; |
4042 | unsigned long flags; | |
a558ccdc MN |
4043 | int hird, exit_latency; |
4044 | int ret; | |
65580b43 AX |
4045 | |
4046 | if (hcd->speed == HCD_USB3 || !xhci->hw_lpm_support || | |
4047 | !udev->lpm_capable) | |
4048 | return -EPERM; | |
4049 | ||
4050 | if (!udev->parent || udev->parent->parent || | |
4051 | udev->descriptor.bDeviceClass == USB_CLASS_HUB) | |
4052 | return -EPERM; | |
4053 | ||
4054 | if (udev->usb2_hw_lpm_capable != 1) | |
4055 | return -EPERM; | |
4056 | ||
4057 | spin_lock_irqsave(&xhci->lock, flags); | |
4058 | ||
4059 | port_array = xhci->usb2_ports; | |
4060 | port_num = udev->portnum - 1; | |
b6e76371 | 4061 | pm_addr = port_array[port_num] + PORTPMSC; |
b0ba9720 | 4062 | pm_val = readl(pm_addr); |
a558ccdc MN |
4063 | hlpm_addr = port_array[port_num] + PORTHLPMC; |
4064 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
65580b43 AX |
4065 | |
4066 | xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n", | |
4067 | enable ? "enable" : "disable", port_num); | |
4068 | ||
65580b43 | 4069 | if (enable) { |
a558ccdc MN |
4070 | /* Host supports BESL timeout instead of HIRD */ |
4071 | if (udev->usb2_hw_lpm_besl_capable) { | |
4072 | /* if device doesn't have a preferred BESL value use a | |
4073 | * default one which works with mixed HIRD and BESL | |
4074 | * systems. See XHCI_DEFAULT_BESL definition in xhci.h | |
4075 | */ | |
4076 | if ((field & USB_BESL_SUPPORT) && | |
4077 | (field & USB_BESL_BASELINE_VALID)) | |
4078 | hird = USB_GET_BESL_BASELINE(field); | |
4079 | else | |
17f34867 | 4080 | hird = udev->l1_params.besl; |
a558ccdc MN |
4081 | |
4082 | exit_latency = xhci_besl_encoding[hird]; | |
4083 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4084 | ||
4085 | /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx | |
4086 | * input context for link powermanagement evaluate | |
4087 | * context commands. It is protected by hcd->bandwidth | |
4088 | * mutex and is shared by all devices. We need to set | |
4089 | * the max ext latency in USB 2 BESL LPM as well, so | |
4090 | * use the same mutex and xhci_change_max_exit_latency() | |
4091 | */ | |
4092 | mutex_lock(hcd->bandwidth_mutex); | |
4093 | ret = xhci_change_max_exit_latency(xhci, udev, | |
4094 | exit_latency); | |
4095 | mutex_unlock(hcd->bandwidth_mutex); | |
4096 | ||
4097 | if (ret < 0) | |
4098 | return ret; | |
4099 | spin_lock_irqsave(&xhci->lock, flags); | |
4100 | ||
4101 | hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev); | |
204b7793 | 4102 | writel(hlpm_val, hlpm_addr); |
a558ccdc | 4103 | /* flush write */ |
b0ba9720 | 4104 | readl(hlpm_addr); |
a558ccdc MN |
4105 | } else { |
4106 | hird = xhci_calculate_hird_besl(xhci, udev); | |
4107 | } | |
4108 | ||
4109 | pm_val &= ~PORT_HIRD_MASK; | |
58e21f73 | 4110 | pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id); |
204b7793 | 4111 | writel(pm_val, pm_addr); |
b0ba9720 | 4112 | pm_val = readl(pm_addr); |
a558ccdc | 4113 | pm_val |= PORT_HLE; |
204b7793 | 4114 | writel(pm_val, pm_addr); |
a558ccdc | 4115 | /* flush write */ |
b0ba9720 | 4116 | readl(pm_addr); |
65580b43 | 4117 | } else { |
58e21f73 | 4118 | pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK); |
204b7793 | 4119 | writel(pm_val, pm_addr); |
a558ccdc | 4120 | /* flush write */ |
b0ba9720 | 4121 | readl(pm_addr); |
a558ccdc MN |
4122 | if (udev->usb2_hw_lpm_besl_capable) { |
4123 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4124 | mutex_lock(hcd->bandwidth_mutex); | |
4125 | xhci_change_max_exit_latency(xhci, udev, 0); | |
4126 | mutex_unlock(hcd->bandwidth_mutex); | |
4127 | return 0; | |
4128 | } | |
65580b43 AX |
4129 | } |
4130 | ||
4131 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4132 | return 0; | |
4133 | } | |
4134 | ||
b630d4b9 MN |
4135 | /* check if a usb2 port supports a given extened capability protocol |
4136 | * only USB2 ports extended protocol capability values are cached. | |
4137 | * Return 1 if capability is supported | |
4138 | */ | |
4139 | static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port, | |
4140 | unsigned capability) | |
4141 | { | |
4142 | u32 port_offset, port_count; | |
4143 | int i; | |
4144 | ||
4145 | for (i = 0; i < xhci->num_ext_caps; i++) { | |
4146 | if (xhci->ext_caps[i] & capability) { | |
4147 | /* port offsets starts at 1 */ | |
4148 | port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1; | |
4149 | port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]); | |
4150 | if (port >= port_offset && | |
4151 | port < port_offset + port_count) | |
4152 | return 1; | |
4153 | } | |
4154 | } | |
4155 | return 0; | |
4156 | } | |
4157 | ||
b01bcbf7 SS |
4158 | int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev) |
4159 | { | |
4160 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
b630d4b9 | 4161 | int portnum = udev->portnum - 1; |
b01bcbf7 | 4162 | |
de68bab4 SS |
4163 | if (hcd->speed == HCD_USB3 || !xhci->sw_lpm_support || |
4164 | !udev->lpm_capable) | |
4165 | return 0; | |
4166 | ||
4167 | /* we only support lpm for non-hub device connected to root hub yet */ | |
4168 | if (!udev->parent || udev->parent->parent || | |
4169 | udev->descriptor.bDeviceClass == USB_CLASS_HUB) | |
4170 | return 0; | |
4171 | ||
4172 | if (xhci->hw_lpm_support == 1 && | |
4173 | xhci_check_usb2_port_capability( | |
4174 | xhci, portnum, XHCI_HLC)) { | |
4175 | udev->usb2_hw_lpm_capable = 1; | |
4176 | udev->l1_params.timeout = XHCI_L1_TIMEOUT; | |
4177 | udev->l1_params.besl = XHCI_DEFAULT_BESL; | |
4178 | if (xhci_check_usb2_port_capability(xhci, portnum, | |
4179 | XHCI_BLC)) | |
4180 | udev->usb2_hw_lpm_besl_capable = 1; | |
b01bcbf7 SS |
4181 | } |
4182 | ||
4183 | return 0; | |
4184 | } | |
4185 | ||
4186 | #else | |
4187 | ||
4188 | int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, | |
4189 | struct usb_device *udev, int enable) | |
4190 | { | |
4191 | return 0; | |
4192 | } | |
4193 | ||
4194 | int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev) | |
4195 | { | |
4196 | return 0; | |
4197 | } | |
4198 | ||
84ebc102 | 4199 | #endif /* CONFIG_PM_RUNTIME */ |
b01bcbf7 | 4200 | |
3b3db026 SS |
4201 | /*---------------------- USB 3.0 Link PM functions ------------------------*/ |
4202 | ||
b01bcbf7 | 4203 | #ifdef CONFIG_PM |
e3567d2c SS |
4204 | /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */ |
4205 | static unsigned long long xhci_service_interval_to_ns( | |
4206 | struct usb_endpoint_descriptor *desc) | |
4207 | { | |
16b45fdf | 4208 | return (1ULL << (desc->bInterval - 1)) * 125 * 1000; |
e3567d2c SS |
4209 | } |
4210 | ||
3b3db026 SS |
4211 | static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev, |
4212 | enum usb3_link_state state) | |
4213 | { | |
4214 | unsigned long long sel; | |
4215 | unsigned long long pel; | |
4216 | unsigned int max_sel_pel; | |
4217 | char *state_name; | |
4218 | ||
4219 | switch (state) { | |
4220 | case USB3_LPM_U1: | |
4221 | /* Convert SEL and PEL stored in nanoseconds to microseconds */ | |
4222 | sel = DIV_ROUND_UP(udev->u1_params.sel, 1000); | |
4223 | pel = DIV_ROUND_UP(udev->u1_params.pel, 1000); | |
4224 | max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL; | |
4225 | state_name = "U1"; | |
4226 | break; | |
4227 | case USB3_LPM_U2: | |
4228 | sel = DIV_ROUND_UP(udev->u2_params.sel, 1000); | |
4229 | pel = DIV_ROUND_UP(udev->u2_params.pel, 1000); | |
4230 | max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL; | |
4231 | state_name = "U2"; | |
4232 | break; | |
4233 | default: | |
4234 | dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n", | |
4235 | __func__); | |
e25e62ae | 4236 | return USB3_LPM_DISABLED; |
3b3db026 SS |
4237 | } |
4238 | ||
4239 | if (sel <= max_sel_pel && pel <= max_sel_pel) | |
4240 | return USB3_LPM_DEVICE_INITIATED; | |
4241 | ||
4242 | if (sel > max_sel_pel) | |
4243 | dev_dbg(&udev->dev, "Device-initiated %s disabled " | |
4244 | "due to long SEL %llu ms\n", | |
4245 | state_name, sel); | |
4246 | else | |
4247 | dev_dbg(&udev->dev, "Device-initiated %s disabled " | |
03e64e96 | 4248 | "due to long PEL %llu ms\n", |
3b3db026 SS |
4249 | state_name, pel); |
4250 | return USB3_LPM_DISABLED; | |
4251 | } | |
4252 | ||
e3567d2c SS |
4253 | /* Returns the hub-encoded U1 timeout value. |
4254 | * The U1 timeout should be the maximum of the following values: | |
4255 | * - For control endpoints, U1 system exit latency (SEL) * 3 | |
4256 | * - For bulk endpoints, U1 SEL * 5 | |
4257 | * - For interrupt endpoints: | |
4258 | * - Notification EPs, U1 SEL * 3 | |
4259 | * - Periodic EPs, max(105% of bInterval, U1 SEL * 2) | |
4260 | * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2) | |
4261 | */ | |
4262 | static u16 xhci_calculate_intel_u1_timeout(struct usb_device *udev, | |
4263 | struct usb_endpoint_descriptor *desc) | |
4264 | { | |
4265 | unsigned long long timeout_ns; | |
4266 | int ep_type; | |
4267 | int intr_type; | |
4268 | ||
4269 | ep_type = usb_endpoint_type(desc); | |
4270 | switch (ep_type) { | |
4271 | case USB_ENDPOINT_XFER_CONTROL: | |
4272 | timeout_ns = udev->u1_params.sel * 3; | |
4273 | break; | |
4274 | case USB_ENDPOINT_XFER_BULK: | |
4275 | timeout_ns = udev->u1_params.sel * 5; | |
4276 | break; | |
4277 | case USB_ENDPOINT_XFER_INT: | |
4278 | intr_type = usb_endpoint_interrupt_type(desc); | |
4279 | if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) { | |
4280 | timeout_ns = udev->u1_params.sel * 3; | |
4281 | break; | |
4282 | } | |
4283 | /* Otherwise the calculation is the same as isoc eps */ | |
4284 | case USB_ENDPOINT_XFER_ISOC: | |
4285 | timeout_ns = xhci_service_interval_to_ns(desc); | |
c88db160 | 4286 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100); |
e3567d2c SS |
4287 | if (timeout_ns < udev->u1_params.sel * 2) |
4288 | timeout_ns = udev->u1_params.sel * 2; | |
4289 | break; | |
4290 | default: | |
4291 | return 0; | |
4292 | } | |
4293 | ||
4294 | /* The U1 timeout is encoded in 1us intervals. */ | |
c88db160 | 4295 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000); |
e3567d2c SS |
4296 | /* Don't return a timeout of zero, because that's USB3_LPM_DISABLED. */ |
4297 | if (timeout_ns == USB3_LPM_DISABLED) | |
4298 | timeout_ns++; | |
4299 | ||
4300 | /* If the necessary timeout value is bigger than what we can set in the | |
4301 | * USB 3.0 hub, we have to disable hub-initiated U1. | |
4302 | */ | |
4303 | if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT) | |
4304 | return timeout_ns; | |
4305 | dev_dbg(&udev->dev, "Hub-initiated U1 disabled " | |
4306 | "due to long timeout %llu ms\n", timeout_ns); | |
4307 | return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1); | |
4308 | } | |
4309 | ||
4310 | /* Returns the hub-encoded U2 timeout value. | |
4311 | * The U2 timeout should be the maximum of: | |
4312 | * - 10 ms (to avoid the bandwidth impact on the scheduler) | |
4313 | * - largest bInterval of any active periodic endpoint (to avoid going | |
4314 | * into lower power link states between intervals). | |
4315 | * - the U2 Exit Latency of the device | |
4316 | */ | |
4317 | static u16 xhci_calculate_intel_u2_timeout(struct usb_device *udev, | |
4318 | struct usb_endpoint_descriptor *desc) | |
4319 | { | |
4320 | unsigned long long timeout_ns; | |
4321 | unsigned long long u2_del_ns; | |
4322 | ||
4323 | timeout_ns = 10 * 1000 * 1000; | |
4324 | ||
4325 | if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) && | |
4326 | (xhci_service_interval_to_ns(desc) > timeout_ns)) | |
4327 | timeout_ns = xhci_service_interval_to_ns(desc); | |
4328 | ||
966e7a85 | 4329 | u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL; |
e3567d2c SS |
4330 | if (u2_del_ns > timeout_ns) |
4331 | timeout_ns = u2_del_ns; | |
4332 | ||
4333 | /* The U2 timeout is encoded in 256us intervals */ | |
c88db160 | 4334 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000); |
e3567d2c SS |
4335 | /* If the necessary timeout value is bigger than what we can set in the |
4336 | * USB 3.0 hub, we have to disable hub-initiated U2. | |
4337 | */ | |
4338 | if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT) | |
4339 | return timeout_ns; | |
4340 | dev_dbg(&udev->dev, "Hub-initiated U2 disabled " | |
4341 | "due to long timeout %llu ms\n", timeout_ns); | |
4342 | return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2); | |
4343 | } | |
4344 | ||
3b3db026 SS |
4345 | static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci, |
4346 | struct usb_device *udev, | |
4347 | struct usb_endpoint_descriptor *desc, | |
4348 | enum usb3_link_state state, | |
4349 | u16 *timeout) | |
4350 | { | |
e3567d2c SS |
4351 | if (state == USB3_LPM_U1) { |
4352 | if (xhci->quirks & XHCI_INTEL_HOST) | |
4353 | return xhci_calculate_intel_u1_timeout(udev, desc); | |
4354 | } else { | |
4355 | if (xhci->quirks & XHCI_INTEL_HOST) | |
4356 | return xhci_calculate_intel_u2_timeout(udev, desc); | |
4357 | } | |
4358 | ||
3b3db026 SS |
4359 | return USB3_LPM_DISABLED; |
4360 | } | |
4361 | ||
4362 | static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci, | |
4363 | struct usb_device *udev, | |
4364 | struct usb_endpoint_descriptor *desc, | |
4365 | enum usb3_link_state state, | |
4366 | u16 *timeout) | |
4367 | { | |
4368 | u16 alt_timeout; | |
4369 | ||
4370 | alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev, | |
4371 | desc, state, timeout); | |
4372 | ||
4373 | /* If we found we can't enable hub-initiated LPM, or | |
4374 | * the U1 or U2 exit latency was too high to allow | |
4375 | * device-initiated LPM as well, just stop searching. | |
4376 | */ | |
4377 | if (alt_timeout == USB3_LPM_DISABLED || | |
4378 | alt_timeout == USB3_LPM_DEVICE_INITIATED) { | |
4379 | *timeout = alt_timeout; | |
4380 | return -E2BIG; | |
4381 | } | |
4382 | if (alt_timeout > *timeout) | |
4383 | *timeout = alt_timeout; | |
4384 | return 0; | |
4385 | } | |
4386 | ||
4387 | static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci, | |
4388 | struct usb_device *udev, | |
4389 | struct usb_host_interface *alt, | |
4390 | enum usb3_link_state state, | |
4391 | u16 *timeout) | |
4392 | { | |
4393 | int j; | |
4394 | ||
4395 | for (j = 0; j < alt->desc.bNumEndpoints; j++) { | |
4396 | if (xhci_update_timeout_for_endpoint(xhci, udev, | |
4397 | &alt->endpoint[j].desc, state, timeout)) | |
4398 | return -E2BIG; | |
4399 | continue; | |
4400 | } | |
4401 | return 0; | |
4402 | } | |
4403 | ||
e3567d2c SS |
4404 | static int xhci_check_intel_tier_policy(struct usb_device *udev, |
4405 | enum usb3_link_state state) | |
4406 | { | |
4407 | struct usb_device *parent; | |
4408 | unsigned int num_hubs; | |
4409 | ||
4410 | if (state == USB3_LPM_U2) | |
4411 | return 0; | |
4412 | ||
4413 | /* Don't enable U1 if the device is on a 2nd tier hub or lower. */ | |
4414 | for (parent = udev->parent, num_hubs = 0; parent->parent; | |
4415 | parent = parent->parent) | |
4416 | num_hubs++; | |
4417 | ||
4418 | if (num_hubs < 2) | |
4419 | return 0; | |
4420 | ||
4421 | dev_dbg(&udev->dev, "Disabling U1 link state for device" | |
4422 | " below second-tier hub.\n"); | |
4423 | dev_dbg(&udev->dev, "Plug device into first-tier hub " | |
4424 | "to decrease power consumption.\n"); | |
4425 | return -E2BIG; | |
4426 | } | |
4427 | ||
3b3db026 SS |
4428 | static int xhci_check_tier_policy(struct xhci_hcd *xhci, |
4429 | struct usb_device *udev, | |
4430 | enum usb3_link_state state) | |
4431 | { | |
e3567d2c SS |
4432 | if (xhci->quirks & XHCI_INTEL_HOST) |
4433 | return xhci_check_intel_tier_policy(udev, state); | |
3b3db026 SS |
4434 | return -EINVAL; |
4435 | } | |
4436 | ||
4437 | /* Returns the U1 or U2 timeout that should be enabled. | |
4438 | * If the tier check or timeout setting functions return with a non-zero exit | |
4439 | * code, that means the timeout value has been finalized and we shouldn't look | |
4440 | * at any more endpoints. | |
4441 | */ | |
4442 | static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd, | |
4443 | struct usb_device *udev, enum usb3_link_state state) | |
4444 | { | |
4445 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4446 | struct usb_host_config *config; | |
4447 | char *state_name; | |
4448 | int i; | |
4449 | u16 timeout = USB3_LPM_DISABLED; | |
4450 | ||
4451 | if (state == USB3_LPM_U1) | |
4452 | state_name = "U1"; | |
4453 | else if (state == USB3_LPM_U2) | |
4454 | state_name = "U2"; | |
4455 | else { | |
4456 | dev_warn(&udev->dev, "Can't enable unknown link state %i\n", | |
4457 | state); | |
4458 | return timeout; | |
4459 | } | |
4460 | ||
4461 | if (xhci_check_tier_policy(xhci, udev, state) < 0) | |
4462 | return timeout; | |
4463 | ||
4464 | /* Gather some information about the currently installed configuration | |
4465 | * and alternate interface settings. | |
4466 | */ | |
4467 | if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc, | |
4468 | state, &timeout)) | |
4469 | return timeout; | |
4470 | ||
4471 | config = udev->actconfig; | |
4472 | if (!config) | |
4473 | return timeout; | |
4474 | ||
64ba419b | 4475 | for (i = 0; i < config->desc.bNumInterfaces; i++) { |
3b3db026 SS |
4476 | struct usb_driver *driver; |
4477 | struct usb_interface *intf = config->interface[i]; | |
4478 | ||
4479 | if (!intf) | |
4480 | continue; | |
4481 | ||
4482 | /* Check if any currently bound drivers want hub-initiated LPM | |
4483 | * disabled. | |
4484 | */ | |
4485 | if (intf->dev.driver) { | |
4486 | driver = to_usb_driver(intf->dev.driver); | |
4487 | if (driver && driver->disable_hub_initiated_lpm) { | |
4488 | dev_dbg(&udev->dev, "Hub-initiated %s disabled " | |
4489 | "at request of driver %s\n", | |
4490 | state_name, driver->name); | |
4491 | return xhci_get_timeout_no_hub_lpm(udev, state); | |
4492 | } | |
4493 | } | |
4494 | ||
4495 | /* Not sure how this could happen... */ | |
4496 | if (!intf->cur_altsetting) | |
4497 | continue; | |
4498 | ||
4499 | if (xhci_update_timeout_for_interface(xhci, udev, | |
4500 | intf->cur_altsetting, | |
4501 | state, &timeout)) | |
4502 | return timeout; | |
4503 | } | |
4504 | return timeout; | |
4505 | } | |
4506 | ||
3b3db026 SS |
4507 | static int calculate_max_exit_latency(struct usb_device *udev, |
4508 | enum usb3_link_state state_changed, | |
4509 | u16 hub_encoded_timeout) | |
4510 | { | |
4511 | unsigned long long u1_mel_us = 0; | |
4512 | unsigned long long u2_mel_us = 0; | |
4513 | unsigned long long mel_us = 0; | |
4514 | bool disabling_u1; | |
4515 | bool disabling_u2; | |
4516 | bool enabling_u1; | |
4517 | bool enabling_u2; | |
4518 | ||
4519 | disabling_u1 = (state_changed == USB3_LPM_U1 && | |
4520 | hub_encoded_timeout == USB3_LPM_DISABLED); | |
4521 | disabling_u2 = (state_changed == USB3_LPM_U2 && | |
4522 | hub_encoded_timeout == USB3_LPM_DISABLED); | |
4523 | ||
4524 | enabling_u1 = (state_changed == USB3_LPM_U1 && | |
4525 | hub_encoded_timeout != USB3_LPM_DISABLED); | |
4526 | enabling_u2 = (state_changed == USB3_LPM_U2 && | |
4527 | hub_encoded_timeout != USB3_LPM_DISABLED); | |
4528 | ||
4529 | /* If U1 was already enabled and we're not disabling it, | |
4530 | * or we're going to enable U1, account for the U1 max exit latency. | |
4531 | */ | |
4532 | if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) || | |
4533 | enabling_u1) | |
4534 | u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000); | |
4535 | if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) || | |
4536 | enabling_u2) | |
4537 | u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000); | |
4538 | ||
4539 | if (u1_mel_us > u2_mel_us) | |
4540 | mel_us = u1_mel_us; | |
4541 | else | |
4542 | mel_us = u2_mel_us; | |
4543 | /* xHCI host controller max exit latency field is only 16 bits wide. */ | |
4544 | if (mel_us > MAX_EXIT) { | |
4545 | dev_warn(&udev->dev, "Link PM max exit latency of %lluus " | |
4546 | "is too big.\n", mel_us); | |
4547 | return -E2BIG; | |
4548 | } | |
4549 | return mel_us; | |
4550 | } | |
4551 | ||
4552 | /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */ | |
4553 | int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, | |
4554 | struct usb_device *udev, enum usb3_link_state state) | |
4555 | { | |
4556 | struct xhci_hcd *xhci; | |
4557 | u16 hub_encoded_timeout; | |
4558 | int mel; | |
4559 | int ret; | |
4560 | ||
4561 | xhci = hcd_to_xhci(hcd); | |
4562 | /* The LPM timeout values are pretty host-controller specific, so don't | |
4563 | * enable hub-initiated timeouts unless the vendor has provided | |
4564 | * information about their timeout algorithm. | |
4565 | */ | |
4566 | if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) || | |
4567 | !xhci->devs[udev->slot_id]) | |
4568 | return USB3_LPM_DISABLED; | |
4569 | ||
4570 | hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state); | |
4571 | mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout); | |
4572 | if (mel < 0) { | |
4573 | /* Max Exit Latency is too big, disable LPM. */ | |
4574 | hub_encoded_timeout = USB3_LPM_DISABLED; | |
4575 | mel = 0; | |
4576 | } | |
4577 | ||
4578 | ret = xhci_change_max_exit_latency(xhci, udev, mel); | |
4579 | if (ret) | |
4580 | return ret; | |
4581 | return hub_encoded_timeout; | |
4582 | } | |
4583 | ||
4584 | int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, | |
4585 | struct usb_device *udev, enum usb3_link_state state) | |
4586 | { | |
4587 | struct xhci_hcd *xhci; | |
4588 | u16 mel; | |
4589 | int ret; | |
4590 | ||
4591 | xhci = hcd_to_xhci(hcd); | |
4592 | if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) || | |
4593 | !xhci->devs[udev->slot_id]) | |
4594 | return 0; | |
4595 | ||
4596 | mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED); | |
4597 | ret = xhci_change_max_exit_latency(xhci, udev, mel); | |
4598 | if (ret) | |
4599 | return ret; | |
4600 | return 0; | |
4601 | } | |
b01bcbf7 | 4602 | #else /* CONFIG_PM */ |
9574323c | 4603 | |
b01bcbf7 SS |
4604 | int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, |
4605 | struct usb_device *udev, enum usb3_link_state state) | |
65580b43 | 4606 | { |
b01bcbf7 | 4607 | return USB3_LPM_DISABLED; |
65580b43 AX |
4608 | } |
4609 | ||
b01bcbf7 SS |
4610 | int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, |
4611 | struct usb_device *udev, enum usb3_link_state state) | |
9574323c AX |
4612 | { |
4613 | return 0; | |
4614 | } | |
b01bcbf7 | 4615 | #endif /* CONFIG_PM */ |
9574323c | 4616 | |
b01bcbf7 | 4617 | /*-------------------------------------------------------------------------*/ |
9574323c | 4618 | |
ac1c1b7f SS |
4619 | /* Once a hub descriptor is fetched for a device, we need to update the xHC's |
4620 | * internal data structures for the device. | |
4621 | */ | |
4622 | int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, | |
4623 | struct usb_tt *tt, gfp_t mem_flags) | |
4624 | { | |
4625 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4626 | struct xhci_virt_device *vdev; | |
4627 | struct xhci_command *config_cmd; | |
4628 | struct xhci_input_control_ctx *ctrl_ctx; | |
4629 | struct xhci_slot_ctx *slot_ctx; | |
4630 | unsigned long flags; | |
4631 | unsigned think_time; | |
4632 | int ret; | |
4633 | ||
4634 | /* Ignore root hubs */ | |
4635 | if (!hdev->parent) | |
4636 | return 0; | |
4637 | ||
4638 | vdev = xhci->devs[hdev->slot_id]; | |
4639 | if (!vdev) { | |
4640 | xhci_warn(xhci, "Cannot update hub desc for unknown device.\n"); | |
4641 | return -EINVAL; | |
4642 | } | |
a1d78c16 | 4643 | config_cmd = xhci_alloc_command(xhci, true, true, mem_flags); |
ac1c1b7f SS |
4644 | if (!config_cmd) { |
4645 | xhci_dbg(xhci, "Could not allocate xHCI command structure.\n"); | |
4646 | return -ENOMEM; | |
4647 | } | |
92f8e767 SS |
4648 | ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx); |
4649 | if (!ctrl_ctx) { | |
4650 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
4651 | __func__); | |
4652 | xhci_free_command(xhci, config_cmd); | |
4653 | return -ENOMEM; | |
4654 | } | |
ac1c1b7f SS |
4655 | |
4656 | spin_lock_irqsave(&xhci->lock, flags); | |
839c817c SS |
4657 | if (hdev->speed == USB_SPEED_HIGH && |
4658 | xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) { | |
4659 | xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n"); | |
4660 | xhci_free_command(xhci, config_cmd); | |
4661 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4662 | return -ENOMEM; | |
4663 | } | |
4664 | ||
ac1c1b7f | 4665 | xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx); |
28ccd296 | 4666 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
ac1c1b7f | 4667 | slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx); |
28ccd296 | 4668 | slot_ctx->dev_info |= cpu_to_le32(DEV_HUB); |
ac1c1b7f | 4669 | if (tt->multi) |
28ccd296 | 4670 | slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); |
ac1c1b7f SS |
4671 | if (xhci->hci_version > 0x95) { |
4672 | xhci_dbg(xhci, "xHCI version %x needs hub " | |
4673 | "TT think time and number of ports\n", | |
4674 | (unsigned int) xhci->hci_version); | |
28ccd296 | 4675 | slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild)); |
ac1c1b7f SS |
4676 | /* Set TT think time - convert from ns to FS bit times. |
4677 | * 0 = 8 FS bit times, 1 = 16 FS bit times, | |
4678 | * 2 = 24 FS bit times, 3 = 32 FS bit times. | |
700b4173 AX |
4679 | * |
4680 | * xHCI 1.0: this field shall be 0 if the device is not a | |
4681 | * High-spped hub. | |
ac1c1b7f SS |
4682 | */ |
4683 | think_time = tt->think_time; | |
4684 | if (think_time != 0) | |
4685 | think_time = (think_time / 666) - 1; | |
700b4173 AX |
4686 | if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH) |
4687 | slot_ctx->tt_info |= | |
4688 | cpu_to_le32(TT_THINK_TIME(think_time)); | |
ac1c1b7f SS |
4689 | } else { |
4690 | xhci_dbg(xhci, "xHCI version %x doesn't need hub " | |
4691 | "TT think time or number of ports\n", | |
4692 | (unsigned int) xhci->hci_version); | |
4693 | } | |
4694 | slot_ctx->dev_state = 0; | |
4695 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4696 | ||
4697 | xhci_dbg(xhci, "Set up %s for hub device.\n", | |
4698 | (xhci->hci_version > 0x95) ? | |
4699 | "configure endpoint" : "evaluate context"); | |
4700 | xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id); | |
4701 | xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0); | |
4702 | ||
4703 | /* Issue and wait for the configure endpoint or | |
4704 | * evaluate context command. | |
4705 | */ | |
4706 | if (xhci->hci_version > 0x95) | |
4707 | ret = xhci_configure_endpoint(xhci, hdev, config_cmd, | |
4708 | false, false); | |
4709 | else | |
4710 | ret = xhci_configure_endpoint(xhci, hdev, config_cmd, | |
4711 | true, false); | |
4712 | ||
4713 | xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id); | |
4714 | xhci_dbg_ctx(xhci, vdev->out_ctx, 0); | |
4715 | ||
4716 | xhci_free_command(xhci, config_cmd); | |
4717 | return ret; | |
4718 | } | |
4719 | ||
66d4eadd SS |
4720 | int xhci_get_frame(struct usb_hcd *hcd) |
4721 | { | |
4722 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4723 | /* EHCI mods by the periodic size. Why? */ | |
b0ba9720 | 4724 | return readl(&xhci->run_regs->microframe_index) >> 3; |
66d4eadd SS |
4725 | } |
4726 | ||
552e0c4f SAS |
4727 | int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks) |
4728 | { | |
4729 | struct xhci_hcd *xhci; | |
4730 | struct device *dev = hcd->self.controller; | |
4731 | int retval; | |
552e0c4f | 4732 | |
f2d9b991 SS |
4733 | /* Limit the block layer scatter-gather lists to half a segment. */ |
4734 | hcd->self.sg_tablesize = TRBS_PER_SEGMENT / 2; | |
fc76051c ML |
4735 | |
4736 | /* support to build packet from discontinuous buffers */ | |
4737 | hcd->self.no_sg_constraint = 1; | |
4738 | ||
19181bc5 HG |
4739 | /* XHCI controllers don't stop the ep queue on short packets :| */ |
4740 | hcd->self.no_stop_on_short = 1; | |
552e0c4f SAS |
4741 | |
4742 | if (usb_hcd_is_primary_hcd(hcd)) { | |
4743 | xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL); | |
4744 | if (!xhci) | |
4745 | return -ENOMEM; | |
4746 | *((struct xhci_hcd **) hcd->hcd_priv) = xhci; | |
4747 | xhci->main_hcd = hcd; | |
4748 | /* Mark the first roothub as being USB 2.0. | |
4749 | * The xHCI driver will register the USB 3.0 roothub. | |
4750 | */ | |
4751 | hcd->speed = HCD_USB2; | |
4752 | hcd->self.root_hub->speed = USB_SPEED_HIGH; | |
4753 | /* | |
4754 | * USB 2.0 roothub under xHCI has an integrated TT, | |
4755 | * (rate matching hub) as opposed to having an OHCI/UHCI | |
4756 | * companion controller. | |
4757 | */ | |
4758 | hcd->has_tt = 1; | |
4759 | } else { | |
4760 | /* xHCI private pointer was set in xhci_pci_probe for the second | |
4761 | * registered roothub. | |
4762 | */ | |
552e0c4f SAS |
4763 | return 0; |
4764 | } | |
4765 | ||
4766 | xhci->cap_regs = hcd->regs; | |
4767 | xhci->op_regs = hcd->regs + | |
b0ba9720 | 4768 | HC_LENGTH(readl(&xhci->cap_regs->hc_capbase)); |
552e0c4f | 4769 | xhci->run_regs = hcd->regs + |
b0ba9720 | 4770 | (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK); |
552e0c4f | 4771 | /* Cache read-only capability registers */ |
b0ba9720 XR |
4772 | xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1); |
4773 | xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2); | |
4774 | xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3); | |
4775 | xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase); | |
552e0c4f | 4776 | xhci->hci_version = HC_VERSION(xhci->hcc_params); |
b0ba9720 | 4777 | xhci->hcc_params = readl(&xhci->cap_regs->hcc_params); |
552e0c4f SAS |
4778 | xhci_print_registers(xhci); |
4779 | ||
4e6a1ee7 TI |
4780 | xhci->quirks = quirks; |
4781 | ||
552e0c4f SAS |
4782 | get_quirks(dev, xhci); |
4783 | ||
07f3cb7c GC |
4784 | /* In xhci controllers which follow xhci 1.0 spec gives a spurious |
4785 | * success event after a short transfer. This quirk will ignore such | |
4786 | * spurious event. | |
4787 | */ | |
4788 | if (xhci->hci_version > 0x96) | |
4789 | xhci->quirks |= XHCI_SPURIOUS_SUCCESS; | |
4790 | ||
552e0c4f SAS |
4791 | /* Make sure the HC is halted. */ |
4792 | retval = xhci_halt(xhci); | |
4793 | if (retval) | |
4794 | goto error; | |
4795 | ||
4796 | xhci_dbg(xhci, "Resetting HCD\n"); | |
4797 | /* Reset the internal HC memory state and registers. */ | |
4798 | retval = xhci_reset(xhci); | |
4799 | if (retval) | |
4800 | goto error; | |
4801 | xhci_dbg(xhci, "Reset complete\n"); | |
4802 | ||
c10cf118 XR |
4803 | /* Set dma_mask and coherent_dma_mask to 64-bits, |
4804 | * if xHC supports 64-bit addressing */ | |
4805 | if (HCC_64BIT_ADDR(xhci->hcc_params) && | |
4806 | !dma_set_mask(dev, DMA_BIT_MASK(64))) { | |
552e0c4f | 4807 | xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n"); |
c10cf118 | 4808 | dma_set_coherent_mask(dev, DMA_BIT_MASK(64)); |
552e0c4f SAS |
4809 | } |
4810 | ||
4811 | xhci_dbg(xhci, "Calling HCD init\n"); | |
4812 | /* Initialize HCD and host controller data structures. */ | |
4813 | retval = xhci_init(hcd); | |
4814 | if (retval) | |
4815 | goto error; | |
4816 | xhci_dbg(xhci, "Called HCD init\n"); | |
4817 | return 0; | |
4818 | error: | |
4819 | kfree(xhci); | |
4820 | return retval; | |
4821 | } | |
4822 | ||
66d4eadd SS |
4823 | MODULE_DESCRIPTION(DRIVER_DESC); |
4824 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
4825 | MODULE_LICENSE("GPL"); | |
4826 | ||
4827 | static int __init xhci_hcd_init(void) | |
4828 | { | |
0cc47d54 | 4829 | int retval; |
66d4eadd SS |
4830 | |
4831 | retval = xhci_register_pci(); | |
66d4eadd | 4832 | if (retval < 0) { |
5c1127d3 | 4833 | pr_debug("Problem registering PCI driver.\n"); |
66d4eadd SS |
4834 | return retval; |
4835 | } | |
3429e91a SAS |
4836 | retval = xhci_register_plat(); |
4837 | if (retval < 0) { | |
5c1127d3 | 4838 | pr_debug("Problem registering platform driver.\n"); |
3429e91a SAS |
4839 | goto unreg_pci; |
4840 | } | |
98441973 SS |
4841 | /* |
4842 | * Check the compiler generated sizes of structures that must be laid | |
4843 | * out in specific ways for hardware access. | |
4844 | */ | |
4845 | BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8); | |
4846 | BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8); | |
4847 | BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8); | |
4848 | /* xhci_device_control has eight fields, and also | |
4849 | * embeds one xhci_slot_ctx and 31 xhci_ep_ctx | |
4850 | */ | |
98441973 SS |
4851 | BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8); |
4852 | BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8); | |
4853 | BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8); | |
4854 | BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8); | |
4855 | BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8); | |
4856 | /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */ | |
4857 | BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8); | |
66d4eadd | 4858 | return 0; |
3429e91a SAS |
4859 | unreg_pci: |
4860 | xhci_unregister_pci(); | |
4861 | return retval; | |
66d4eadd SS |
4862 | } |
4863 | module_init(xhci_hcd_init); | |
4864 | ||
4865 | static void __exit xhci_hcd_cleanup(void) | |
4866 | { | |
66d4eadd | 4867 | xhci_unregister_pci(); |
3429e91a | 4868 | xhci_unregister_plat(); |
66d4eadd SS |
4869 | } |
4870 | module_exit(xhci_hcd_cleanup); |