[deliverable/linux.git] / drivers / usb / musb / am35x.c

/*
 * Texas Instruments AM35x "glue layer"
 *
 * Copyright (c) 2010, by Texas Instruments
 *
 * Based on the DA8xx "glue layer" code.
 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
 *
 * This file is part of the Inventra Controller Driver for Linux.
 *
 * The Inventra Controller Driver for Linux is free software; you
 * can redistribute it and/or modify it under the terms of the GNU
 * General Public License version 2 as published by the Free Software
 * Foundation.
 *
 * The Inventra Controller Driver for Linux is distributed in
 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
 * without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
 * License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with The Inventra Controller Driver for Linux ; if not,
 * write to the Free Software Foundation, Inc., 59 Temple Place,
 * Suite 330, Boston, MA  02111-1307  USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>

#include <plat/usb.h>

#include "musb_core.h"

/*
 * AM35x specific definitions
 */
/* USB 2.0 OTG module registers */
#define USB_REVISION_REG	0x00
#define USB_CTRL_REG		0x04
#define USB_STAT_REG		0x08
#define USB_EMULATION_REG	0x0c
/* 0x10 Reserved */
#define USB_AUTOREQ_REG		0x14
#define USB_SRP_FIX_TIME_REG	0x18
#define USB_TEARDOWN_REG	0x1c
#define EP_INTR_SRC_REG		0x20
#define EP_INTR_SRC_SET_REG	0x24
#define EP_INTR_SRC_CLEAR_REG	0x28
#define EP_INTR_MASK_REG	0x2c
#define EP_INTR_MASK_SET_REG	0x30
#define EP_INTR_MASK_CLEAR_REG	0x34
#define EP_INTR_SRC_MASKED_REG	0x38
#define CORE_INTR_SRC_REG	0x40
#define CORE_INTR_SRC_SET_REG	0x44
#define CORE_INTR_SRC_CLEAR_REG	0x48
#define CORE_INTR_MASK_REG	0x4c
#define CORE_INTR_MASK_SET_REG	0x50
#define CORE_INTR_MASK_CLEAR_REG 0x54
#define CORE_INTR_SRC_MASKED_REG 0x58
/* 0x5c Reserved */
#define USB_END_OF_INTR_REG	0x60

/* Control register bits */
#define AM35X_SOFT_RESET_MASK	1

/* USB interrupt register bits */
#define AM35X_INTR_USB_SHIFT	16
#define AM35X_INTR_USB_MASK	(0x1ff << AM35X_INTR_USB_SHIFT)
#define AM35X_INTR_DRVVBUS	0x100
#define AM35X_INTR_RX_SHIFT	16
#define AM35X_INTR_TX_SHIFT	0
#define AM35X_TX_EP_MASK	0xffff		/* EP0 + 15 Tx EPs */
#define AM35X_RX_EP_MASK	0xfffe		/* 15 Rx EPs */
#define AM35X_TX_INTR_MASK	(AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
#define AM35X_RX_INTR_MASK	(AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)

#define USB_MENTOR_CORE_OFFSET	0x400

struct am35x_glue {
	struct device		*dev;
	struct platform_device	*musb;
	struct clk		*phy_clk;
	struct clk		*clk;
};
#define glue_to_musb(g)		platform_get_drvdata(g->musb)

/*
 * am35x_musb_enable - enable interrupts
 */
static void am35x_musb_enable(struct musb *musb)
{
	void __iomem *reg_base = musb->ctrl_base;
	u32 epmask;

	/* Workaround: setup IRQs through both register sets. */
	epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
	       ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);

	musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
	musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);

	/* Force the DRVVBUS IRQ so we can start polling for ID change. */
	if (is_otg_enabled(musb))
		musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
			    AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
}

/*
 * am35x_musb_disable - disable HDRC and flush interrupts
 */
static void am35x_musb_disable(struct musb *musb)
{
	void __iomem *reg_base = musb->ctrl_base;

	musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
	musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
			 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
	musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
}

#define portstate(stmt)		stmt

static void am35x_musb_set_vbus(struct musb *musb, int is_on)
{
	WARN_ON(is_on && is_peripheral_active(musb));
}

#define	POLL_SECONDS	2

static struct timer_list otg_workaround;

static void otg_timer(unsigned long _musb)
{
	struct musb		*musb = (void *)_musb;
	void __iomem		*mregs = musb->mregs;
	u8			devctl;
	unsigned long		flags;

	/*
	 * We poll because AM35x's won't expose several OTG-critical
	 * status change events (from the transceiver) otherwise.
	 */
	devctl = musb_readb(mregs, MUSB_DEVCTL);
	dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
		otg_state_string(musb->xceiv->state));

	spin_lock_irqsave(&musb->lock, flags);
	switch (musb->xceiv->state) {
	case OTG_STATE_A_WAIT_BCON:
		devctl &= ~MUSB_DEVCTL_SESSION;
		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);

		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
		if (devctl & MUSB_DEVCTL_BDEVICE) {
			musb->xceiv->state = OTG_STATE_B_IDLE;
			MUSB_DEV_MODE(musb);
		} else {
			musb->xceiv->state = OTG_STATE_A_IDLE;
			MUSB_HST_MODE(musb);
		}
		break;
	case OTG_STATE_A_WAIT_VFALL:
		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
		musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
			    MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
		break;
	case OTG_STATE_B_IDLE:
		if (!is_peripheral_enabled(musb))
			break;

		devctl = musb_readb(mregs, MUSB_DEVCTL);
		if (devctl & MUSB_DEVCTL_BDEVICE)
			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
		else
			musb->xceiv->state = OTG_STATE_A_IDLE;
		break;
	default:
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);
}

static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
{
	static unsigned long last_timer;

	if (!is_otg_enabled(musb))
		return;

	if (timeout == 0)
		timeout = jiffies + msecs_to_jiffies(3);

	/* Never idle if active, or when VBUS timeout is not set as host */
	if (musb->is_active || (musb->a_wait_bcon == 0 &&
				musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
		dev_dbg(musb->controller, "%s active, deleting timer\n",
			otg_state_string(musb->xceiv->state));
		del_timer(&otg_workaround);
		last_timer = jiffies;
		return;
	}

	if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
		dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
		return;
	}
	last_timer = timeout;

	dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
		otg_state_string(musb->xceiv->state),
		jiffies_to_msecs(timeout - jiffies));
	mod_timer(&otg_workaround, timeout);
}

static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
{
	struct musb  *musb = hci;
	void __iomem *reg_base = musb->ctrl_base;
	struct device *dev = musb->controller;
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;
	struct usb_otg *otg = musb->xceiv->otg;
	unsigned long flags;
	irqreturn_t ret = IRQ_NONE;
	u32 epintr, usbintr;

	spin_lock_irqsave(&musb->lock, flags);

	/* Get endpoint interrupts */
	epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);

	if (epintr) {
		musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);

		musb->int_rx =
			(epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
		musb->int_tx =
			(epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
	}

	/* Get usb core interrupts */
	usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
	if (!usbintr && !epintr)
		goto eoi;

	if (usbintr) {
		musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);

		musb->int_usb =
			(usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
	}
	/*
	 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
	 * AM35x's missing ID change IRQ.  We need an ID change IRQ to
	 * switch appropriately between halves of the OTG state machine.
	 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
	 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
	 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
	 */
	if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
		int drvvbus = musb_readl(reg_base, USB_STAT_REG);
		void __iomem *mregs = musb->mregs;
		u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
		int err;

		err = is_host_enabled(musb) && (musb->int_usb &
						MUSB_INTR_VBUSERROR);
		if (err) {
			/*
			 * The Mentor core doesn't debounce VBUS as needed
			 * to cope with device connect current spikes. This
			 * means it's not uncommon for bus-powered devices
			 * to get VBUS errors during enumeration.
			 *
			 * This is a workaround, but newer RTL from Mentor
			 * seems to allow a better one: "re"-starting sessions
			 * without waiting for VBUS to stop registering in
			 * devctl.
			 */
			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
			WARNING("VBUS error workaround (delay coming)\n");
		} else if (is_host_enabled(musb) && drvvbus) {
			MUSB_HST_MODE(musb);
			otg->default_a = 1;
			musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
			portstate(musb->port1_status |= USB_PORT_STAT_POWER);
			del_timer(&otg_workaround);
		} else {
			musb->is_active = 0;
			MUSB_DEV_MODE(musb);
			otg->default_a = 0;
			musb->xceiv->state = OTG_STATE_B_IDLE;
			portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
		}

		/* NOTE: this must complete power-on within 100 ms. */
		dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
				drvvbus ? "on" : "off",
				otg_state_string(musb->xceiv->state),
				err ? " ERROR" : "",
				devctl);
		ret = IRQ_HANDLED;
	}

	if (musb->int_tx || musb->int_rx || musb->int_usb)
		ret |= musb_interrupt(musb);

eoi:
	/* EOI needs to be written for the IRQ to be re-asserted. */
	if (ret == IRQ_HANDLED || epintr || usbintr) {
		/* clear level interrupt */
		if (data->clear_irq)
			data->clear_irq();
		/* write EOI */
		musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
	}

	/* Poll for ID change */
	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
		mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);

	spin_unlock_irqrestore(&musb->lock, flags);

	return ret;
}

static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
{
	struct device *dev = musb->controller;
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;
	int     retval = 0;

	if (data->set_mode)
		data->set_mode(musb_mode);
	else
		retval = -EIO;

	return retval;
}

static int am35x_musb_init(struct musb *musb)
{
	struct device *dev = musb->controller;
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;
	void __iomem *reg_base = musb->ctrl_base;
	u32 rev;

	musb->mregs += USB_MENTOR_CORE_OFFSET;

	/* Returns zero if e.g. not clocked */
	rev = musb_readl(reg_base, USB_REVISION_REG);
	if (!rev)
		return -ENODEV;

	usb_nop_xceiv_register();
	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
	if (IS_ERR_OR_NULL(musb->xceiv))
		return -ENODEV;

	if (is_host_enabled(musb))
		setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);

	/* Reset the musb */
	if (data->reset)
		data->reset();

	/* Reset the controller */
	musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);

	/* Start the on-chip PHY and its PLL. */
	if (data->set_phy_power)
		data->set_phy_power(1);

	msleep(5);

	musb->isr = am35x_musb_interrupt;

	/* clear level interrupt */
	if (data->clear_irq)
		data->clear_irq();

	return 0;
}

static int am35x_musb_exit(struct musb *musb)
{
	struct device *dev = musb->controller;
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;

	if (is_host_enabled(musb))
		del_timer_sync(&otg_workaround);

	/* Shutdown the on-chip PHY and its PLL. */
	if (data->set_phy_power)
		data->set_phy_power(0);

	usb_put_phy(musb->xceiv);
	usb_nop_xceiv_unregister();

	return 0;
}

/* AM35x supports only 32bit read operation */
void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
{
	void __iomem *fifo = hw_ep->fifo;
	u32		val;
	int		i;

	/* Read for 32bit-aligned destination address */
	if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
		readsl(fifo, dst, len >> 2);
		dst += len & ~0x03;
		len &= 0x03;
	}
	/*
	 * Now read the remaining 1 to 3 byte or complete length if
	 * unaligned address.
	 */
	if (len > 4) {
		for (i = 0; i < (len >> 2); i++) {
			*(u32 *) dst = musb_readl(fifo, 0);
			dst += 4;
		}
		len &= 0x03;
	}
	if (len > 0) {
		val = musb_readl(fifo, 0);
		memcpy(dst, &val, len);
	}
}

static const struct musb_platform_ops am35x_ops = {
	.init		= am35x_musb_init,
	.exit		= am35x_musb_exit,

	.enable		= am35x_musb_enable,
	.disable	= am35x_musb_disable,

	.set_mode	= am35x_musb_set_mode,
	.try_idle	= am35x_musb_try_idle,

	.set_vbus	= am35x_musb_set_vbus,
};

static u64 am35x_dmamask = DMA_BIT_MASK(32);

static int __devinit am35x_probe(struct platform_device *pdev)
{
	struct musb_hdrc_platform_data	*pdata = pdev->dev.platform_data;
	struct platform_device		*musb;
	struct am35x_glue		*glue;

	struct clk			*phy_clk;
	struct clk			*clk;

	int				ret = -ENOMEM;

	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
	if (!glue) {
		dev_err(&pdev->dev, "failed to allocate glue context\n");
		goto err0;
	}

	musb = platform_device_alloc("musb-hdrc", -1);
	if (!musb) {
		dev_err(&pdev->dev, "failed to allocate musb device\n");
		goto err1;
	}

	phy_clk = clk_get(&pdev->dev, "fck");
	if (IS_ERR(phy_clk)) {
		dev_err(&pdev->dev, "failed to get PHY clock\n");
		ret = PTR_ERR(phy_clk);
		goto err2;
	}

	clk = clk_get(&pdev->dev, "ick");
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "failed to get clock\n");
		ret = PTR_ERR(clk);
		goto err3;
	}

	ret = clk_enable(phy_clk);
	if (ret) {
		dev_err(&pdev->dev, "failed to enable PHY clock\n");
		goto err4;
	}

	ret = clk_enable(clk);
	if (ret) {
		dev_err(&pdev->dev, "failed to enable clock\n");
		goto err5;
	}

	musb->dev.parent		= &pdev->dev;
	musb->dev.dma_mask		= &am35x_dmamask;
	musb->dev.coherent_dma_mask	= am35x_dmamask;

	glue->dev			= &pdev->dev;
	glue->musb			= musb;
	glue->phy_clk			= phy_clk;
	glue->clk			= clk;

	pdata->platform_ops		= &am35x_ops;

	platform_set_drvdata(pdev, glue);

	ret = platform_device_add_resources(musb, pdev->resource,
			pdev->num_resources);
	if (ret) {
		dev_err(&pdev->dev, "failed to add resources\n");
		goto err6;
	}

	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	if (ret) {
		dev_err(&pdev->dev, "failed to add platform_data\n");
		goto err6;
	}

	ret = platform_device_add(musb);
	if (ret) {
		dev_err(&pdev->dev, "failed to register musb device\n");
		goto err6;
	}

	return 0;

err6:
	clk_disable(clk);

err5:
	clk_disable(phy_clk);

err4:
	clk_put(clk);

err3:
	clk_put(phy_clk);

err2:
	platform_device_put(musb);

err1:
	kfree(glue);

err0:
	return ret;
}

static int __devexit am35x_remove(struct platform_device *pdev)
{
	struct am35x_glue	*glue = platform_get_drvdata(pdev);

	platform_device_del(glue->musb);
	platform_device_put(glue->musb);
	clk_disable(glue->clk);
	clk_disable(glue->phy_clk);
	clk_put(glue->clk);
	clk_put(glue->phy_clk);
	kfree(glue);

	return 0;
}

#ifdef CONFIG_PM
static int am35x_suspend(struct device *dev)
{
	struct am35x_glue	*glue = dev_get_drvdata(dev);
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;

	/* Shutdown the on-chip PHY and its PLL. */
	if (data->set_phy_power)
		data->set_phy_power(0);

	clk_disable(glue->phy_clk);
	clk_disable(glue->clk);

	return 0;
}

static int am35x_resume(struct device *dev)
{
	struct am35x_glue	*glue = dev_get_drvdata(dev);
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;
	int			ret;

	/* Start the on-chip PHY and its PLL. */
	if (data->set_phy_power)
		data->set_phy_power(1);

	ret = clk_enable(glue->phy_clk);
	if (ret) {
		dev_err(dev, "failed to enable PHY clock\n");
		return ret;
	}

	ret = clk_enable(glue->clk);
	if (ret) {
		dev_err(dev, "failed to enable clock\n");
		return ret;
	}

	return 0;
}

static struct dev_pm_ops am35x_pm_ops = {
	.suspend	= am35x_suspend,
	.resume		= am35x_resume,
};

#define DEV_PM_OPS	&am35x_pm_ops
#else
#define DEV_PM_OPS	NULL
#endif

static struct platform_driver am35x_driver = {
	.probe		= am35x_probe,
	.remove		= __devexit_p(am35x_remove),
	.driver		= {
		.name	= "musb-am35x",
		.pm	= DEV_PM_OPS,
	},
};

MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
MODULE_LICENSE("GPL v2");

static int __init am35x_init(void)
{
	return platform_driver_register(&am35x_driver);
}
module_init(am35x_init);

static void __exit am35x_exit(void)
{
	platform_driver_unregister(&am35x_driver);
}
module_exit(am35x_exit);
Commit	Line	Data
eb83092c AKG	1	/*
	2	* Texas Instruments AM35x "glue layer"
	3	*
	4	* Copyright (c) 2010, by Texas Instruments
	5	*
	6	* Based on the DA8xx "glue layer" code.
	7	* Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
	8	*
	9	* This file is part of the Inventra Controller Driver for Linux.
	10	*
	11	* The Inventra Controller Driver for Linux is free software; you
	12	* can redistribute it and/or modify it under the terms of the GNU
	13	* General Public License version 2 as published by the Free Software
	14	* Foundation.
	15	*
	16	* The Inventra Controller Driver for Linux is distributed in
	17	* the hope that it will be useful, but WITHOUT ANY WARRANTY;
	18	* without even the implied warranty of MERCHANTABILITY or
	19	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	20	* License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with The Inventra Controller Driver for Linux ; if not,
	24	* write to the Free Software Foundation, Inc., 59 Temple Place,
	25	* Suite 330, Boston, MA 02111-1307 USA
	26	*
	27	*/
	28
	29	#include <linux/init.h>
ab570da2	30	#include <linux/module.h>
eb83092c	31	#include <linux/clk.h>
ded017ee	32	#include <linux/err.h>
eb83092c	33	#include <linux/io.h>
ce40c576 FB	34	#include <linux/platform_device.h>
ce40c576 FB	35	#include <linux/dma-mapping.h>
eb83092c	36
eb83092c AKG	37	#include <plat/usb.h>
	38
	39	#include "musb_core.h"
	40
	41	/*
	42	* AM35x specific definitions
	43	*/
	44	/* USB 2.0 OTG module registers */
	45	#define USB_REVISION_REG 0x00
	46	#define USB_CTRL_REG 0x04
	47	#define USB_STAT_REG 0x08
	48	#define USB_EMULATION_REG 0x0c
	49	/* 0x10 Reserved */
	50	#define USB_AUTOREQ_REG 0x14
	51	#define USB_SRP_FIX_TIME_REG 0x18
	52	#define USB_TEARDOWN_REG 0x1c
	53	#define EP_INTR_SRC_REG 0x20
	54	#define EP_INTR_SRC_SET_REG 0x24
	55	#define EP_INTR_SRC_CLEAR_REG 0x28
	56	#define EP_INTR_MASK_REG 0x2c
	57	#define EP_INTR_MASK_SET_REG 0x30
	58	#define EP_INTR_MASK_CLEAR_REG 0x34
	59	#define EP_INTR_SRC_MASKED_REG 0x38
	60	#define CORE_INTR_SRC_REG 0x40
	61	#define CORE_INTR_SRC_SET_REG 0x44
	62	#define CORE_INTR_SRC_CLEAR_REG 0x48
	63	#define CORE_INTR_MASK_REG 0x4c
	64	#define CORE_INTR_MASK_SET_REG 0x50
	65	#define CORE_INTR_MASK_CLEAR_REG 0x54
	66	#define CORE_INTR_SRC_MASKED_REG 0x58
	67	/* 0x5c Reserved */
	68	#define USB_END_OF_INTR_REG 0x60
	69
	70	/* Control register bits */
	71	#define AM35X_SOFT_RESET_MASK 1
	72
	73	/* USB interrupt register bits */
	74	#define AM35X_INTR_USB_SHIFT 16
	75	#define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
	76	#define AM35X_INTR_DRVVBUS 0x100
	77	#define AM35X_INTR_RX_SHIFT 16
	78	#define AM35X_INTR_TX_SHIFT 0
	79	#define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
	80	#define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
	81	#define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
	82	#define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
	83
	84	#define USB_MENTOR_CORE_OFFSET 0x400
	85
0919dfc1 FB	86	struct am35x_glue {
	87	struct device *dev;
	88	struct platform_device *musb;
03491761 FB	89	struct clk *phy_clk;
03491761 FB	90	struct clk *clk;
0919dfc1	91	};
6f783e28	92	#define glue_to_musb(g) platform_get_drvdata(g->musb)
0919dfc1	93
eb83092c	94	/*
743411b3	95	* am35x_musb_enable - enable interrupts
eb83092c	96	*/
743411b3	97	static void am35x_musb_enable(struct musb *musb)
eb83092c AKG	98	{
	99	void __iomem *reg_base = musb->ctrl_base;
	100	u32 epmask;
	101
	102	/* Workaround: setup IRQs through both register sets. */
	103	epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) \|
	104	((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
	105
	106	musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
	107	musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
	108
	109	/* Force the DRVVBUS IRQ so we can start polling for ID change. */
	110	if (is_otg_enabled(musb))
	111	musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
	112	AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
	113	}
	114
	115	/*
743411b3	116	* am35x_musb_disable - disable HDRC and flush interrupts
eb83092c	117	*/
743411b3	118	static void am35x_musb_disable(struct musb *musb)
eb83092c AKG	119	{
	120	void __iomem *reg_base = musb->ctrl_base;
	121
	122	musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
	123	musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
	124	AM35X_TX_INTR_MASK \| AM35X_RX_INTR_MASK);
	125	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
	126	musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
	127	}
	128
eb83092c	129	#define portstate(stmt) stmt
eb83092c	130
743411b3	131	static void am35x_musb_set_vbus(struct musb *musb, int is_on)
eb83092c AKG	132	{
	133	WARN_ON(is_on && is_peripheral_active(musb));
	134	}
	135
	136	#define POLL_SECONDS 2
	137
	138	static struct timer_list otg_workaround;
	139
	140	static void otg_timer(unsigned long _musb)
	141	{
	142	struct musb musb = (void )_musb;
	143	void __iomem *mregs = musb->mregs;
	144	u8 devctl;
	145	unsigned long flags;
	146
	147	/*
	148	* We poll because AM35x's won't expose several OTG-critical
	149	* status change events (from the transceiver) otherwise.
	150	*/
	151	devctl = musb_readb(mregs, MUSB_DEVCTL);
5c8a86e1	152	dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
3df00453	153	otg_state_string(musb->xceiv->state));
eb83092c AKG	154
	155	spin_lock_irqsave(&musb->lock, flags);
	156	switch (musb->xceiv->state) {
	157	case OTG_STATE_A_WAIT_BCON:
	158	devctl &= ~MUSB_DEVCTL_SESSION;
	159	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
	160
	161	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
	162	if (devctl & MUSB_DEVCTL_BDEVICE) {
	163	musb->xceiv->state = OTG_STATE_B_IDLE;
	164	MUSB_DEV_MODE(musb);
	165	} else {
	166	musb->xceiv->state = OTG_STATE_A_IDLE;
	167	MUSB_HST_MODE(musb);
	168	}
	169	break;
	170	case OTG_STATE_A_WAIT_VFALL:
	171	musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
	172	musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
	173	MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
	174	break;
	175	case OTG_STATE_B_IDLE:
	176	if (!is_peripheral_enabled(musb))
	177	break;
	178
	179	devctl = musb_readb(mregs, MUSB_DEVCTL);
	180	if (devctl & MUSB_DEVCTL_BDEVICE)
	181	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	182	else
	183	musb->xceiv->state = OTG_STATE_A_IDLE;
	184	break;
	185	default:
	186	break;
	187	}
	188	spin_unlock_irqrestore(&musb->lock, flags);
	189	}
	190
743411b3	191	static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
eb83092c AKG	192	{
	193	static unsigned long last_timer;
	194
	195	if (!is_otg_enabled(musb))
	196	return;
	197
	198	if (timeout == 0)
	199	timeout = jiffies + msecs_to_jiffies(3);
	200
	201	/* Never idle if active, or when VBUS timeout is not set as host */
	202	if (musb->is_active \|\| (musb->a_wait_bcon == 0 &&
	203	musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
5c8a86e1	204	dev_dbg(musb->controller, "%s active, deleting timer\n",
3df00453	205	otg_state_string(musb->xceiv->state));
eb83092c AKG	206	del_timer(&otg_workaround);
	207	last_timer = jiffies;
	208	return;
	209	}
	210
	211	if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
5c8a86e1	212	dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
eb83092c AKG	213	return;
	214	}
	215	last_timer = timeout;
	216
5c8a86e1	217	dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
3df00453 AG	218	otg_state_string(musb->xceiv->state),
3df00453 AG	219	jiffies_to_msecs(timeout - jiffies));
eb83092c AKG	220	mod_timer(&otg_workaround, timeout);
	221	}
	222
743411b3	223	static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
eb83092c AKG	224	{
	225	struct musb *musb = hci;
	226	void __iomem *reg_base = musb->ctrl_base;
a9c03783 AKG	227	struct device *dev = musb->controller;
	228	struct musb_hdrc_platform_data *plat = dev->platform_data;
	229	struct omap_musb_board_data *data = plat->board_data;
d445b6da	230	struct usb_otg *otg = musb->xceiv->otg;
eb83092c AKG	231	unsigned long flags;
eb83092c AKG	232	irqreturn_t ret = IRQ_NONE;
a9c03783	233	u32 epintr, usbintr;
eb83092c AKG	234
	235	spin_lock_irqsave(&musb->lock, flags);
	236
	237	/* Get endpoint interrupts */
	238	epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
	239
	240	if (epintr) {
	241	musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
	242
	243	musb->int_rx =
	244	(epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
	245	musb->int_tx =
	246	(epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
	247	}
	248
	249	/* Get usb core interrupts */
	250	usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
	251	if (!usbintr && !epintr)
	252	goto eoi;
	253
	254	if (usbintr) {
	255	musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
	256
	257	musb->int_usb =
	258	(usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
	259	}
	260	/*
	261	* DRVVBUS IRQs are the only proxy we have (a very poor one!) for
	262	* AM35x's missing ID change IRQ. We need an ID change IRQ to
	263	* switch appropriately between halves of the OTG state machine.
	264	* Managing DEVCTL.SESSION per Mentor docs requires that we know its
	265	* value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
	266	* Also, DRVVBUS pulses for SRP (but not at 5V) ...
	267	*/
	268	if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
	269	int drvvbus = musb_readl(reg_base, USB_STAT_REG);
	270	void __iomem *mregs = musb->mregs;
	271	u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
	272	int err;
	273
	274	err = is_host_enabled(musb) && (musb->int_usb &
	275	MUSB_INTR_VBUSERROR);
	276	if (err) {
	277	/*
	278	* The Mentor core doesn't debounce VBUS as needed
	279	* to cope with device connect current spikes. This
	280	* means it's not uncommon for bus-powered devices
	281	* to get VBUS errors during enumeration.
	282	*
	283	* This is a workaround, but newer RTL from Mentor
	284	* seems to allow a better one: "re"-starting sessions
	285	* without waiting for VBUS to stop registering in
	286	* devctl.
	287	*/
	288	musb->int_usb &= ~MUSB_INTR_VBUSERROR;
	289	musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
	290	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	291	WARNING("VBUS error workaround (delay coming)\n");
	292	} else if (is_host_enabled(musb) && drvvbus) {
	293	MUSB_HST_MODE(musb);
d445b6da	294	otg->default_a = 1;
eb83092c AKG	295	musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
	296	portstate(musb->port1_status \|= USB_PORT_STAT_POWER);
	297	del_timer(&otg_workaround);
	298	} else {
	299	musb->is_active = 0;
	300	MUSB_DEV_MODE(musb);
d445b6da	301	otg->default_a = 0;
eb83092c AKG	302	musb->xceiv->state = OTG_STATE_B_IDLE;
	303	portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
	304	}
	305
	306	/* NOTE: this must complete power-on within 100 ms. */
5c8a86e1	307	dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
eb83092c	308	drvvbus ? "on" : "off",
3df00453	309	otg_state_string(musb->xceiv->state),
eb83092c AKG	310	err ? " ERROR" : "",
	311	devctl);
	312	ret = IRQ_HANDLED;
	313	}
	314
	315	if (musb->int_tx \|\| musb->int_rx \|\| musb->int_usb)
	316	ret \|= musb_interrupt(musb);
	317
	318	eoi:
	319	/* EOI needs to be written for the IRQ to be re-asserted. */
	320	if (ret == IRQ_HANDLED \|\| epintr \|\| usbintr) {
	321	/* clear level interrupt */
a9c03783 AKG	322	if (data->clear_irq)
a9c03783 AKG	323	data->clear_irq();
eb83092c AKG	324	/* write EOI */
	325	musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
	326	}
	327
	328	/* Poll for ID change */
	329	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
	330	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	331
	332	spin_unlock_irqrestore(&musb->lock, flags);
	333
	334	return ret;
	335	}
	336
743411b3	337	static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
eb83092c	338	{
a9c03783 AKG	339	struct device *dev = musb->controller;
	340	struct musb_hdrc_platform_data *plat = dev->platform_data;
	341	struct omap_musb_board_data *data = plat->board_data;
	342	int retval = 0;
eb83092c	343
a9c03783 AKG	344	if (data->set_mode)
	345	data->set_mode(musb_mode);
	346	else
	347	retval = -EIO;
eb83092c	348
a9c03783	349	return retval;
eb83092c AKG	350	}
eb83092c AKG	351
743411b3	352	static int am35x_musb_init(struct musb *musb)
eb83092c	353	{
a9c03783 AKG	354	struct device *dev = musb->controller;
	355	struct musb_hdrc_platform_data *plat = dev->platform_data;
	356	struct omap_musb_board_data *data = plat->board_data;
eb83092c	357	void __iomem *reg_base = musb->ctrl_base;
a9c03783	358	u32 rev;
eb83092c AKG	359
	360	musb->mregs += USB_MENTOR_CORE_OFFSET;
	361
eb83092c AKG	362	/* Returns zero if e.g. not clocked */
eb83092c AKG	363	rev = musb_readl(reg_base, USB_REVISION_REG);
03491761 FB	364	if (!rev)
03491761 FB	365	return -ENODEV;
eb83092c AKG	366
eb83092c AKG	367	usb_nop_xceiv_register();
662dca54	368	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
ded017ee	369	if (IS_ERR_OR_NULL(musb->xceiv))
03491761	370	return -ENODEV;
eb83092c AKG	371
	372	if (is_host_enabled(musb))
	373	setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
	374
a9c03783 AKG	375	/* Reset the musb */
	376	if (data->reset)
	377	data->reset();
eb83092c AKG	378
	379	/* Reset the controller */
	380	musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
	381
	382	/* Start the on-chip PHY and its PLL. */
a9c03783 AKG	383	if (data->set_phy_power)
a9c03783 AKG	384	data->set_phy_power(1);
eb83092c AKG	385
	386	msleep(5);
	387
743411b3	388	musb->isr = am35x_musb_interrupt;
eb83092c AKG	389
eb83092c AKG	390	/* clear level interrupt */
a9c03783 AKG	391	if (data->clear_irq)
a9c03783 AKG	392	data->clear_irq();
03491761	393
eb83092c	394	return 0;
eb83092c AKG	395	}
eb83092c AKG	396
743411b3	397	static int am35x_musb_exit(struct musb *musb)
eb83092c	398	{
a9c03783 AKG	399	struct device *dev = musb->controller;
	400	struct musb_hdrc_platform_data *plat = dev->platform_data;
	401	struct omap_musb_board_data *data = plat->board_data;
	402
eb83092c AKG	403	if (is_host_enabled(musb))
	404	del_timer_sync(&otg_workaround);
	405
a9c03783 AKG	406	/* Shutdown the on-chip PHY and its PLL. */
	407	if (data->set_phy_power)
	408	data->set_phy_power(0);
eb83092c	409
721002ec	410	usb_put_phy(musb->xceiv);
eb83092c AKG	411	usb_nop_xceiv_unregister();
eb83092c AKG	412
eb83092c AKG	413	return 0;
	414	}
	415
843bb1d0 AKG	416	/* AM35x supports only 32bit read operation */
	417	void musb_read_fifo(struct musb_hw_ep hw_ep, u16 len, u8 dst)
	418	{
	419	void __iomem *fifo = hw_ep->fifo;
	420	u32 val;
	421	int i;
	422
	423	/* Read for 32bit-aligned destination address */
	424	if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
	425	readsl(fifo, dst, len >> 2);
	426	dst += len & ~0x03;
	427	len &= 0x03;
	428	}
	429	/*
	430	* Now read the remaining 1 to 3 byte or complete length if
	431	* unaligned address.
	432	*/
	433	if (len > 4) {
	434	for (i = 0; i < (len >> 2); i++) {
	435	(u32 ) dst = musb_readl(fifo, 0);
	436	dst += 4;
	437	}
	438	len &= 0x03;
	439	}
	440	if (len > 0) {
	441	val = musb_readl(fifo, 0);
	442	memcpy(dst, &val, len);
	443	}
	444	}
743411b3	445
f7ec9437	446	static const struct musb_platform_ops am35x_ops = {
743411b3 FB	447	.init = am35x_musb_init,
	448	.exit = am35x_musb_exit,
	449
	450	.enable = am35x_musb_enable,
	451	.disable = am35x_musb_disable,
	452
	453	.set_mode = am35x_musb_set_mode,
	454	.try_idle = am35x_musb_try_idle,
	455
	456	.set_vbus = am35x_musb_set_vbus,
	457	};
ce40c576 FB	458
	459	static u64 am35x_dmamask = DMA_BIT_MASK(32);
	460
e9e8c85e	461	static int __devinit am35x_probe(struct platform_device *pdev)
ce40c576 FB	462	{
	463	struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
	464	struct platform_device *musb;
0919dfc1	465	struct am35x_glue *glue;
ce40c576	466
03491761 FB	467	struct clk *phy_clk;
	468	struct clk *clk;
	469
ce40c576 FB	470	int ret = -ENOMEM;
ce40c576 FB	471
0919dfc1 FB	472	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
	473	if (!glue) {
	474	dev_err(&pdev->dev, "failed to allocate glue context\n");
	475	goto err0;
	476	}
	477
ce40c576 FB	478	musb = platform_device_alloc("musb-hdrc", -1);
	479	if (!musb) {
	480	dev_err(&pdev->dev, "failed to allocate musb device\n");
0919dfc1	481	goto err1;
ce40c576 FB	482	}
ce40c576 FB	483
03491761 FB	484	phy_clk = clk_get(&pdev->dev, "fck");
	485	if (IS_ERR(phy_clk)) {
	486	dev_err(&pdev->dev, "failed to get PHY clock\n");
	487	ret = PTR_ERR(phy_clk);
	488	goto err2;
	489	}
	490
	491	clk = clk_get(&pdev->dev, "ick");
	492	if (IS_ERR(clk)) {
	493	dev_err(&pdev->dev, "failed to get clock\n");
	494	ret = PTR_ERR(clk);
	495	goto err3;
	496	}
	497
	498	ret = clk_enable(phy_clk);
	499	if (ret) {
	500	dev_err(&pdev->dev, "failed to enable PHY clock\n");
	501	goto err4;
	502	}
	503
	504	ret = clk_enable(clk);
	505	if (ret) {
	506	dev_err(&pdev->dev, "failed to enable clock\n");
	507	goto err5;
	508	}
	509
ce40c576 FB	510	musb->dev.parent = &pdev->dev;
	511	musb->dev.dma_mask = &am35x_dmamask;
	512	musb->dev.coherent_dma_mask = am35x_dmamask;
	513
0919dfc1 FB	514	glue->dev = &pdev->dev;
0919dfc1 FB	515	glue->musb = musb;
03491761 FB	516	glue->phy_clk = phy_clk;
03491761 FB	517	glue->clk = clk;
0919dfc1	518
f7ec9437 FB	519	pdata->platform_ops = &am35x_ops;
f7ec9437 FB	520
0919dfc1	521	platform_set_drvdata(pdev, glue);
ce40c576 FB	522
	523	ret = platform_device_add_resources(musb, pdev->resource,
	524	pdev->num_resources);
	525	if (ret) {
	526	dev_err(&pdev->dev, "failed to add resources\n");
03491761	527	goto err6;
ce40c576 FB	528	}
	529
	530	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	531	if (ret) {
	532	dev_err(&pdev->dev, "failed to add platform_data\n");
03491761	533	goto err6;
ce40c576 FB	534	}
	535
	536	ret = platform_device_add(musb);
	537	if (ret) {
	538	dev_err(&pdev->dev, "failed to register musb device\n");
03491761	539	goto err6;
ce40c576 FB	540	}
	541
	542	return 0;
	543
03491761 FB	544	err6:
	545	clk_disable(clk);
	546
	547	err5:
	548	clk_disable(phy_clk);
	549
	550	err4:
	551	clk_put(clk);
	552
	553	err3:
	554	clk_put(phy_clk);
	555
0919dfc1	556	err2:
ce40c576 FB	557	platform_device_put(musb);
ce40c576 FB	558
0919dfc1 FB	559	err1:
	560	kfree(glue);
	561
ce40c576 FB	562	err0:
	563	return ret;
	564	}
	565
e9e8c85e	566	static int __devexit am35x_remove(struct platform_device *pdev)
ce40c576	567	{
0919dfc1	568	struct am35x_glue *glue = platform_get_drvdata(pdev);
ce40c576	569
0919dfc1 FB	570	platform_device_del(glue->musb);
0919dfc1 FB	571	platform_device_put(glue->musb);
03491761 FB	572	clk_disable(glue->clk);
	573	clk_disable(glue->phy_clk);
	574	clk_put(glue->clk);
	575	clk_put(glue->phy_clk);
0919dfc1	576	kfree(glue);
ce40c576 FB	577
	578	return 0;
	579	}
	580
6f783e28 FB	581	#ifdef CONFIG_PM
	582	static int am35x_suspend(struct device *dev)
	583	{
	584	struct am35x_glue *glue = dev_get_drvdata(dev);
a9c03783 AKG	585	struct musb_hdrc_platform_data *plat = dev->platform_data;
	586	struct omap_musb_board_data *data = plat->board_data;
	587
	588	/* Shutdown the on-chip PHY and its PLL. */
	589	if (data->set_phy_power)
	590	data->set_phy_power(0);
6f783e28	591
6f783e28 FB	592	clk_disable(glue->phy_clk);
	593	clk_disable(glue->clk);
	594
	595	return 0;
	596	}
	597
	598	static int am35x_resume(struct device *dev)
	599	{
	600	struct am35x_glue *glue = dev_get_drvdata(dev);
a9c03783 AKG	601	struct musb_hdrc_platform_data *plat = dev->platform_data;
a9c03783 AKG	602	struct omap_musb_board_data *data = plat->board_data;
6f783e28 FB	603	int ret;
6f783e28 FB	604
a9c03783 AKG	605	/* Start the on-chip PHY and its PLL. */
	606	if (data->set_phy_power)
	607	data->set_phy_power(1);
	608
6f783e28 FB	609	ret = clk_enable(glue->phy_clk);
	610	if (ret) {
	611	dev_err(dev, "failed to enable PHY clock\n");
	612	return ret;
	613	}
	614
	615	ret = clk_enable(glue->clk);
	616	if (ret) {
	617	dev_err(dev, "failed to enable clock\n");
	618	return ret;
	619	}
	620
	621	return 0;
	622	}
	623
	624	static struct dev_pm_ops am35x_pm_ops = {
	625	.suspend = am35x_suspend,
	626	.resume = am35x_resume,
	627	};
	628
	629	#define DEV_PM_OPS &am35x_pm_ops
	630	#else
	631	#define DEV_PM_OPS NULL
	632	#endif
	633
ce40c576	634	static struct platform_driver am35x_driver = {
e9e8c85e FB	635	.probe = am35x_probe,
e9e8c85e FB	636	.remove = __devexit_p(am35x_remove),
ce40c576 FB	637	.driver = {
ce40c576 FB	638	.name = "musb-am35x",
6f783e28	639	.pm = DEV_PM_OPS,
ce40c576 FB	640	},
	641	};
	642
	643	MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
	644	MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
	645	MODULE_LICENSE("GPL v2");
	646
	647	static int __init am35x_init(void)
	648	{
e9e8c85e	649	return platform_driver_register(&am35x_driver);
ce40c576	650	}
e9e8c85e	651	module_init(am35x_init);
ce40c576 FB	652
	653	static void __exit am35x_exit(void)
	654	{
	655	platform_driver_unregister(&am35x_driver);
	656	}
	657	module_exit(am35x_exit);