[deliverable/linux.git] / drivers / usb / musb / am35x.c

/*
 * Texas Instruments AM35x "glue layer"
 *
 * Copyright (c) 2010, by Texas Instruments
 *
 * Based on the DA8xx "glue layer" code.
 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
 *
 * This file is part of the Inventra Controller Driver for Linux.
 *
 * The Inventra Controller Driver for Linux is free software; you
 * can redistribute it and/or modify it under the terms of the GNU
 * General Public License version 2 as published by the Free Software
 * Foundation.
 *
 * The Inventra Controller Driver for Linux is distributed in
 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
 * without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
 * License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with The Inventra Controller Driver for Linux ; if not,
 * write to the Free Software Foundation, Inc., 59 Temple Place,
 * Suite 330, Boston, MA  02111-1307  USA
 *
 */

#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>

#include <plat/control.h>
#include <plat/usb.h>

#include "musb_core.h"

/*
 * AM35x specific definitions
 */
/* USB 2.0 OTG module registers */
#define USB_REVISION_REG	0x00
#define USB_CTRL_REG		0x04
#define USB_STAT_REG		0x08
#define USB_EMULATION_REG	0x0c
/* 0x10 Reserved */
#define USB_AUTOREQ_REG		0x14
#define USB_SRP_FIX_TIME_REG	0x18
#define USB_TEARDOWN_REG	0x1c
#define EP_INTR_SRC_REG		0x20
#define EP_INTR_SRC_SET_REG	0x24
#define EP_INTR_SRC_CLEAR_REG	0x28
#define EP_INTR_MASK_REG	0x2c
#define EP_INTR_MASK_SET_REG	0x30
#define EP_INTR_MASK_CLEAR_REG	0x34
#define EP_INTR_SRC_MASKED_REG	0x38
#define CORE_INTR_SRC_REG	0x40
#define CORE_INTR_SRC_SET_REG	0x44
#define CORE_INTR_SRC_CLEAR_REG	0x48
#define CORE_INTR_MASK_REG	0x4c
#define CORE_INTR_MASK_SET_REG	0x50
#define CORE_INTR_MASK_CLEAR_REG 0x54
#define CORE_INTR_SRC_MASKED_REG 0x58
/* 0x5c Reserved */
#define USB_END_OF_INTR_REG	0x60

/* Control register bits */
#define AM35X_SOFT_RESET_MASK	1

/* USB interrupt register bits */
#define AM35X_INTR_USB_SHIFT	16
#define AM35X_INTR_USB_MASK	(0x1ff << AM35X_INTR_USB_SHIFT)
#define AM35X_INTR_DRVVBUS	0x100
#define AM35X_INTR_RX_SHIFT	16
#define AM35X_INTR_TX_SHIFT	0
#define AM35X_TX_EP_MASK	0xffff		/* EP0 + 15 Tx EPs */
#define AM35X_RX_EP_MASK	0xfffe		/* 15 Rx EPs */
#define AM35X_TX_INTR_MASK	(AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
#define AM35X_RX_INTR_MASK	(AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)

#define USB_MENTOR_CORE_OFFSET	0x400

struct am35x_glue {
	struct device		*dev;
	struct platform_device	*musb;
};

static inline void phy_on(void)
{
	unsigned long timeout = jiffies + msecs_to_jiffies(100);
	u32 devconf2;

	/*
	 * Start the on-chip PHY and its PLL.
	 */
	devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);

	devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
	devconf2 |= CONF2_PHY_PLLON;

	omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);

	DBG(1, "Waiting for PHY clock good...\n");
	while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
			& CONF2_PHYCLKGD)) {
		cpu_relax();

		if (time_after(jiffies, timeout)) {
			DBG(1, "musb PHY clock good timed out\n");
			break;
		}
	}
}

static inline void phy_off(void)
{
	u32 devconf2;

	/*
	 * Power down the on-chip PHY.
	 */
	devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);

	devconf2 &= ~CONF2_PHY_PLLON;
	devconf2 |=  CONF2_PHYPWRDN | CONF2_OTGPWRDN;
	omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
}

/*
 * am35x_musb_enable - enable interrupts
 */
static void am35x_musb_enable(struct musb *musb)
{
	void __iomem *reg_base = musb->ctrl_base;
	u32 epmask;

	/* Workaround: setup IRQs through both register sets. */
	epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
	       ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);

	musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
	musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);

	/* Force the DRVVBUS IRQ so we can start polling for ID change. */
	if (is_otg_enabled(musb))
		musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
			    AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
}

/*
 * am35x_musb_disable - disable HDRC and flush interrupts
 */
static void am35x_musb_disable(struct musb *musb)
{
	void __iomem *reg_base = musb->ctrl_base;

	musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
	musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
			 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
	musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
}

#ifdef CONFIG_USB_MUSB_HDRC_HCD
#define portstate(stmt)		stmt
#else
#define portstate(stmt)
#endif

static void am35x_musb_set_vbus(struct musb *musb, int is_on)
{
	WARN_ON(is_on && is_peripheral_active(musb));
}

#define	POLL_SECONDS	2

static struct timer_list otg_workaround;

static void otg_timer(unsigned long _musb)
{
	struct musb		*musb = (void *)_musb;
	void __iomem		*mregs = musb->mregs;
	u8			devctl;
	unsigned long		flags;

	/*
	 * We poll because AM35x's won't expose several OTG-critical
	 * status change events (from the transceiver) otherwise.
	 */
	devctl = musb_readb(mregs, MUSB_DEVCTL);
	DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb));

	spin_lock_irqsave(&musb->lock, flags);
	switch (musb->xceiv->state) {
	case OTG_STATE_A_WAIT_BCON:
		devctl &= ~MUSB_DEVCTL_SESSION;
		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);

		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
		if (devctl & MUSB_DEVCTL_BDEVICE) {
			musb->xceiv->state = OTG_STATE_B_IDLE;
			MUSB_DEV_MODE(musb);
		} else {
			musb->xceiv->state = OTG_STATE_A_IDLE;
			MUSB_HST_MODE(musb);
		}
		break;
	case OTG_STATE_A_WAIT_VFALL:
		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
		musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
			    MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
		break;
	case OTG_STATE_B_IDLE:
		if (!is_peripheral_enabled(musb))
			break;

		devctl = musb_readb(mregs, MUSB_DEVCTL);
		if (devctl & MUSB_DEVCTL_BDEVICE)
			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
		else
			musb->xceiv->state = OTG_STATE_A_IDLE;
		break;
	default:
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);
}

static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
{
	static unsigned long last_timer;

	if (!is_otg_enabled(musb))
		return;

	if (timeout == 0)
		timeout = jiffies + msecs_to_jiffies(3);

	/* Never idle if active, or when VBUS timeout is not set as host */
	if (musb->is_active || (musb->a_wait_bcon == 0 &&
				musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
		DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
		del_timer(&otg_workaround);
		last_timer = jiffies;
		return;
	}

	if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
		DBG(4, "Longer idle timer already pending, ignoring...\n");
		return;
	}
	last_timer = timeout;

	DBG(4, "%s inactive, starting idle timer for %u ms\n",
	    otg_state_string(musb), jiffies_to_msecs(timeout - jiffies));
	mod_timer(&otg_workaround, timeout);
}

static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
{
	struct musb  *musb = hci;
	void __iomem *reg_base = musb->ctrl_base;
	unsigned long flags;
	irqreturn_t ret = IRQ_NONE;
	u32 epintr, usbintr, lvl_intr;

	spin_lock_irqsave(&musb->lock, flags);

	/* Get endpoint interrupts */
	epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);

	if (epintr) {
		musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);

		musb->int_rx =
			(epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
		musb->int_tx =
			(epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
	}

	/* Get usb core interrupts */
	usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
	if (!usbintr && !epintr)
		goto eoi;

	if (usbintr) {
		musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);

		musb->int_usb =
			(usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
	}
	/*
	 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
	 * AM35x's missing ID change IRQ.  We need an ID change IRQ to
	 * switch appropriately between halves of the OTG state machine.
	 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
	 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
	 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
	 */
	if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
		int drvvbus = musb_readl(reg_base, USB_STAT_REG);
		void __iomem *mregs = musb->mregs;
		u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
		int err;

		err = is_host_enabled(musb) && (musb->int_usb &
						MUSB_INTR_VBUSERROR);
		if (err) {
			/*
			 * The Mentor core doesn't debounce VBUS as needed
			 * to cope with device connect current spikes. This
			 * means it's not uncommon for bus-powered devices
			 * to get VBUS errors during enumeration.
			 *
			 * This is a workaround, but newer RTL from Mentor
			 * seems to allow a better one: "re"-starting sessions
			 * without waiting for VBUS to stop registering in
			 * devctl.
			 */
			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
			WARNING("VBUS error workaround (delay coming)\n");
		} else if (is_host_enabled(musb) && drvvbus) {
			MUSB_HST_MODE(musb);
			musb->xceiv->default_a = 1;
			musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
			portstate(musb->port1_status |= USB_PORT_STAT_POWER);
			del_timer(&otg_workaround);
		} else {
			musb->is_active = 0;
			MUSB_DEV_MODE(musb);
			musb->xceiv->default_a = 0;
			musb->xceiv->state = OTG_STATE_B_IDLE;
			portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
		}

		/* NOTE: this must complete power-on within 100 ms. */
		DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
				drvvbus ? "on" : "off",
				otg_state_string(musb),
				err ? " ERROR" : "",
				devctl);
		ret = IRQ_HANDLED;
	}

	if (musb->int_tx || musb->int_rx || musb->int_usb)
		ret |= musb_interrupt(musb);

eoi:
	/* EOI needs to be written for the IRQ to be re-asserted. */
	if (ret == IRQ_HANDLED || epintr || usbintr) {
		/* clear level interrupt */
		lvl_intr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
		lvl_intr |= AM35XX_USBOTGSS_INT_CLR;
		omap_ctrl_writel(lvl_intr, AM35XX_CONTROL_LVL_INTR_CLEAR);
		/* write EOI */
		musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
	}

	/* Poll for ID change */
	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
		mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);

	spin_unlock_irqrestore(&musb->lock, flags);

	return ret;
}

static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
{
	u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);

	devconf2 &= ~CONF2_OTGMODE;
	switch (musb_mode) {
#ifdef	CONFIG_USB_MUSB_HDRC_HCD
	case MUSB_HOST:		/* Force VBUS valid, ID = 0 */
		devconf2 |= CONF2_FORCE_HOST;
		break;
#endif
#ifdef	CONFIG_USB_GADGET_MUSB_HDRC
	case MUSB_PERIPHERAL:	/* Force VBUS valid, ID = 1 */
		devconf2 |= CONF2_FORCE_DEVICE;
		break;
#endif
#ifdef	CONFIG_USB_MUSB_OTG
	case MUSB_OTG:		/* Don't override the VBUS/ID comparators */
		devconf2 |= CONF2_NO_OVERRIDE;
		break;
#endif
	default:
		DBG(2, "Trying to set unsupported mode %u\n", musb_mode);
	}

	omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
	return 0;
}

static int am35x_musb_init(struct musb *musb)
{
	void __iomem *reg_base = musb->ctrl_base;
	u32 rev, lvl_intr, sw_reset;
	int status;

	musb->mregs += USB_MENTOR_CORE_OFFSET;

	clk_enable(musb->clock);
	DBG(2, "musb->clock=%lud\n", clk_get_rate(musb->clock));

	musb->phy_clock = clk_get(musb->controller, "fck");
	if (IS_ERR(musb->phy_clock)) {
		status = PTR_ERR(musb->phy_clock);
		goto exit0;
	}
	clk_enable(musb->phy_clock);
	DBG(2, "musb->phy_clock=%lud\n", clk_get_rate(musb->phy_clock));

	/* Returns zero if e.g. not clocked */
	rev = musb_readl(reg_base, USB_REVISION_REG);
	if (!rev) {
		status = -ENODEV;
		goto exit1;
	}

	usb_nop_xceiv_register();
	musb->xceiv = otg_get_transceiver();
	if (!musb->xceiv) {
		status = -ENODEV;
		goto exit1;
	}

	if (is_host_enabled(musb))
		setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);

	musb->board_set_vbus = am35x_musb_set_vbus;

	/* Global reset */
	sw_reset = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);

	sw_reset |= AM35XX_USBOTGSS_SW_RST;
	omap_ctrl_writel(sw_reset, AM35XX_CONTROL_IP_SW_RESET);

	sw_reset &= ~AM35XX_USBOTGSS_SW_RST;
	omap_ctrl_writel(sw_reset, AM35XX_CONTROL_IP_SW_RESET);

	/* Reset the controller */
	musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);

	/* Start the on-chip PHY and its PLL. */
	phy_on();

	msleep(5);

	musb->isr = am35x_musb_interrupt;

	/* clear level interrupt */
	lvl_intr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
	lvl_intr |= AM35XX_USBOTGSS_INT_CLR;
	omap_ctrl_writel(lvl_intr, AM35XX_CONTROL_LVL_INTR_CLEAR);
	return 0;
exit1:
	clk_disable(musb->phy_clock);
	clk_put(musb->phy_clock);
exit0:
	clk_disable(musb->clock);
	return status;
}

static int am35x_musb_exit(struct musb *musb)
{
	if (is_host_enabled(musb))
		del_timer_sync(&otg_workaround);

	phy_off();

	otg_put_transceiver(musb->xceiv);
	usb_nop_xceiv_unregister();

	clk_disable(musb->clock);

	clk_disable(musb->phy_clock);
	clk_put(musb->phy_clock);

	return 0;
}

#ifdef CONFIG_PM
void musb_platform_save_context(struct musb *musb,
	struct musb_context_registers *musb_context)
{
	phy_off();
}

void musb_platform_restore_context(struct musb *musb,
	struct musb_context_registers *musb_context)
{
	phy_on();
}
#endif

/* AM35x supports only 32bit read operation */
void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
{
	void __iomem *fifo = hw_ep->fifo;
	u32		val;
	int		i;

	/* Read for 32bit-aligned destination address */
	if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
		readsl(fifo, dst, len >> 2);
		dst += len & ~0x03;
		len &= 0x03;
	}
	/*
	 * Now read the remaining 1 to 3 byte or complete length if
	 * unaligned address.
	 */
	if (len > 4) {
		for (i = 0; i < (len >> 2); i++) {
			*(u32 *) dst = musb_readl(fifo, 0);
			dst += 4;
		}
		len &= 0x03;
	}
	if (len > 0) {
		val = musb_readl(fifo, 0);
		memcpy(dst, &val, len);
	}
}

static const struct musb_platform_ops am35x_ops = {
	.init		= am35x_musb_init,
	.exit		= am35x_musb_exit,

	.enable		= am35x_musb_enable,
	.disable	= am35x_musb_disable,

	.set_mode	= am35x_musb_set_mode,
	.try_idle	= am35x_musb_try_idle,

	.set_vbus	= am35x_musb_set_vbus,
};

static u64 am35x_dmamask = DMA_BIT_MASK(32);

static int __init am35x_probe(struct platform_device *pdev)
{
	struct musb_hdrc_platform_data	*pdata = pdev->dev.platform_data;
	struct platform_device		*musb;
	struct am35x_glue		*glue;

	int				ret = -ENOMEM;

	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
	if (!glue) {
		dev_err(&pdev->dev, "failed to allocate glue context\n");
		goto err0;
	}

	musb = platform_device_alloc("musb-hdrc", -1);
	if (!musb) {
		dev_err(&pdev->dev, "failed to allocate musb device\n");
		goto err1;
	}

	musb->dev.parent		= &pdev->dev;
	musb->dev.dma_mask		= &am35x_dmamask;
	musb->dev.coherent_dma_mask	= am35x_dmamask;

	glue->dev			= &pdev->dev;
	glue->musb			= musb;

	pdata->platform_ops		= &am35x_ops;

	platform_set_drvdata(pdev, glue);

	ret = platform_device_add_resources(musb, pdev->resource,
			pdev->num_resources);
	if (ret) {
		dev_err(&pdev->dev, "failed to add resources\n");
		goto err2;
	}

	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	if (ret) {
		dev_err(&pdev->dev, "failed to add platform_data\n");
		goto err2;
	}

	ret = platform_device_add(musb);
	if (ret) {
		dev_err(&pdev->dev, "failed to register musb device\n");
		goto err2;
	}

	return 0;

err2:
	platform_device_put(musb);

err1:
	kfree(glue);

err0:
	return ret;
}

static int __exit am35x_remove(struct platform_device *pdev)
{
	struct am35x_glue	*glue = platform_get_drvdata(pdev);

	platform_device_del(glue->musb);
	platform_device_put(glue->musb);
	kfree(glue);

	return 0;
}

static struct platform_driver am35x_driver = {
	.remove		= __exit_p(am35x_remove),
	.driver		= {
		.name	= "musb-am35x",
	},
};

MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
MODULE_LICENSE("GPL v2");

static int __init am35x_init(void)
{
	return platform_driver_probe(&am35x_driver, am35x_probe);
}
subsys_initcall(am35x_init);

static void __exit am35x_exit(void)
{
	platform_driver_unregister(&am35x_driver);
}
module_exit(am35x_exit);
Commit	Line	Data
eb83092c AKG	1	/*
	2	* Texas Instruments AM35x "glue layer"
	3	*
	4	* Copyright (c) 2010, by Texas Instruments
	5	*
	6	* Based on the DA8xx "glue layer" code.
	7	* Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
	8	*
	9	* This file is part of the Inventra Controller Driver for Linux.
	10	*
	11	* The Inventra Controller Driver for Linux is free software; you
	12	* can redistribute it and/or modify it under the terms of the GNU
	13	* General Public License version 2 as published by the Free Software
	14	* Foundation.
	15	*
	16	* The Inventra Controller Driver for Linux is distributed in
	17	* the hope that it will be useful, but WITHOUT ANY WARRANTY;
	18	* without even the implied warranty of MERCHANTABILITY or
	19	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	20	* License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with The Inventra Controller Driver for Linux ; if not,
	24	* write to the Free Software Foundation, Inc., 59 Temple Place,
	25	* Suite 330, Boston, MA 02111-1307 USA
	26	*
	27	*/
	28
	29	#include <linux/init.h>
	30	#include <linux/clk.h>
	31	#include <linux/io.h>
ce40c576 FB	32	#include <linux/platform_device.h>
ce40c576 FB	33	#include <linux/dma-mapping.h>
eb83092c AKG	34
	35	#include <plat/control.h>
	36	#include <plat/usb.h>
	37
	38	#include "musb_core.h"
	39
	40	/*
	41	* AM35x specific definitions
	42	*/
	43	/* USB 2.0 OTG module registers */
	44	#define USB_REVISION_REG 0x00
	45	#define USB_CTRL_REG 0x04
	46	#define USB_STAT_REG 0x08
	47	#define USB_EMULATION_REG 0x0c
	48	/* 0x10 Reserved */
	49	#define USB_AUTOREQ_REG 0x14
	50	#define USB_SRP_FIX_TIME_REG 0x18
	51	#define USB_TEARDOWN_REG 0x1c
	52	#define EP_INTR_SRC_REG 0x20
	53	#define EP_INTR_SRC_SET_REG 0x24
	54	#define EP_INTR_SRC_CLEAR_REG 0x28
	55	#define EP_INTR_MASK_REG 0x2c
	56	#define EP_INTR_MASK_SET_REG 0x30
	57	#define EP_INTR_MASK_CLEAR_REG 0x34
	58	#define EP_INTR_SRC_MASKED_REG 0x38
	59	#define CORE_INTR_SRC_REG 0x40
	60	#define CORE_INTR_SRC_SET_REG 0x44
	61	#define CORE_INTR_SRC_CLEAR_REG 0x48
	62	#define CORE_INTR_MASK_REG 0x4c
	63	#define CORE_INTR_MASK_SET_REG 0x50
	64	#define CORE_INTR_MASK_CLEAR_REG 0x54
	65	#define CORE_INTR_SRC_MASKED_REG 0x58
	66	/* 0x5c Reserved */
	67	#define USB_END_OF_INTR_REG 0x60
	68
	69	/* Control register bits */
	70	#define AM35X_SOFT_RESET_MASK 1
	71
	72	/* USB interrupt register bits */
	73	#define AM35X_INTR_USB_SHIFT 16
	74	#define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
	75	#define AM35X_INTR_DRVVBUS 0x100
	76	#define AM35X_INTR_RX_SHIFT 16
	77	#define AM35X_INTR_TX_SHIFT 0
	78	#define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
	79	#define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
	80	#define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
	81	#define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
	82
	83	#define USB_MENTOR_CORE_OFFSET 0x400
	84
0919dfc1 FB	85	struct am35x_glue {
	86	struct device *dev;
	87	struct platform_device *musb;
	88	};
	89
eb83092c AKG	90	static inline void phy_on(void)
	91	{
	92	unsigned long timeout = jiffies + msecs_to_jiffies(100);
	93	u32 devconf2;
	94
	95	/*
	96	* Start the on-chip PHY and its PLL.
	97	*/
	98	devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
	99
	100	devconf2 &= ~(CONF2_RESET \| CONF2_PHYPWRDN \| CONF2_OTGPWRDN);
	101	devconf2 \|= CONF2_PHY_PLLON;
	102
	103	omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
	104
	105	DBG(1, "Waiting for PHY clock good...\n");
	106	while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
	107	& CONF2_PHYCLKGD)) {
	108	cpu_relax();
	109
	110	if (time_after(jiffies, timeout)) {
	111	DBG(1, "musb PHY clock good timed out\n");
	112	break;
	113	}
	114	}
	115	}
	116
	117	static inline void phy_off(void)
	118	{
	119	u32 devconf2;
	120
	121	/*
	122	* Power down the on-chip PHY.
	123	*/
	124	devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
	125
	126	devconf2 &= ~CONF2_PHY_PLLON;
	127	devconf2 \|= CONF2_PHYPWRDN \| CONF2_OTGPWRDN;
	128	omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
	129	}
	130
	131	/*
743411b3	132	* am35x_musb_enable - enable interrupts
eb83092c	133	*/
743411b3	134	static void am35x_musb_enable(struct musb *musb)
eb83092c AKG	135	{
	136	void __iomem *reg_base = musb->ctrl_base;
	137	u32 epmask;
	138
	139	/* Workaround: setup IRQs through both register sets. */
	140	epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) \|
	141	((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
	142
	143	musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
	144	musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
	145
	146	/* Force the DRVVBUS IRQ so we can start polling for ID change. */
	147	if (is_otg_enabled(musb))
	148	musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
	149	AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
	150	}
	151
	152	/*
743411b3	153	* am35x_musb_disable - disable HDRC and flush interrupts
eb83092c	154	*/
743411b3	155	static void am35x_musb_disable(struct musb *musb)
eb83092c AKG	156	{
	157	void __iomem *reg_base = musb->ctrl_base;
	158
	159	musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
	160	musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
	161	AM35X_TX_INTR_MASK \| AM35X_RX_INTR_MASK);
	162	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
	163	musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
	164	}
	165
	166	#ifdef CONFIG_USB_MUSB_HDRC_HCD
	167	#define portstate(stmt) stmt
	168	#else
	169	#define portstate(stmt)
	170	#endif
	171
743411b3	172	static void am35x_musb_set_vbus(struct musb *musb, int is_on)
eb83092c AKG	173	{
	174	WARN_ON(is_on && is_peripheral_active(musb));
	175	}
	176
	177	#define POLL_SECONDS 2
	178
	179	static struct timer_list otg_workaround;
	180
	181	static void otg_timer(unsigned long _musb)
	182	{
	183	struct musb musb = (void )_musb;
	184	void __iomem *mregs = musb->mregs;
	185	u8 devctl;
	186	unsigned long flags;
	187
	188	/*
	189	* We poll because AM35x's won't expose several OTG-critical
	190	* status change events (from the transceiver) otherwise.
	191	*/
	192	devctl = musb_readb(mregs, MUSB_DEVCTL);
	193	DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
	194
	195	spin_lock_irqsave(&musb->lock, flags);
	196	switch (musb->xceiv->state) {
	197	case OTG_STATE_A_WAIT_BCON:
	198	devctl &= ~MUSB_DEVCTL_SESSION;
	199	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
	200
	201	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
	202	if (devctl & MUSB_DEVCTL_BDEVICE) {
	203	musb->xceiv->state = OTG_STATE_B_IDLE;
	204	MUSB_DEV_MODE(musb);
	205	} else {
	206	musb->xceiv->state = OTG_STATE_A_IDLE;
	207	MUSB_HST_MODE(musb);
	208	}
	209	break;
	210	case OTG_STATE_A_WAIT_VFALL:
	211	musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
	212	musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
	213	MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
	214	break;
	215	case OTG_STATE_B_IDLE:
	216	if (!is_peripheral_enabled(musb))
	217	break;
	218
	219	devctl = musb_readb(mregs, MUSB_DEVCTL);
	220	if (devctl & MUSB_DEVCTL_BDEVICE)
	221	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	222	else
	223	musb->xceiv->state = OTG_STATE_A_IDLE;
	224	break;
	225	default:
	226	break;
	227	}
	228	spin_unlock_irqrestore(&musb->lock, flags);
	229	}
	230
743411b3	231	static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
eb83092c AKG	232	{
	233	static unsigned long last_timer;
	234
	235	if (!is_otg_enabled(musb))
	236	return;
	237
	238	if (timeout == 0)
	239	timeout = jiffies + msecs_to_jiffies(3);
	240
	241	/* Never idle if active, or when VBUS timeout is not set as host */
	242	if (musb->is_active \|\| (musb->a_wait_bcon == 0 &&
	243	musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
	244	DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
	245	del_timer(&otg_workaround);
	246	last_timer = jiffies;
	247	return;
	248	}
	249
	250	if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
	251	DBG(4, "Longer idle timer already pending, ignoring...\n");
	252	return;
	253	}
	254	last_timer = timeout;
	255
	256	DBG(4, "%s inactive, starting idle timer for %u ms\n",
	257	otg_state_string(musb), jiffies_to_msecs(timeout - jiffies));
	258	mod_timer(&otg_workaround, timeout);
	259	}
	260
743411b3	261	static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
eb83092c AKG	262	{
	263	struct musb *musb = hci;
	264	void __iomem *reg_base = musb->ctrl_base;
	265	unsigned long flags;
	266	irqreturn_t ret = IRQ_NONE;
	267	u32 epintr, usbintr, lvl_intr;
	268
	269	spin_lock_irqsave(&musb->lock, flags);
	270
	271	/* Get endpoint interrupts */
	272	epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
	273
	274	if (epintr) {
	275	musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
	276
	277	musb->int_rx =
	278	(epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
	279	musb->int_tx =
	280	(epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
	281	}
	282
	283	/* Get usb core interrupts */
	284	usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
	285	if (!usbintr && !epintr)
	286	goto eoi;
	287
	288	if (usbintr) {
	289	musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
	290
	291	musb->int_usb =
	292	(usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
	293	}
	294	/*
	295	* DRVVBUS IRQs are the only proxy we have (a very poor one!) for
	296	* AM35x's missing ID change IRQ. We need an ID change IRQ to
	297	* switch appropriately between halves of the OTG state machine.
	298	* Managing DEVCTL.SESSION per Mentor docs requires that we know its
	299	* value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
	300	* Also, DRVVBUS pulses for SRP (but not at 5V) ...
	301	*/
	302	if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
	303	int drvvbus = musb_readl(reg_base, USB_STAT_REG);
	304	void __iomem *mregs = musb->mregs;
	305	u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
	306	int err;
	307
	308	err = is_host_enabled(musb) && (musb->int_usb &
	309	MUSB_INTR_VBUSERROR);
	310	if (err) {
	311	/*
	312	* The Mentor core doesn't debounce VBUS as needed
	313	* to cope with device connect current spikes. This
	314	* means it's not uncommon for bus-powered devices
	315	* to get VBUS errors during enumeration.
	316	*
	317	* This is a workaround, but newer RTL from Mentor
	318	* seems to allow a better one: "re"-starting sessions
	319	* without waiting for VBUS to stop registering in
	320	* devctl.
	321	*/
	322	musb->int_usb &= ~MUSB_INTR_VBUSERROR;
	323	musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
	324	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	325	WARNING("VBUS error workaround (delay coming)\n");
326	} else if (is_host_enabled(musb) && drvvbus) {
327	MUSB_HST_MODE(musb);
328	musb->xceiv->default_a = 1;
329	musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
330	portstate(musb->port1_status \|= USB_PORT_STAT_POWER);
331	del_timer(&otg_workaround);
332	} else {
333	musb->is_active = 0;
334	MUSB_DEV_MODE(musb);
335	musb->xceiv->default_a = 0;
336	musb->xceiv->state = OTG_STATE_B_IDLE;
337	portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
338	}
339
340	/* NOTE: this must complete power-on within 100 ms. */
341	DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
342	drvvbus ? "on" : "off",
343	otg_state_string(musb),
344	err ? " ERROR" : "",
345	devctl);
346	ret = IRQ_HANDLED;
347	}
348
349	if (musb->int_tx \|\| musb->int_rx \|\| musb->int_usb)
350	ret \|= musb_interrupt(musb);
351
352	eoi:
353	/* EOI needs to be written for the IRQ to be re-asserted. */
354	if (ret == IRQ_HANDLED \|\| epintr \|\| usbintr) {
355	/* clear level interrupt */
356	lvl_intr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
357	lvl_intr \|= AM35XX_USBOTGSS_INT_CLR;
358	omap_ctrl_writel(lvl_intr, AM35XX_CONTROL_LVL_INTR_CLEAR);
359	/* write EOI */
360	musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
361	}
362
363	/* Poll for ID change */
364	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
365	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
366
367	spin_unlock_irqrestore(&musb->lock, flags);
368
369	return ret;
370	}
371
743411b3	372	static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
eb83092c AKG	373	{
	374	u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
	375
	376	devconf2 &= ~CONF2_OTGMODE;
	377	switch (musb_mode) {
	378	#ifdef CONFIG_USB_MUSB_HDRC_HCD
	379	case MUSB_HOST: /* Force VBUS valid, ID = 0 */
	380	devconf2 \|= CONF2_FORCE_HOST;
	381	break;
	382	#endif
	383	#ifdef CONFIG_USB_GADGET_MUSB_HDRC
	384	case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
	385	devconf2 \|= CONF2_FORCE_DEVICE;
	386	break;
	387	#endif
	388	#ifdef CONFIG_USB_MUSB_OTG
	389	case MUSB_OTG: /* Don't override the VBUS/ID comparators */
	390	devconf2 \|= CONF2_NO_OVERRIDE;
	391	break;
	392	#endif
	393	default:
	394	DBG(2, "Trying to set unsupported mode %u\n", musb_mode);
	395	}
	396
	397	omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
	398	return 0;
	399	}
	400
743411b3	401	static int am35x_musb_init(struct musb *musb)
eb83092c AKG	402	{
	403	void __iomem *reg_base = musb->ctrl_base;
	404	u32 rev, lvl_intr, sw_reset;
	405	int status;
	406
	407	musb->mregs += USB_MENTOR_CORE_OFFSET;
	408
	409	clk_enable(musb->clock);
	410	DBG(2, "musb->clock=%lud\n", clk_get_rate(musb->clock));
	411
	412	musb->phy_clock = clk_get(musb->controller, "fck");
	413	if (IS_ERR(musb->phy_clock)) {
	414	status = PTR_ERR(musb->phy_clock);
	415	goto exit0;
	416	}
	417	clk_enable(musb->phy_clock);
	418	DBG(2, "musb->phy_clock=%lud\n", clk_get_rate(musb->phy_clock));
	419
	420	/* Returns zero if e.g. not clocked */
	421	rev = musb_readl(reg_base, USB_REVISION_REG);
	422	if (!rev) {
	423	status = -ENODEV;
	424	goto exit1;
	425	}
	426
	427	usb_nop_xceiv_register();
	428	musb->xceiv = otg_get_transceiver();
	429	if (!musb->xceiv) {
	430	status = -ENODEV;
	431	goto exit1;
	432	}
	433
	434	if (is_host_enabled(musb))
	435	setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
	436
743411b3	437	musb->board_set_vbus = am35x_musb_set_vbus;
eb83092c AKG	438
	439	/* Global reset */
	440	sw_reset = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
	441
	442	sw_reset \|= AM35XX_USBOTGSS_SW_RST;
	443	omap_ctrl_writel(sw_reset, AM35XX_CONTROL_IP_SW_RESET);
	444
	445	sw_reset &= ~AM35XX_USBOTGSS_SW_RST;
	446	omap_ctrl_writel(sw_reset, AM35XX_CONTROL_IP_SW_RESET);
	447
	448	/* Reset the controller */
	449	musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
	450
	451	/* Start the on-chip PHY and its PLL. */
	452	phy_on();
	453
	454	msleep(5);
	455
743411b3	456	musb->isr = am35x_musb_interrupt;
eb83092c AKG	457
	458	/* clear level interrupt */
	459	lvl_intr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
	460	lvl_intr \|= AM35XX_USBOTGSS_INT_CLR;
	461	omap_ctrl_writel(lvl_intr, AM35XX_CONTROL_LVL_INTR_CLEAR);
	462	return 0;
	463	exit1:
	464	clk_disable(musb->phy_clock);
	465	clk_put(musb->phy_clock);
	466	exit0:
	467	clk_disable(musb->clock);
	468	return status;
	469	}
	470
743411b3	471	static int am35x_musb_exit(struct musb *musb)
eb83092c AKG	472	{
	473	if (is_host_enabled(musb))
	474	del_timer_sync(&otg_workaround);
	475
	476	phy_off();
	477
	478	otg_put_transceiver(musb->xceiv);
	479	usb_nop_xceiv_unregister();
	480
	481	clk_disable(musb->clock);
	482
	483	clk_disable(musb->phy_clock);
	484	clk_put(musb->phy_clock);
	485
	486	return 0;
	487	}
	488
	489	#ifdef CONFIG_PM
	490	void musb_platform_save_context(struct musb *musb,
	491	struct musb_context_registers *musb_context)
	492	{
	493	phy_off();
	494	}
	495
	496	void musb_platform_restore_context(struct musb *musb,
	497	struct musb_context_registers *musb_context)
	498	{
	499	phy_on();
	500	}
	501	#endif
843bb1d0 AKG	502
	503	/* AM35x supports only 32bit read operation */
	504	void musb_read_fifo(struct musb_hw_ep hw_ep, u16 len, u8 dst)
	505	{
	506	void __iomem *fifo = hw_ep->fifo;
	507	u32 val;
	508	int i;
	509
	510	/* Read for 32bit-aligned destination address */
	511	if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
	512	readsl(fifo, dst, len >> 2);
	513	dst += len & ~0x03;
	514	len &= 0x03;
	515	}
	516	/*
	517	* Now read the remaining 1 to 3 byte or complete length if
	518	* unaligned address.
	519	*/
	520	if (len > 4) {
	521	for (i = 0; i < (len >> 2); i++) {
	522	(u32 ) dst = musb_readl(fifo, 0);
	523	dst += 4;
	524	}
	525	len &= 0x03;
	526	}
	527	if (len > 0) {
	528	val = musb_readl(fifo, 0);
	529	memcpy(dst, &val, len);
	530	}
	531	}
743411b3	532
f7ec9437	533	static const struct musb_platform_ops am35x_ops = {
743411b3 FB	534	.init = am35x_musb_init,
	535	.exit = am35x_musb_exit,
	536
	537	.enable = am35x_musb_enable,
	538	.disable = am35x_musb_disable,
	539
	540	.set_mode = am35x_musb_set_mode,
	541	.try_idle = am35x_musb_try_idle,
	542
	543	.set_vbus = am35x_musb_set_vbus,
	544	};
ce40c576 FB	545
	546	static u64 am35x_dmamask = DMA_BIT_MASK(32);
	547
	548	static int __init am35x_probe(struct platform_device *pdev)
	549	{
	550	struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
	551	struct platform_device *musb;
0919dfc1	552	struct am35x_glue *glue;
ce40c576 FB	553
	554	int ret = -ENOMEM;
	555
0919dfc1 FB	556	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
	557	if (!glue) {
	558	dev_err(&pdev->dev, "failed to allocate glue context\n");
	559	goto err0;
	560	}
	561
ce40c576 FB	562	musb = platform_device_alloc("musb-hdrc", -1);
	563	if (!musb) {
	564	dev_err(&pdev->dev, "failed to allocate musb device\n");
0919dfc1	565	goto err1;
ce40c576 FB	566	}
	567
	568	musb->dev.parent = &pdev->dev;
	569	musb->dev.dma_mask = &am35x_dmamask;
	570	musb->dev.coherent_dma_mask = am35x_dmamask;
	571
0919dfc1 FB	572	glue->dev = &pdev->dev;
	573	glue->musb = musb;
	574
f7ec9437 FB	575	pdata->platform_ops = &am35x_ops;
f7ec9437 FB	576
0919dfc1	577	platform_set_drvdata(pdev, glue);
ce40c576 FB	578
	579	ret = platform_device_add_resources(musb, pdev->resource,
	580	pdev->num_resources);
	581	if (ret) {
	582	dev_err(&pdev->dev, "failed to add resources\n");
0919dfc1	583	goto err2;
ce40c576 FB	584	}
	585
	586	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	587	if (ret) {
	588	dev_err(&pdev->dev, "failed to add platform_data\n");
0919dfc1	589	goto err2;
ce40c576 FB	590	}
	591
	592	ret = platform_device_add(musb);
	593	if (ret) {
	594	dev_err(&pdev->dev, "failed to register musb device\n");
0919dfc1	595	goto err2;
ce40c576 FB	596	}
	597
	598	return 0;
	599
0919dfc1	600	err2:
ce40c576 FB	601	platform_device_put(musb);
ce40c576 FB	602
0919dfc1 FB	603	err1:
	604	kfree(glue);
	605
ce40c576 FB	606	err0:
	607	return ret;
	608	}
	609
	610	static int __exit am35x_remove(struct platform_device *pdev)
	611	{
0919dfc1	612	struct am35x_glue *glue = platform_get_drvdata(pdev);
ce40c576	613
0919dfc1 FB	614	platform_device_del(glue->musb);
	615	platform_device_put(glue->musb);
	616	kfree(glue);
ce40c576 FB	617
	618	return 0;
	619	}
	620
	621	static struct platform_driver am35x_driver = {
	622	.remove = __exit_p(am35x_remove),
	623	.driver = {
	624	.name = "musb-am35x",
	625	},
	626	};
	627
	628	MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
	629	MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
	630	MODULE_LICENSE("GPL v2");
	631
	632	static int __init am35x_init(void)
	633	{
	634	return platform_driver_probe(&am35x_driver, am35x_probe);
	635	}
	636	subsys_initcall(am35x_init);
	637
	638	static void __exit am35x_exit(void)
	639	{
	640	platform_driver_unregister(&am35x_driver);
	641	}
	642	module_exit(am35x_exit);