Commit | Line | Data |
---|---|---|
eb83092c AKG |
1 | /* |
2 | * Texas Instruments AM35x "glue layer" | |
3 | * | |
4 | * Copyright (c) 2010, by Texas Instruments | |
5 | * | |
6 | * Based on the DA8xx "glue layer" code. | |
7 | * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com> | |
8 | * | |
9 | * This file is part of the Inventra Controller Driver for Linux. | |
10 | * | |
11 | * The Inventra Controller Driver for Linux is free software; you | |
12 | * can redistribute it and/or modify it under the terms of the GNU | |
13 | * General Public License version 2 as published by the Free Software | |
14 | * Foundation. | |
15 | * | |
16 | * The Inventra Controller Driver for Linux is distributed in | |
17 | * the hope that it will be useful, but WITHOUT ANY WARRANTY; | |
18 | * without even the implied warranty of MERCHANTABILITY or | |
19 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
20 | * License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with The Inventra Controller Driver for Linux ; if not, | |
24 | * write to the Free Software Foundation, Inc., 59 Temple Place, | |
25 | * Suite 330, Boston, MA 02111-1307 USA | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/init.h> | |
30 | #include <linux/clk.h> | |
31 | #include <linux/io.h> | |
ce40c576 FB |
32 | #include <linux/platform_device.h> |
33 | #include <linux/dma-mapping.h> | |
eb83092c | 34 | |
eb83092c AKG |
35 | #include <plat/usb.h> |
36 | ||
37 | #include "musb_core.h" | |
38 | ||
39 | /* | |
40 | * AM35x specific definitions | |
41 | */ | |
42 | /* USB 2.0 OTG module registers */ | |
43 | #define USB_REVISION_REG 0x00 | |
44 | #define USB_CTRL_REG 0x04 | |
45 | #define USB_STAT_REG 0x08 | |
46 | #define USB_EMULATION_REG 0x0c | |
47 | /* 0x10 Reserved */ | |
48 | #define USB_AUTOREQ_REG 0x14 | |
49 | #define USB_SRP_FIX_TIME_REG 0x18 | |
50 | #define USB_TEARDOWN_REG 0x1c | |
51 | #define EP_INTR_SRC_REG 0x20 | |
52 | #define EP_INTR_SRC_SET_REG 0x24 | |
53 | #define EP_INTR_SRC_CLEAR_REG 0x28 | |
54 | #define EP_INTR_MASK_REG 0x2c | |
55 | #define EP_INTR_MASK_SET_REG 0x30 | |
56 | #define EP_INTR_MASK_CLEAR_REG 0x34 | |
57 | #define EP_INTR_SRC_MASKED_REG 0x38 | |
58 | #define CORE_INTR_SRC_REG 0x40 | |
59 | #define CORE_INTR_SRC_SET_REG 0x44 | |
60 | #define CORE_INTR_SRC_CLEAR_REG 0x48 | |
61 | #define CORE_INTR_MASK_REG 0x4c | |
62 | #define CORE_INTR_MASK_SET_REG 0x50 | |
63 | #define CORE_INTR_MASK_CLEAR_REG 0x54 | |
64 | #define CORE_INTR_SRC_MASKED_REG 0x58 | |
65 | /* 0x5c Reserved */ | |
66 | #define USB_END_OF_INTR_REG 0x60 | |
67 | ||
68 | /* Control register bits */ | |
69 | #define AM35X_SOFT_RESET_MASK 1 | |
70 | ||
71 | /* USB interrupt register bits */ | |
72 | #define AM35X_INTR_USB_SHIFT 16 | |
73 | #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT) | |
74 | #define AM35X_INTR_DRVVBUS 0x100 | |
75 | #define AM35X_INTR_RX_SHIFT 16 | |
76 | #define AM35X_INTR_TX_SHIFT 0 | |
77 | #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */ | |
78 | #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */ | |
79 | #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT) | |
80 | #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT) | |
81 | ||
82 | #define USB_MENTOR_CORE_OFFSET 0x400 | |
83 | ||
0919dfc1 FB |
84 | struct am35x_glue { |
85 | struct device *dev; | |
86 | struct platform_device *musb; | |
03491761 FB |
87 | struct clk *phy_clk; |
88 | struct clk *clk; | |
0919dfc1 | 89 | }; |
6f783e28 | 90 | #define glue_to_musb(g) platform_get_drvdata(g->musb) |
0919dfc1 | 91 | |
eb83092c | 92 | /* |
743411b3 | 93 | * am35x_musb_enable - enable interrupts |
eb83092c | 94 | */ |
743411b3 | 95 | static void am35x_musb_enable(struct musb *musb) |
eb83092c AKG |
96 | { |
97 | void __iomem *reg_base = musb->ctrl_base; | |
98 | u32 epmask; | |
99 | ||
100 | /* Workaround: setup IRQs through both register sets. */ | |
101 | epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) | | |
102 | ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT); | |
103 | ||
104 | musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask); | |
105 | musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK); | |
106 | ||
107 | /* Force the DRVVBUS IRQ so we can start polling for ID change. */ | |
108 | if (is_otg_enabled(musb)) | |
109 | musb_writel(reg_base, CORE_INTR_SRC_SET_REG, | |
110 | AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT); | |
111 | } | |
112 | ||
113 | /* | |
743411b3 | 114 | * am35x_musb_disable - disable HDRC and flush interrupts |
eb83092c | 115 | */ |
743411b3 | 116 | static void am35x_musb_disable(struct musb *musb) |
eb83092c AKG |
117 | { |
118 | void __iomem *reg_base = musb->ctrl_base; | |
119 | ||
120 | musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK); | |
121 | musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG, | |
122 | AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK); | |
123 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
124 | musb_writel(reg_base, USB_END_OF_INTR_REG, 0); | |
125 | } | |
126 | ||
127 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
128 | #define portstate(stmt) stmt | |
129 | #else | |
130 | #define portstate(stmt) | |
131 | #endif | |
132 | ||
743411b3 | 133 | static void am35x_musb_set_vbus(struct musb *musb, int is_on) |
eb83092c AKG |
134 | { |
135 | WARN_ON(is_on && is_peripheral_active(musb)); | |
136 | } | |
137 | ||
138 | #define POLL_SECONDS 2 | |
139 | ||
140 | static struct timer_list otg_workaround; | |
141 | ||
142 | static void otg_timer(unsigned long _musb) | |
143 | { | |
144 | struct musb *musb = (void *)_musb; | |
145 | void __iomem *mregs = musb->mregs; | |
146 | u8 devctl; | |
147 | unsigned long flags; | |
148 | ||
149 | /* | |
150 | * We poll because AM35x's won't expose several OTG-critical | |
151 | * status change events (from the transceiver) otherwise. | |
152 | */ | |
153 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
154 | DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb)); | |
155 | ||
156 | spin_lock_irqsave(&musb->lock, flags); | |
157 | switch (musb->xceiv->state) { | |
158 | case OTG_STATE_A_WAIT_BCON: | |
159 | devctl &= ~MUSB_DEVCTL_SESSION; | |
160 | musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); | |
161 | ||
162 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
163 | if (devctl & MUSB_DEVCTL_BDEVICE) { | |
164 | musb->xceiv->state = OTG_STATE_B_IDLE; | |
165 | MUSB_DEV_MODE(musb); | |
166 | } else { | |
167 | musb->xceiv->state = OTG_STATE_A_IDLE; | |
168 | MUSB_HST_MODE(musb); | |
169 | } | |
170 | break; | |
171 | case OTG_STATE_A_WAIT_VFALL: | |
172 | musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; | |
173 | musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG, | |
174 | MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT); | |
175 | break; | |
176 | case OTG_STATE_B_IDLE: | |
177 | if (!is_peripheral_enabled(musb)) | |
178 | break; | |
179 | ||
180 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
181 | if (devctl & MUSB_DEVCTL_BDEVICE) | |
182 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
183 | else | |
184 | musb->xceiv->state = OTG_STATE_A_IDLE; | |
185 | break; | |
186 | default: | |
187 | break; | |
188 | } | |
189 | spin_unlock_irqrestore(&musb->lock, flags); | |
190 | } | |
191 | ||
743411b3 | 192 | static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout) |
eb83092c AKG |
193 | { |
194 | static unsigned long last_timer; | |
195 | ||
196 | if (!is_otg_enabled(musb)) | |
197 | return; | |
198 | ||
199 | if (timeout == 0) | |
200 | timeout = jiffies + msecs_to_jiffies(3); | |
201 | ||
202 | /* Never idle if active, or when VBUS timeout is not set as host */ | |
203 | if (musb->is_active || (musb->a_wait_bcon == 0 && | |
204 | musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) { | |
205 | DBG(4, "%s active, deleting timer\n", otg_state_string(musb)); | |
206 | del_timer(&otg_workaround); | |
207 | last_timer = jiffies; | |
208 | return; | |
209 | } | |
210 | ||
211 | if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) { | |
212 | DBG(4, "Longer idle timer already pending, ignoring...\n"); | |
213 | return; | |
214 | } | |
215 | last_timer = timeout; | |
216 | ||
217 | DBG(4, "%s inactive, starting idle timer for %u ms\n", | |
218 | otg_state_string(musb), jiffies_to_msecs(timeout - jiffies)); | |
219 | mod_timer(&otg_workaround, timeout); | |
220 | } | |
221 | ||
743411b3 | 222 | static irqreturn_t am35x_musb_interrupt(int irq, void *hci) |
eb83092c AKG |
223 | { |
224 | struct musb *musb = hci; | |
225 | void __iomem *reg_base = musb->ctrl_base; | |
a9c03783 AKG |
226 | struct device *dev = musb->controller; |
227 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
228 | struct omap_musb_board_data *data = plat->board_data; | |
eb83092c AKG |
229 | unsigned long flags; |
230 | irqreturn_t ret = IRQ_NONE; | |
a9c03783 | 231 | u32 epintr, usbintr; |
eb83092c AKG |
232 | |
233 | spin_lock_irqsave(&musb->lock, flags); | |
234 | ||
235 | /* Get endpoint interrupts */ | |
236 | epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG); | |
237 | ||
238 | if (epintr) { | |
239 | musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr); | |
240 | ||
241 | musb->int_rx = | |
242 | (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT; | |
243 | musb->int_tx = | |
244 | (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT; | |
245 | } | |
246 | ||
247 | /* Get usb core interrupts */ | |
248 | usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG); | |
249 | if (!usbintr && !epintr) | |
250 | goto eoi; | |
251 | ||
252 | if (usbintr) { | |
253 | musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr); | |
254 | ||
255 | musb->int_usb = | |
256 | (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT; | |
257 | } | |
258 | /* | |
259 | * DRVVBUS IRQs are the only proxy we have (a very poor one!) for | |
260 | * AM35x's missing ID change IRQ. We need an ID change IRQ to | |
261 | * switch appropriately between halves of the OTG state machine. | |
262 | * Managing DEVCTL.SESSION per Mentor docs requires that we know its | |
263 | * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set. | |
264 | * Also, DRVVBUS pulses for SRP (but not at 5V) ... | |
265 | */ | |
266 | if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) { | |
267 | int drvvbus = musb_readl(reg_base, USB_STAT_REG); | |
268 | void __iomem *mregs = musb->mregs; | |
269 | u8 devctl = musb_readb(mregs, MUSB_DEVCTL); | |
270 | int err; | |
271 | ||
272 | err = is_host_enabled(musb) && (musb->int_usb & | |
273 | MUSB_INTR_VBUSERROR); | |
274 | if (err) { | |
275 | /* | |
276 | * The Mentor core doesn't debounce VBUS as needed | |
277 | * to cope with device connect current spikes. This | |
278 | * means it's not uncommon for bus-powered devices | |
279 | * to get VBUS errors during enumeration. | |
280 | * | |
281 | * This is a workaround, but newer RTL from Mentor | |
282 | * seems to allow a better one: "re"-starting sessions | |
283 | * without waiting for VBUS to stop registering in | |
284 | * devctl. | |
285 | */ | |
286 | musb->int_usb &= ~MUSB_INTR_VBUSERROR; | |
287 | musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; | |
288 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
289 | WARNING("VBUS error workaround (delay coming)\n"); | |
290 | } else if (is_host_enabled(musb) && drvvbus) { | |
291 | MUSB_HST_MODE(musb); | |
292 | musb->xceiv->default_a = 1; | |
293 | musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; | |
294 | portstate(musb->port1_status |= USB_PORT_STAT_POWER); | |
295 | del_timer(&otg_workaround); | |
296 | } else { | |
297 | musb->is_active = 0; | |
298 | MUSB_DEV_MODE(musb); | |
299 | musb->xceiv->default_a = 0; | |
300 | musb->xceiv->state = OTG_STATE_B_IDLE; | |
301 | portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); | |
302 | } | |
303 | ||
304 | /* NOTE: this must complete power-on within 100 ms. */ | |
305 | DBG(2, "VBUS %s (%s)%s, devctl %02x\n", | |
306 | drvvbus ? "on" : "off", | |
307 | otg_state_string(musb), | |
308 | err ? " ERROR" : "", | |
309 | devctl); | |
310 | ret = IRQ_HANDLED; | |
311 | } | |
312 | ||
313 | if (musb->int_tx || musb->int_rx || musb->int_usb) | |
314 | ret |= musb_interrupt(musb); | |
315 | ||
316 | eoi: | |
317 | /* EOI needs to be written for the IRQ to be re-asserted. */ | |
318 | if (ret == IRQ_HANDLED || epintr || usbintr) { | |
319 | /* clear level interrupt */ | |
a9c03783 AKG |
320 | if (data->clear_irq) |
321 | data->clear_irq(); | |
eb83092c AKG |
322 | /* write EOI */ |
323 | musb_writel(reg_base, USB_END_OF_INTR_REG, 0); | |
324 | } | |
325 | ||
326 | /* Poll for ID change */ | |
327 | if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE) | |
328 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
329 | ||
330 | spin_unlock_irqrestore(&musb->lock, flags); | |
331 | ||
332 | return ret; | |
333 | } | |
334 | ||
743411b3 | 335 | static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode) |
eb83092c | 336 | { |
a9c03783 AKG |
337 | struct device *dev = musb->controller; |
338 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
339 | struct omap_musb_board_data *data = plat->board_data; | |
340 | int retval = 0; | |
eb83092c | 341 | |
a9c03783 AKG |
342 | if (data->set_mode) |
343 | data->set_mode(musb_mode); | |
344 | else | |
345 | retval = -EIO; | |
eb83092c | 346 | |
a9c03783 | 347 | return retval; |
eb83092c AKG |
348 | } |
349 | ||
743411b3 | 350 | static int am35x_musb_init(struct musb *musb) |
eb83092c | 351 | { |
a9c03783 AKG |
352 | struct device *dev = musb->controller; |
353 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
354 | struct omap_musb_board_data *data = plat->board_data; | |
eb83092c | 355 | void __iomem *reg_base = musb->ctrl_base; |
a9c03783 | 356 | u32 rev; |
eb83092c AKG |
357 | |
358 | musb->mregs += USB_MENTOR_CORE_OFFSET; | |
359 | ||
eb83092c AKG |
360 | /* Returns zero if e.g. not clocked */ |
361 | rev = musb_readl(reg_base, USB_REVISION_REG); | |
03491761 FB |
362 | if (!rev) |
363 | return -ENODEV; | |
eb83092c AKG |
364 | |
365 | usb_nop_xceiv_register(); | |
366 | musb->xceiv = otg_get_transceiver(); | |
03491761 FB |
367 | if (!musb->xceiv) |
368 | return -ENODEV; | |
eb83092c AKG |
369 | |
370 | if (is_host_enabled(musb)) | |
371 | setup_timer(&otg_workaround, otg_timer, (unsigned long) musb); | |
372 | ||
a9c03783 AKG |
373 | /* Reset the musb */ |
374 | if (data->reset) | |
375 | data->reset(); | |
eb83092c AKG |
376 | |
377 | /* Reset the controller */ | |
378 | musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK); | |
379 | ||
380 | /* Start the on-chip PHY and its PLL. */ | |
a9c03783 AKG |
381 | if (data->set_phy_power) |
382 | data->set_phy_power(1); | |
eb83092c AKG |
383 | |
384 | msleep(5); | |
385 | ||
743411b3 | 386 | musb->isr = am35x_musb_interrupt; |
eb83092c AKG |
387 | |
388 | /* clear level interrupt */ | |
a9c03783 AKG |
389 | if (data->clear_irq) |
390 | data->clear_irq(); | |
03491761 | 391 | |
eb83092c | 392 | return 0; |
eb83092c AKG |
393 | } |
394 | ||
743411b3 | 395 | static int am35x_musb_exit(struct musb *musb) |
eb83092c | 396 | { |
a9c03783 AKG |
397 | struct device *dev = musb->controller; |
398 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
399 | struct omap_musb_board_data *data = plat->board_data; | |
400 | ||
eb83092c AKG |
401 | if (is_host_enabled(musb)) |
402 | del_timer_sync(&otg_workaround); | |
403 | ||
a9c03783 AKG |
404 | /* Shutdown the on-chip PHY and its PLL. */ |
405 | if (data->set_phy_power) | |
406 | data->set_phy_power(0); | |
eb83092c AKG |
407 | |
408 | otg_put_transceiver(musb->xceiv); | |
409 | usb_nop_xceiv_unregister(); | |
410 | ||
eb83092c AKG |
411 | return 0; |
412 | } | |
413 | ||
843bb1d0 AKG |
414 | /* AM35x supports only 32bit read operation */ |
415 | void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) | |
416 | { | |
417 | void __iomem *fifo = hw_ep->fifo; | |
418 | u32 val; | |
419 | int i; | |
420 | ||
421 | /* Read for 32bit-aligned destination address */ | |
422 | if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) { | |
423 | readsl(fifo, dst, len >> 2); | |
424 | dst += len & ~0x03; | |
425 | len &= 0x03; | |
426 | } | |
427 | /* | |
428 | * Now read the remaining 1 to 3 byte or complete length if | |
429 | * unaligned address. | |
430 | */ | |
431 | if (len > 4) { | |
432 | for (i = 0; i < (len >> 2); i++) { | |
433 | *(u32 *) dst = musb_readl(fifo, 0); | |
434 | dst += 4; | |
435 | } | |
436 | len &= 0x03; | |
437 | } | |
438 | if (len > 0) { | |
439 | val = musb_readl(fifo, 0); | |
440 | memcpy(dst, &val, len); | |
441 | } | |
442 | } | |
743411b3 | 443 | |
f7ec9437 | 444 | static const struct musb_platform_ops am35x_ops = { |
743411b3 FB |
445 | .init = am35x_musb_init, |
446 | .exit = am35x_musb_exit, | |
447 | ||
448 | .enable = am35x_musb_enable, | |
449 | .disable = am35x_musb_disable, | |
450 | ||
451 | .set_mode = am35x_musb_set_mode, | |
452 | .try_idle = am35x_musb_try_idle, | |
453 | ||
454 | .set_vbus = am35x_musb_set_vbus, | |
455 | }; | |
ce40c576 FB |
456 | |
457 | static u64 am35x_dmamask = DMA_BIT_MASK(32); | |
458 | ||
459 | static int __init am35x_probe(struct platform_device *pdev) | |
460 | { | |
461 | struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data; | |
462 | struct platform_device *musb; | |
0919dfc1 | 463 | struct am35x_glue *glue; |
ce40c576 | 464 | |
03491761 FB |
465 | struct clk *phy_clk; |
466 | struct clk *clk; | |
467 | ||
ce40c576 FB |
468 | int ret = -ENOMEM; |
469 | ||
0919dfc1 FB |
470 | glue = kzalloc(sizeof(*glue), GFP_KERNEL); |
471 | if (!glue) { | |
472 | dev_err(&pdev->dev, "failed to allocate glue context\n"); | |
473 | goto err0; | |
474 | } | |
475 | ||
ce40c576 FB |
476 | musb = platform_device_alloc("musb-hdrc", -1); |
477 | if (!musb) { | |
478 | dev_err(&pdev->dev, "failed to allocate musb device\n"); | |
0919dfc1 | 479 | goto err1; |
ce40c576 FB |
480 | } |
481 | ||
03491761 FB |
482 | phy_clk = clk_get(&pdev->dev, "fck"); |
483 | if (IS_ERR(phy_clk)) { | |
484 | dev_err(&pdev->dev, "failed to get PHY clock\n"); | |
485 | ret = PTR_ERR(phy_clk); | |
486 | goto err2; | |
487 | } | |
488 | ||
489 | clk = clk_get(&pdev->dev, "ick"); | |
490 | if (IS_ERR(clk)) { | |
491 | dev_err(&pdev->dev, "failed to get clock\n"); | |
492 | ret = PTR_ERR(clk); | |
493 | goto err3; | |
494 | } | |
495 | ||
496 | ret = clk_enable(phy_clk); | |
497 | if (ret) { | |
498 | dev_err(&pdev->dev, "failed to enable PHY clock\n"); | |
499 | goto err4; | |
500 | } | |
501 | ||
502 | ret = clk_enable(clk); | |
503 | if (ret) { | |
504 | dev_err(&pdev->dev, "failed to enable clock\n"); | |
505 | goto err5; | |
506 | } | |
507 | ||
ce40c576 FB |
508 | musb->dev.parent = &pdev->dev; |
509 | musb->dev.dma_mask = &am35x_dmamask; | |
510 | musb->dev.coherent_dma_mask = am35x_dmamask; | |
511 | ||
0919dfc1 FB |
512 | glue->dev = &pdev->dev; |
513 | glue->musb = musb; | |
03491761 FB |
514 | glue->phy_clk = phy_clk; |
515 | glue->clk = clk; | |
0919dfc1 | 516 | |
f7ec9437 FB |
517 | pdata->platform_ops = &am35x_ops; |
518 | ||
0919dfc1 | 519 | platform_set_drvdata(pdev, glue); |
ce40c576 FB |
520 | |
521 | ret = platform_device_add_resources(musb, pdev->resource, | |
522 | pdev->num_resources); | |
523 | if (ret) { | |
524 | dev_err(&pdev->dev, "failed to add resources\n"); | |
03491761 | 525 | goto err6; |
ce40c576 FB |
526 | } |
527 | ||
528 | ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); | |
529 | if (ret) { | |
530 | dev_err(&pdev->dev, "failed to add platform_data\n"); | |
03491761 | 531 | goto err6; |
ce40c576 FB |
532 | } |
533 | ||
534 | ret = platform_device_add(musb); | |
535 | if (ret) { | |
536 | dev_err(&pdev->dev, "failed to register musb device\n"); | |
03491761 | 537 | goto err6; |
ce40c576 FB |
538 | } |
539 | ||
540 | return 0; | |
541 | ||
03491761 FB |
542 | err6: |
543 | clk_disable(clk); | |
544 | ||
545 | err5: | |
546 | clk_disable(phy_clk); | |
547 | ||
548 | err4: | |
549 | clk_put(clk); | |
550 | ||
551 | err3: | |
552 | clk_put(phy_clk); | |
553 | ||
0919dfc1 | 554 | err2: |
ce40c576 FB |
555 | platform_device_put(musb); |
556 | ||
0919dfc1 FB |
557 | err1: |
558 | kfree(glue); | |
559 | ||
ce40c576 FB |
560 | err0: |
561 | return ret; | |
562 | } | |
563 | ||
564 | static int __exit am35x_remove(struct platform_device *pdev) | |
565 | { | |
0919dfc1 | 566 | struct am35x_glue *glue = platform_get_drvdata(pdev); |
ce40c576 | 567 | |
0919dfc1 FB |
568 | platform_device_del(glue->musb); |
569 | platform_device_put(glue->musb); | |
03491761 FB |
570 | clk_disable(glue->clk); |
571 | clk_disable(glue->phy_clk); | |
572 | clk_put(glue->clk); | |
573 | clk_put(glue->phy_clk); | |
0919dfc1 | 574 | kfree(glue); |
ce40c576 FB |
575 | |
576 | return 0; | |
577 | } | |
578 | ||
6f783e28 FB |
579 | #ifdef CONFIG_PM |
580 | static int am35x_suspend(struct device *dev) | |
581 | { | |
582 | struct am35x_glue *glue = dev_get_drvdata(dev); | |
a9c03783 AKG |
583 | struct musb_hdrc_platform_data *plat = dev->platform_data; |
584 | struct omap_musb_board_data *data = plat->board_data; | |
585 | ||
586 | /* Shutdown the on-chip PHY and its PLL. */ | |
587 | if (data->set_phy_power) | |
588 | data->set_phy_power(0); | |
6f783e28 | 589 | |
6f783e28 FB |
590 | clk_disable(glue->phy_clk); |
591 | clk_disable(glue->clk); | |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
596 | static int am35x_resume(struct device *dev) | |
597 | { | |
598 | struct am35x_glue *glue = dev_get_drvdata(dev); | |
a9c03783 AKG |
599 | struct musb_hdrc_platform_data *plat = dev->platform_data; |
600 | struct omap_musb_board_data *data = plat->board_data; | |
6f783e28 FB |
601 | int ret; |
602 | ||
a9c03783 AKG |
603 | /* Start the on-chip PHY and its PLL. */ |
604 | if (data->set_phy_power) | |
605 | data->set_phy_power(1); | |
606 | ||
6f783e28 FB |
607 | ret = clk_enable(glue->phy_clk); |
608 | if (ret) { | |
609 | dev_err(dev, "failed to enable PHY clock\n"); | |
610 | return ret; | |
611 | } | |
612 | ||
613 | ret = clk_enable(glue->clk); | |
614 | if (ret) { | |
615 | dev_err(dev, "failed to enable clock\n"); | |
616 | return ret; | |
617 | } | |
618 | ||
619 | return 0; | |
620 | } | |
621 | ||
622 | static struct dev_pm_ops am35x_pm_ops = { | |
623 | .suspend = am35x_suspend, | |
624 | .resume = am35x_resume, | |
625 | }; | |
626 | ||
627 | #define DEV_PM_OPS &am35x_pm_ops | |
628 | #else | |
629 | #define DEV_PM_OPS NULL | |
630 | #endif | |
631 | ||
ce40c576 FB |
632 | static struct platform_driver am35x_driver = { |
633 | .remove = __exit_p(am35x_remove), | |
634 | .driver = { | |
635 | .name = "musb-am35x", | |
6f783e28 | 636 | .pm = DEV_PM_OPS, |
ce40c576 FB |
637 | }, |
638 | }; | |
639 | ||
640 | MODULE_DESCRIPTION("AM35x MUSB Glue Layer"); | |
641 | MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>"); | |
642 | MODULE_LICENSE("GPL v2"); | |
643 | ||
644 | static int __init am35x_init(void) | |
645 | { | |
646 | return platform_driver_probe(&am35x_driver, am35x_probe); | |
647 | } | |
648 | subsys_initcall(am35x_init); | |
649 | ||
650 | static void __exit am35x_exit(void) | |
651 | { | |
652 | platform_driver_unregister(&am35x_driver); | |
653 | } | |
654 | module_exit(am35x_exit); |