[deliverable/linux.git] / drivers / usb / musb / blackfin.c

/*
 * MUSB OTG controller driver for Blackfin Processors
 *
 * Copyright 2006-2008 Analog Devices Inc.
 *
 * Enter bugs at http://blackfin.uclinux.org/
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/list.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/prefetch.h>
#include <linux/usb/usb_phy_generic.h>

#include <asm/cacheflush.h>

#include "musb_core.h"
#include "musbhsdma.h"
#include "blackfin.h"

struct bfin_glue {
	struct device		*dev;
	struct platform_device	*musb;
	struct platform_device	*phy;
};
#define glue_to_musb(g)		platform_get_drvdata(g->musb)

static u32 bfin_fifo_offset(u8 epnum)
{
	return USB_OFFSET(USB_EP0_FIFO) + (epnum * 8);
}

static u8 bfin_readb(const void __iomem *addr, unsigned offset)
{
	return (u8)(bfin_read16(addr + offset));
}

static u16 bfin_readw(const void __iomem *addr, unsigned offset)
{
	return bfin_read16(addr + offset);
}

static u32 bfin_readl(const void __iomem *addr, unsigned offset)
{
	return (u32)(bfin_read16(addr + offset));
}

static void bfin_writeb(void __iomem *addr, unsigned offset, u8 data)
{
	bfin_write16(addr + offset, (u16)data);
}

static void bfin_writew(void __iomem *addr, unsigned offset, u16 data)
{
	bfin_write16(addr + offset, data);
}

static void bfin_writel(void __iomem *addr, unsigned offset, u32 data)
{
	bfin_write16(addr + offset, (u16)data);
}

/*
 * Load an endpoint's FIFO
 */
static void bfin_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
{
	struct musb *musb = hw_ep->musb;
	void __iomem *fifo = hw_ep->fifo;
	void __iomem *epio = hw_ep->regs;
	u8 epnum = hw_ep->epnum;

	prefetch((u8 *)src);

	musb_writew(epio, MUSB_TXCOUNT, len);

	dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
			hw_ep->epnum, fifo, len, src, epio);

	dump_fifo_data(src, len);

	if (!ANOMALY_05000380 && epnum != 0) {
		u16 dma_reg;

		flush_dcache_range((unsigned long)src,
			(unsigned long)(src + len));

		/* Setup DMA address register */
		dma_reg = (u32)src;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
		SSYNC();

		dma_reg = (u32)src >> 16;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
		SSYNC();

		/* Setup DMA count register */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
		SSYNC();

		/* Enable the DMA */
		dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
		SSYNC();

		/* Wait for complete */
		while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
			cpu_relax();

		/* acknowledge dma interrupt */
		bfin_write_USB_DMA_INTERRUPT(1 << epnum);
		SSYNC();

		/* Reset DMA */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
		SSYNC();
	} else {
		SSYNC();

		if (unlikely((unsigned long)src & 0x01))
			outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
		else
			outsw((unsigned long)fifo, src, (len + 1) >> 1);
	}
}
/*
 * Unload an endpoint's FIFO
 */
static void bfin_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
{
	struct musb *musb = hw_ep->musb;
	void __iomem *fifo = hw_ep->fifo;
	u8 epnum = hw_ep->epnum;

	if (ANOMALY_05000467 && epnum != 0) {
		u16 dma_reg;

		invalidate_dcache_range((unsigned long)dst,
			(unsigned long)(dst + len));

		/* Setup DMA address register */
		dma_reg = (u32)dst;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
		SSYNC();

		dma_reg = (u32)dst >> 16;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
		SSYNC();

		/* Setup DMA count register */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
		SSYNC();

		/* Enable the DMA */
		dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
		SSYNC();

		/* Wait for complete */
		while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
			cpu_relax();

		/* acknowledge dma interrupt */
		bfin_write_USB_DMA_INTERRUPT(1 << epnum);
		SSYNC();

		/* Reset DMA */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
		SSYNC();
	} else {
		SSYNC();
		/* Read the last byte of packet with odd size from address fifo + 4
		 * to trigger 1 byte access to EP0 FIFO.
		 */
		if (len == 1)
			*dst = (u8)inw((unsigned long)fifo + 4);
		else {
			if (unlikely((unsigned long)dst & 0x01))
				insw_8((unsigned long)fifo, dst, len >> 1);
			else
				insw((unsigned long)fifo, dst, len >> 1);

			if (len & 0x01)
				*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
		}
	}
	dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
			'R', hw_ep->epnum, fifo, len, dst);

	dump_fifo_data(dst, len);
}

static irqreturn_t blackfin_interrupt(int irq, void *__hci)
{
	unsigned long	flags;
	irqreturn_t	retval = IRQ_NONE;
	struct musb	*musb = __hci;

	spin_lock_irqsave(&musb->lock, flags);

	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);

	if (musb->int_usb || musb->int_tx || musb->int_rx) {
		musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
		musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
		musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
		retval = musb_interrupt(musb);
	}

	/* Start sampling ID pin, when plug is removed from MUSB */
	if ((musb->xceiv->otg->state == OTG_STATE_B_IDLE
		|| musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON) ||
		(musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
		musb->a_wait_bcon = TIMER_DELAY;
	}

	spin_unlock_irqrestore(&musb->lock, flags);

	return retval;
}

static void musb_conn_timer_handler(unsigned long _musb)
{
	struct musb *musb = (void *)_musb;
	unsigned long flags;
	u16 val;
	static u8 toggle;

	spin_lock_irqsave(&musb->lock, flags);
	switch (musb->xceiv->otg->state) {
	case OTG_STATE_A_IDLE:
	case OTG_STATE_A_WAIT_BCON:
		/* Start a new session */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);
		val &= ~MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);
		val |= MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);
		/* Check if musb is host or peripheral. */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);

		if (!(val & MUSB_DEVCTL_BDEVICE)) {
			gpio_set_value(musb->config->gpio_vrsel, 1);
			musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
		} else {
			gpio_set_value(musb->config->gpio_vrsel, 0);
			/* Ignore VBUSERROR and SUSPEND IRQ */
			val = musb_readb(musb->mregs, MUSB_INTRUSBE);
			val &= ~MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSBE, val);

			val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSB, val);
			musb->xceiv->otg->state = OTG_STATE_B_IDLE;
		}
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
		break;
	case OTG_STATE_B_IDLE:
		/*
		 * Start a new session.  It seems that MUSB needs taking
		 * some time to recognize the type of the plug inserted?
		 */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);
		val |= MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);
		val = musb_readw(musb->mregs, MUSB_DEVCTL);

		if (!(val & MUSB_DEVCTL_BDEVICE)) {
			gpio_set_value(musb->config->gpio_vrsel, 1);
			musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
		} else {
			gpio_set_value(musb->config->gpio_vrsel, 0);

			/* Ignore VBUSERROR and SUSPEND IRQ */
			val = musb_readb(musb->mregs, MUSB_INTRUSBE);
			val &= ~MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSBE, val);

			val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSB, val);

			/* Toggle the Soft Conn bit, so that we can response to
			 * the inserting of either A-plug or B-plug.
			 */
			if (toggle) {
				val = musb_readb(musb->mregs, MUSB_POWER);
				val &= ~MUSB_POWER_SOFTCONN;
				musb_writeb(musb->mregs, MUSB_POWER, val);
				toggle = 0;
			} else {
				val = musb_readb(musb->mregs, MUSB_POWER);
				val |= MUSB_POWER_SOFTCONN;
				musb_writeb(musb->mregs, MUSB_POWER, val);
				toggle = 1;
			}
			/* The delay time is set to 1/4 second by default,
			 * shortening it, if accelerating A-plug detection
			 * is needed in OTG mode.
			 */
			mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
		}
		break;
	default:
		dev_dbg(musb->controller, "%s state not handled\n",
			usb_otg_state_string(musb->xceiv->otg->state));
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);

	dev_dbg(musb->controller, "state is %s\n",
		usb_otg_state_string(musb->xceiv->otg->state));
}

static void bfin_musb_enable(struct musb *musb)
{
	/* REVISIT is this really correct ? */
}

static void bfin_musb_disable(struct musb *musb)
{
}

static void bfin_musb_set_vbus(struct musb *musb, int is_on)
{
	int value = musb->config->gpio_vrsel_active;
	if (!is_on)
		value = !value;
	gpio_set_value(musb->config->gpio_vrsel, value);

	dev_dbg(musb->controller, "VBUS %s, devctl %02x "
		/* otg %3x conf %08x prcm %08x */ "\n",
		usb_otg_state_string(musb->xceiv->otg->state),
		musb_readb(musb->mregs, MUSB_DEVCTL));
}

static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)
{
	return 0;
}

static int bfin_musb_vbus_status(struct musb *musb)
{
	return 0;
}

static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
{
	return -EIO;
}

static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
				u16 packet_sz, u8 *mode,
				dma_addr_t *dma_addr, u32 *len)
{
	struct musb_dma_channel *musb_channel = channel->private_data;

	/*
	 * Anomaly 05000450 might cause data corruption when using DMA
	 * MODE 1 transmits with short packet.  So to work around this,
	 * we truncate all MODE 1 transfers down to a multiple of the
	 * max packet size, and then do the last short packet transfer
	 * (if there is any) using MODE 0.
	 */
	if (ANOMALY_05000450) {
		if (musb_channel->transmit && *mode == 1)
			*len = *len - (*len % packet_sz);
	}

	return 0;
}

static void bfin_musb_reg_init(struct musb *musb)
{
	if (ANOMALY_05000346) {
		bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
		SSYNC();
	}

	if (ANOMALY_05000347) {
		bfin_write_USB_APHY_CNTRL(0x0);
		SSYNC();
	}

	/* Configure PLL oscillator register */
	bfin_write_USB_PLLOSC_CTRL(0x3080 |
			((480/musb->config->clkin) << 1));
	SSYNC();

	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
	SSYNC();

	bfin_write_USB_EP_NI0_RXMAXP(64);
	SSYNC();

	bfin_write_USB_EP_NI0_TXMAXP(64);
	SSYNC();

	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
	bfin_write_USB_GLOBINTR(0x7);
	SSYNC();

	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
				EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
				EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
				EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
				EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
	SSYNC();
}

static int bfin_musb_init(struct musb *musb)
{

	/*
	 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
	 * and OTG HOST modes, while rev 1.1 and greater require PE7 to
	 * be low for DEVICE mode and high for HOST mode. We set it high
	 * here because we are in host mode
	 */

	if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
		printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
			musb->config->gpio_vrsel);
		return -ENODEV;
	}
	gpio_direction_output(musb->config->gpio_vrsel, 0);

	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
	if (IS_ERR_OR_NULL(musb->xceiv)) {
		gpio_free(musb->config->gpio_vrsel);
		return -EPROBE_DEFER;
	}

	bfin_musb_reg_init(musb);

	setup_timer(&musb_conn_timer, musb_conn_timer_handler,
			(unsigned long) musb);

	musb->xceiv->set_power = bfin_musb_set_power;

	musb->isr = blackfin_interrupt;
	musb->double_buffer_not_ok = true;

	return 0;
}

static int bfin_musb_exit(struct musb *musb)
{
	gpio_free(musb->config->gpio_vrsel);
	usb_put_phy(musb->xceiv);

	return 0;
}

static const struct musb_platform_ops bfin_ops = {
	.init		= bfin_musb_init,
	.exit		= bfin_musb_exit,

	.readb		= bfin_readb,
	.writeb		= bfin_writeb,
	.readw		= bfin_readw,
	.writew		= bfin_writew,
	.readl		= bfin_readl,
	.writel		= bfin_writel,
	.fifo_mode	= 2,
	.read_fifo	= bfin_read_fifo,
	.write_fifo	= bfin_write_fifo,
	.enable		= bfin_musb_enable,
	.disable	= bfin_musb_disable,

	.set_mode	= bfin_musb_set_mode,

	.vbus_status	= bfin_musb_vbus_status,
	.set_vbus	= bfin_musb_set_vbus,

	.adjust_channel_params = bfin_musb_adjust_channel_params,
};

static u64 bfin_dmamask = DMA_BIT_MASK(32);

static int bfin_probe(struct platform_device *pdev)
{
	struct resource musb_resources[2];
	struct musb_hdrc_platform_data	*pdata = dev_get_platdata(&pdev->dev);
	struct platform_device		*musb;
	struct bfin_glue		*glue;

	int				ret = -ENOMEM;

	glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
	if (!glue)
		goto err0;

	musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
	if (!musb)
		goto err0;

	musb->dev.parent		= &pdev->dev;
	musb->dev.dma_mask		= &bfin_dmamask;
	musb->dev.coherent_dma_mask	= bfin_dmamask;

	glue->dev			= &pdev->dev;
	glue->musb			= musb;

	pdata->platform_ops		= &bfin_ops;

	glue->phy = usb_phy_generic_register();
	if (IS_ERR(glue->phy))
		goto err1;
	platform_set_drvdata(pdev, glue);

	memset(musb_resources, 0x00, sizeof(*musb_resources) *
			ARRAY_SIZE(musb_resources));

	musb_resources[0].name = pdev->resource[0].name;
	musb_resources[0].start = pdev->resource[0].start;
	musb_resources[0].end = pdev->resource[0].end;
	musb_resources[0].flags = pdev->resource[0].flags;

	musb_resources[1].name = pdev->resource[1].name;
	musb_resources[1].start = pdev->resource[1].start;
	musb_resources[1].end = pdev->resource[1].end;
	musb_resources[1].flags = pdev->resource[1].flags;

	ret = platform_device_add_resources(musb, musb_resources,
			ARRAY_SIZE(musb_resources));
	if (ret) {
		dev_err(&pdev->dev, "failed to add resources\n");
		goto err2;
	}

	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	if (ret) {
		dev_err(&pdev->dev, "failed to add platform_data\n");
		goto err2;
	}

	ret = platform_device_add(musb);
	if (ret) {
		dev_err(&pdev->dev, "failed to register musb device\n");
		goto err2;
	}

	return 0;

err2:
	usb_phy_generic_unregister(glue->phy);

err1:
	platform_device_put(musb);

err0:
	return ret;
}

static int bfin_remove(struct platform_device *pdev)
{
	struct bfin_glue		*glue = platform_get_drvdata(pdev);

	platform_device_unregister(glue->musb);
	usb_phy_generic_unregister(glue->phy);

	return 0;
}

#ifdef CONFIG_PM
static int bfin_suspend(struct device *dev)
{
	struct bfin_glue	*glue = dev_get_drvdata(dev);
	struct musb		*musb = glue_to_musb(glue);

	if (is_host_active(musb))
		/*
		 * During hibernate gpio_vrsel will change from high to low
		 * low which will generate wakeup event resume the system
		 * immediately.  Set it to 0 before hibernate to avoid this
		 * wakeup event.
		 */
		gpio_set_value(musb->config->gpio_vrsel, 0);

	return 0;
}

static int bfin_resume(struct device *dev)
{
	struct bfin_glue	*glue = dev_get_drvdata(dev);
	struct musb		*musb = glue_to_musb(glue);

	bfin_musb_reg_init(musb);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(bfin_pm_ops, bfin_suspend, bfin_resume);

static struct platform_driver bfin_driver = {
	.probe		= bfin_probe,
	.remove		= bfin_remove,
	.driver		= {
		.name	= "musb-blackfin",
		.pm	= &bfin_pm_ops,
	},
};

MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
MODULE_LICENSE("GPL v2");
module_platform_driver(bfin_driver);
Commit	Line	Data
0c6a8818 BW	1	/*
	2	* MUSB OTG controller driver for Blackfin Processors
	3	*
	4	* Copyright 2006-2008 Analog Devices Inc.
	5	*
	6	* Enter bugs at http://blackfin.uclinux.org/
	7	*
	8	* Licensed under the GPL-2 or later.
	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/kernel.h>
	13	#include <linux/sched.h>
0c6a8818	14	#include <linux/list.h>
0c6a8818 BW	15	#include <linux/gpio.h>
0c6a8818 BW	16	#include <linux/io.h>
ded017ee	17	#include <linux/err.h>
9cb0308e FB	18	#include <linux/platform_device.h>
9cb0308e FB	19	#include <linux/dma-mapping.h>
ad50c1b2	20	#include <linux/prefetch.h>
d7078df6	21	#include <linux/usb/usb_phy_generic.h>
0c6a8818 BW	22
	23	#include <asm/cacheflush.h>
	24
	25	#include "musb_core.h"
13254307	26	#include "musbhsdma.h"
0c6a8818 BW	27	#include "blackfin.h"
0c6a8818 BW	28
a023c631 FB	29	struct bfin_glue {
	30	struct device *dev;
	31	struct platform_device *musb;
2f36ff69	32	struct platform_device *phy;
a023c631	33	};
fcd22e3b	34	#define glue_to_musb(g) platform_get_drvdata(g->musb)
a023c631	35
cc92f681 TL	36	static u32 bfin_fifo_offset(u8 epnum)
	37	{
	38	return USB_OFFSET(USB_EP0_FIFO) + (epnum * 8);
	39	}
	40
	41	static u8 bfin_readb(const void __iomem *addr, unsigned offset)
	42	{
	43	return (u8)(bfin_read16(addr + offset));
	44	}
	45
	46	static u16 bfin_readw(const void __iomem *addr, unsigned offset)
	47	{
	48	return bfin_read16(addr + offset);
	49	}
	50
	51	static u32 bfin_readl(const void __iomem *addr, unsigned offset)
	52	{
	53	return (u32)(bfin_read16(addr + offset));
	54	}
	55
	56	static void bfin_writeb(void __iomem *addr, unsigned offset, u8 data)
	57	{
	58	bfin_write16(addr + offset, (u16)data);
	59	}
	60
	61	static void bfin_writew(void __iomem *addr, unsigned offset, u16 data)
	62	{
	63	bfin_write16(addr + offset, data);
	64	}
	65
b1d34783	66	static void bfin_writel(void __iomem *addr, unsigned offset, u32 data)
cc92f681 TL	67	{
	68	bfin_write16(addr + offset, (u16)data);
	69	}
	70
0c6a8818 BW	71	/*
	72	* Load an endpoint's FIFO
	73	*/
1b40fc57	74	static void bfin_write_fifo(struct musb_hw_ep hw_ep, u16 len, const u8 src)
0c6a8818	75	{
28e49705	76	struct musb *musb = hw_ep->musb;
0c6a8818 BW	77	void __iomem *fifo = hw_ep->fifo;
0c6a8818 BW	78	void __iomem *epio = hw_ep->regs;
1c4bdc01	79	u8 epnum = hw_ep->epnum;
0c6a8818 BW	80
	81	prefetch((u8 *)src);
	82
	83	musb_writew(epio, MUSB_TXCOUNT, len);
	84
5c8a86e1	85	dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
0c6a8818 BW	86	hw_ep->epnum, fifo, len, src, epio);
	87
	88	dump_fifo_data(src, len);
	89
1c4bdc01	90	if (!ANOMALY_05000380 && epnum != 0) {
1ca9e9ca BW	91	u16 dma_reg;
	92
	93	flush_dcache_range((unsigned long)src,
	94	(unsigned long)(src + len));
1c4bdc01 BW	95
1c4bdc01 BW	96	/* Setup DMA address register */
1ca9e9ca	97	dma_reg = (u32)src;
1c4bdc01 BW	98	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
	99	SSYNC();
	100
1ca9e9ca	101	dma_reg = (u32)src >> 16;
1c4bdc01 BW	102	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
	103	SSYNC();
	104
	105	/* Setup DMA count register */
	106	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
	107	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
	108	SSYNC();
	109
	110	/* Enable the DMA */
	111	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA \| DIRECTION;
	112	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
	113	SSYNC();
	114
5ae477b0	115	/* Wait for complete */
1c4bdc01 BW	116	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
	117	cpu_relax();
	118
	119	/* acknowledge dma interrupt */
	120	bfin_write_USB_DMA_INTERRUPT(1 << epnum);
	121	SSYNC();
	122
	123	/* Reset DMA */
	124	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
	125	SSYNC();
	126	} else {
	127	SSYNC();
	128
	129	if (unlikely((unsigned long)src & 0x01))
1ca9e9ca	130	outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
1c4bdc01	131	else
1ca9e9ca	132	outsw((unsigned long)fifo, src, (len + 1) >> 1);
1c4bdc01	133	}
0c6a8818	134	}
0c6a8818 BW	135	/*
	136	* Unload an endpoint's FIFO
	137	*/
1b40fc57	138	static void bfin_read_fifo(struct musb_hw_ep hw_ep, u16 len, u8 dst)
0c6a8818	139	{
28e49705	140	struct musb *musb = hw_ep->musb;
0c6a8818 BW	141	void __iomem *fifo = hw_ep->fifo;
0c6a8818 BW	142	u8 epnum = hw_ep->epnum;
0c6a8818	143
1c4bdc01	144	if (ANOMALY_05000467 && epnum != 0) {
1ca9e9ca	145	u16 dma_reg;
1c4bdc01	146
1ca9e9ca BW	147	invalidate_dcache_range((unsigned long)dst,
1ca9e9ca BW	148	(unsigned long)(dst + len));
1c4bdc01 BW	149
1c4bdc01 BW	150	/* Setup DMA address register */
1ca9e9ca	151	dma_reg = (u32)dst;
1c4bdc01 BW	152	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
	153	SSYNC();
	154
1ca9e9ca	155	dma_reg = (u32)dst >> 16;
1c4bdc01 BW	156	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
	157	SSYNC();
	158
	159	/* Setup DMA count register */
	160	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
	161	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
	162	SSYNC();
	163
	164	/* Enable the DMA */
	165	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA;
	166	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
	167	SSYNC();
	168
5ae477b0	169	/* Wait for complete */
1c4bdc01 BW	170	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
	171	cpu_relax();
	172
	173	/* acknowledge dma interrupt */
	174	bfin_write_USB_DMA_INTERRUPT(1 << epnum);
	175	SSYNC();
	176
	177	/* Reset DMA */
	178	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
	179	SSYNC();
	180	} else {
	181	SSYNC();
	182	/* Read the last byte of packet with odd size from address fifo + 4
	183	* to trigger 1 byte access to EP0 FIFO.
	184	*/
	185	if (len == 1)
	186	*dst = (u8)inw((unsigned long)fifo + 4);
	187	else {
	188	if (unlikely((unsigned long)dst & 0x01))
	189	insw_8((unsigned long)fifo, dst, len >> 1);
	190	else
	191	insw((unsigned long)fifo, dst, len >> 1);
	192
	193	if (len & 0x01)
	194	*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
	195	}
	196	}
5c8a86e1	197	dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
04f4086f MF	198	'R', hw_ep->epnum, fifo, len, dst);
04f4086f MF	199
0c6a8818 BW	200	dump_fifo_data(dst, len);
	201	}
	202
	203	static irqreturn_t blackfin_interrupt(int irq, void *__hci)
	204	{
	205	unsigned long flags;
	206	irqreturn_t retval = IRQ_NONE;
	207	struct musb *musb = __hci;
	208
	209	spin_lock_irqsave(&musb->lock, flags);
	210
	211	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
	212	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
	213	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
	214
	215	if (musb->int_usb \|\| musb->int_tx \|\| musb->int_rx) {
	216	musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
	217	musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
	218	musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
	219	retval = musb_interrupt(musb);
	220	}
	221
ff927add	222	/* Start sampling ID pin, when plug is removed from MUSB */
e47d9254 AT	223	if ((musb->xceiv->otg->state == OTG_STATE_B_IDLE
e47d9254 AT	224	\|\| musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON) \|\|
68f64714	225	(musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
ff927add CC	226	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	227	musb->a_wait_bcon = TIMER_DELAY;
	228	}
	229
0c6a8818 BW	230	spin_unlock_irqrestore(&musb->lock, flags);
0c6a8818 BW	231
2f831751	232	return retval;
0c6a8818 BW	233	}
	234
	235	static void musb_conn_timer_handler(unsigned long _musb)
	236	{
	237	struct musb musb = (void )_musb;
	238	unsigned long flags;
	239	u16 val;
ff927add	240	static u8 toggle;
0c6a8818 BW	241
0c6a8818 BW	242	spin_lock_irqsave(&musb->lock, flags);
e47d9254	243	switch (musb->xceiv->otg->state) {
0c6a8818 BW	244	case OTG_STATE_A_IDLE:
	245	case OTG_STATE_A_WAIT_BCON:
	246	/* Start a new session */
	247	val = musb_readw(musb->mregs, MUSB_DEVCTL);
ff927add CC	248	val &= ~MUSB_DEVCTL_SESSION;
ff927add CC	249	musb_writew(musb->mregs, MUSB_DEVCTL, val);
0c6a8818 BW	250	val \|= MUSB_DEVCTL_SESSION;
0c6a8818 BW	251	musb_writew(musb->mregs, MUSB_DEVCTL, val);
ff927add CC	252	/* Check if musb is host or peripheral. */
	253	val = musb_readw(musb->mregs, MUSB_DEVCTL);
	254
	255	if (!(val & MUSB_DEVCTL_BDEVICE)) {
	256	gpio_set_value(musb->config->gpio_vrsel, 1);
e47d9254	257	musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
ff927add CC	258	} else {
	259	gpio_set_value(musb->config->gpio_vrsel, 0);
	260	/* Ignore VBUSERROR and SUSPEND IRQ */
	261	val = musb_readb(musb->mregs, MUSB_INTRUSBE);
	262	val &= ~MUSB_INTR_VBUSERROR;
	263	musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
	264
	265	val = MUSB_INTR_SUSPEND \| MUSB_INTR_VBUSERROR;
	266	musb_writeb(musb->mregs, MUSB_INTRUSB, val);
e47d9254	267	musb->xceiv->otg->state = OTG_STATE_B_IDLE;
ff927add CC	268	}
	269	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	270	break;
	271	case OTG_STATE_B_IDLE:
032ec49f FB	272	/*
032ec49f FB	273	* Start a new session. It seems that MUSB needs taking
ff927add CC	274	* some time to recognize the type of the plug inserted?
	275	*/
	276	val = musb_readw(musb->mregs, MUSB_DEVCTL);
	277	val \|= MUSB_DEVCTL_SESSION;
	278	musb_writew(musb->mregs, MUSB_DEVCTL, val);
0c6a8818	279	val = musb_readw(musb->mregs, MUSB_DEVCTL);
ff927add	280
0c6a8818 BW	281	if (!(val & MUSB_DEVCTL_BDEVICE)) {
0c6a8818 BW	282	gpio_set_value(musb->config->gpio_vrsel, 1);
e47d9254	283	musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
0c6a8818 BW	284	} else {
	285	gpio_set_value(musb->config->gpio_vrsel, 0);
	286
	287	/* Ignore VBUSERROR and SUSPEND IRQ */
	288	val = musb_readb(musb->mregs, MUSB_INTRUSBE);
	289	val &= ~MUSB_INTR_VBUSERROR;
	290	musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
	291
	292	val = MUSB_INTR_SUSPEND \| MUSB_INTR_VBUSERROR;
	293	musb_writeb(musb->mregs, MUSB_INTRUSB, val);
	294
ff927add CC	295	/* Toggle the Soft Conn bit, so that we can response to
	296	* the inserting of either A-plug or B-plug.
	297	*/
	298	if (toggle) {
	299	val = musb_readb(musb->mregs, MUSB_POWER);
	300	val &= ~MUSB_POWER_SOFTCONN;
	301	musb_writeb(musb->mregs, MUSB_POWER, val);
	302	toggle = 0;
	303	} else {
	304	val = musb_readb(musb->mregs, MUSB_POWER);
	305	val \|= MUSB_POWER_SOFTCONN;
	306	musb_writeb(musb->mregs, MUSB_POWER, val);
	307	toggle = 1;
	308	}
	309	/* The delay time is set to 1/4 second by default,
	310	* shortening it, if accelerating A-plug detection
	311	* is needed in OTG mode.
	312	*/
	313	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
0c6a8818	314	}
0c6a8818	315	break;
0c6a8818	316	default:
5c8a86e1	317	dev_dbg(musb->controller, "%s state not handled\n",
e47d9254	318	usb_otg_state_string(musb->xceiv->otg->state));
0c6a8818 BW	319	break;
	320	}
	321	spin_unlock_irqrestore(&musb->lock, flags);
	322
5c8a86e1	323	dev_dbg(musb->controller, "state is %s\n",
e47d9254	324	usb_otg_state_string(musb->xceiv->otg->state));
0c6a8818 BW	325	}
0c6a8818 BW	326
743411b3	327	static void bfin_musb_enable(struct musb *musb)
0c6a8818	328	{
032ec49f	329	/* REVISIT is this really correct ? */
0c6a8818 BW	330	}
0c6a8818 BW	331
743411b3	332	static void bfin_musb_disable(struct musb *musb)
0c6a8818 BW	333	{
	334	}
	335
743411b3	336	static void bfin_musb_set_vbus(struct musb *musb, int is_on)
0c6a8818	337	{
6ddc6dae CC	338	int value = musb->config->gpio_vrsel_active;
	339	if (!is_on)
	340	value = !value;
	341	gpio_set_value(musb->config->gpio_vrsel, value);
0c6a8818	342
5c8a86e1	343	dev_dbg(musb->controller, "VBUS %s, devctl %02x "
0c6a8818	344	/* otg %3x conf %08x prcm %08x */ "\n",
e47d9254	345	usb_otg_state_string(musb->xceiv->otg->state),
0c6a8818 BW	346	musb_readb(musb->mregs, MUSB_DEVCTL));
	347	}
	348
86753811	349	static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)
0c6a8818 BW	350	{
	351	return 0;
	352	}
	353
45567c28	354	static int bfin_musb_vbus_status(struct musb *musb)
0c6a8818 BW	355	{
	356	return 0;
	357	}
	358
743411b3	359	static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
0c6a8818	360	{
2002e768	361	return -EIO;
0c6a8818 BW	362	}
0c6a8818 BW	363
13254307 MF	364	static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
	365	u16 packet_sz, u8 *mode,
	366	dma_addr_t dma_addr, u32 len)
	367	{
	368	struct musb_dma_channel *musb_channel = channel->private_data;
	369
	370	/*
	371	* Anomaly 05000450 might cause data corruption when using DMA
	372	* MODE 1 transmits with short packet. So to work around this,
	373	* we truncate all MODE 1 transfers down to a multiple of the
	374	* max packet size, and then do the last short packet transfer
	375	* (if there is any) using MODE 0.
	376	*/
	377	if (ANOMALY_05000450) {
	378	if (musb_channel->transmit && *mode == 1)
	379	len = len - (*len % packet_sz);
	380	}
	381
	382	return 0;
	383	}
	384
743411b3	385	static void bfin_musb_reg_init(struct musb *musb)
0c6a8818	386	{
d426e60d RG	387	if (ANOMALY_05000346) {
	388	bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
	389	SSYNC();
	390	}
0c6a8818	391
d426e60d RG	392	if (ANOMALY_05000347) {
	393	bfin_write_USB_APHY_CNTRL(0x0);
	394	SSYNC();
	395	}
0c6a8818	396
0c6a8818	397	/* Configure PLL oscillator register */
9c756462 BL	398	bfin_write_USB_PLLOSC_CTRL(0x3080 \|
9c756462 BL	399	((480/musb->config->clkin) << 1));
0c6a8818 BW	400	SSYNC();
	401
	402	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
	403	SSYNC();
	404
	405	bfin_write_USB_EP_NI0_RXMAXP(64);
	406	SSYNC();
	407
	408	bfin_write_USB_EP_NI0_TXMAXP(64);
	409	SSYNC();
	410
	411	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
	412	bfin_write_USB_GLOBINTR(0x7);
	413	SSYNC();
	414
	415	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA \| EP1_TX_ENA \| EP2_TX_ENA \|
	416	EP3_TX_ENA \| EP4_TX_ENA \| EP5_TX_ENA \|
	417	EP6_TX_ENA \| EP7_TX_ENA \| EP1_RX_ENA \|
	418	EP2_RX_ENA \| EP3_RX_ENA \| EP4_RX_ENA \|
	419	EP5_RX_ENA \| EP6_RX_ENA \| EP7_RX_ENA);
	420	SSYNC();
743411b3 FB	421	}
	422
	423	static int bfin_musb_init(struct musb *musb)
	424	{
	425
	426	/*
	427	* Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
	428	* and OTG HOST modes, while rev 1.1 and greater require PE7 to
	429	* be low for DEVICE mode and high for HOST mode. We set it high
	430	* here because we are in host mode
	431	*/
	432
	433	if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
	434	printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
	435	musb->config->gpio_vrsel);
	436	return -ENODEV;
	437	}
	438	gpio_direction_output(musb->config->gpio_vrsel, 0);
	439
662dca54	440	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
ded017ee	441	if (IS_ERR_OR_NULL(musb->xceiv)) {
743411b3	442	gpio_free(musb->config->gpio_vrsel);
25736e0c	443	return -EPROBE_DEFER;
743411b3 FB	444	}
	445
	446	bfin_musb_reg_init(musb);
0c6a8818	447
032ec49f FB	448	setup_timer(&musb_conn_timer, musb_conn_timer_handler,
	449	(unsigned long) musb);
	450
	451	musb->xceiv->set_power = bfin_musb_set_power;
0c6a8818 BW	452
0c6a8818 BW	453	musb->isr = blackfin_interrupt;
06624818	454	musb->double_buffer_not_ok = true;
0c6a8818 BW	455
	456	return 0;
	457	}
	458
743411b3	459	static int bfin_musb_exit(struct musb *musb)
0c6a8818	460	{
0c6a8818	461	gpio_free(musb->config->gpio_vrsel);
721002ec	462	usb_put_phy(musb->xceiv);
e741e637	463
0c6a8818 BW	464	return 0;
0c6a8818 BW	465	}
743411b3	466
f7ec9437	467	static const struct musb_platform_ops bfin_ops = {
743411b3 FB	468	.init = bfin_musb_init,
	469	.exit = bfin_musb_exit,
	470
cc92f681 TL	471	.readb = bfin_readb,
	472	.writeb = bfin_writeb,
	473	.readw = bfin_readw,
	474	.writew = bfin_writew,
	475	.readl = bfin_readl,
	476	.writel = bfin_writel,
8a77f05a	477	.fifo_mode = 2,
1b40fc57 TL	478	.read_fifo = bfin_read_fifo,
1b40fc57 TL	479	.write_fifo = bfin_write_fifo,
743411b3 FB	480	.enable = bfin_musb_enable,
	481	.disable = bfin_musb_disable,
	482
	483	.set_mode = bfin_musb_set_mode,
743411b3 FB	484
	485	.vbus_status = bfin_musb_vbus_status,
	486	.set_vbus = bfin_musb_set_vbus,
13254307 MF	487
13254307 MF	488	.adjust_channel_params = bfin_musb_adjust_channel_params,
743411b3	489	};
9cb0308e FB	490
	491	static u64 bfin_dmamask = DMA_BIT_MASK(32);
	492
41ac7b3a	493	static int bfin_probe(struct platform_device *pdev)
9cb0308e	494	{
09fc7d22	495	struct resource musb_resources[2];
c1a7d67c	496	struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
9cb0308e	497	struct platform_device *musb;
a023c631	498	struct bfin_glue *glue;
9cb0308e FB	499
	500	int ret = -ENOMEM;
	501
f875bf35	502	glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
65469790	503	if (!glue)
a023c631	504	goto err0;
a023c631	505
2f771164	506	musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
65469790	507	if (!musb)
f875bf35	508	goto err0;
9cb0308e FB	509
	510	musb->dev.parent = &pdev->dev;
	511	musb->dev.dma_mask = &bfin_dmamask;
	512	musb->dev.coherent_dma_mask = bfin_dmamask;
	513
a023c631 FB	514	glue->dev = &pdev->dev;
	515	glue->musb = musb;
	516
f7ec9437 FB	517	pdata->platform_ops = &bfin_ops;
f7ec9437 FB	518
2f36ff69 FB	519	glue->phy = usb_phy_generic_register();
2f36ff69 FB	520	if (IS_ERR(glue->phy))
f875bf35	521	goto err1;
a023c631	522	platform_set_drvdata(pdev, glue);
9cb0308e	523
09fc7d22 FB	524	memset(musb_resources, 0x00, sizeof(musb_resources)
	525	ARRAY_SIZE(musb_resources));
	526
	527	musb_resources[0].name = pdev->resource[0].name;
	528	musb_resources[0].start = pdev->resource[0].start;
	529	musb_resources[0].end = pdev->resource[0].end;
	530	musb_resources[0].flags = pdev->resource[0].flags;
	531
	532	musb_resources[1].name = pdev->resource[1].name;
	533	musb_resources[1].start = pdev->resource[1].start;
	534	musb_resources[1].end = pdev->resource[1].end;
	535	musb_resources[1].flags = pdev->resource[1].flags;
	536
	537	ret = platform_device_add_resources(musb, musb_resources,
	538	ARRAY_SIZE(musb_resources));
9cb0308e FB	539	if (ret) {
9cb0308e FB	540	dev_err(&pdev->dev, "failed to add resources\n");
f875bf35	541	goto err2;
9cb0308e FB	542	}
	543
	544	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	545	if (ret) {
	546	dev_err(&pdev->dev, "failed to add platform_data\n");
f875bf35	547	goto err2;
9cb0308e FB	548	}
	549
	550	ret = platform_device_add(musb);
	551	if (ret) {
	552	dev_err(&pdev->dev, "failed to register musb device\n");
f875bf35	553	goto err2;
9cb0308e FB	554	}
	555
	556	return 0;
	557
2f36ff69	558	err2:
f875bf35	559	usb_phy_generic_unregister(glue->phy);
9cb0308e	560
a023c631	561	err1:
f875bf35	562	platform_device_put(musb);
a023c631	563
9cb0308e FB	564	err0:
	565	return ret;
	566	}
	567
fb4e98ab	568	static int bfin_remove(struct platform_device *pdev)
9cb0308e	569	{
a023c631	570	struct bfin_glue *glue = platform_get_drvdata(pdev);
9cb0308e	571
01e40da0	572	platform_device_unregister(glue->musb);
2f36ff69	573	usb_phy_generic_unregister(glue->phy);
9cb0308e FB	574
	575	return 0;
	576	}
	577
fcd22e3b FB	578	#ifdef CONFIG_PM
	579	static int bfin_suspend(struct device *dev)
	580	{
	581	struct bfin_glue *glue = dev_get_drvdata(dev);
	582	struct musb *musb = glue_to_musb(glue);
	583
	584	if (is_host_active(musb))
	585	/*
	586	* During hibernate gpio_vrsel will change from high to low
	587	* low which will generate wakeup event resume the system
	588	* immediately. Set it to 0 before hibernate to avoid this
	589	* wakeup event.
	590	*/
	591	gpio_set_value(musb->config->gpio_vrsel, 0);
	592
	593	return 0;
	594	}
	595
	596	static int bfin_resume(struct device *dev)
	597	{
	598	struct bfin_glue *glue = dev_get_drvdata(dev);
	599	struct musb *musb = glue_to_musb(glue);
	600
	601	bfin_musb_reg_init(musb);
	602
	603	return 0;
	604	}
fcd22e3b FB	605	#endif
fcd22e3b FB	606
0967313b DM	607	static SIMPLE_DEV_PM_OPS(bfin_pm_ops, bfin_suspend, bfin_resume);
0967313b DM	608
9cb0308e	609	static struct platform_driver bfin_driver = {
e9e8c85e	610	.probe = bfin_probe,
d9b2b19f	611	.remove = bfin_remove,
9cb0308e	612	.driver = {
417ddf86	613	.name = "musb-blackfin",
0967313b	614	.pm = &bfin_pm_ops,
9cb0308e FB	615	},
	616	};
	617
	618	MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
	619	MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
	620	MODULE_LICENSE("GPL v2");
692373e1	621	module_platform_driver(bfin_driver);