[deliverable/linux.git] / drivers / usb / musb / blackfin.c

/*
 * MUSB OTG controller driver for Blackfin Processors
 *
 * Copyright 2006-2008 Analog Devices Inc.
 *
 * Enter bugs at http://blackfin.uclinux.org/
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/prefetch.h>

#include <asm/cacheflush.h>

#include "musb_core.h"
#include "musbhsdma.h"
#include "blackfin.h"

struct bfin_glue {
	struct device		*dev;
	struct platform_device	*musb;
};
#define glue_to_musb(g)		platform_get_drvdata(g->musb)

/*
 * Load an endpoint's FIFO
 */
void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
{
	struct musb *musb = hw_ep->musb;
	void __iomem *fifo = hw_ep->fifo;
	void __iomem *epio = hw_ep->regs;
	u8 epnum = hw_ep->epnum;

	prefetch((u8 *)src);

	musb_writew(epio, MUSB_TXCOUNT, len);

	dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
			hw_ep->epnum, fifo, len, src, epio);

	dump_fifo_data(src, len);

	if (!ANOMALY_05000380 && epnum != 0) {
		u16 dma_reg;

		flush_dcache_range((unsigned long)src,
			(unsigned long)(src + len));

		/* Setup DMA address register */
		dma_reg = (u32)src;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
		SSYNC();

		dma_reg = (u32)src >> 16;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
		SSYNC();

		/* Setup DMA count register */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
		SSYNC();

		/* Enable the DMA */
		dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
		SSYNC();

		/* Wait for compelete */
		while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
			cpu_relax();

		/* acknowledge dma interrupt */
		bfin_write_USB_DMA_INTERRUPT(1 << epnum);
		SSYNC();

		/* Reset DMA */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
		SSYNC();
	} else {
		SSYNC();

		if (unlikely((unsigned long)src & 0x01))
			outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
		else
			outsw((unsigned long)fifo, src, (len + 1) >> 1);
	}
}
/*
 * Unload an endpoint's FIFO
 */
void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
{
	struct musb *musb = hw_ep->musb;
	void __iomem *fifo = hw_ep->fifo;
	u8 epnum = hw_ep->epnum;

	if (ANOMALY_05000467 && epnum != 0) {
		u16 dma_reg;

		invalidate_dcache_range((unsigned long)dst,
			(unsigned long)(dst + len));

		/* Setup DMA address register */
		dma_reg = (u32)dst;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
		SSYNC();

		dma_reg = (u32)dst >> 16;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
		SSYNC();

		/* Setup DMA count register */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
		SSYNC();

		/* Enable the DMA */
		dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
		SSYNC();

		/* Wait for compelete */
		while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
			cpu_relax();

		/* acknowledge dma interrupt */
		bfin_write_USB_DMA_INTERRUPT(1 << epnum);
		SSYNC();

		/* Reset DMA */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
		SSYNC();
	} else {
		SSYNC();
		/* Read the last byte of packet with odd size from address fifo + 4
		 * to trigger 1 byte access to EP0 FIFO.
		 */
		if (len == 1)
			*dst = (u8)inw((unsigned long)fifo + 4);
		else {
			if (unlikely((unsigned long)dst & 0x01))
				insw_8((unsigned long)fifo, dst, len >> 1);
			else
				insw((unsigned long)fifo, dst, len >> 1);

			if (len & 0x01)
				*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
		}
	}
	dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
			'R', hw_ep->epnum, fifo, len, dst);

	dump_fifo_data(dst, len);
}

static irqreturn_t blackfin_interrupt(int irq, void *__hci)
{
	unsigned long	flags;
	irqreturn_t	retval = IRQ_NONE;
	struct musb	*musb = __hci;

	spin_lock_irqsave(&musb->lock, flags);

	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);

	if (musb->int_usb || musb->int_tx || musb->int_rx) {
		musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
		musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
		musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
		retval = musb_interrupt(musb);
	}

	/* Start sampling ID pin, when plug is removed from MUSB */
	if ((is_otg_enabled(musb) && (musb->xceiv->state == OTG_STATE_B_IDLE
		|| musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) ||
		(musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
		musb->a_wait_bcon = TIMER_DELAY;
	}

	spin_unlock_irqrestore(&musb->lock, flags);

	return retval;
}

static void musb_conn_timer_handler(unsigned long _musb)
{
	struct musb *musb = (void *)_musb;
	unsigned long flags;
	u16 val;
	static u8 toggle;

	spin_lock_irqsave(&musb->lock, flags);
	switch (musb->xceiv->state) {
	case OTG_STATE_A_IDLE:
	case OTG_STATE_A_WAIT_BCON:
		/* Start a new session */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);
		val &= ~MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);
		val |= MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);
		/* Check if musb is host or peripheral. */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);

		if (!(val & MUSB_DEVCTL_BDEVICE)) {
			gpio_set_value(musb->config->gpio_vrsel, 1);
			musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
		} else {
			gpio_set_value(musb->config->gpio_vrsel, 0);
			/* Ignore VBUSERROR and SUSPEND IRQ */
			val = musb_readb(musb->mregs, MUSB_INTRUSBE);
			val &= ~MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSBE, val);

			val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSB, val);
			if (is_otg_enabled(musb))
				musb->xceiv->state = OTG_STATE_B_IDLE;
			else
				musb_writeb(musb->mregs, MUSB_POWER, MUSB_POWER_HSENAB);
		}
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
		break;
	case OTG_STATE_B_IDLE:

		if (!is_peripheral_enabled(musb))
			break;
		/* Start a new session.  It seems that MUSB needs taking
		 * some time to recognize the type of the plug inserted?
		 */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);
		val |= MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);
		val = musb_readw(musb->mregs, MUSB_DEVCTL);

		if (!(val & MUSB_DEVCTL_BDEVICE)) {
			gpio_set_value(musb->config->gpio_vrsel, 1);
			musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
		} else {
			gpio_set_value(musb->config->gpio_vrsel, 0);

			/* Ignore VBUSERROR and SUSPEND IRQ */
			val = musb_readb(musb->mregs, MUSB_INTRUSBE);
			val &= ~MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSBE, val);

			val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSB, val);

			/* Toggle the Soft Conn bit, so that we can response to
			 * the inserting of either A-plug or B-plug.
			 */
			if (toggle) {
				val = musb_readb(musb->mregs, MUSB_POWER);
				val &= ~MUSB_POWER_SOFTCONN;
				musb_writeb(musb->mregs, MUSB_POWER, val);
				toggle = 0;
			} else {
				val = musb_readb(musb->mregs, MUSB_POWER);
				val |= MUSB_POWER_SOFTCONN;
				musb_writeb(musb->mregs, MUSB_POWER, val);
				toggle = 1;
			}
			/* The delay time is set to 1/4 second by default,
			 * shortening it, if accelerating A-plug detection
			 * is needed in OTG mode.
			 */
			mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
		}
		break;
	default:
		dev_dbg(musb->controller, "%s state not handled\n",
			otg_state_string(musb->xceiv->state));
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);

	dev_dbg(musb->controller, "state is %s\n",
		otg_state_string(musb->xceiv->state));
}

static void bfin_musb_enable(struct musb *musb)
{
	if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
		musb->a_wait_bcon = TIMER_DELAY;
	}
}

static void bfin_musb_disable(struct musb *musb)
{
}

static void bfin_musb_set_vbus(struct musb *musb, int is_on)
{
	int value = musb->config->gpio_vrsel_active;
	if (!is_on)
		value = !value;
	gpio_set_value(musb->config->gpio_vrsel, value);

	dev_dbg(musb->controller, "VBUS %s, devctl %02x "
		/* otg %3x conf %08x prcm %08x */ "\n",
		otg_state_string(musb->xceiv->state),
		musb_readb(musb->mregs, MUSB_DEVCTL));
}

static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)
{
	return 0;
}

static void bfin_musb_try_idle(struct musb *musb, unsigned long timeout)
{
	if (!is_otg_enabled(musb) && is_host_enabled(musb))
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
}

static int bfin_musb_vbus_status(struct musb *musb)
{
	return 0;
}

static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
{
	return -EIO;
}

static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
				u16 packet_sz, u8 *mode,
				dma_addr_t *dma_addr, u32 *len)
{
	struct musb_dma_channel *musb_channel = channel->private_data;

	/*
	 * Anomaly 05000450 might cause data corruption when using DMA
	 * MODE 1 transmits with short packet.  So to work around this,
	 * we truncate all MODE 1 transfers down to a multiple of the
	 * max packet size, and then do the last short packet transfer
	 * (if there is any) using MODE 0.
	 */
	if (ANOMALY_05000450) {
		if (musb_channel->transmit && *mode == 1)
			*len = *len - (*len % packet_sz);
	}

	return 0;
}

static void bfin_musb_reg_init(struct musb *musb)
{
	if (ANOMALY_05000346) {
		bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
		SSYNC();
	}

	if (ANOMALY_05000347) {
		bfin_write_USB_APHY_CNTRL(0x0);
		SSYNC();
	}

	/* Configure PLL oscillator register */
	bfin_write_USB_PLLOSC_CTRL(0x3080 |
			((480/musb->config->clkin) << 1));
	SSYNC();

	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
	SSYNC();

	bfin_write_USB_EP_NI0_RXMAXP(64);
	SSYNC();

	bfin_write_USB_EP_NI0_TXMAXP(64);
	SSYNC();

	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
	bfin_write_USB_GLOBINTR(0x7);
	SSYNC();

	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
				EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
				EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
				EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
				EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
	SSYNC();
}

static int bfin_musb_init(struct musb *musb)
{

	/*
	 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
	 * and OTG HOST modes, while rev 1.1 and greater require PE7 to
	 * be low for DEVICE mode and high for HOST mode. We set it high
	 * here because we are in host mode
	 */

	if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
		printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
			musb->config->gpio_vrsel);
		return -ENODEV;
	}
	gpio_direction_output(musb->config->gpio_vrsel, 0);

	usb_nop_xceiv_register();
	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
	if (IS_ERR_OR_NULL(musb->xceiv)) {
		gpio_free(musb->config->gpio_vrsel);
		return -ENODEV;
	}

	bfin_musb_reg_init(musb);

	if (is_host_enabled(musb)) {
		setup_timer(&musb_conn_timer,
			musb_conn_timer_handler, (unsigned long) musb);
	}
	if (is_peripheral_enabled(musb))
		musb->xceiv->set_power = bfin_musb_set_power;

	musb->isr = blackfin_interrupt;
	musb->double_buffer_not_ok = true;

	return 0;
}

static int bfin_musb_exit(struct musb *musb)
{
	gpio_free(musb->config->gpio_vrsel);

	usb_put_phy(musb->xceiv);
	usb_nop_xceiv_unregister();
	return 0;
}

static const struct musb_platform_ops bfin_ops = {
	.init		= bfin_musb_init,
	.exit		= bfin_musb_exit,

	.enable		= bfin_musb_enable,
	.disable	= bfin_musb_disable,

	.set_mode	= bfin_musb_set_mode,
	.try_idle	= bfin_musb_try_idle,

	.vbus_status	= bfin_musb_vbus_status,
	.set_vbus	= bfin_musb_set_vbus,

	.adjust_channel_params = bfin_musb_adjust_channel_params,
};

static u64 bfin_dmamask = DMA_BIT_MASK(32);

static int __devinit bfin_probe(struct platform_device *pdev)
{
	struct musb_hdrc_platform_data	*pdata = pdev->dev.platform_data;
	struct platform_device		*musb;
	struct bfin_glue		*glue;

	int				ret = -ENOMEM;

	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
	if (!glue) {
		dev_err(&pdev->dev, "failed to allocate glue context\n");
		goto err0;
	}

	musb = platform_device_alloc("musb-hdrc", -1);
	if (!musb) {
		dev_err(&pdev->dev, "failed to allocate musb device\n");
		goto err1;
	}

	musb->dev.parent		= &pdev->dev;
	musb->dev.dma_mask		= &bfin_dmamask;
	musb->dev.coherent_dma_mask	= bfin_dmamask;

	glue->dev			= &pdev->dev;
	glue->musb			= musb;

	pdata->platform_ops		= &bfin_ops;

	platform_set_drvdata(pdev, glue);

	ret = platform_device_add_resources(musb, pdev->resource,
			pdev->num_resources);
	if (ret) {
		dev_err(&pdev->dev, "failed to add resources\n");
		goto err2;
	}

	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	if (ret) {
		dev_err(&pdev->dev, "failed to add platform_data\n");
		goto err2;
	}

	ret = platform_device_add(musb);
	if (ret) {
		dev_err(&pdev->dev, "failed to register musb device\n");
		goto err2;
	}

	return 0;

err2:
	platform_device_put(musb);

err1:
	kfree(glue);

err0:
	return ret;
}

static int __devexit bfin_remove(struct platform_device *pdev)
{
	struct bfin_glue		*glue = platform_get_drvdata(pdev);

	platform_device_del(glue->musb);
	platform_device_put(glue->musb);
	kfree(glue);

	return 0;
}

#ifdef CONFIG_PM
static int bfin_suspend(struct device *dev)
{
	struct bfin_glue	*glue = dev_get_drvdata(dev);
	struct musb		*musb = glue_to_musb(glue);

	if (is_host_active(musb))
		/*
		 * During hibernate gpio_vrsel will change from high to low
		 * low which will generate wakeup event resume the system
		 * immediately.  Set it to 0 before hibernate to avoid this
		 * wakeup event.
		 */
		gpio_set_value(musb->config->gpio_vrsel, 0);

	return 0;
}

static int bfin_resume(struct device *dev)
{
	struct bfin_glue	*glue = dev_get_drvdata(dev);
	struct musb		*musb = glue_to_musb(glue);

	bfin_musb_reg_init(musb);

	return 0;
}

static struct dev_pm_ops bfin_pm_ops = {
	.suspend	= bfin_suspend,
	.resume		= bfin_resume,
};

#define DEV_PM_OPS	&bfin_pm_ops
#else
#define DEV_PM_OPS	NULL
#endif

static struct platform_driver bfin_driver = {
	.probe		= bfin_probe,
	.remove		= __exit_p(bfin_remove),
	.driver		= {
		.name	= "musb-blackfin",
		.pm	= DEV_PM_OPS,
	},
};

MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
MODULE_LICENSE("GPL v2");

static int __init bfin_init(void)
{
	return platform_driver_register(&bfin_driver);
}
module_init(bfin_init);

static void __exit bfin_exit(void)
{
	platform_driver_unregister(&bfin_driver);
}
module_exit(bfin_exit);
Commit	Line	Data
0c6a8818 BW	1	/*
	2	* MUSB OTG controller driver for Blackfin Processors
	3	*
	4	* Copyright 2006-2008 Analog Devices Inc.
	5	*
	6	* Enter bugs at http://blackfin.uclinux.org/
	7	*
	8	* Licensed under the GPL-2 or later.
	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/kernel.h>
	13	#include <linux/sched.h>
0c6a8818 BW	14	#include <linux/init.h>
0c6a8818 BW	15	#include <linux/list.h>
0c6a8818 BW	16	#include <linux/gpio.h>
0c6a8818 BW	17	#include <linux/io.h>
ded017ee	18	#include <linux/err.h>
9cb0308e FB	19	#include <linux/platform_device.h>
9cb0308e FB	20	#include <linux/dma-mapping.h>
ad50c1b2	21	#include <linux/prefetch.h>
0c6a8818 BW	22
	23	#include <asm/cacheflush.h>
	24
	25	#include "musb_core.h"
13254307	26	#include "musbhsdma.h"
0c6a8818 BW	27	#include "blackfin.h"
0c6a8818 BW	28
a023c631 FB	29	struct bfin_glue {
	30	struct device *dev;
	31	struct platform_device *musb;
	32	};
fcd22e3b	33	#define glue_to_musb(g) platform_get_drvdata(g->musb)
a023c631	34
0c6a8818 BW	35	/*
	36	* Load an endpoint's FIFO
	37	*/
	38	void musb_write_fifo(struct musb_hw_ep hw_ep, u16 len, const u8 src)
	39	{
28e49705	40	struct musb *musb = hw_ep->musb;
0c6a8818 BW	41	void __iomem *fifo = hw_ep->fifo;
0c6a8818 BW	42	void __iomem *epio = hw_ep->regs;
1c4bdc01	43	u8 epnum = hw_ep->epnum;
0c6a8818 BW	44
	45	prefetch((u8 *)src);
	46
	47	musb_writew(epio, MUSB_TXCOUNT, len);
	48
5c8a86e1	49	dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
0c6a8818 BW	50	hw_ep->epnum, fifo, len, src, epio);
	51
	52	dump_fifo_data(src, len);
	53
1c4bdc01	54	if (!ANOMALY_05000380 && epnum != 0) {
1ca9e9ca BW	55	u16 dma_reg;
	56
	57	flush_dcache_range((unsigned long)src,
	58	(unsigned long)(src + len));
1c4bdc01 BW	59
1c4bdc01 BW	60	/* Setup DMA address register */
1ca9e9ca	61	dma_reg = (u32)src;
1c4bdc01 BW	62	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
	63	SSYNC();
	64
1ca9e9ca	65	dma_reg = (u32)src >> 16;
1c4bdc01 BW	66	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
	67	SSYNC();
	68
	69	/* Setup DMA count register */
	70	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
	71	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
	72	SSYNC();
	73
	74	/* Enable the DMA */
	75	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA \| DIRECTION;
	76	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
	77	SSYNC();
	78
	79	/* Wait for compelete */
	80	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
	81	cpu_relax();
	82
	83	/* acknowledge dma interrupt */
	84	bfin_write_USB_DMA_INTERRUPT(1 << epnum);
	85	SSYNC();
	86
	87	/* Reset DMA */
	88	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
	89	SSYNC();
	90	} else {
	91	SSYNC();
	92
	93	if (unlikely((unsigned long)src & 0x01))
1ca9e9ca	94	outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
1c4bdc01	95	else
1ca9e9ca	96	outsw((unsigned long)fifo, src, (len + 1) >> 1);
1c4bdc01	97	}
0c6a8818	98	}
0c6a8818 BW	99	/*
	100	* Unload an endpoint's FIFO
	101	*/
	102	void musb_read_fifo(struct musb_hw_ep hw_ep, u16 len, u8 dst)
	103	{
28e49705	104	struct musb *musb = hw_ep->musb;
0c6a8818 BW	105	void __iomem *fifo = hw_ep->fifo;
0c6a8818 BW	106	u8 epnum = hw_ep->epnum;
0c6a8818	107
1c4bdc01	108	if (ANOMALY_05000467 && epnum != 0) {
1ca9e9ca	109	u16 dma_reg;
1c4bdc01	110
1ca9e9ca BW	111	invalidate_dcache_range((unsigned long)dst,
1ca9e9ca BW	112	(unsigned long)(dst + len));
1c4bdc01 BW	113
1c4bdc01 BW	114	/* Setup DMA address register */
1ca9e9ca	115	dma_reg = (u32)dst;
1c4bdc01 BW	116	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
	117	SSYNC();
	118
1ca9e9ca	119	dma_reg = (u32)dst >> 16;
1c4bdc01 BW	120	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
	121	SSYNC();
	122
	123	/* Setup DMA count register */
	124	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
	125	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
	126	SSYNC();
	127
	128	/* Enable the DMA */
	129	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA;
	130	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
	131	SSYNC();
	132
	133	/* Wait for compelete */
	134	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
	135	cpu_relax();
	136
	137	/* acknowledge dma interrupt */
	138	bfin_write_USB_DMA_INTERRUPT(1 << epnum);
	139	SSYNC();
	140
	141	/* Reset DMA */
	142	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
	143	SSYNC();
	144	} else {
	145	SSYNC();
	146	/* Read the last byte of packet with odd size from address fifo + 4
	147	* to trigger 1 byte access to EP0 FIFO.
	148	*/
	149	if (len == 1)
	150	*dst = (u8)inw((unsigned long)fifo + 4);
	151	else {
	152	if (unlikely((unsigned long)dst & 0x01))
	153	insw_8((unsigned long)fifo, dst, len >> 1);
	154	else
	155	insw((unsigned long)fifo, dst, len >> 1);
	156
	157	if (len & 0x01)
	158	*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
	159	}
	160	}
5c8a86e1	161	dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
04f4086f MF	162	'R', hw_ep->epnum, fifo, len, dst);
04f4086f MF	163
0c6a8818 BW	164	dump_fifo_data(dst, len);
	165	}
	166
	167	static irqreturn_t blackfin_interrupt(int irq, void *__hci)
	168	{
	169	unsigned long flags;
	170	irqreturn_t retval = IRQ_NONE;
	171	struct musb *musb = __hci;
	172
	173	spin_lock_irqsave(&musb->lock, flags);
	174
	175	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
	176	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
	177	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
	178
	179	if (musb->int_usb \|\| musb->int_tx \|\| musb->int_rx) {
	180	musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
	181	musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
	182	musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
	183	retval = musb_interrupt(musb);
	184	}
	185
ff927add	186	/* Start sampling ID pin, when plug is removed from MUSB */
68f64714 BL	187	if ((is_otg_enabled(musb) && (musb->xceiv->state == OTG_STATE_B_IDLE
	188	\|\| musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) \|\|
	189	(musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
ff927add CC	190	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	191	musb->a_wait_bcon = TIMER_DELAY;
	192	}
	193
0c6a8818 BW	194	spin_unlock_irqrestore(&musb->lock, flags);
0c6a8818 BW	195
2f831751	196	return retval;
0c6a8818 BW	197	}
	198
	199	static void musb_conn_timer_handler(unsigned long _musb)
	200	{
	201	struct musb musb = (void )_musb;
	202	unsigned long flags;
	203	u16 val;
ff927add	204	static u8 toggle;
0c6a8818 BW	205
0c6a8818 BW	206	spin_lock_irqsave(&musb->lock, flags);
84e250ff	207	switch (musb->xceiv->state) {
0c6a8818 BW	208	case OTG_STATE_A_IDLE:
	209	case OTG_STATE_A_WAIT_BCON:
	210	/* Start a new session */
	211	val = musb_readw(musb->mregs, MUSB_DEVCTL);
ff927add CC	212	val &= ~MUSB_DEVCTL_SESSION;
ff927add CC	213	musb_writew(musb->mregs, MUSB_DEVCTL, val);
0c6a8818 BW	214	val \|= MUSB_DEVCTL_SESSION;
0c6a8818 BW	215	musb_writew(musb->mregs, MUSB_DEVCTL, val);
ff927add CC	216	/* Check if musb is host or peripheral. */
	217	val = musb_readw(musb->mregs, MUSB_DEVCTL);
	218
	219	if (!(val & MUSB_DEVCTL_BDEVICE)) {
	220	gpio_set_value(musb->config->gpio_vrsel, 1);
	221	musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
	222	} else {
	223	gpio_set_value(musb->config->gpio_vrsel, 0);
	224	/* Ignore VBUSERROR and SUSPEND IRQ */
	225	val = musb_readb(musb->mregs, MUSB_INTRUSBE);
	226	val &= ~MUSB_INTR_VBUSERROR;
	227	musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
	228
	229	val = MUSB_INTR_SUSPEND \| MUSB_INTR_VBUSERROR;
	230	musb_writeb(musb->mregs, MUSB_INTRUSB, val);
	231	if (is_otg_enabled(musb))
	232	musb->xceiv->state = OTG_STATE_B_IDLE;
	233	else
	234	musb_writeb(musb->mregs, MUSB_POWER, MUSB_POWER_HSENAB);
	235	}
	236	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	237	break;
	238	case OTG_STATE_B_IDLE:
0c6a8818	239
ff927add CC	240	if (!is_peripheral_enabled(musb))
	241	break;
	242	/* Start a new session. It seems that MUSB needs taking
	243	* some time to recognize the type of the plug inserted?
	244	*/
	245	val = musb_readw(musb->mregs, MUSB_DEVCTL);
	246	val \|= MUSB_DEVCTL_SESSION;
	247	musb_writew(musb->mregs, MUSB_DEVCTL, val);
0c6a8818	248	val = musb_readw(musb->mregs, MUSB_DEVCTL);
ff927add	249
0c6a8818 BW	250	if (!(val & MUSB_DEVCTL_BDEVICE)) {
0c6a8818 BW	251	gpio_set_value(musb->config->gpio_vrsel, 1);
84e250ff	252	musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
0c6a8818 BW	253	} else {
	254	gpio_set_value(musb->config->gpio_vrsel, 0);
	255
	256	/* Ignore VBUSERROR and SUSPEND IRQ */
	257	val = musb_readb(musb->mregs, MUSB_INTRUSBE);
	258	val &= ~MUSB_INTR_VBUSERROR;
	259	musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
	260
	261	val = MUSB_INTR_SUSPEND \| MUSB_INTR_VBUSERROR;
	262	musb_writeb(musb->mregs, MUSB_INTRUSB, val);
	263
ff927add CC	264	/* Toggle the Soft Conn bit, so that we can response to
	265	* the inserting of either A-plug or B-plug.
	266	*/
	267	if (toggle) {
	268	val = musb_readb(musb->mregs, MUSB_POWER);
	269	val &= ~MUSB_POWER_SOFTCONN;
	270	musb_writeb(musb->mregs, MUSB_POWER, val);
	271	toggle = 0;
	272	} else {
	273	val = musb_readb(musb->mregs, MUSB_POWER);
	274	val \|= MUSB_POWER_SOFTCONN;
	275	musb_writeb(musb->mregs, MUSB_POWER, val);
	276	toggle = 1;
	277	}
	278	/* The delay time is set to 1/4 second by default,
	279	* shortening it, if accelerating A-plug detection
	280	* is needed in OTG mode.
	281	*/
	282	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
0c6a8818	283	}
0c6a8818	284	break;
0c6a8818	285	default:
5c8a86e1	286	dev_dbg(musb->controller, "%s state not handled\n",
3df00453	287	otg_state_string(musb->xceiv->state));
0c6a8818 BW	288	break;
	289	}
	290	spin_unlock_irqrestore(&musb->lock, flags);
	291
5c8a86e1 FB	292	dev_dbg(musb->controller, "state is %s\n",
5c8a86e1 FB	293	otg_state_string(musb->xceiv->state));
0c6a8818 BW	294	}
0c6a8818 BW	295
743411b3	296	static void bfin_musb_enable(struct musb *musb)
0c6a8818	297	{
ff927add	298	if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
0c6a8818 BW	299	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	300	musb->a_wait_bcon = TIMER_DELAY;
	301	}
	302	}
	303
743411b3	304	static void bfin_musb_disable(struct musb *musb)
0c6a8818 BW	305	{
	306	}
	307
743411b3	308	static void bfin_musb_set_vbus(struct musb *musb, int is_on)
0c6a8818	309	{
6ddc6dae CC	310	int value = musb->config->gpio_vrsel_active;
	311	if (!is_on)
	312	value = !value;
	313	gpio_set_value(musb->config->gpio_vrsel, value);
0c6a8818	314
5c8a86e1	315	dev_dbg(musb->controller, "VBUS %s, devctl %02x "
0c6a8818	316	/* otg %3x conf %08x prcm %08x */ "\n",
3df00453	317	otg_state_string(musb->xceiv->state),
0c6a8818 BW	318	musb_readb(musb->mregs, MUSB_DEVCTL));
	319	}
	320
86753811	321	static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)
0c6a8818 BW	322	{
	323	return 0;
	324	}
	325
743411b3	326	static void bfin_musb_try_idle(struct musb *musb, unsigned long timeout)
0c6a8818	327	{
ff927add	328	if (!is_otg_enabled(musb) && is_host_enabled(musb))
0c6a8818 BW	329	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	330	}
	331
45567c28	332	static int bfin_musb_vbus_status(struct musb *musb)
0c6a8818 BW	333	{
	334	return 0;
	335	}
	336
743411b3	337	static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
0c6a8818	338	{
2002e768	339	return -EIO;
0c6a8818 BW	340	}
0c6a8818 BW	341
13254307 MF	342	static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
	343	u16 packet_sz, u8 *mode,
	344	dma_addr_t dma_addr, u32 len)
	345	{
	346	struct musb_dma_channel *musb_channel = channel->private_data;
	347
	348	/*
	349	* Anomaly 05000450 might cause data corruption when using DMA
	350	* MODE 1 transmits with short packet. So to work around this,
	351	* we truncate all MODE 1 transfers down to a multiple of the
	352	* max packet size, and then do the last short packet transfer
	353	* (if there is any) using MODE 0.
	354	*/
	355	if (ANOMALY_05000450) {
	356	if (musb_channel->transmit && *mode == 1)
	357	len = len - (*len % packet_sz);
	358	}
	359
	360	return 0;
	361	}
	362
743411b3	363	static void bfin_musb_reg_init(struct musb *musb)
0c6a8818	364	{
d426e60d RG	365	if (ANOMALY_05000346) {
	366	bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
	367	SSYNC();
	368	}
0c6a8818	369
d426e60d RG	370	if (ANOMALY_05000347) {
	371	bfin_write_USB_APHY_CNTRL(0x0);
	372	SSYNC();
	373	}
0c6a8818	374
0c6a8818	375	/* Configure PLL oscillator register */
9c756462 BL	376	bfin_write_USB_PLLOSC_CTRL(0x3080 \|
9c756462 BL	377	((480/musb->config->clkin) << 1));
0c6a8818 BW	378	SSYNC();
	379
	380	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
	381	SSYNC();
	382
	383	bfin_write_USB_EP_NI0_RXMAXP(64);
	384	SSYNC();
	385
	386	bfin_write_USB_EP_NI0_TXMAXP(64);
	387	SSYNC();
	388
	389	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
	390	bfin_write_USB_GLOBINTR(0x7);
	391	SSYNC();
	392
	393	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA \| EP1_TX_ENA \| EP2_TX_ENA \|
	394	EP3_TX_ENA \| EP4_TX_ENA \| EP5_TX_ENA \|
	395	EP6_TX_ENA \| EP7_TX_ENA \| EP1_RX_ENA \|
	396	EP2_RX_ENA \| EP3_RX_ENA \| EP4_RX_ENA \|
	397	EP5_RX_ENA \| EP6_RX_ENA \| EP7_RX_ENA);
	398	SSYNC();
743411b3 FB	399	}
	400
	401	static int bfin_musb_init(struct musb *musb)
	402	{
	403
	404	/*
	405	* Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
	406	* and OTG HOST modes, while rev 1.1 and greater require PE7 to
	407	* be low for DEVICE mode and high for HOST mode. We set it high
	408	* here because we are in host mode
	409	*/
	410
	411	if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
	412	printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
	413	musb->config->gpio_vrsel);
	414	return -ENODEV;
	415	}
	416	gpio_direction_output(musb->config->gpio_vrsel, 0);
	417
	418	usb_nop_xceiv_register();
662dca54	419	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
ded017ee	420	if (IS_ERR_OR_NULL(musb->xceiv)) {
743411b3 FB	421	gpio_free(musb->config->gpio_vrsel);
	422	return -ENODEV;
	423	}
	424
	425	bfin_musb_reg_init(musb);
0c6a8818 BW	426
0c6a8818 BW	427	if (is_host_enabled(musb)) {
0c6a8818 BW	428	setup_timer(&musb_conn_timer,
	429	musb_conn_timer_handler, (unsigned long) musb);
	430	}
	431	if (is_peripheral_enabled(musb))
743411b3	432	musb->xceiv->set_power = bfin_musb_set_power;
0c6a8818 BW	433
0c6a8818 BW	434	musb->isr = blackfin_interrupt;
06624818	435	musb->double_buffer_not_ok = true;
0c6a8818 BW	436
	437	return 0;
	438	}
	439
743411b3	440	static int bfin_musb_exit(struct musb *musb)
0c6a8818	441	{
0c6a8818	442	gpio_free(musb->config->gpio_vrsel);
0c6a8818	443
721002ec	444	usb_put_phy(musb->xceiv);
3daad24d	445	usb_nop_xceiv_unregister();
0c6a8818 BW	446	return 0;
0c6a8818 BW	447	}
743411b3	448
f7ec9437	449	static const struct musb_platform_ops bfin_ops = {
743411b3 FB	450	.init = bfin_musb_init,
	451	.exit = bfin_musb_exit,
	452
	453	.enable = bfin_musb_enable,
	454	.disable = bfin_musb_disable,
	455
	456	.set_mode = bfin_musb_set_mode,
	457	.try_idle = bfin_musb_try_idle,
	458
	459	.vbus_status = bfin_musb_vbus_status,
	460	.set_vbus = bfin_musb_set_vbus,
13254307 MF	461
13254307 MF	462	.adjust_channel_params = bfin_musb_adjust_channel_params,
743411b3	463	};
9cb0308e FB	464
	465	static u64 bfin_dmamask = DMA_BIT_MASK(32);
	466
e9e8c85e	467	static int __devinit bfin_probe(struct platform_device *pdev)
9cb0308e FB	468	{
	469	struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
	470	struct platform_device *musb;
a023c631	471	struct bfin_glue *glue;
9cb0308e FB	472
	473	int ret = -ENOMEM;
	474
a023c631 FB	475	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
	476	if (!glue) {
	477	dev_err(&pdev->dev, "failed to allocate glue context\n");
	478	goto err0;
	479	}
	480
9cb0308e FB	481	musb = platform_device_alloc("musb-hdrc", -1);
	482	if (!musb) {
	483	dev_err(&pdev->dev, "failed to allocate musb device\n");
a023c631	484	goto err1;
9cb0308e FB	485	}
	486
	487	musb->dev.parent = &pdev->dev;
	488	musb->dev.dma_mask = &bfin_dmamask;
	489	musb->dev.coherent_dma_mask = bfin_dmamask;
	490
a023c631 FB	491	glue->dev = &pdev->dev;
	492	glue->musb = musb;
	493
f7ec9437 FB	494	pdata->platform_ops = &bfin_ops;
f7ec9437 FB	495
a023c631	496	platform_set_drvdata(pdev, glue);
9cb0308e FB	497
	498	ret = platform_device_add_resources(musb, pdev->resource,
	499	pdev->num_resources);
	500	if (ret) {
	501	dev_err(&pdev->dev, "failed to add resources\n");
a023c631	502	goto err2;
9cb0308e FB	503	}
	504
	505	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	506	if (ret) {
	507	dev_err(&pdev->dev, "failed to add platform_data\n");
a023c631	508	goto err2;
9cb0308e FB	509	}
	510
	511	ret = platform_device_add(musb);
	512	if (ret) {
	513	dev_err(&pdev->dev, "failed to register musb device\n");
a023c631	514	goto err2;
9cb0308e FB	515	}
	516
	517	return 0;
	518
a023c631	519	err2:
9cb0308e FB	520	platform_device_put(musb);
9cb0308e FB	521
a023c631 FB	522	err1:
	523	kfree(glue);
	524
9cb0308e FB	525	err0:
	526	return ret;
	527	}
	528
e9e8c85e	529	static int __devexit bfin_remove(struct platform_device *pdev)
9cb0308e	530	{
a023c631	531	struct bfin_glue *glue = platform_get_drvdata(pdev);
9cb0308e	532
a023c631 FB	533	platform_device_del(glue->musb);
	534	platform_device_put(glue->musb);
	535	kfree(glue);
9cb0308e FB	536
	537	return 0;
	538	}
	539
fcd22e3b FB	540	#ifdef CONFIG_PM
	541	static int bfin_suspend(struct device *dev)
	542	{
	543	struct bfin_glue *glue = dev_get_drvdata(dev);
	544	struct musb *musb = glue_to_musb(glue);
	545
	546	if (is_host_active(musb))
	547	/*
	548	* During hibernate gpio_vrsel will change from high to low
	549	* low which will generate wakeup event resume the system
	550	* immediately. Set it to 0 before hibernate to avoid this
	551	* wakeup event.
	552	*/
	553	gpio_set_value(musb->config->gpio_vrsel, 0);
	554
	555	return 0;
	556	}
	557
	558	static int bfin_resume(struct device *dev)
	559	{
	560	struct bfin_glue *glue = dev_get_drvdata(dev);
	561	struct musb *musb = glue_to_musb(glue);
	562
	563	bfin_musb_reg_init(musb);
	564
	565	return 0;
	566	}
	567
	568	static struct dev_pm_ops bfin_pm_ops = {
	569	.suspend = bfin_suspend,
	570	.resume = bfin_resume,
	571	};
	572
8f7e7b87	573	#define DEV_PM_OPS &bfin_pm_ops
fcd22e3b FB	574	#else
	575	#define DEV_PM_OPS NULL
	576	#endif
	577
9cb0308e	578	static struct platform_driver bfin_driver = {
e9e8c85e	579	.probe = bfin_probe,
9cb0308e FB	580	.remove = __exit_p(bfin_remove),
9cb0308e FB	581	.driver = {
417ddf86	582	.name = "musb-blackfin",
fcd22e3b	583	.pm = DEV_PM_OPS,
9cb0308e FB	584	},
	585	};
	586
	587	MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
	588	MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
	589	MODULE_LICENSE("GPL v2");
	590
	591	static int __init bfin_init(void)
	592	{
e9e8c85e	593	return platform_driver_register(&bfin_driver);
9cb0308e	594	}
e9e8c85e	595	module_init(bfin_init);
9cb0308e FB	596
	597	static void __exit bfin_exit(void)
	598	{
	599	platform_driver_unregister(&bfin_driver);
	600	}
	601	module_exit(bfin_exit);