[deliverable/linux.git] / drivers / usb / musb / blackfin.c

/*
 * MUSB OTG controller driver for Blackfin Processors
 *
 * Copyright 2006-2008 Analog Devices Inc.
 *
 * Enter bugs at http://blackfin.uclinux.org/
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/io.h>

#include <asm/cacheflush.h>

#include "musb_core.h"
#include "blackfin.h"

/*
 * Load an endpoint's FIFO
 */
void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
{
	void __iomem *fifo = hw_ep->fifo;
	void __iomem *epio = hw_ep->regs;

	prefetch((u8 *)src);

	musb_writew(epio, MUSB_TXCOUNT, len);

	DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
			hw_ep->epnum, fifo, len, src, epio);

	dump_fifo_data(src, len);

	if (unlikely((unsigned long)src & 0x01))
		outsw_8((unsigned long)fifo, src,
			len & 0x01 ? (len >> 1) + 1 : len >> 1);
	else
		outsw((unsigned long)fifo, src,
			len & 0x01 ? (len >> 1) + 1 : len >> 1);
}

/*
 * Unload an endpoint's FIFO
 */
void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
{
	void __iomem *fifo = hw_ep->fifo;
	u8 epnum = hw_ep->epnum;
	u16 dma_reg = 0;

	DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
			'R', hw_ep->epnum, fifo, len, dst);

#ifdef CONFIG_BF52x
	invalidate_dcache_range((unsigned int)dst,
		(unsigned int)(dst + len));

	/* Setup DMA address register */
	dma_reg = (u16) ((u32) dst & 0xFFFF);
	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
	SSYNC();

	dma_reg = (u16) (((u32) dst >> 16) & 0xFFFF);
	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
	SSYNC();

	/* Setup DMA count register */
	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
	SSYNC();

	/* Enable the DMA */
	dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
	SSYNC();

	/* Wait for compelete */
	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
		cpu_relax();

	/* acknowledge dma interrupt */
	bfin_write_USB_DMA_INTERRUPT(1 << epnum);
	SSYNC();

	/* Reset DMA */
	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
	SSYNC();
#else
	if (unlikely((unsigned long)dst & 0x01))
		insw_8((unsigned long)fifo, dst,
			len & 0x01 ? (len >> 1) + 1 : len >> 1);
	else
		insw((unsigned long)fifo, dst,
			len & 0x01 ? (len >> 1) + 1 : len >> 1);
#endif

	dump_fifo_data(dst, len);
}

static irqreturn_t blackfin_interrupt(int irq, void *__hci)
{
	unsigned long	flags;
	irqreturn_t	retval = IRQ_NONE;
	struct musb	*musb = __hci;

	spin_lock_irqsave(&musb->lock, flags);

	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);

	if (musb->int_usb || musb->int_tx || musb->int_rx) {
		musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
		musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
		musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
		retval = musb_interrupt(musb);
	}

	spin_unlock_irqrestore(&musb->lock, flags);

	/* REVISIT we sometimes get spurious IRQs on g_ep0
	 * not clear why... fall in BF54x too.
	 */
	if (retval != IRQ_HANDLED)
		DBG(5, "spurious?\n");

	return IRQ_HANDLED;
}

static void musb_conn_timer_handler(unsigned long _musb)
{
	struct musb *musb = (void *)_musb;
	unsigned long flags;
	u16 val;

	spin_lock_irqsave(&musb->lock, flags);
	switch (musb->xceiv->state) {
	case OTG_STATE_A_IDLE:
	case OTG_STATE_A_WAIT_BCON:
		/* Start a new session */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);
		val |= MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);

		val = musb_readw(musb->mregs, MUSB_DEVCTL);
		if (!(val & MUSB_DEVCTL_BDEVICE)) {
			gpio_set_value(musb->config->gpio_vrsel, 1);
			musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
		} else {
			gpio_set_value(musb->config->gpio_vrsel, 0);

			/* Ignore VBUSERROR and SUSPEND IRQ */
			val = musb_readb(musb->mregs, MUSB_INTRUSBE);
			val &= ~MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSBE, val);

			val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSB, val);

			val = MUSB_POWER_HSENAB;
			musb_writeb(musb->mregs, MUSB_POWER, val);
		}
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
		break;

	default:
		DBG(1, "%s state not handled\n", otg_state_string(musb));
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);

	DBG(4, "state is %s\n", otg_state_string(musb));
}

void musb_platform_enable(struct musb *musb)
{
	if (is_host_enabled(musb)) {
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
		musb->a_wait_bcon = TIMER_DELAY;
	}
}

void musb_platform_disable(struct musb *musb)
{
}

static void bfin_vbus_power(struct musb *musb, int is_on, int sleeping)
{
}

static void bfin_set_vbus(struct musb *musb, int is_on)
{
	if (is_on)
		gpio_set_value(musb->config->gpio_vrsel, 1);
	else
		gpio_set_value(musb->config->gpio_vrsel, 0);

	DBG(1, "VBUS %s, devctl %02x "
		/* otg %3x conf %08x prcm %08x */ "\n",
		otg_state_string(musb),
		musb_readb(musb->mregs, MUSB_DEVCTL));
}

static int bfin_set_power(struct otg_transceiver *x, unsigned mA)
{
	return 0;
}

void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
{
	if (is_host_enabled(musb))
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
}

int musb_platform_get_vbus_status(struct musb *musb)
{
	return 0;
}

void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
{
}

int __init musb_platform_init(struct musb *musb)
{

	/*
	 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
	 * and OTG HOST modes, while rev 1.1 and greater require PE7 to
	 * be low for DEVICE mode and high for HOST mode. We set it high
	 * here because we are in host mode
	 */

	if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
		printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d \n",
			musb->config->gpio_vrsel);
		return -ENODEV;
	}
	gpio_direction_output(musb->config->gpio_vrsel, 0);

	usb_nop_xceiv_register();
	musb->xceiv = otg_get_transceiver();
	if (!musb->xceiv)
		return -ENODEV;

	if (ANOMALY_05000346) {
		bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
		SSYNC();
	}

	if (ANOMALY_05000347) {
		bfin_write_USB_APHY_CNTRL(0x0);
		SSYNC();
	}

	/* TODO
	 * Set SIC-IVG register
	 */

	/* Configure PLL oscillator register */
	bfin_write_USB_PLLOSC_CTRL(0x30a8);
	SSYNC();

	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
	SSYNC();

	bfin_write_USB_EP_NI0_RXMAXP(64);
	SSYNC();

	bfin_write_USB_EP_NI0_TXMAXP(64);
	SSYNC();

	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
	bfin_write_USB_GLOBINTR(0x7);
	SSYNC();

	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
				EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
				EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
				EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
				EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
	SSYNC();

	if (is_host_enabled(musb)) {
		musb->board_set_vbus = bfin_set_vbus;
		setup_timer(&musb_conn_timer,
			musb_conn_timer_handler, (unsigned long) musb);
	}
	if (is_peripheral_enabled(musb))
		musb->xceiv->set_power = bfin_set_power;

	musb->isr = blackfin_interrupt;

	return 0;
}

int musb_platform_suspend(struct musb *musb)
{
	return 0;
}

int musb_platform_resume(struct musb *musb)
{
	return 0;
}


int musb_platform_exit(struct musb *musb)
{

	bfin_vbus_power(musb, 0 /*off*/, 1);
	gpio_free(musb->config->gpio_vrsel);
	musb_platform_suspend(musb);

	return 0;
}
Commit	Line	Data
0c6a8818 BW	1	/*
	2	* MUSB OTG controller driver for Blackfin Processors
	3	*
	4	* Copyright 2006-2008 Analog Devices Inc.
	5	*
	6	* Enter bugs at http://blackfin.uclinux.org/
	7	*
	8	* Licensed under the GPL-2 or later.
	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/kernel.h>
	13	#include <linux/sched.h>
	14	#include <linux/slab.h>
	15	#include <linux/init.h>
	16	#include <linux/list.h>
	17	#include <linux/clk.h>
	18	#include <linux/gpio.h>
	19	#include <linux/io.h>
	20
	21	#include <asm/cacheflush.h>
	22
	23	#include "musb_core.h"
	24	#include "blackfin.h"
	25
	26	/*
	27	* Load an endpoint's FIFO
	28	*/
	29	void musb_write_fifo(struct musb_hw_ep hw_ep, u16 len, const u8 src)
	30	{
	31	void __iomem *fifo = hw_ep->fifo;
	32	void __iomem *epio = hw_ep->regs;
	33
	34	prefetch((u8 *)src);
	35
	36	musb_writew(epio, MUSB_TXCOUNT, len);
	37
	38	DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
	39	hw_ep->epnum, fifo, len, src, epio);
	40
	41	dump_fifo_data(src, len);
	42
	43	if (unlikely((unsigned long)src & 0x01))
e22b582e BW	44	outsw_8((unsigned long)fifo, src,
e22b582e BW	45	len & 0x01 ? (len >> 1) + 1 : len >> 1);
0c6a8818	46	else
e22b582e BW	47	outsw((unsigned long)fifo, src,
e22b582e BW	48	len & 0x01 ? (len >> 1) + 1 : len >> 1);
0c6a8818 BW	49	}
	50
	51	/*
	52	* Unload an endpoint's FIFO
	53	*/
	54	void musb_read_fifo(struct musb_hw_ep hw_ep, u16 len, u8 dst)
	55	{
	56	void __iomem *fifo = hw_ep->fifo;
	57	u8 epnum = hw_ep->epnum;
	58	u16 dma_reg = 0;
0c6a8818 BW	59
	60	DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
	61	'R', hw_ep->epnum, fifo, len, dst);
	62
	63	#ifdef CONFIG_BF52x
	64	invalidate_dcache_range((unsigned int)dst,
	65	(unsigned int)(dst + len));
	66
	67	/* Setup DMA address register */
	68	dma_reg = (u16) ((u32) dst & 0xFFFF);
	69	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
	70	SSYNC();
	71
	72	dma_reg = (u16) (((u32) dst >> 16) & 0xFFFF);
	73	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
	74	SSYNC();
	75
	76	/* Setup DMA count register */
	77	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
	78	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
	79	SSYNC();
	80
	81	/* Enable the DMA */
	82	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA;
	83	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
	84	SSYNC();
	85
	86	/* Wait for compelete */
	87	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
	88	cpu_relax();
	89
	90	/* acknowledge dma interrupt */
	91	bfin_write_USB_DMA_INTERRUPT(1 << epnum);
	92	SSYNC();
	93
	94	/* Reset DMA */
	95	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
	96	SSYNC();
	97	#else
	98	if (unlikely((unsigned long)dst & 0x01))
e22b582e BW	99	insw_8((unsigned long)fifo, dst,
e22b582e BW	100	len & 0x01 ? (len >> 1) + 1 : len >> 1);
0c6a8818	101	else
e22b582e BW	102	insw((unsigned long)fifo, dst,
e22b582e BW	103	len & 0x01 ? (len >> 1) + 1 : len >> 1);
0c6a8818 BW	104	#endif
	105
	106	dump_fifo_data(dst, len);
	107	}
	108
	109	static irqreturn_t blackfin_interrupt(int irq, void *__hci)
	110	{
	111	unsigned long flags;
	112	irqreturn_t retval = IRQ_NONE;
	113	struct musb *musb = __hci;
	114
	115	spin_lock_irqsave(&musb->lock, flags);
	116
	117	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
	118	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
	119	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
	120
	121	if (musb->int_usb \|\| musb->int_tx \|\| musb->int_rx) {
	122	musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
	123	musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
	124	musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
	125	retval = musb_interrupt(musb);
	126	}
	127
	128	spin_unlock_irqrestore(&musb->lock, flags);
	129
	130	/* REVISIT we sometimes get spurious IRQs on g_ep0
	131	* not clear why... fall in BF54x too.
	132	*/
	133	if (retval != IRQ_HANDLED)
	134	DBG(5, "spurious?\n");
	135
	136	return IRQ_HANDLED;
	137	}
	138
	139	static void musb_conn_timer_handler(unsigned long _musb)
	140	{
	141	struct musb musb = (void )_musb;
	142	unsigned long flags;
	143	u16 val;
	144
	145	spin_lock_irqsave(&musb->lock, flags);
84e250ff	146	switch (musb->xceiv->state) {
0c6a8818 BW	147	case OTG_STATE_A_IDLE:
	148	case OTG_STATE_A_WAIT_BCON:
	149	/* Start a new session */
	150	val = musb_readw(musb->mregs, MUSB_DEVCTL);
	151	val \|= MUSB_DEVCTL_SESSION;
	152	musb_writew(musb->mregs, MUSB_DEVCTL, val);
	153
	154	val = musb_readw(musb->mregs, MUSB_DEVCTL);
	155	if (!(val & MUSB_DEVCTL_BDEVICE)) {
	156	gpio_set_value(musb->config->gpio_vrsel, 1);
84e250ff	157	musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
0c6a8818 BW	158	} else {
	159	gpio_set_value(musb->config->gpio_vrsel, 0);
	160
	161	/* Ignore VBUSERROR and SUSPEND IRQ */
	162	val = musb_readb(musb->mregs, MUSB_INTRUSBE);
	163	val &= ~MUSB_INTR_VBUSERROR;
	164	musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
	165
	166	val = MUSB_INTR_SUSPEND \| MUSB_INTR_VBUSERROR;
	167	musb_writeb(musb->mregs, MUSB_INTRUSB, val);
	168
	169	val = MUSB_POWER_HSENAB;
	170	musb_writeb(musb->mregs, MUSB_POWER, val);
	171	}
	172	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	173	break;
	174
	175	default:
	176	DBG(1, "%s state not handled\n", otg_state_string(musb));
	177	break;
	178	}
	179	spin_unlock_irqrestore(&musb->lock, flags);
	180
	181	DBG(4, "state is %s\n", otg_state_string(musb));
	182	}
	183
	184	void musb_platform_enable(struct musb *musb)
	185	{
	186	if (is_host_enabled(musb)) {
	187	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	188	musb->a_wait_bcon = TIMER_DELAY;
	189	}
	190	}
	191
	192	void musb_platform_disable(struct musb *musb)
	193	{
	194	}
	195
	196	static void bfin_vbus_power(struct musb *musb, int is_on, int sleeping)
	197	{
	198	}
	199
	200	static void bfin_set_vbus(struct musb *musb, int is_on)
	201	{
	202	if (is_on)
	203	gpio_set_value(musb->config->gpio_vrsel, 1);
	204	else
	205	gpio_set_value(musb->config->gpio_vrsel, 0);
	206
	207	DBG(1, "VBUS %s, devctl %02x "
	208	/* otg %3x conf %08x prcm %08x */ "\n",
	209	otg_state_string(musb),
	210	musb_readb(musb->mregs, MUSB_DEVCTL));
	211	}
	212
	213	static int bfin_set_power(struct otg_transceiver *x, unsigned mA)
	214	{
	215	return 0;
	216	}
	217
	218	void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
	219	{
	220	if (is_host_enabled(musb))
	221	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
222	}
223
224	int musb_platform_get_vbus_status(struct musb *musb)
225	{
226	return 0;
227	}
228
229	void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
230	{
231	}
232
233	int __init musb_platform_init(struct musb *musb)
234	{
235
236	/*
237	* Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
238	* and OTG HOST modes, while rev 1.1 and greater require PE7 to
239	* be low for DEVICE mode and high for HOST mode. We set it high
240	* here because we are in host mode
241	*/
242
243	if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
244	printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d \n",
245	musb->config->gpio_vrsel);
246	return -ENODEV;
247	}
248	gpio_direction_output(musb->config->gpio_vrsel, 0);
249
84e250ff DB	250	usb_nop_xceiv_register();
	251	musb->xceiv = otg_get_transceiver();
	252	if (!musb->xceiv)
	253	return -ENODEV;
	254
d426e60d RG	255	if (ANOMALY_05000346) {
	256	bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
	257	SSYNC();
	258	}
0c6a8818	259
d426e60d RG	260	if (ANOMALY_05000347) {
	261	bfin_write_USB_APHY_CNTRL(0x0);
	262	SSYNC();
	263	}
0c6a8818 BW	264
	265	/* TODO
	266	* Set SIC-IVG register
	267	*/
	268
	269	/* Configure PLL oscillator register */
	270	bfin_write_USB_PLLOSC_CTRL(0x30a8);
	271	SSYNC();
	272
	273	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
	274	SSYNC();
	275
	276	bfin_write_USB_EP_NI0_RXMAXP(64);
	277	SSYNC();
	278
	279	bfin_write_USB_EP_NI0_TXMAXP(64);
	280	SSYNC();
	281
	282	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
	283	bfin_write_USB_GLOBINTR(0x7);
	284	SSYNC();
	285
	286	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA \| EP1_TX_ENA \| EP2_TX_ENA \|
	287	EP3_TX_ENA \| EP4_TX_ENA \| EP5_TX_ENA \|
	288	EP6_TX_ENA \| EP7_TX_ENA \| EP1_RX_ENA \|
	289	EP2_RX_ENA \| EP3_RX_ENA \| EP4_RX_ENA \|
	290	EP5_RX_ENA \| EP6_RX_ENA \| EP7_RX_ENA);
	291	SSYNC();
	292
	293	if (is_host_enabled(musb)) {
	294	musb->board_set_vbus = bfin_set_vbus;
	295	setup_timer(&musb_conn_timer,
	296	musb_conn_timer_handler, (unsigned long) musb);
	297	}
	298	if (is_peripheral_enabled(musb))
84e250ff	299	musb->xceiv->set_power = bfin_set_power;
0c6a8818 BW	300
	301	musb->isr = blackfin_interrupt;
	302
	303	return 0;
	304	}
	305
	306	int musb_platform_suspend(struct musb *musb)
	307	{
	308	return 0;
	309	}
	310
	311	int musb_platform_resume(struct musb *musb)
	312	{
	313	return 0;
	314	}
	315
	316
	317	int musb_platform_exit(struct musb *musb)
	318	{
	319
	320	bfin_vbus_power(musb, 0 /off/, 1);
	321	gpio_free(musb->config->gpio_vrsel);
	322	musb_platform_suspend(musb);
	323
	324	return 0;
	325	}