[deliverable/linux.git] / drivers / usb / musb / blackfin.c

/*
 * MUSB OTG controller driver for Blackfin Processors
 *
 * Copyright 2006-2008 Analog Devices Inc.
 *
 * Enter bugs at http://blackfin.uclinux.org/
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>

#include <asm/cacheflush.h>

#include "musb_core.h"
#include "musbhsdma.h"
#include "blackfin.h"

struct bfin_glue {
	struct device		*dev;
	struct platform_device	*musb;
};
#define glue_to_musb(g)		platform_get_drvdata(g->musb)

/*
 * Load an endpoint's FIFO
 */
void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
{
	void __iomem *fifo = hw_ep->fifo;
	void __iomem *epio = hw_ep->regs;
	u8 epnum = hw_ep->epnum;

	prefetch((u8 *)src);

	musb_writew(epio, MUSB_TXCOUNT, len);

	DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
			hw_ep->epnum, fifo, len, src, epio);

	dump_fifo_data(src, len);

	if (!ANOMALY_05000380 && epnum != 0) {
		u16 dma_reg;

		flush_dcache_range((unsigned long)src,
			(unsigned long)(src + len));

		/* Setup DMA address register */
		dma_reg = (u32)src;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
		SSYNC();

		dma_reg = (u32)src >> 16;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
		SSYNC();

		/* Setup DMA count register */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
		SSYNC();

		/* Enable the DMA */
		dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
		SSYNC();

		/* Wait for compelete */
		while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
			cpu_relax();

		/* acknowledge dma interrupt */
		bfin_write_USB_DMA_INTERRUPT(1 << epnum);
		SSYNC();

		/* Reset DMA */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
		SSYNC();
	} else {
		SSYNC();

		if (unlikely((unsigned long)src & 0x01))
			outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
		else
			outsw((unsigned long)fifo, src, (len + 1) >> 1);
	}
}
/*
 * Unload an endpoint's FIFO
 */
void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
{
	void __iomem *fifo = hw_ep->fifo;
	u8 epnum = hw_ep->epnum;

	if (ANOMALY_05000467 && epnum != 0) {
		u16 dma_reg;

		invalidate_dcache_range((unsigned long)dst,
			(unsigned long)(dst + len));

		/* Setup DMA address register */
		dma_reg = (u32)dst;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
		SSYNC();

		dma_reg = (u32)dst >> 16;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
		SSYNC();

		/* Setup DMA count register */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
		SSYNC();

		/* Enable the DMA */
		dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
		SSYNC();

		/* Wait for compelete */
		while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
			cpu_relax();

		/* acknowledge dma interrupt */
		bfin_write_USB_DMA_INTERRUPT(1 << epnum);
		SSYNC();

		/* Reset DMA */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
		SSYNC();
	} else {
		SSYNC();
		/* Read the last byte of packet with odd size from address fifo + 4
		 * to trigger 1 byte access to EP0 FIFO.
		 */
		if (len == 1)
			*dst = (u8)inw((unsigned long)fifo + 4);
		else {
			if (unlikely((unsigned long)dst & 0x01))
				insw_8((unsigned long)fifo, dst, len >> 1);
			else
				insw((unsigned long)fifo, dst, len >> 1);

			if (len & 0x01)
				*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
		}
	}
	DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
			'R', hw_ep->epnum, fifo, len, dst);

	dump_fifo_data(dst, len);
}

static irqreturn_t blackfin_interrupt(int irq, void *__hci)
{
	unsigned long	flags;
	irqreturn_t	retval = IRQ_NONE;
	struct musb	*musb = __hci;

	spin_lock_irqsave(&musb->lock, flags);

	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);

	if (musb->int_usb || musb->int_tx || musb->int_rx) {
		musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
		musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
		musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
		retval = musb_interrupt(musb);
	}

	/* Start sampling ID pin, when plug is removed from MUSB */
	if ((is_otg_enabled(musb) && (musb->xceiv->state == OTG_STATE_B_IDLE
		|| musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) ||
		(musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
		musb->a_wait_bcon = TIMER_DELAY;
	}

	spin_unlock_irqrestore(&musb->lock, flags);

	return retval;
}

static void musb_conn_timer_handler(unsigned long _musb)
{
	struct musb *musb = (void *)_musb;
	unsigned long flags;
	u16 val;
	static u8 toggle;

	spin_lock_irqsave(&musb->lock, flags);
	switch (musb->xceiv->state) {
	case OTG_STATE_A_IDLE:
	case OTG_STATE_A_WAIT_BCON:
		/* Start a new session */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);
		val &= ~MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);
		val |= MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);
		/* Check if musb is host or peripheral. */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);

		if (!(val & MUSB_DEVCTL_BDEVICE)) {
			gpio_set_value(musb->config->gpio_vrsel, 1);
			musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
		} else {
			gpio_set_value(musb->config->gpio_vrsel, 0);
			/* Ignore VBUSERROR and SUSPEND IRQ */
			val = musb_readb(musb->mregs, MUSB_INTRUSBE);
			val &= ~MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSBE, val);

			val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSB, val);
			if (is_otg_enabled(musb))
				musb->xceiv->state = OTG_STATE_B_IDLE;
			else
				musb_writeb(musb->mregs, MUSB_POWER, MUSB_POWER_HSENAB);
		}
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
		break;
	case OTG_STATE_B_IDLE:

		if (!is_peripheral_enabled(musb))
			break;
		/* Start a new session.  It seems that MUSB needs taking
		 * some time to recognize the type of the plug inserted?
		 */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);
		val |= MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);
		val = musb_readw(musb->mregs, MUSB_DEVCTL);

		if (!(val & MUSB_DEVCTL_BDEVICE)) {
			gpio_set_value(musb->config->gpio_vrsel, 1);
			musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
		} else {
			gpio_set_value(musb->config->gpio_vrsel, 0);

			/* Ignore VBUSERROR and SUSPEND IRQ */
			val = musb_readb(musb->mregs, MUSB_INTRUSBE);
			val &= ~MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSBE, val);

			val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSB, val);

			/* Toggle the Soft Conn bit, so that we can response to
			 * the inserting of either A-plug or B-plug.
			 */
			if (toggle) {
				val = musb_readb(musb->mregs, MUSB_POWER);
				val &= ~MUSB_POWER_SOFTCONN;
				musb_writeb(musb->mregs, MUSB_POWER, val);
				toggle = 0;
			} else {
				val = musb_readb(musb->mregs, MUSB_POWER);
				val |= MUSB_POWER_SOFTCONN;
				musb_writeb(musb->mregs, MUSB_POWER, val);
				toggle = 1;
			}
			/* The delay time is set to 1/4 second by default,
			 * shortening it, if accelerating A-plug detection
			 * is needed in OTG mode.
			 */
			mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
		}
		break;
	default:
		DBG(1, "%s state not handled\n",
			otg_state_string(musb->xceiv->state));
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);

	DBG(4, "state is %s\n", otg_state_string(musb->xceiv->state));
}

static void bfin_musb_enable(struct musb *musb)
{
	if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
		musb->a_wait_bcon = TIMER_DELAY;
	}
}

static void bfin_musb_disable(struct musb *musb)
{
}

static void bfin_musb_set_vbus(struct musb *musb, int is_on)
{
	int value = musb->config->gpio_vrsel_active;
	if (!is_on)
		value = !value;
	gpio_set_value(musb->config->gpio_vrsel, value);

	DBG(1, "VBUS %s, devctl %02x "
		/* otg %3x conf %08x prcm %08x */ "\n",
		otg_state_string(musb->xceiv->state),
		musb_readb(musb->mregs, MUSB_DEVCTL));
}

static int bfin_musb_set_power(struct otg_transceiver *x, unsigned mA)
{
	return 0;
}

static void bfin_musb_try_idle(struct musb *musb, unsigned long timeout)
{
	if (!is_otg_enabled(musb) && is_host_enabled(musb))
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
}

static int bfin_musb_vbus_status(struct musb *musb)
{
	return 0;
}

static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
{
	return -EIO;
}

static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
				u16 packet_sz, u8 *mode,
				dma_addr_t *dma_addr, u32 *len)
{
	struct musb_dma_channel *musb_channel = channel->private_data;

	/*
	 * Anomaly 05000450 might cause data corruption when using DMA
	 * MODE 1 transmits with short packet.  So to work around this,
	 * we truncate all MODE 1 transfers down to a multiple of the
	 * max packet size, and then do the last short packet transfer
	 * (if there is any) using MODE 0.
	 */
	if (ANOMALY_05000450) {
		if (musb_channel->transmit && *mode == 1)
			*len = *len - (*len % packet_sz);
	}

	return 0;
}

static void bfin_musb_reg_init(struct musb *musb)
{
	if (ANOMALY_05000346) {
		bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
		SSYNC();
	}

	if (ANOMALY_05000347) {
		bfin_write_USB_APHY_CNTRL(0x0);
		SSYNC();
	}

	/* Configure PLL oscillator register */
	bfin_write_USB_PLLOSC_CTRL(0x3080 |
			((480/musb->config->clkin) << 1));
	SSYNC();

	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
	SSYNC();

	bfin_write_USB_EP_NI0_RXMAXP(64);
	SSYNC();

	bfin_write_USB_EP_NI0_TXMAXP(64);
	SSYNC();

	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
	bfin_write_USB_GLOBINTR(0x7);
	SSYNC();

	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
				EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
				EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
				EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
				EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
	SSYNC();
}

static int bfin_musb_init(struct musb *musb)
{

	/*
	 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
	 * and OTG HOST modes, while rev 1.1 and greater require PE7 to
	 * be low for DEVICE mode and high for HOST mode. We set it high
	 * here because we are in host mode
	 */

	if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
		printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
			musb->config->gpio_vrsel);
		return -ENODEV;
	}
	gpio_direction_output(musb->config->gpio_vrsel, 0);

	usb_nop_xceiv_register();
	musb->xceiv = otg_get_transceiver();
	if (!musb->xceiv) {
		gpio_free(musb->config->gpio_vrsel);
		return -ENODEV;
	}

	bfin_musb_reg_init(musb);

	if (is_host_enabled(musb)) {
		setup_timer(&musb_conn_timer,
			musb_conn_timer_handler, (unsigned long) musb);
	}
	if (is_peripheral_enabled(musb))
		musb->xceiv->set_power = bfin_musb_set_power;

	musb->isr = blackfin_interrupt;
	musb->double_buffer_not_ok = true;

	return 0;
}

static int bfin_musb_exit(struct musb *musb)
{
	gpio_free(musb->config->gpio_vrsel);

	otg_put_transceiver(musb->xceiv);
	usb_nop_xceiv_unregister();
	return 0;
}

static const struct musb_platform_ops bfin_ops = {
	.init		= bfin_musb_init,
	.exit		= bfin_musb_exit,

	.enable		= bfin_musb_enable,
	.disable	= bfin_musb_disable,

	.set_mode	= bfin_musb_set_mode,
	.try_idle	= bfin_musb_try_idle,

	.vbus_status	= bfin_musb_vbus_status,
	.set_vbus	= bfin_musb_set_vbus,

	.adjust_channel_params = bfin_musb_adjust_channel_params,
};

static u64 bfin_dmamask = DMA_BIT_MASK(32);

static int __init bfin_probe(struct platform_device *pdev)
{
	struct musb_hdrc_platform_data	*pdata = pdev->dev.platform_data;
	struct platform_device		*musb;
	struct bfin_glue		*glue;

	int				ret = -ENOMEM;

	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
	if (!glue) {
		dev_err(&pdev->dev, "failed to allocate glue context\n");
		goto err0;
	}

	musb = platform_device_alloc("musb-hdrc", -1);
	if (!musb) {
		dev_err(&pdev->dev, "failed to allocate musb device\n");
		goto err1;
	}

	musb->dev.parent		= &pdev->dev;
	musb->dev.dma_mask		= &bfin_dmamask;
	musb->dev.coherent_dma_mask	= bfin_dmamask;

	glue->dev			= &pdev->dev;
	glue->musb			= musb;

	pdata->platform_ops		= &bfin_ops;

	platform_set_drvdata(pdev, glue);

	ret = platform_device_add_resources(musb, pdev->resource,
			pdev->num_resources);
	if (ret) {
		dev_err(&pdev->dev, "failed to add resources\n");
		goto err2;
	}

	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	if (ret) {
		dev_err(&pdev->dev, "failed to add platform_data\n");
		goto err2;
	}

	ret = platform_device_add(musb);
	if (ret) {
		dev_err(&pdev->dev, "failed to register musb device\n");
		goto err2;
	}

	return 0;

err2:
	platform_device_put(musb);

err1:
	kfree(glue);

err0:
	return ret;
}

static int __exit bfin_remove(struct platform_device *pdev)
{
	struct bfin_glue		*glue = platform_get_drvdata(pdev);

	platform_device_del(glue->musb);
	platform_device_put(glue->musb);
	kfree(glue);

	return 0;
}

#ifdef CONFIG_PM
static int bfin_suspend(struct device *dev)
{
	struct bfin_glue	*glue = dev_get_drvdata(dev);
	struct musb		*musb = glue_to_musb(glue);

	if (is_host_active(musb))
		/*
		 * During hibernate gpio_vrsel will change from high to low
		 * low which will generate wakeup event resume the system
		 * immediately.  Set it to 0 before hibernate to avoid this
		 * wakeup event.
		 */
		gpio_set_value(musb->config->gpio_vrsel, 0);

	return 0;
}

static int bfin_resume(struct device *dev)
{
	struct bfin_glue	*glue = dev_get_drvdata(dev);
	struct musb		*musb = glue_to_musb(glue);

	bfin_musb_reg_init(musb);

	return 0;
}

static struct dev_pm_ops bfin_pm_ops = {
	.suspend	= bfin_suspend,
	.resume		= bfin_resume,
};

#define DEV_PM_OPS	&bfin_pm_ops
#else
#define DEV_PM_OPS	NULL
#endif

static struct platform_driver bfin_driver = {
	.remove		= __exit_p(bfin_remove),
	.driver		= {
		.name	= "musb-blackfin",
		.pm	= DEV_PM_OPS,
	},
};

MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
MODULE_LICENSE("GPL v2");

static int __init bfin_init(void)
{
	return platform_driver_probe(&bfin_driver, bfin_probe);
}
subsys_initcall(bfin_init);

static void __exit bfin_exit(void)
{
	platform_driver_unregister(&bfin_driver);
}
module_exit(bfin_exit);
Commit	Line	Data
0c6a8818 BW	1	/*
	2	* MUSB OTG controller driver for Blackfin Processors
	3	*
	4	* Copyright 2006-2008 Analog Devices Inc.
	5	*
	6	* Enter bugs at http://blackfin.uclinux.org/
	7	*
	8	* Licensed under the GPL-2 or later.
	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/kernel.h>
	13	#include <linux/sched.h>
0c6a8818 BW	14	#include <linux/init.h>
0c6a8818 BW	15	#include <linux/list.h>
0c6a8818 BW	16	#include <linux/gpio.h>
0c6a8818 BW	17	#include <linux/io.h>
9cb0308e FB	18	#include <linux/platform_device.h>
9cb0308e FB	19	#include <linux/dma-mapping.h>
0c6a8818 BW	20
	21	#include <asm/cacheflush.h>
	22
	23	#include "musb_core.h"
13254307	24	#include "musbhsdma.h"
0c6a8818 BW	25	#include "blackfin.h"
0c6a8818 BW	26
a023c631 FB	27	struct bfin_glue {
	28	struct device *dev;
	29	struct platform_device *musb;
	30	};
fcd22e3b	31	#define glue_to_musb(g) platform_get_drvdata(g->musb)
a023c631	32
0c6a8818 BW	33	/*
	34	* Load an endpoint's FIFO
	35	*/
	36	void musb_write_fifo(struct musb_hw_ep hw_ep, u16 len, const u8 src)
	37	{
	38	void __iomem *fifo = hw_ep->fifo;
	39	void __iomem *epio = hw_ep->regs;
1c4bdc01	40	u8 epnum = hw_ep->epnum;
0c6a8818 BW	41
	42	prefetch((u8 *)src);
	43
	44	musb_writew(epio, MUSB_TXCOUNT, len);
	45
	46	DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
	47	hw_ep->epnum, fifo, len, src, epio);
	48
	49	dump_fifo_data(src, len);
	50
1c4bdc01	51	if (!ANOMALY_05000380 && epnum != 0) {
1ca9e9ca BW	52	u16 dma_reg;
	53
	54	flush_dcache_range((unsigned long)src,
	55	(unsigned long)(src + len));
1c4bdc01 BW	56
1c4bdc01 BW	57	/* Setup DMA address register */
1ca9e9ca	58	dma_reg = (u32)src;
1c4bdc01 BW	59	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
	60	SSYNC();
	61
1ca9e9ca	62	dma_reg = (u32)src >> 16;
1c4bdc01 BW	63	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
	64	SSYNC();
	65
	66	/* Setup DMA count register */
	67	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
	68	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
	69	SSYNC();
	70
	71	/* Enable the DMA */
	72	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA \| DIRECTION;
	73	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
	74	SSYNC();
	75
	76	/* Wait for compelete */
	77	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
	78	cpu_relax();
	79
	80	/* acknowledge dma interrupt */
	81	bfin_write_USB_DMA_INTERRUPT(1 << epnum);
	82	SSYNC();
	83
	84	/* Reset DMA */
	85	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
	86	SSYNC();
	87	} else {
	88	SSYNC();
	89
	90	if (unlikely((unsigned long)src & 0x01))
1ca9e9ca	91	outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
1c4bdc01	92	else
1ca9e9ca	93	outsw((unsigned long)fifo, src, (len + 1) >> 1);
1c4bdc01	94	}
0c6a8818	95	}
0c6a8818 BW	96	/*
	97	* Unload an endpoint's FIFO
	98	*/
	99	void musb_read_fifo(struct musb_hw_ep hw_ep, u16 len, u8 dst)
	100	{
	101	void __iomem *fifo = hw_ep->fifo;
	102	u8 epnum = hw_ep->epnum;
0c6a8818	103
1c4bdc01	104	if (ANOMALY_05000467 && epnum != 0) {
1ca9e9ca	105	u16 dma_reg;
1c4bdc01	106
1ca9e9ca BW	107	invalidate_dcache_range((unsigned long)dst,
1ca9e9ca BW	108	(unsigned long)(dst + len));
1c4bdc01 BW	109
1c4bdc01 BW	110	/* Setup DMA address register */
1ca9e9ca	111	dma_reg = (u32)dst;
1c4bdc01 BW	112	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
	113	SSYNC();
	114
1ca9e9ca	115	dma_reg = (u32)dst >> 16;
1c4bdc01 BW	116	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
	117	SSYNC();
	118
	119	/* Setup DMA count register */
	120	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
	121	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
	122	SSYNC();
	123
	124	/* Enable the DMA */
	125	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA;
	126	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
	127	SSYNC();
	128
	129	/* Wait for compelete */
	130	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
	131	cpu_relax();
	132
	133	/* acknowledge dma interrupt */
	134	bfin_write_USB_DMA_INTERRUPT(1 << epnum);
	135	SSYNC();
	136
	137	/* Reset DMA */
	138	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
	139	SSYNC();
	140	} else {
	141	SSYNC();
	142	/* Read the last byte of packet with odd size from address fifo + 4
	143	* to trigger 1 byte access to EP0 FIFO.
	144	*/
	145	if (len == 1)
	146	*dst = (u8)inw((unsigned long)fifo + 4);
	147	else {
	148	if (unlikely((unsigned long)dst & 0x01))
	149	insw_8((unsigned long)fifo, dst, len >> 1);
	150	else
	151	insw((unsigned long)fifo, dst, len >> 1);
	152
	153	if (len & 0x01)
	154	*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
	155	}
	156	}
04f4086f MF	157	DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
	158	'R', hw_ep->epnum, fifo, len, dst);
	159
0c6a8818 BW	160	dump_fifo_data(dst, len);
	161	}
	162
	163	static irqreturn_t blackfin_interrupt(int irq, void *__hci)
	164	{
	165	unsigned long flags;
	166	irqreturn_t retval = IRQ_NONE;
	167	struct musb *musb = __hci;
	168
	169	spin_lock_irqsave(&musb->lock, flags);
	170
	171	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
	172	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
	173	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
	174
	175	if (musb->int_usb \|\| musb->int_tx \|\| musb->int_rx) {
	176	musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
	177	musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
	178	musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
	179	retval = musb_interrupt(musb);
	180	}
	181
ff927add	182	/* Start sampling ID pin, when plug is removed from MUSB */
68f64714 BL	183	if ((is_otg_enabled(musb) && (musb->xceiv->state == OTG_STATE_B_IDLE
	184	\|\| musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) \|\|
	185	(musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
ff927add CC	186	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	187	musb->a_wait_bcon = TIMER_DELAY;
	188	}
	189
0c6a8818 BW	190	spin_unlock_irqrestore(&musb->lock, flags);
0c6a8818 BW	191
2f831751	192	return retval;
0c6a8818 BW	193	}
	194
	195	static void musb_conn_timer_handler(unsigned long _musb)
	196	{
	197	struct musb musb = (void )_musb;
	198	unsigned long flags;
	199	u16 val;
ff927add	200	static u8 toggle;
0c6a8818 BW	201
0c6a8818 BW	202	spin_lock_irqsave(&musb->lock, flags);
84e250ff	203	switch (musb->xceiv->state) {
0c6a8818 BW	204	case OTG_STATE_A_IDLE:
	205	case OTG_STATE_A_WAIT_BCON:
	206	/* Start a new session */
	207	val = musb_readw(musb->mregs, MUSB_DEVCTL);
ff927add CC	208	val &= ~MUSB_DEVCTL_SESSION;
ff927add CC	209	musb_writew(musb->mregs, MUSB_DEVCTL, val);
0c6a8818 BW	210	val \|= MUSB_DEVCTL_SESSION;
0c6a8818 BW	211	musb_writew(musb->mregs, MUSB_DEVCTL, val);
ff927add CC	212	/* Check if musb is host or peripheral. */
	213	val = musb_readw(musb->mregs, MUSB_DEVCTL);
	214
	215	if (!(val & MUSB_DEVCTL_BDEVICE)) {
	216	gpio_set_value(musb->config->gpio_vrsel, 1);
	217	musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
	218	} else {
	219	gpio_set_value(musb->config->gpio_vrsel, 0);
	220	/* Ignore VBUSERROR and SUSPEND IRQ */
	221	val = musb_readb(musb->mregs, MUSB_INTRUSBE);
	222	val &= ~MUSB_INTR_VBUSERROR;
	223	musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
	224
	225	val = MUSB_INTR_SUSPEND \| MUSB_INTR_VBUSERROR;
	226	musb_writeb(musb->mregs, MUSB_INTRUSB, val);
	227	if (is_otg_enabled(musb))
	228	musb->xceiv->state = OTG_STATE_B_IDLE;
	229	else
	230	musb_writeb(musb->mregs, MUSB_POWER, MUSB_POWER_HSENAB);
	231	}
	232	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	233	break;
	234	case OTG_STATE_B_IDLE:
0c6a8818	235
ff927add CC	236	if (!is_peripheral_enabled(musb))
	237	break;
	238	/* Start a new session. It seems that MUSB needs taking
	239	* some time to recognize the type of the plug inserted?
	240	*/
	241	val = musb_readw(musb->mregs, MUSB_DEVCTL);
	242	val \|= MUSB_DEVCTL_SESSION;
	243	musb_writew(musb->mregs, MUSB_DEVCTL, val);
0c6a8818	244	val = musb_readw(musb->mregs, MUSB_DEVCTL);
ff927add	245
0c6a8818 BW	246	if (!(val & MUSB_DEVCTL_BDEVICE)) {
0c6a8818 BW	247	gpio_set_value(musb->config->gpio_vrsel, 1);
84e250ff	248	musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
0c6a8818 BW	249	} else {
	250	gpio_set_value(musb->config->gpio_vrsel, 0);
	251
	252	/* Ignore VBUSERROR and SUSPEND IRQ */
	253	val = musb_readb(musb->mregs, MUSB_INTRUSBE);
	254	val &= ~MUSB_INTR_VBUSERROR;
	255	musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
	256
	257	val = MUSB_INTR_SUSPEND \| MUSB_INTR_VBUSERROR;
	258	musb_writeb(musb->mregs, MUSB_INTRUSB, val);
	259
ff927add CC	260	/* Toggle the Soft Conn bit, so that we can response to
	261	* the inserting of either A-plug or B-plug.
	262	*/
	263	if (toggle) {
	264	val = musb_readb(musb->mregs, MUSB_POWER);
	265	val &= ~MUSB_POWER_SOFTCONN;
	266	musb_writeb(musb->mregs, MUSB_POWER, val);
	267	toggle = 0;
	268	} else {
	269	val = musb_readb(musb->mregs, MUSB_POWER);
	270	val \|= MUSB_POWER_SOFTCONN;
	271	musb_writeb(musb->mregs, MUSB_POWER, val);
	272	toggle = 1;
	273	}
	274	/* The delay time is set to 1/4 second by default,
	275	* shortening it, if accelerating A-plug detection
	276	* is needed in OTG mode.
	277	*/
	278	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
0c6a8818	279	}
0c6a8818	280	break;
0c6a8818	281	default:
3df00453 AG	282	DBG(1, "%s state not handled\n",
3df00453 AG	283	otg_state_string(musb->xceiv->state));
0c6a8818 BW	284	break;
	285	}
	286	spin_unlock_irqrestore(&musb->lock, flags);
	287
3df00453	288	DBG(4, "state is %s\n", otg_state_string(musb->xceiv->state));
0c6a8818 BW	289	}
0c6a8818 BW	290
743411b3	291	static void bfin_musb_enable(struct musb *musb)
0c6a8818	292	{
ff927add	293	if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
0c6a8818 BW	294	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	295	musb->a_wait_bcon = TIMER_DELAY;
	296	}
	297	}
	298
743411b3	299	static void bfin_musb_disable(struct musb *musb)
0c6a8818 BW	300	{
	301	}
	302
743411b3	303	static void bfin_musb_set_vbus(struct musb *musb, int is_on)
0c6a8818	304	{
6ddc6dae CC	305	int value = musb->config->gpio_vrsel_active;
	306	if (!is_on)
	307	value = !value;
	308	gpio_set_value(musb->config->gpio_vrsel, value);
0c6a8818 BW	309
	310	DBG(1, "VBUS %s, devctl %02x "
	311	/* otg %3x conf %08x prcm %08x */ "\n",
3df00453	312	otg_state_string(musb->xceiv->state),
0c6a8818 BW	313	musb_readb(musb->mregs, MUSB_DEVCTL));
	314	}
	315
743411b3	316	static int bfin_musb_set_power(struct otg_transceiver *x, unsigned mA)
0c6a8818 BW	317	{
	318	return 0;
	319	}
	320
743411b3	321	static void bfin_musb_try_idle(struct musb *musb, unsigned long timeout)
0c6a8818	322	{
ff927add	323	if (!is_otg_enabled(musb) && is_host_enabled(musb))
0c6a8818 BW	324	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	325	}
	326
45567c28	327	static int bfin_musb_vbus_status(struct musb *musb)
0c6a8818 BW	328	{
	329	return 0;
	330	}
	331
743411b3	332	static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
0c6a8818	333	{
2002e768	334	return -EIO;
0c6a8818 BW	335	}
0c6a8818 BW	336
13254307 MF	337	static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
	338	u16 packet_sz, u8 *mode,
	339	dma_addr_t dma_addr, u32 len)
	340	{
	341	struct musb_dma_channel *musb_channel = channel->private_data;
	342
	343	/*
	344	* Anomaly 05000450 might cause data corruption when using DMA
	345	* MODE 1 transmits with short packet. So to work around this,
	346	* we truncate all MODE 1 transfers down to a multiple of the
	347	* max packet size, and then do the last short packet transfer
	348	* (if there is any) using MODE 0.
	349	*/
	350	if (ANOMALY_05000450) {
	351	if (musb_channel->transmit && *mode == 1)
	352	len = len - (*len % packet_sz);
	353	}
	354
	355	return 0;
	356	}
	357
743411b3	358	static void bfin_musb_reg_init(struct musb *musb)
0c6a8818	359	{
d426e60d RG	360	if (ANOMALY_05000346) {
	361	bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
	362	SSYNC();
	363	}
0c6a8818	364
d426e60d RG	365	if (ANOMALY_05000347) {
	366	bfin_write_USB_APHY_CNTRL(0x0);
	367	SSYNC();
	368	}
0c6a8818	369
0c6a8818	370	/* Configure PLL oscillator register */
9c756462 BL	371	bfin_write_USB_PLLOSC_CTRL(0x3080 \|
9c756462 BL	372	((480/musb->config->clkin) << 1));
0c6a8818 BW	373	SSYNC();
	374
	375	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
	376	SSYNC();
	377
	378	bfin_write_USB_EP_NI0_RXMAXP(64);
	379	SSYNC();
	380
	381	bfin_write_USB_EP_NI0_TXMAXP(64);
	382	SSYNC();
	383
	384	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
	385	bfin_write_USB_GLOBINTR(0x7);
	386	SSYNC();
	387
	388	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA \| EP1_TX_ENA \| EP2_TX_ENA \|
	389	EP3_TX_ENA \| EP4_TX_ENA \| EP5_TX_ENA \|
	390	EP6_TX_ENA \| EP7_TX_ENA \| EP1_RX_ENA \|
	391	EP2_RX_ENA \| EP3_RX_ENA \| EP4_RX_ENA \|
	392	EP5_RX_ENA \| EP6_RX_ENA \| EP7_RX_ENA);
	393	SSYNC();
743411b3 FB	394	}
	395
	396	static int bfin_musb_init(struct musb *musb)
	397	{
	398
	399	/*
	400	* Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
	401	* and OTG HOST modes, while rev 1.1 and greater require PE7 to
	402	* be low for DEVICE mode and high for HOST mode. We set it high
	403	* here because we are in host mode
	404	*/
	405
	406	if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
	407	printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
	408	musb->config->gpio_vrsel);
	409	return -ENODEV;
	410	}
	411	gpio_direction_output(musb->config->gpio_vrsel, 0);
	412
	413	usb_nop_xceiv_register();
	414	musb->xceiv = otg_get_transceiver();
	415	if (!musb->xceiv) {
	416	gpio_free(musb->config->gpio_vrsel);
	417	return -ENODEV;
	418	}
	419
	420	bfin_musb_reg_init(musb);
0c6a8818 BW	421
0c6a8818 BW	422	if (is_host_enabled(musb)) {
0c6a8818 BW	423	setup_timer(&musb_conn_timer,
	424	musb_conn_timer_handler, (unsigned long) musb);
	425	}
	426	if (is_peripheral_enabled(musb))
743411b3	427	musb->xceiv->set_power = bfin_musb_set_power;
0c6a8818 BW	428
0c6a8818 BW	429	musb->isr = blackfin_interrupt;
06624818	430	musb->double_buffer_not_ok = true;
0c6a8818 BW	431
	432	return 0;
	433	}
	434
743411b3	435	static int bfin_musb_exit(struct musb *musb)
0c6a8818	436	{
0c6a8818	437	gpio_free(musb->config->gpio_vrsel);
0c6a8818	438
f4053874	439	otg_put_transceiver(musb->xceiv);
3daad24d	440	usb_nop_xceiv_unregister();
0c6a8818 BW	441	return 0;
0c6a8818 BW	442	}
743411b3	443
f7ec9437	444	static const struct musb_platform_ops bfin_ops = {
743411b3 FB	445	.init = bfin_musb_init,
	446	.exit = bfin_musb_exit,
	447
	448	.enable = bfin_musb_enable,
	449	.disable = bfin_musb_disable,
	450
	451	.set_mode = bfin_musb_set_mode,
	452	.try_idle = bfin_musb_try_idle,
	453
	454	.vbus_status = bfin_musb_vbus_status,
	455	.set_vbus = bfin_musb_set_vbus,
13254307 MF	456
13254307 MF	457	.adjust_channel_params = bfin_musb_adjust_channel_params,
743411b3	458	};
9cb0308e FB	459
	460	static u64 bfin_dmamask = DMA_BIT_MASK(32);
	461
	462	static int __init bfin_probe(struct platform_device *pdev)
	463	{
	464	struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
	465	struct platform_device *musb;
a023c631	466	struct bfin_glue *glue;
9cb0308e FB	467
	468	int ret = -ENOMEM;
	469
a023c631 FB	470	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
	471	if (!glue) {
	472	dev_err(&pdev->dev, "failed to allocate glue context\n");
	473	goto err0;
	474	}
	475
9cb0308e FB	476	musb = platform_device_alloc("musb-hdrc", -1);
	477	if (!musb) {
	478	dev_err(&pdev->dev, "failed to allocate musb device\n");
a023c631	479	goto err1;
9cb0308e FB	480	}
	481
	482	musb->dev.parent = &pdev->dev;
	483	musb->dev.dma_mask = &bfin_dmamask;
	484	musb->dev.coherent_dma_mask = bfin_dmamask;
	485
a023c631 FB	486	glue->dev = &pdev->dev;
	487	glue->musb = musb;
	488
f7ec9437 FB	489	pdata->platform_ops = &bfin_ops;
f7ec9437 FB	490
a023c631	491	platform_set_drvdata(pdev, glue);
9cb0308e FB	492
	493	ret = platform_device_add_resources(musb, pdev->resource,
	494	pdev->num_resources);
	495	if (ret) {
	496	dev_err(&pdev->dev, "failed to add resources\n");
a023c631	497	goto err2;
9cb0308e FB	498	}
	499
	500	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	501	if (ret) {
	502	dev_err(&pdev->dev, "failed to add platform_data\n");
a023c631	503	goto err2;
9cb0308e FB	504	}
	505
	506	ret = platform_device_add(musb);
	507	if (ret) {
	508	dev_err(&pdev->dev, "failed to register musb device\n");
a023c631	509	goto err2;
9cb0308e FB	510	}
	511
	512	return 0;
	513
a023c631	514	err2:
9cb0308e FB	515	platform_device_put(musb);
9cb0308e FB	516
a023c631 FB	517	err1:
	518	kfree(glue);
	519
9cb0308e FB	520	err0:
	521	return ret;
	522	}
	523
	524	static int __exit bfin_remove(struct platform_device *pdev)
	525	{
a023c631	526	struct bfin_glue *glue = platform_get_drvdata(pdev);
9cb0308e	527
a023c631 FB	528	platform_device_del(glue->musb);
	529	platform_device_put(glue->musb);
	530	kfree(glue);
9cb0308e FB	531
	532	return 0;
	533	}
	534
fcd22e3b FB	535	#ifdef CONFIG_PM
	536	static int bfin_suspend(struct device *dev)
	537	{
	538	struct bfin_glue *glue = dev_get_drvdata(dev);
	539	struct musb *musb = glue_to_musb(glue);
	540
	541	if (is_host_active(musb))
	542	/*
	543	* During hibernate gpio_vrsel will change from high to low
	544	* low which will generate wakeup event resume the system
	545	* immediately. Set it to 0 before hibernate to avoid this
	546	* wakeup event.
	547	*/
	548	gpio_set_value(musb->config->gpio_vrsel, 0);
	549
	550	return 0;
	551	}
	552
	553	static int bfin_resume(struct device *dev)
	554	{
	555	struct bfin_glue *glue = dev_get_drvdata(dev);
	556	struct musb *musb = glue_to_musb(glue);
	557
	558	bfin_musb_reg_init(musb);
	559
	560	return 0;
	561	}
	562
	563	static struct dev_pm_ops bfin_pm_ops = {
	564	.suspend = bfin_suspend,
	565	.resume = bfin_resume,
	566	};
	567
8f7e7b87	568	#define DEV_PM_OPS &bfin_pm_ops
fcd22e3b FB	569	#else
	570	#define DEV_PM_OPS NULL
	571	#endif
	572
9cb0308e FB	573	static struct platform_driver bfin_driver = {
	574	.remove = __exit_p(bfin_remove),
	575	.driver = {
417ddf86	576	.name = "musb-blackfin",
fcd22e3b	577	.pm = DEV_PM_OPS,
9cb0308e FB	578	},
	579	};
	580
	581	MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
	582	MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
	583	MODULE_LICENSE("GPL v2");
	584
	585	static int __init bfin_init(void)
	586	{
	587	return platform_driver_probe(&bfin_driver, bfin_probe);
	588	}
	589	subsys_initcall(bfin_init);
	590
	591	static void __exit bfin_exit(void)
	592	{
	593	platform_driver_unregister(&bfin_driver);
	594	}
	595	module_exit(bfin_exit);