[deliverable/linux.git] / drivers / usb / musb / blackfin.c

/*
 * MUSB OTG controller driver for Blackfin Processors
 *
 * Copyright 2006-2008 Analog Devices Inc.
 *
 * Enter bugs at http://blackfin.uclinux.org/
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/gpio.h>
#include <linux/io.h>

#include <asm/cacheflush.h>

#include "musb_core.h"
#include "blackfin.h"

/*
 * Load an endpoint's FIFO
 */
void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
{
	void __iomem *fifo = hw_ep->fifo;
	void __iomem *epio = hw_ep->regs;
	u8 epnum = hw_ep->epnum;

	prefetch((u8 *)src);

	musb_writew(epio, MUSB_TXCOUNT, len);

	DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
			hw_ep->epnum, fifo, len, src, epio);

	dump_fifo_data(src, len);

	if (!ANOMALY_05000380 && epnum != 0) {
		u16 dma_reg;

		flush_dcache_range((unsigned long)src,
			(unsigned long)(src + len));

		/* Setup DMA address register */
		dma_reg = (u32)src;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
		SSYNC();

		dma_reg = (u32)src >> 16;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
		SSYNC();

		/* Setup DMA count register */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
		SSYNC();

		/* Enable the DMA */
		dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
		SSYNC();

		/* Wait for compelete */
		while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
			cpu_relax();

		/* acknowledge dma interrupt */
		bfin_write_USB_DMA_INTERRUPT(1 << epnum);
		SSYNC();

		/* Reset DMA */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
		SSYNC();
	} else {
		SSYNC();

		if (unlikely((unsigned long)src & 0x01))
			outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
		else
			outsw((unsigned long)fifo, src, (len + 1) >> 1);
	}
}
/*
 * Unload an endpoint's FIFO
 */
void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
{
	void __iomem *fifo = hw_ep->fifo;
	u8 epnum = hw_ep->epnum;

	if (ANOMALY_05000467 && epnum != 0) {
		u16 dma_reg;

		invalidate_dcache_range((unsigned long)dst,
			(unsigned long)(dst + len));

		/* Setup DMA address register */
		dma_reg = (u32)dst;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
		SSYNC();

		dma_reg = (u32)dst >> 16;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
		SSYNC();

		/* Setup DMA count register */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
		SSYNC();

		/* Enable the DMA */
		dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
		SSYNC();

		/* Wait for compelete */
		while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
			cpu_relax();

		/* acknowledge dma interrupt */
		bfin_write_USB_DMA_INTERRUPT(1 << epnum);
		SSYNC();

		/* Reset DMA */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
		SSYNC();
	} else {
		SSYNC();
		/* Read the last byte of packet with odd size from address fifo + 4
		 * to trigger 1 byte access to EP0 FIFO.
		 */
		if (len == 1)
			*dst = (u8)inw((unsigned long)fifo + 4);
		else {
			if (unlikely((unsigned long)dst & 0x01))
				insw_8((unsigned long)fifo, dst, len >> 1);
			else
				insw((unsigned long)fifo, dst, len >> 1);

			if (len & 0x01)
				*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
		}
	}
	DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
			'R', hw_ep->epnum, fifo, len, dst);

	dump_fifo_data(dst, len);
}

static irqreturn_t blackfin_interrupt(int irq, void *__hci)
{
	unsigned long	flags;
	irqreturn_t	retval = IRQ_NONE;
	struct musb	*musb = __hci;

	spin_lock_irqsave(&musb->lock, flags);

	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);

	if (musb->int_usb || musb->int_tx || musb->int_rx) {
		musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
		musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
		musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
		retval = musb_interrupt(musb);
	}

	spin_unlock_irqrestore(&musb->lock, flags);

	return retval;
}

static void musb_conn_timer_handler(unsigned long _musb)
{
	struct musb *musb = (void *)_musb;
	unsigned long flags;
	u16 val;

	spin_lock_irqsave(&musb->lock, flags);
	switch (musb->xceiv->state) {
	case OTG_STATE_A_IDLE:
	case OTG_STATE_A_WAIT_BCON:
		/* Start a new session */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);
		val |= MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);

		val = musb_readw(musb->mregs, MUSB_DEVCTL);
		if (!(val & MUSB_DEVCTL_BDEVICE)) {
			gpio_set_value(musb->config->gpio_vrsel, 1);
			musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
		} else {
			gpio_set_value(musb->config->gpio_vrsel, 0);

			/* Ignore VBUSERROR and SUSPEND IRQ */
			val = musb_readb(musb->mregs, MUSB_INTRUSBE);
			val &= ~MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSBE, val);

			val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSB, val);

			val = MUSB_POWER_HSENAB;
			musb_writeb(musb->mregs, MUSB_POWER, val);
		}
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
		break;

	default:
		DBG(1, "%s state not handled\n", otg_state_string(musb));
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);

	DBG(4, "state is %s\n", otg_state_string(musb));
}

void musb_platform_enable(struct musb *musb)
{
	if (is_host_enabled(musb)) {
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
		musb->a_wait_bcon = TIMER_DELAY;
	}
}

void musb_platform_disable(struct musb *musb)
{
}

static void bfin_vbus_power(struct musb *musb, int is_on, int sleeping)
{
}

static void bfin_set_vbus(struct musb *musb, int is_on)
{
	int value = musb->config->gpio_vrsel_active;
	if (!is_on)
		value = !value;
	gpio_set_value(musb->config->gpio_vrsel, value);

	DBG(1, "VBUS %s, devctl %02x "
		/* otg %3x conf %08x prcm %08x */ "\n",
		otg_state_string(musb),
		musb_readb(musb->mregs, MUSB_DEVCTL));
}

static int bfin_set_power(struct otg_transceiver *x, unsigned mA)
{
	return 0;
}

void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
{
	if (is_host_enabled(musb))
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
}

int musb_platform_get_vbus_status(struct musb *musb)
{
	return 0;
}

int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
{
	return -EIO;
}

int __init musb_platform_init(struct musb *musb, void *board_data)
{

	/*
	 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
	 * and OTG HOST modes, while rev 1.1 and greater require PE7 to
	 * be low for DEVICE mode and high for HOST mode. We set it high
	 * here because we are in host mode
	 */

	if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
		printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d \n",
			musb->config->gpio_vrsel);
		return -ENODEV;
	}
	gpio_direction_output(musb->config->gpio_vrsel, 0);

	usb_nop_xceiv_register();
	musb->xceiv = otg_get_transceiver();
	if (!musb->xceiv)
		return -ENODEV;

	if (ANOMALY_05000346) {
		bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
		SSYNC();
	}

	if (ANOMALY_05000347) {
		bfin_write_USB_APHY_CNTRL(0x0);
		SSYNC();
	}

	/* Configure PLL oscillator register */
	bfin_write_USB_PLLOSC_CTRL(0x30a8);
	SSYNC();

	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
	SSYNC();

	bfin_write_USB_EP_NI0_RXMAXP(64);
	SSYNC();

	bfin_write_USB_EP_NI0_TXMAXP(64);
	SSYNC();

	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
	bfin_write_USB_GLOBINTR(0x7);
	SSYNC();

	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
				EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
				EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
				EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
				EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
	SSYNC();

	if (is_host_enabled(musb)) {
		musb->board_set_vbus = bfin_set_vbus;
		setup_timer(&musb_conn_timer,
			musb_conn_timer_handler, (unsigned long) musb);
	}
	if (is_peripheral_enabled(musb))
		musb->xceiv->set_power = bfin_set_power;

	musb->isr = blackfin_interrupt;

	return 0;
}

int musb_platform_suspend(struct musb *musb)
{
	return 0;
}

int musb_platform_resume(struct musb *musb)
{
	return 0;
}


int musb_platform_exit(struct musb *musb)
{

	bfin_vbus_power(musb, 0 /*off*/, 1);
	gpio_free(musb->config->gpio_vrsel);
	musb_platform_suspend(musb);

	return 0;
}
Commit	Line	Data
0c6a8818 BW	1	/*
	2	* MUSB OTG controller driver for Blackfin Processors
	3	*
	4	* Copyright 2006-2008 Analog Devices Inc.
	5	*
	6	* Enter bugs at http://blackfin.uclinux.org/
	7	*
	8	* Licensed under the GPL-2 or later.
	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/kernel.h>
	13	#include <linux/sched.h>
0c6a8818 BW	14	#include <linux/init.h>
0c6a8818 BW	15	#include <linux/list.h>
0c6a8818 BW	16	#include <linux/gpio.h>
	17	#include <linux/io.h>
	18
	19	#include <asm/cacheflush.h>
	20
	21	#include "musb_core.h"
	22	#include "blackfin.h"
	23
	24	/*
	25	* Load an endpoint's FIFO
	26	*/
	27	void musb_write_fifo(struct musb_hw_ep hw_ep, u16 len, const u8 src)
	28	{
	29	void __iomem *fifo = hw_ep->fifo;
	30	void __iomem *epio = hw_ep->regs;
1c4bdc01	31	u8 epnum = hw_ep->epnum;
0c6a8818 BW	32
	33	prefetch((u8 *)src);
	34
	35	musb_writew(epio, MUSB_TXCOUNT, len);
	36
	37	DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
	38	hw_ep->epnum, fifo, len, src, epio);
	39
	40	dump_fifo_data(src, len);
	41
1c4bdc01	42	if (!ANOMALY_05000380 && epnum != 0) {
1ca9e9ca BW	43	u16 dma_reg;
	44
	45	flush_dcache_range((unsigned long)src,
	46	(unsigned long)(src + len));
1c4bdc01 BW	47
1c4bdc01 BW	48	/* Setup DMA address register */
1ca9e9ca	49	dma_reg = (u32)src;
1c4bdc01 BW	50	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
	51	SSYNC();
	52
1ca9e9ca	53	dma_reg = (u32)src >> 16;
1c4bdc01 BW	54	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
	55	SSYNC();
	56
	57	/* Setup DMA count register */
	58	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
	59	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
	60	SSYNC();
	61
	62	/* Enable the DMA */
	63	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA \| DIRECTION;
	64	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
	65	SSYNC();
	66
	67	/* Wait for compelete */
	68	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
	69	cpu_relax();
	70
	71	/* acknowledge dma interrupt */
	72	bfin_write_USB_DMA_INTERRUPT(1 << epnum);
	73	SSYNC();
	74
	75	/* Reset DMA */
	76	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
	77	SSYNC();
	78	} else {
	79	SSYNC();
	80
	81	if (unlikely((unsigned long)src & 0x01))
1ca9e9ca	82	outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
1c4bdc01	83	else
1ca9e9ca	84	outsw((unsigned long)fifo, src, (len + 1) >> 1);
1c4bdc01	85	}
0c6a8818	86	}
0c6a8818 BW	87	/*
	88	* Unload an endpoint's FIFO
	89	*/
	90	void musb_read_fifo(struct musb_hw_ep hw_ep, u16 len, u8 dst)
	91	{
	92	void __iomem *fifo = hw_ep->fifo;
	93	u8 epnum = hw_ep->epnum;
0c6a8818	94
1c4bdc01	95	if (ANOMALY_05000467 && epnum != 0) {
1ca9e9ca	96	u16 dma_reg;
1c4bdc01	97
1ca9e9ca BW	98	invalidate_dcache_range((unsigned long)dst,
1ca9e9ca BW	99	(unsigned long)(dst + len));
1c4bdc01 BW	100
1c4bdc01 BW	101	/* Setup DMA address register */
1ca9e9ca	102	dma_reg = (u32)dst;
1c4bdc01 BW	103	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
	104	SSYNC();
	105
1ca9e9ca	106	dma_reg = (u32)dst >> 16;
1c4bdc01 BW	107	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
	108	SSYNC();
	109
	110	/* Setup DMA count register */
	111	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
	112	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
	113	SSYNC();
	114
	115	/* Enable the DMA */
	116	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA;
	117	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
	118	SSYNC();
	119
	120	/* Wait for compelete */
	121	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
	122	cpu_relax();
	123
	124	/* acknowledge dma interrupt */
	125	bfin_write_USB_DMA_INTERRUPT(1 << epnum);
	126	SSYNC();
	127
	128	/* Reset DMA */
	129	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
	130	SSYNC();
	131	} else {
	132	SSYNC();
	133	/* Read the last byte of packet with odd size from address fifo + 4
	134	* to trigger 1 byte access to EP0 FIFO.
	135	*/
	136	if (len == 1)
	137	*dst = (u8)inw((unsigned long)fifo + 4);
	138	else {
	139	if (unlikely((unsigned long)dst & 0x01))
	140	insw_8((unsigned long)fifo, dst, len >> 1);
	141	else
	142	insw((unsigned long)fifo, dst, len >> 1);
	143
	144	if (len & 0x01)
	145	*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
	146	}
	147	}
04f4086f MF	148	DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
	149	'R', hw_ep->epnum, fifo, len, dst);
	150
0c6a8818 BW	151	dump_fifo_data(dst, len);
	152	}
	153
	154	static irqreturn_t blackfin_interrupt(int irq, void *__hci)
	155	{
	156	unsigned long flags;
	157	irqreturn_t retval = IRQ_NONE;
	158	struct musb *musb = __hci;
	159
	160	spin_lock_irqsave(&musb->lock, flags);
	161
	162	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
	163	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
	164	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
	165
	166	if (musb->int_usb \|\| musb->int_tx \|\| musb->int_rx) {
	167	musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
	168	musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
	169	musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
	170	retval = musb_interrupt(musb);
	171	}
	172
	173	spin_unlock_irqrestore(&musb->lock, flags);
	174
2f831751	175	return retval;
0c6a8818 BW	176	}
	177
	178	static void musb_conn_timer_handler(unsigned long _musb)
	179	{
	180	struct musb musb = (void )_musb;
	181	unsigned long flags;
	182	u16 val;
	183
	184	spin_lock_irqsave(&musb->lock, flags);
84e250ff	185	switch (musb->xceiv->state) {
0c6a8818 BW	186	case OTG_STATE_A_IDLE:
	187	case OTG_STATE_A_WAIT_BCON:
	188	/* Start a new session */
	189	val = musb_readw(musb->mregs, MUSB_DEVCTL);
	190	val \|= MUSB_DEVCTL_SESSION;
	191	musb_writew(musb->mregs, MUSB_DEVCTL, val);
	192
	193	val = musb_readw(musb->mregs, MUSB_DEVCTL);
	194	if (!(val & MUSB_DEVCTL_BDEVICE)) {
	195	gpio_set_value(musb->config->gpio_vrsel, 1);
84e250ff	196	musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
0c6a8818 BW	197	} else {
	198	gpio_set_value(musb->config->gpio_vrsel, 0);
	199
	200	/* Ignore VBUSERROR and SUSPEND IRQ */
	201	val = musb_readb(musb->mregs, MUSB_INTRUSBE);
	202	val &= ~MUSB_INTR_VBUSERROR;
	203	musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
	204
	205	val = MUSB_INTR_SUSPEND \| MUSB_INTR_VBUSERROR;
	206	musb_writeb(musb->mregs, MUSB_INTRUSB, val);
	207
	208	val = MUSB_POWER_HSENAB;
	209	musb_writeb(musb->mregs, MUSB_POWER, val);
	210	}
	211	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	212	break;
	213
	214	default:
	215	DBG(1, "%s state not handled\n", otg_state_string(musb));
	216	break;
	217	}
	218	spin_unlock_irqrestore(&musb->lock, flags);
	219
	220	DBG(4, "state is %s\n", otg_state_string(musb));
	221	}
	222
	223	void musb_platform_enable(struct musb *musb)
	224	{
	225	if (is_host_enabled(musb)) {
	226	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	227	musb->a_wait_bcon = TIMER_DELAY;
	228	}
	229	}
	230
	231	void musb_platform_disable(struct musb *musb)
	232	{
	233	}
	234
	235	static void bfin_vbus_power(struct musb *musb, int is_on, int sleeping)
	236	{
	237	}
	238
	239	static void bfin_set_vbus(struct musb *musb, int is_on)
	240	{
6ddc6dae CC	241	int value = musb->config->gpio_vrsel_active;
	242	if (!is_on)
	243	value = !value;
	244	gpio_set_value(musb->config->gpio_vrsel, value);
0c6a8818 BW	245
	246	DBG(1, "VBUS %s, devctl %02x "
	247	/* otg %3x conf %08x prcm %08x */ "\n",
	248	otg_state_string(musb),
	249	musb_readb(musb->mregs, MUSB_DEVCTL));
	250	}
	251
	252	static int bfin_set_power(struct otg_transceiver *x, unsigned mA)
	253	{
	254	return 0;
	255	}
	256
	257	void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
	258	{
	259	if (is_host_enabled(musb))
	260	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	261	}
	262
	263	int musb_platform_get_vbus_status(struct musb *musb)
	264	{
	265	return 0;
	266	}
	267
2002e768	268	int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
0c6a8818	269	{
2002e768	270	return -EIO;
0c6a8818 BW	271	}
0c6a8818 BW	272
de2e1b0c	273	int __init musb_platform_init(struct musb musb, void board_data)
0c6a8818 BW	274	{
	275
	276	/*
	277	* Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
	278	* and OTG HOST modes, while rev 1.1 and greater require PE7 to
	279	* be low for DEVICE mode and high for HOST mode. We set it high
	280	* here because we are in host mode
	281	*/
	282
	283	if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
	284	printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d \n",
	285	musb->config->gpio_vrsel);
	286	return -ENODEV;
	287	}
	288	gpio_direction_output(musb->config->gpio_vrsel, 0);
	289
84e250ff DB	290	usb_nop_xceiv_register();
	291	musb->xceiv = otg_get_transceiver();
	292	if (!musb->xceiv)
	293	return -ENODEV;
	294
d426e60d RG	295	if (ANOMALY_05000346) {
	296	bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
	297	SSYNC();
	298	}
0c6a8818	299
d426e60d RG	300	if (ANOMALY_05000347) {
	301	bfin_write_USB_APHY_CNTRL(0x0);
	302	SSYNC();
	303	}
0c6a8818	304
0c6a8818 BW	305	/* Configure PLL oscillator register */
	306	bfin_write_USB_PLLOSC_CTRL(0x30a8);
	307	SSYNC();
	308
	309	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
	310	SSYNC();
	311
	312	bfin_write_USB_EP_NI0_RXMAXP(64);
	313	SSYNC();
	314
	315	bfin_write_USB_EP_NI0_TXMAXP(64);
	316	SSYNC();
	317
	318	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
	319	bfin_write_USB_GLOBINTR(0x7);
	320	SSYNC();
	321
	322	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA \| EP1_TX_ENA \| EP2_TX_ENA \|
	323	EP3_TX_ENA \| EP4_TX_ENA \| EP5_TX_ENA \|
	324	EP6_TX_ENA \| EP7_TX_ENA \| EP1_RX_ENA \|
	325	EP2_RX_ENA \| EP3_RX_ENA \| EP4_RX_ENA \|
	326	EP5_RX_ENA \| EP6_RX_ENA \| EP7_RX_ENA);
	327	SSYNC();
	328
	329	if (is_host_enabled(musb)) {
	330	musb->board_set_vbus = bfin_set_vbus;
	331	setup_timer(&musb_conn_timer,
	332	musb_conn_timer_handler, (unsigned long) musb);
	333	}
	334	if (is_peripheral_enabled(musb))
84e250ff	335	musb->xceiv->set_power = bfin_set_power;
0c6a8818 BW	336
	337	musb->isr = blackfin_interrupt;
	338
	339	return 0;
	340	}
	341
	342	int musb_platform_suspend(struct musb *musb)
	343	{
	344	return 0;
	345	}
	346
	347	int musb_platform_resume(struct musb *musb)
	348	{
	349	return 0;
	350	}
	351
	352
	353	int musb_platform_exit(struct musb *musb)
	354	{
	355
	356	bfin_vbus_power(musb, 0 /off/, 1);
	357	gpio_free(musb->config->gpio_vrsel);
	358	musb_platform_suspend(musb);
	359
	360	return 0;
	361	}