[deliverable/linux.git] / drivers / usb / musb / blackfin.c

/*
 * MUSB OTG controller driver for Blackfin Processors
 *
 * Copyright 2006-2008 Analog Devices Inc.
 *
 * Enter bugs at http://blackfin.uclinux.org/
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/list.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/prefetch.h>
#include <linux/usb/usb_phy_generic.h>

#include <asm/cacheflush.h>

#include "musb_core.h"
#include "musbhsdma.h"
#include "blackfin.h"

struct bfin_glue {
	struct device		*dev;
	struct platform_device	*musb;
};
#define glue_to_musb(g)		platform_get_drvdata(g->musb)

/*
 * Load an endpoint's FIFO
 */
void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
{
	struct musb *musb = hw_ep->musb;
	void __iomem *fifo = hw_ep->fifo;
	void __iomem *epio = hw_ep->regs;
	u8 epnum = hw_ep->epnum;

	prefetch((u8 *)src);

	musb_writew(epio, MUSB_TXCOUNT, len);

	dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
			hw_ep->epnum, fifo, len, src, epio);

	dump_fifo_data(src, len);

	if (!ANOMALY_05000380 && epnum != 0) {
		u16 dma_reg;

		flush_dcache_range((unsigned long)src,
			(unsigned long)(src + len));

		/* Setup DMA address register */
		dma_reg = (u32)src;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
		SSYNC();

		dma_reg = (u32)src >> 16;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
		SSYNC();

		/* Setup DMA count register */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
		SSYNC();

		/* Enable the DMA */
		dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
		SSYNC();

		/* Wait for complete */
		while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
			cpu_relax();

		/* acknowledge dma interrupt */
		bfin_write_USB_DMA_INTERRUPT(1 << epnum);
		SSYNC();

		/* Reset DMA */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
		SSYNC();
	} else {
		SSYNC();

		if (unlikely((unsigned long)src & 0x01))
			outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
		else
			outsw((unsigned long)fifo, src, (len + 1) >> 1);
	}
}
/*
 * Unload an endpoint's FIFO
 */
void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
{
	struct musb *musb = hw_ep->musb;
	void __iomem *fifo = hw_ep->fifo;
	u8 epnum = hw_ep->epnum;

	if (ANOMALY_05000467 && epnum != 0) {
		u16 dma_reg;

		invalidate_dcache_range((unsigned long)dst,
			(unsigned long)(dst + len));

		/* Setup DMA address register */
		dma_reg = (u32)dst;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
		SSYNC();

		dma_reg = (u32)dst >> 16;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
		SSYNC();

		/* Setup DMA count register */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
		SSYNC();

		/* Enable the DMA */
		dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
		SSYNC();

		/* Wait for complete */
		while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
			cpu_relax();

		/* acknowledge dma interrupt */
		bfin_write_USB_DMA_INTERRUPT(1 << epnum);
		SSYNC();

		/* Reset DMA */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
		SSYNC();
	} else {
		SSYNC();
		/* Read the last byte of packet with odd size from address fifo + 4
		 * to trigger 1 byte access to EP0 FIFO.
		 */
		if (len == 1)
			*dst = (u8)inw((unsigned long)fifo + 4);
		else {
			if (unlikely((unsigned long)dst & 0x01))
				insw_8((unsigned long)fifo, dst, len >> 1);
			else
				insw((unsigned long)fifo, dst, len >> 1);

			if (len & 0x01)
				*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
		}
	}
	dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
			'R', hw_ep->epnum, fifo, len, dst);

	dump_fifo_data(dst, len);
}

static irqreturn_t blackfin_interrupt(int irq, void *__hci)
{
	unsigned long	flags;
	irqreturn_t	retval = IRQ_NONE;
	struct musb	*musb = __hci;

	spin_lock_irqsave(&musb->lock, flags);

	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);

	if (musb->int_usb || musb->int_tx || musb->int_rx) {
		musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
		musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
		musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
		retval = musb_interrupt(musb);
	}

	/* Start sampling ID pin, when plug is removed from MUSB */
	if ((musb->xceiv->state == OTG_STATE_B_IDLE
		|| musb->xceiv->state == OTG_STATE_A_WAIT_BCON) ||
		(musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
		musb->a_wait_bcon = TIMER_DELAY;
	}

	spin_unlock_irqrestore(&musb->lock, flags);

	return retval;
}

static void musb_conn_timer_handler(unsigned long _musb)
{
	struct musb *musb = (void *)_musb;
	unsigned long flags;
	u16 val;
	static u8 toggle;

	spin_lock_irqsave(&musb->lock, flags);
	switch (musb->xceiv->state) {
	case OTG_STATE_A_IDLE:
	case OTG_STATE_A_WAIT_BCON:
		/* Start a new session */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);
		val &= ~MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);
		val |= MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);
		/* Check if musb is host or peripheral. */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);

		if (!(val & MUSB_DEVCTL_BDEVICE)) {
			gpio_set_value(musb->config->gpio_vrsel, 1);
			musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
		} else {
			gpio_set_value(musb->config->gpio_vrsel, 0);
			/* Ignore VBUSERROR and SUSPEND IRQ */
			val = musb_readb(musb->mregs, MUSB_INTRUSBE);
			val &= ~MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSBE, val);

			val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSB, val);
			musb->xceiv->state = OTG_STATE_B_IDLE;
		}
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
		break;
	case OTG_STATE_B_IDLE:
		/*
		 * Start a new session.  It seems that MUSB needs taking
		 * some time to recognize the type of the plug inserted?
		 */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);
		val |= MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);
		val = musb_readw(musb->mregs, MUSB_DEVCTL);

		if (!(val & MUSB_DEVCTL_BDEVICE)) {
			gpio_set_value(musb->config->gpio_vrsel, 1);
			musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
		} else {
			gpio_set_value(musb->config->gpio_vrsel, 0);

			/* Ignore VBUSERROR and SUSPEND IRQ */
			val = musb_readb(musb->mregs, MUSB_INTRUSBE);
			val &= ~MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSBE, val);

			val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSB, val);

			/* Toggle the Soft Conn bit, so that we can response to
			 * the inserting of either A-plug or B-plug.
			 */
			if (toggle) {
				val = musb_readb(musb->mregs, MUSB_POWER);
				val &= ~MUSB_POWER_SOFTCONN;
				musb_writeb(musb->mregs, MUSB_POWER, val);
				toggle = 0;
			} else {
				val = musb_readb(musb->mregs, MUSB_POWER);
				val |= MUSB_POWER_SOFTCONN;
				musb_writeb(musb->mregs, MUSB_POWER, val);
				toggle = 1;
			}
			/* The delay time is set to 1/4 second by default,
			 * shortening it, if accelerating A-plug detection
			 * is needed in OTG mode.
			 */
			mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
		}
		break;
	default:
		dev_dbg(musb->controller, "%s state not handled\n",
			usb_otg_state_string(musb->xceiv->state));
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);

	dev_dbg(musb->controller, "state is %s\n",
		usb_otg_state_string(musb->xceiv->state));
}

static void bfin_musb_enable(struct musb *musb)
{
	/* REVISIT is this really correct ? */
}

static void bfin_musb_disable(struct musb *musb)
{
}

static void bfin_musb_set_vbus(struct musb *musb, int is_on)
{
	int value = musb->config->gpio_vrsel_active;
	if (!is_on)
		value = !value;
	gpio_set_value(musb->config->gpio_vrsel, value);

	dev_dbg(musb->controller, "VBUS %s, devctl %02x "
		/* otg %3x conf %08x prcm %08x */ "\n",
		usb_otg_state_string(musb->xceiv->state),
		musb_readb(musb->mregs, MUSB_DEVCTL));
}

static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)
{
	return 0;
}

static int bfin_musb_vbus_status(struct musb *musb)
{
	return 0;
}

static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
{
	return -EIO;
}

static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
				u16 packet_sz, u8 *mode,
				dma_addr_t *dma_addr, u32 *len)
{
	struct musb_dma_channel *musb_channel = channel->private_data;

	/*
	 * Anomaly 05000450 might cause data corruption when using DMA
	 * MODE 1 transmits with short packet.  So to work around this,
	 * we truncate all MODE 1 transfers down to a multiple of the
	 * max packet size, and then do the last short packet transfer
	 * (if there is any) using MODE 0.
	 */
	if (ANOMALY_05000450) {
		if (musb_channel->transmit && *mode == 1)
			*len = *len - (*len % packet_sz);
	}

	return 0;
}

static void bfin_musb_reg_init(struct musb *musb)
{
	if (ANOMALY_05000346) {
		bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
		SSYNC();
	}

	if (ANOMALY_05000347) {
		bfin_write_USB_APHY_CNTRL(0x0);
		SSYNC();
	}

	/* Configure PLL oscillator register */
	bfin_write_USB_PLLOSC_CTRL(0x3080 |
			((480/musb->config->clkin) << 1));
	SSYNC();

	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
	SSYNC();

	bfin_write_USB_EP_NI0_RXMAXP(64);
	SSYNC();

	bfin_write_USB_EP_NI0_TXMAXP(64);
	SSYNC();

	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
	bfin_write_USB_GLOBINTR(0x7);
	SSYNC();

	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
				EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
				EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
				EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
				EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
	SSYNC();
}

static int bfin_musb_init(struct musb *musb)
{

	/*
	 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
	 * and OTG HOST modes, while rev 1.1 and greater require PE7 to
	 * be low for DEVICE mode and high for HOST mode. We set it high
	 * here because we are in host mode
	 */

	if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
		printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
			musb->config->gpio_vrsel);
		return -ENODEV;
	}
	gpio_direction_output(musb->config->gpio_vrsel, 0);

	usb_phy_generic_register();
	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
	if (IS_ERR_OR_NULL(musb->xceiv)) {
		gpio_free(musb->config->gpio_vrsel);
		return -EPROBE_DEFER;
	}

	bfin_musb_reg_init(musb);

	setup_timer(&musb_conn_timer, musb_conn_timer_handler,
			(unsigned long) musb);

	musb->xceiv->set_power = bfin_musb_set_power;

	musb->isr = blackfin_interrupt;
	musb->double_buffer_not_ok = true;

	return 0;
}

static int bfin_musb_exit(struct musb *musb)
{
	gpio_free(musb->config->gpio_vrsel);

	usb_put_phy(musb->xceiv);
	usb_phy_generic_unregister();
	return 0;
}

static const struct musb_platform_ops bfin_ops = {
	.init		= bfin_musb_init,
	.exit		= bfin_musb_exit,

	.enable		= bfin_musb_enable,
	.disable	= bfin_musb_disable,

	.set_mode	= bfin_musb_set_mode,

	.vbus_status	= bfin_musb_vbus_status,
	.set_vbus	= bfin_musb_set_vbus,

	.adjust_channel_params = bfin_musb_adjust_channel_params,
};

static u64 bfin_dmamask = DMA_BIT_MASK(32);

static int bfin_probe(struct platform_device *pdev)
{
	struct resource musb_resources[2];
	struct musb_hdrc_platform_data	*pdata = dev_get_platdata(&pdev->dev);
	struct platform_device		*musb;
	struct bfin_glue		*glue;

	int				ret = -ENOMEM;

	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
	if (!glue) {
		dev_err(&pdev->dev, "failed to allocate glue context\n");
		goto err0;
	}

	musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
	if (!musb) {
		dev_err(&pdev->dev, "failed to allocate musb device\n");
		goto err1;
	}

	musb->dev.parent		= &pdev->dev;
	musb->dev.dma_mask		= &bfin_dmamask;
	musb->dev.coherent_dma_mask	= bfin_dmamask;

	glue->dev			= &pdev->dev;
	glue->musb			= musb;

	pdata->platform_ops		= &bfin_ops;

	platform_set_drvdata(pdev, glue);

	memset(musb_resources, 0x00, sizeof(*musb_resources) *
			ARRAY_SIZE(musb_resources));

	musb_resources[0].name = pdev->resource[0].name;
	musb_resources[0].start = pdev->resource[0].start;
	musb_resources[0].end = pdev->resource[0].end;
	musb_resources[0].flags = pdev->resource[0].flags;

	musb_resources[1].name = pdev->resource[1].name;
	musb_resources[1].start = pdev->resource[1].start;
	musb_resources[1].end = pdev->resource[1].end;
	musb_resources[1].flags = pdev->resource[1].flags;

	ret = platform_device_add_resources(musb, musb_resources,
			ARRAY_SIZE(musb_resources));
	if (ret) {
		dev_err(&pdev->dev, "failed to add resources\n");
		goto err3;
	}

	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	if (ret) {
		dev_err(&pdev->dev, "failed to add platform_data\n");
		goto err3;
	}

	ret = platform_device_add(musb);
	if (ret) {
		dev_err(&pdev->dev, "failed to register musb device\n");
		goto err3;
	}

	return 0;

err3:
	platform_device_put(musb);

err1:
	kfree(glue);

err0:
	return ret;
}

static int bfin_remove(struct platform_device *pdev)
{
	struct bfin_glue		*glue = platform_get_drvdata(pdev);

	platform_device_unregister(glue->musb);
	kfree(glue);

	return 0;
}

#ifdef CONFIG_PM
static int bfin_suspend(struct device *dev)
{
	struct bfin_glue	*glue = dev_get_drvdata(dev);
	struct musb		*musb = glue_to_musb(glue);

	if (is_host_active(musb))
		/*
		 * During hibernate gpio_vrsel will change from high to low
		 * low which will generate wakeup event resume the system
		 * immediately.  Set it to 0 before hibernate to avoid this
		 * wakeup event.
		 */
		gpio_set_value(musb->config->gpio_vrsel, 0);

	return 0;
}

static int bfin_resume(struct device *dev)
{
	struct bfin_glue	*glue = dev_get_drvdata(dev);
	struct musb		*musb = glue_to_musb(glue);

	bfin_musb_reg_init(musb);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(bfin_pm_ops, bfin_suspend, bfin_resume);

static struct platform_driver bfin_driver = {
	.probe		= bfin_probe,
	.remove		= __exit_p(bfin_remove),
	.driver		= {
		.name	= "musb-blackfin",
		.pm	= &bfin_pm_ops,
	},
};

MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
MODULE_LICENSE("GPL v2");
module_platform_driver(bfin_driver);
Commit	Line	Data
0c6a8818 BW	1	/*
	2	* MUSB OTG controller driver for Blackfin Processors
	3	*
	4	* Copyright 2006-2008 Analog Devices Inc.
	5	*
	6	* Enter bugs at http://blackfin.uclinux.org/
	7	*
	8	* Licensed under the GPL-2 or later.
	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/kernel.h>
	13	#include <linux/sched.h>
0c6a8818	14	#include <linux/list.h>
0c6a8818 BW	15	#include <linux/gpio.h>
0c6a8818 BW	16	#include <linux/io.h>
ded017ee	17	#include <linux/err.h>
9cb0308e FB	18	#include <linux/platform_device.h>
9cb0308e FB	19	#include <linux/dma-mapping.h>
ad50c1b2	20	#include <linux/prefetch.h>
d7078df6	21	#include <linux/usb/usb_phy_generic.h>
0c6a8818 BW	22
	23	#include <asm/cacheflush.h>
	24
	25	#include "musb_core.h"
13254307	26	#include "musbhsdma.h"
0c6a8818 BW	27	#include "blackfin.h"
0c6a8818 BW	28
a023c631 FB	29	struct bfin_glue {
	30	struct device *dev;
	31	struct platform_device *musb;
	32	};
fcd22e3b	33	#define glue_to_musb(g) platform_get_drvdata(g->musb)
a023c631	34
0c6a8818 BW	35	/*
	36	* Load an endpoint's FIFO
	37	*/
	38	void musb_write_fifo(struct musb_hw_ep hw_ep, u16 len, const u8 src)
	39	{
28e49705	40	struct musb *musb = hw_ep->musb;
0c6a8818 BW	41	void __iomem *fifo = hw_ep->fifo;
0c6a8818 BW	42	void __iomem *epio = hw_ep->regs;
1c4bdc01	43	u8 epnum = hw_ep->epnum;
0c6a8818 BW	44
	45	prefetch((u8 *)src);
	46
	47	musb_writew(epio, MUSB_TXCOUNT, len);
	48
5c8a86e1	49	dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
0c6a8818 BW	50	hw_ep->epnum, fifo, len, src, epio);
	51
	52	dump_fifo_data(src, len);
	53
1c4bdc01	54	if (!ANOMALY_05000380 && epnum != 0) {
1ca9e9ca BW	55	u16 dma_reg;
	56
	57	flush_dcache_range((unsigned long)src,
	58	(unsigned long)(src + len));
1c4bdc01 BW	59
1c4bdc01 BW	60	/* Setup DMA address register */
1ca9e9ca	61	dma_reg = (u32)src;
1c4bdc01 BW	62	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
	63	SSYNC();
	64
1ca9e9ca	65	dma_reg = (u32)src >> 16;
1c4bdc01 BW	66	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
	67	SSYNC();
	68
	69	/* Setup DMA count register */
	70	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
	71	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
	72	SSYNC();
	73
	74	/* Enable the DMA */
	75	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA \| DIRECTION;
	76	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
	77	SSYNC();
	78
5ae477b0	79	/* Wait for complete */
1c4bdc01 BW	80	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
	81	cpu_relax();
	82
	83	/* acknowledge dma interrupt */
	84	bfin_write_USB_DMA_INTERRUPT(1 << epnum);
	85	SSYNC();
	86
	87	/* Reset DMA */
	88	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
	89	SSYNC();
	90	} else {
	91	SSYNC();
	92
	93	if (unlikely((unsigned long)src & 0x01))
1ca9e9ca	94	outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
1c4bdc01	95	else
1ca9e9ca	96	outsw((unsigned long)fifo, src, (len + 1) >> 1);
1c4bdc01	97	}
0c6a8818	98	}
0c6a8818 BW	99	/*
	100	* Unload an endpoint's FIFO
	101	*/
	102	void musb_read_fifo(struct musb_hw_ep hw_ep, u16 len, u8 dst)
	103	{
28e49705	104	struct musb *musb = hw_ep->musb;
0c6a8818 BW	105	void __iomem *fifo = hw_ep->fifo;
0c6a8818 BW	106	u8 epnum = hw_ep->epnum;
0c6a8818	107
1c4bdc01	108	if (ANOMALY_05000467 && epnum != 0) {
1ca9e9ca	109	u16 dma_reg;
1c4bdc01	110
1ca9e9ca BW	111	invalidate_dcache_range((unsigned long)dst,
1ca9e9ca BW	112	(unsigned long)(dst + len));
1c4bdc01 BW	113
1c4bdc01 BW	114	/* Setup DMA address register */
1ca9e9ca	115	dma_reg = (u32)dst;
1c4bdc01 BW	116	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
	117	SSYNC();
	118
1ca9e9ca	119	dma_reg = (u32)dst >> 16;
1c4bdc01 BW	120	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
	121	SSYNC();
	122
	123	/* Setup DMA count register */
	124	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
	125	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
	126	SSYNC();
	127
	128	/* Enable the DMA */
	129	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA;
	130	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
	131	SSYNC();
	132
5ae477b0	133	/* Wait for complete */
1c4bdc01 BW	134	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
	135	cpu_relax();
	136
	137	/* acknowledge dma interrupt */
	138	bfin_write_USB_DMA_INTERRUPT(1 << epnum);
	139	SSYNC();
	140
	141	/* Reset DMA */
	142	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
	143	SSYNC();
	144	} else {
	145	SSYNC();
	146	/* Read the last byte of packet with odd size from address fifo + 4
	147	* to trigger 1 byte access to EP0 FIFO.
	148	*/
	149	if (len == 1)
	150	*dst = (u8)inw((unsigned long)fifo + 4);
	151	else {
	152	if (unlikely((unsigned long)dst & 0x01))
	153	insw_8((unsigned long)fifo, dst, len >> 1);
	154	else
	155	insw((unsigned long)fifo, dst, len >> 1);
	156
	157	if (len & 0x01)
	158	*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
	159	}
	160	}
5c8a86e1	161	dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
04f4086f MF	162	'R', hw_ep->epnum, fifo, len, dst);
04f4086f MF	163
0c6a8818 BW	164	dump_fifo_data(dst, len);
	165	}
	166
	167	static irqreturn_t blackfin_interrupt(int irq, void *__hci)
	168	{
	169	unsigned long flags;
	170	irqreturn_t retval = IRQ_NONE;
	171	struct musb *musb = __hci;
	172
	173	spin_lock_irqsave(&musb->lock, flags);
	174
	175	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
	176	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
	177	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
	178
	179	if (musb->int_usb \|\| musb->int_tx \|\| musb->int_rx) {
	180	musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
	181	musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
	182	musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
	183	retval = musb_interrupt(musb);
	184	}
	185
ff927add	186	/* Start sampling ID pin, when plug is removed from MUSB */
032ec49f FB	187	if ((musb->xceiv->state == OTG_STATE_B_IDLE
032ec49f FB	188	\|\| musb->xceiv->state == OTG_STATE_A_WAIT_BCON) \|\|
68f64714	189	(musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
ff927add CC	190	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	191	musb->a_wait_bcon = TIMER_DELAY;
	192	}
	193
0c6a8818 BW	194	spin_unlock_irqrestore(&musb->lock, flags);
0c6a8818 BW	195
2f831751	196	return retval;
0c6a8818 BW	197	}
	198
	199	static void musb_conn_timer_handler(unsigned long _musb)
	200	{
	201	struct musb musb = (void )_musb;
	202	unsigned long flags;
	203	u16 val;
ff927add	204	static u8 toggle;
0c6a8818 BW	205
0c6a8818 BW	206	spin_lock_irqsave(&musb->lock, flags);
84e250ff	207	switch (musb->xceiv->state) {
0c6a8818 BW	208	case OTG_STATE_A_IDLE:
	209	case OTG_STATE_A_WAIT_BCON:
	210	/* Start a new session */
	211	val = musb_readw(musb->mregs, MUSB_DEVCTL);
ff927add CC	212	val &= ~MUSB_DEVCTL_SESSION;
ff927add CC	213	musb_writew(musb->mregs, MUSB_DEVCTL, val);
0c6a8818 BW	214	val \|= MUSB_DEVCTL_SESSION;
0c6a8818 BW	215	musb_writew(musb->mregs, MUSB_DEVCTL, val);
ff927add CC	216	/* Check if musb is host or peripheral. */
	217	val = musb_readw(musb->mregs, MUSB_DEVCTL);
	218
	219	if (!(val & MUSB_DEVCTL_BDEVICE)) {
	220	gpio_set_value(musb->config->gpio_vrsel, 1);
	221	musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
	222	} else {
	223	gpio_set_value(musb->config->gpio_vrsel, 0);
	224	/* Ignore VBUSERROR and SUSPEND IRQ */
	225	val = musb_readb(musb->mregs, MUSB_INTRUSBE);
	226	val &= ~MUSB_INTR_VBUSERROR;
	227	musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
	228
	229	val = MUSB_INTR_SUSPEND \| MUSB_INTR_VBUSERROR;
	230	musb_writeb(musb->mregs, MUSB_INTRUSB, val);
032ec49f	231	musb->xceiv->state = OTG_STATE_B_IDLE;
ff927add CC	232	}
	233	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	234	break;
	235	case OTG_STATE_B_IDLE:
032ec49f FB	236	/*
032ec49f FB	237	* Start a new session. It seems that MUSB needs taking
ff927add CC	238	* some time to recognize the type of the plug inserted?
	239	*/
	240	val = musb_readw(musb->mregs, MUSB_DEVCTL);
	241	val \|= MUSB_DEVCTL_SESSION;
	242	musb_writew(musb->mregs, MUSB_DEVCTL, val);
0c6a8818	243	val = musb_readw(musb->mregs, MUSB_DEVCTL);
ff927add	244
0c6a8818 BW	245	if (!(val & MUSB_DEVCTL_BDEVICE)) {
0c6a8818 BW	246	gpio_set_value(musb->config->gpio_vrsel, 1);
84e250ff	247	musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
0c6a8818 BW	248	} else {
	249	gpio_set_value(musb->config->gpio_vrsel, 0);
	250
	251	/* Ignore VBUSERROR and SUSPEND IRQ */
	252	val = musb_readb(musb->mregs, MUSB_INTRUSBE);
	253	val &= ~MUSB_INTR_VBUSERROR;
	254	musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
	255
	256	val = MUSB_INTR_SUSPEND \| MUSB_INTR_VBUSERROR;
	257	musb_writeb(musb->mregs, MUSB_INTRUSB, val);
	258
ff927add CC	259	/* Toggle the Soft Conn bit, so that we can response to
	260	* the inserting of either A-plug or B-plug.
	261	*/
	262	if (toggle) {
	263	val = musb_readb(musb->mregs, MUSB_POWER);
	264	val &= ~MUSB_POWER_SOFTCONN;
	265	musb_writeb(musb->mregs, MUSB_POWER, val);
	266	toggle = 0;
	267	} else {
	268	val = musb_readb(musb->mregs, MUSB_POWER);
	269	val \|= MUSB_POWER_SOFTCONN;
	270	musb_writeb(musb->mregs, MUSB_POWER, val);
	271	toggle = 1;
	272	}
	273	/* The delay time is set to 1/4 second by default,
	274	* shortening it, if accelerating A-plug detection
	275	* is needed in OTG mode.
	276	*/
	277	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
0c6a8818	278	}
0c6a8818	279	break;
0c6a8818	280	default:
5c8a86e1	281	dev_dbg(musb->controller, "%s state not handled\n",
42c0bf1c	282	usb_otg_state_string(musb->xceiv->state));
0c6a8818 BW	283	break;
	284	}
	285	spin_unlock_irqrestore(&musb->lock, flags);
	286
5c8a86e1	287	dev_dbg(musb->controller, "state is %s\n",
42c0bf1c	288	usb_otg_state_string(musb->xceiv->state));
0c6a8818 BW	289	}
0c6a8818 BW	290
743411b3	291	static void bfin_musb_enable(struct musb *musb)
0c6a8818	292	{
032ec49f	293	/* REVISIT is this really correct ? */
0c6a8818 BW	294	}
0c6a8818 BW	295
743411b3	296	static void bfin_musb_disable(struct musb *musb)
0c6a8818 BW	297	{
	298	}
	299
743411b3	300	static void bfin_musb_set_vbus(struct musb *musb, int is_on)
0c6a8818	301	{
6ddc6dae CC	302	int value = musb->config->gpio_vrsel_active;
	303	if (!is_on)
	304	value = !value;
	305	gpio_set_value(musb->config->gpio_vrsel, value);
0c6a8818	306
5c8a86e1	307	dev_dbg(musb->controller, "VBUS %s, devctl %02x "
0c6a8818	308	/* otg %3x conf %08x prcm %08x */ "\n",
42c0bf1c	309	usb_otg_state_string(musb->xceiv->state),
0c6a8818 BW	310	musb_readb(musb->mregs, MUSB_DEVCTL));
	311	}
	312
86753811	313	static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)
0c6a8818 BW	314	{
	315	return 0;
	316	}
	317
45567c28	318	static int bfin_musb_vbus_status(struct musb *musb)
0c6a8818 BW	319	{
	320	return 0;
	321	}
	322
743411b3	323	static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
0c6a8818	324	{
2002e768	325	return -EIO;
0c6a8818 BW	326	}
0c6a8818 BW	327
13254307 MF	328	static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
	329	u16 packet_sz, u8 *mode,
	330	dma_addr_t dma_addr, u32 len)
	331	{
	332	struct musb_dma_channel *musb_channel = channel->private_data;
	333
	334	/*
	335	* Anomaly 05000450 might cause data corruption when using DMA
	336	* MODE 1 transmits with short packet. So to work around this,
	337	* we truncate all MODE 1 transfers down to a multiple of the
	338	* max packet size, and then do the last short packet transfer
	339	* (if there is any) using MODE 0.
	340	*/
	341	if (ANOMALY_05000450) {
	342	if (musb_channel->transmit && *mode == 1)
	343	len = len - (*len % packet_sz);
	344	}
	345
	346	return 0;
	347	}
	348
743411b3	349	static void bfin_musb_reg_init(struct musb *musb)
0c6a8818	350	{
d426e60d RG	351	if (ANOMALY_05000346) {
	352	bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
	353	SSYNC();
	354	}
0c6a8818	355
d426e60d RG	356	if (ANOMALY_05000347) {
	357	bfin_write_USB_APHY_CNTRL(0x0);
	358	SSYNC();
	359	}
0c6a8818	360
0c6a8818	361	/* Configure PLL oscillator register */
9c756462 BL	362	bfin_write_USB_PLLOSC_CTRL(0x3080 \|
9c756462 BL	363	((480/musb->config->clkin) << 1));
0c6a8818 BW	364	SSYNC();
	365
	366	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
	367	SSYNC();
	368
	369	bfin_write_USB_EP_NI0_RXMAXP(64);
	370	SSYNC();
	371
	372	bfin_write_USB_EP_NI0_TXMAXP(64);
	373	SSYNC();
	374
	375	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
	376	bfin_write_USB_GLOBINTR(0x7);
	377	SSYNC();
	378
	379	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA \| EP1_TX_ENA \| EP2_TX_ENA \|
	380	EP3_TX_ENA \| EP4_TX_ENA \| EP5_TX_ENA \|
	381	EP6_TX_ENA \| EP7_TX_ENA \| EP1_RX_ENA \|
	382	EP2_RX_ENA \| EP3_RX_ENA \| EP4_RX_ENA \|
	383	EP5_RX_ENA \| EP6_RX_ENA \| EP7_RX_ENA);
	384	SSYNC();
743411b3 FB	385	}
	386
	387	static int bfin_musb_init(struct musb *musb)
	388	{
	389
	390	/*
	391	* Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
	392	* and OTG HOST modes, while rev 1.1 and greater require PE7 to
	393	* be low for DEVICE mode and high for HOST mode. We set it high
	394	* here because we are in host mode
	395	*/
	396
	397	if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
	398	printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
	399	musb->config->gpio_vrsel);
	400	return -ENODEV;
	401	}
	402	gpio_direction_output(musb->config->gpio_vrsel, 0);
	403
4525beeb	404	usb_phy_generic_register();
662dca54	405	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
ded017ee	406	if (IS_ERR_OR_NULL(musb->xceiv)) {
743411b3	407	gpio_free(musb->config->gpio_vrsel);
25736e0c	408	return -EPROBE_DEFER;
743411b3 FB	409	}
	410
	411	bfin_musb_reg_init(musb);
0c6a8818	412
032ec49f FB	413	setup_timer(&musb_conn_timer, musb_conn_timer_handler,
	414	(unsigned long) musb);
	415
	416	musb->xceiv->set_power = bfin_musb_set_power;
0c6a8818 BW	417
0c6a8818 BW	418	musb->isr = blackfin_interrupt;
06624818	419	musb->double_buffer_not_ok = true;
0c6a8818 BW	420
	421	return 0;
	422	}
	423
743411b3	424	static int bfin_musb_exit(struct musb *musb)
0c6a8818	425	{
0c6a8818	426	gpio_free(musb->config->gpio_vrsel);
0c6a8818	427
721002ec	428	usb_put_phy(musb->xceiv);
4525beeb	429	usb_phy_generic_unregister();
0c6a8818 BW	430	return 0;
0c6a8818 BW	431	}
743411b3	432
f7ec9437	433	static const struct musb_platform_ops bfin_ops = {
743411b3 FB	434	.init = bfin_musb_init,
	435	.exit = bfin_musb_exit,
	436
	437	.enable = bfin_musb_enable,
	438	.disable = bfin_musb_disable,
	439
	440	.set_mode = bfin_musb_set_mode,
743411b3 FB	441
	442	.vbus_status = bfin_musb_vbus_status,
	443	.set_vbus = bfin_musb_set_vbus,
13254307 MF	444
13254307 MF	445	.adjust_channel_params = bfin_musb_adjust_channel_params,
743411b3	446	};
9cb0308e FB	447
	448	static u64 bfin_dmamask = DMA_BIT_MASK(32);
	449
41ac7b3a	450	static int bfin_probe(struct platform_device *pdev)
9cb0308e	451	{
09fc7d22	452	struct resource musb_resources[2];
c1a7d67c	453	struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
9cb0308e	454	struct platform_device *musb;
a023c631	455	struct bfin_glue *glue;
9cb0308e FB	456
	457	int ret = -ENOMEM;
	458
a023c631 FB	459	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
	460	if (!glue) {
	461	dev_err(&pdev->dev, "failed to allocate glue context\n");
	462	goto err0;
	463	}
	464
2f771164	465	musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
9cb0308e FB	466	if (!musb) {
9cb0308e FB	467	dev_err(&pdev->dev, "failed to allocate musb device\n");
2f771164	468	goto err1;
9cb0308e FB	469	}
	470
	471	musb->dev.parent = &pdev->dev;
	472	musb->dev.dma_mask = &bfin_dmamask;
	473	musb->dev.coherent_dma_mask = bfin_dmamask;
	474
a023c631 FB	475	glue->dev = &pdev->dev;
	476	glue->musb = musb;
	477
f7ec9437 FB	478	pdata->platform_ops = &bfin_ops;
f7ec9437 FB	479
a023c631	480	platform_set_drvdata(pdev, glue);
9cb0308e	481
09fc7d22 FB	482	memset(musb_resources, 0x00, sizeof(musb_resources)
	483	ARRAY_SIZE(musb_resources));
	484
	485	musb_resources[0].name = pdev->resource[0].name;
	486	musb_resources[0].start = pdev->resource[0].start;
	487	musb_resources[0].end = pdev->resource[0].end;
	488	musb_resources[0].flags = pdev->resource[0].flags;
	489
	490	musb_resources[1].name = pdev->resource[1].name;
	491	musb_resources[1].start = pdev->resource[1].start;
	492	musb_resources[1].end = pdev->resource[1].end;
	493	musb_resources[1].flags = pdev->resource[1].flags;
	494
	495	ret = platform_device_add_resources(musb, musb_resources,
	496	ARRAY_SIZE(musb_resources));
9cb0308e FB	497	if (ret) {
9cb0308e FB	498	dev_err(&pdev->dev, "failed to add resources\n");
65b3d52d	499	goto err3;
9cb0308e FB	500	}
	501
	502	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	503	if (ret) {
	504	dev_err(&pdev->dev, "failed to add platform_data\n");
65b3d52d	505	goto err3;
9cb0308e FB	506	}
	507
	508	ret = platform_device_add(musb);
	509	if (ret) {
	510	dev_err(&pdev->dev, "failed to register musb device\n");
65b3d52d	511	goto err3;
9cb0308e FB	512	}
	513
	514	return 0;
	515
65b3d52d	516	err3:
9cb0308e FB	517	platform_device_put(musb);
9cb0308e FB	518
a023c631 FB	519	err1:
	520	kfree(glue);
	521
9cb0308e FB	522	err0:
	523	return ret;
	524	}
	525
fb4e98ab	526	static int bfin_remove(struct platform_device *pdev)
9cb0308e	527	{
a023c631	528	struct bfin_glue *glue = platform_get_drvdata(pdev);
9cb0308e	529
01e40da0	530	platform_device_unregister(glue->musb);
a023c631	531	kfree(glue);
9cb0308e FB	532
	533	return 0;
	534	}
	535
fcd22e3b FB	536	#ifdef CONFIG_PM
	537	static int bfin_suspend(struct device *dev)
	538	{
	539	struct bfin_glue *glue = dev_get_drvdata(dev);
	540	struct musb *musb = glue_to_musb(glue);
	541
	542	if (is_host_active(musb))
	543	/*
	544	* During hibernate gpio_vrsel will change from high to low
	545	* low which will generate wakeup event resume the system
	546	* immediately. Set it to 0 before hibernate to avoid this
	547	* wakeup event.
	548	*/
	549	gpio_set_value(musb->config->gpio_vrsel, 0);
	550
	551	return 0;
	552	}
	553
	554	static int bfin_resume(struct device *dev)
	555	{
	556	struct bfin_glue *glue = dev_get_drvdata(dev);
	557	struct musb *musb = glue_to_musb(glue);
	558
	559	bfin_musb_reg_init(musb);
	560
	561	return 0;
	562	}
fcd22e3b FB	563	#endif
fcd22e3b FB	564
0967313b DM	565	static SIMPLE_DEV_PM_OPS(bfin_pm_ops, bfin_suspend, bfin_resume);
0967313b DM	566
9cb0308e	567	static struct platform_driver bfin_driver = {
e9e8c85e	568	.probe = bfin_probe,
9cb0308e FB	569	.remove = __exit_p(bfin_remove),
9cb0308e FB	570	.driver = {
417ddf86	571	.name = "musb-blackfin",
0967313b	572	.pm = &bfin_pm_ops,
9cb0308e FB	573	},
	574	};
	575
	576	MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
	577	MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
	578	MODULE_LICENSE("GPL v2");
692373e1	579	module_platform_driver(bfin_driver);