[deliverable/linux.git] / drivers / usb / musb / blackfin.c

/*
 * MUSB OTG controller driver for Blackfin Processors
 *
 * Copyright 2006-2008 Analog Devices Inc.
 *
 * Enter bugs at http://blackfin.uclinux.org/
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>

#include <asm/cacheflush.h>

#include "musb_core.h"
#include "blackfin.h"

/*
 * Load an endpoint's FIFO
 */
void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
{
	void __iomem *fifo = hw_ep->fifo;
	void __iomem *epio = hw_ep->regs;
	u8 epnum = hw_ep->epnum;

	prefetch((u8 *)src);

	musb_writew(epio, MUSB_TXCOUNT, len);

	DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
			hw_ep->epnum, fifo, len, src, epio);

	dump_fifo_data(src, len);

	if (!ANOMALY_05000380 && epnum != 0) {
		u16 dma_reg;

		flush_dcache_range((unsigned long)src,
			(unsigned long)(src + len));

		/* Setup DMA address register */
		dma_reg = (u32)src;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
		SSYNC();

		dma_reg = (u32)src >> 16;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
		SSYNC();

		/* Setup DMA count register */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
		SSYNC();

		/* Enable the DMA */
		dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
		SSYNC();

		/* Wait for compelete */
		while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
			cpu_relax();

		/* acknowledge dma interrupt */
		bfin_write_USB_DMA_INTERRUPT(1 << epnum);
		SSYNC();

		/* Reset DMA */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
		SSYNC();
	} else {
		SSYNC();

		if (unlikely((unsigned long)src & 0x01))
			outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
		else
			outsw((unsigned long)fifo, src, (len + 1) >> 1);
	}
}
/*
 * Unload an endpoint's FIFO
 */
void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
{
	void __iomem *fifo = hw_ep->fifo;
	u8 epnum = hw_ep->epnum;

	if (ANOMALY_05000467 && epnum != 0) {
		u16 dma_reg;

		invalidate_dcache_range((unsigned long)dst,
			(unsigned long)(dst + len));

		/* Setup DMA address register */
		dma_reg = (u32)dst;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
		SSYNC();

		dma_reg = (u32)dst >> 16;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
		SSYNC();

		/* Setup DMA count register */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
		SSYNC();

		/* Enable the DMA */
		dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
		SSYNC();

		/* Wait for compelete */
		while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
			cpu_relax();

		/* acknowledge dma interrupt */
		bfin_write_USB_DMA_INTERRUPT(1 << epnum);
		SSYNC();

		/* Reset DMA */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
		SSYNC();
	} else {
		SSYNC();
		/* Read the last byte of packet with odd size from address fifo + 4
		 * to trigger 1 byte access to EP0 FIFO.
		 */
		if (len == 1)
			*dst = (u8)inw((unsigned long)fifo + 4);
		else {
			if (unlikely((unsigned long)dst & 0x01))
				insw_8((unsigned long)fifo, dst, len >> 1);
			else
				insw((unsigned long)fifo, dst, len >> 1);

			if (len & 0x01)
				*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
		}
	}
	DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
			'R', hw_ep->epnum, fifo, len, dst);

	dump_fifo_data(dst, len);
}

static irqreturn_t blackfin_interrupt(int irq, void *__hci)
{
	unsigned long	flags;
	irqreturn_t	retval = IRQ_NONE;
	struct musb	*musb = __hci;

	spin_lock_irqsave(&musb->lock, flags);

	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);

	if (musb->int_usb || musb->int_tx || musb->int_rx) {
		musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
		musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
		musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
		retval = musb_interrupt(musb);
	}

	/* Start sampling ID pin, when plug is removed from MUSB */
	if (is_otg_enabled(musb) && (musb->xceiv->state == OTG_STATE_B_IDLE
		|| musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
		musb->a_wait_bcon = TIMER_DELAY;
	}

	spin_unlock_irqrestore(&musb->lock, flags);

	return retval;
}

static void musb_conn_timer_handler(unsigned long _musb)
{
	struct musb *musb = (void *)_musb;
	unsigned long flags;
	u16 val;
	static u8 toggle;

	spin_lock_irqsave(&musb->lock, flags);
	switch (musb->xceiv->state) {
	case OTG_STATE_A_IDLE:
	case OTG_STATE_A_WAIT_BCON:
		/* Start a new session */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);
		val &= ~MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);
		val |= MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);
		/* Check if musb is host or peripheral. */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);

		if (!(val & MUSB_DEVCTL_BDEVICE)) {
			gpio_set_value(musb->config->gpio_vrsel, 1);
			musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
		} else {
			gpio_set_value(musb->config->gpio_vrsel, 0);
			/* Ignore VBUSERROR and SUSPEND IRQ */
			val = musb_readb(musb->mregs, MUSB_INTRUSBE);
			val &= ~MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSBE, val);

			val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSB, val);
			if (is_otg_enabled(musb))
				musb->xceiv->state = OTG_STATE_B_IDLE;
			else
				musb_writeb(musb->mregs, MUSB_POWER, MUSB_POWER_HSENAB);
		}
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
		break;
	case OTG_STATE_B_IDLE:

		if (!is_peripheral_enabled(musb))
			break;
		/* Start a new session.  It seems that MUSB needs taking
		 * some time to recognize the type of the plug inserted?
		 */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);
		val |= MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);
		val = musb_readw(musb->mregs, MUSB_DEVCTL);

		if (!(val & MUSB_DEVCTL_BDEVICE)) {
			gpio_set_value(musb->config->gpio_vrsel, 1);
			musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
		} else {
			gpio_set_value(musb->config->gpio_vrsel, 0);

			/* Ignore VBUSERROR and SUSPEND IRQ */
			val = musb_readb(musb->mregs, MUSB_INTRUSBE);
			val &= ~MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSBE, val);

			val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSB, val);

			/* Toggle the Soft Conn bit, so that we can response to
			 * the inserting of either A-plug or B-plug.
			 */
			if (toggle) {
				val = musb_readb(musb->mregs, MUSB_POWER);
				val &= ~MUSB_POWER_SOFTCONN;
				musb_writeb(musb->mregs, MUSB_POWER, val);
				toggle = 0;
			} else {
				val = musb_readb(musb->mregs, MUSB_POWER);
				val |= MUSB_POWER_SOFTCONN;
				musb_writeb(musb->mregs, MUSB_POWER, val);
				toggle = 1;
			}
			/* The delay time is set to 1/4 second by default,
			 * shortening it, if accelerating A-plug detection
			 * is needed in OTG mode.
			 */
			mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
		}
		break;
	default:
		DBG(1, "%s state not handled\n", otg_state_string(musb));
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);

	DBG(4, "state is %s\n", otg_state_string(musb));
}

static void bfin_musb_enable(struct musb *musb)
{
	if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
		musb->a_wait_bcon = TIMER_DELAY;
	}
}

static void bfin_musb_disable(struct musb *musb)
{
}

static void bfin_musb_set_vbus(struct musb *musb, int is_on)
{
	int value = musb->config->gpio_vrsel_active;
	if (!is_on)
		value = !value;
	gpio_set_value(musb->config->gpio_vrsel, value);

	DBG(1, "VBUS %s, devctl %02x "
		/* otg %3x conf %08x prcm %08x */ "\n",
		otg_state_string(musb),
		musb_readb(musb->mregs, MUSB_DEVCTL));
}

static int bfin_musb_set_power(struct otg_transceiver *x, unsigned mA)
{
	return 0;
}

static void bfin_musb_try_idle(struct musb *musb, unsigned long timeout)
{
	if (!is_otg_enabled(musb) && is_host_enabled(musb))
		mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
}

static int bfin_musb_get_vbus_status(struct musb *musb)
{
	return 0;
}

static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
{
	return -EIO;
}

static void bfin_musb_reg_init(struct musb *musb)
{
	if (ANOMALY_05000346) {
		bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
		SSYNC();
	}

	if (ANOMALY_05000347) {
		bfin_write_USB_APHY_CNTRL(0x0);
		SSYNC();
	}

	/* Configure PLL oscillator register */
	bfin_write_USB_PLLOSC_CTRL(0x30a8);
	SSYNC();

	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
	SSYNC();

	bfin_write_USB_EP_NI0_RXMAXP(64);
	SSYNC();

	bfin_write_USB_EP_NI0_TXMAXP(64);
	SSYNC();

	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
	bfin_write_USB_GLOBINTR(0x7);
	SSYNC();

	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
				EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
				EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
				EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
				EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
	SSYNC();
}

static int bfin_musb_init(struct musb *musb)
{

	/*
	 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
	 * and OTG HOST modes, while rev 1.1 and greater require PE7 to
	 * be low for DEVICE mode and high for HOST mode. We set it high
	 * here because we are in host mode
	 */

	if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
		printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
			musb->config->gpio_vrsel);
		return -ENODEV;
	}
	gpio_direction_output(musb->config->gpio_vrsel, 0);

	usb_nop_xceiv_register();
	musb->xceiv = otg_get_transceiver();
	if (!musb->xceiv) {
		gpio_free(musb->config->gpio_vrsel);
		return -ENODEV;
	}

	bfin_musb_reg_init(musb);

	if (is_host_enabled(musb)) {
		musb->board_set_vbus = bfin_musb_set_vbus;
		setup_timer(&musb_conn_timer,
			musb_conn_timer_handler, (unsigned long) musb);
	}
	if (is_peripheral_enabled(musb))
		musb->xceiv->set_power = bfin_musb_set_power;

	musb->isr = blackfin_interrupt;

	return 0;
}

#ifdef CONFIG_PM
void musb_platform_save_context(struct musb *musb,
			struct musb_context_registers *musb_context)
{
	if (is_host_active(musb))
		/*
		 * During hibernate gpio_vrsel will change from high to low
		 * low which will generate wakeup event resume the system
		 * immediately.  Set it to 0 before hibernate to avoid this
		 * wakeup event.
		 */
		gpio_set_value(musb->config->gpio_vrsel, 0);
}

void musb_platform_restore_context(struct musb *musb,
			struct musb_context_registers *musb_context)
{
	bfin_musb_reg_init(musb);
}
#endif

static int bfin_musb_exit(struct musb *musb)
{
	gpio_free(musb->config->gpio_vrsel);

	otg_put_transceiver(musb->xceiv);
	usb_nop_xceiv_unregister();
	return 0;
}

const struct musb_platform_ops musb_ops = {
	.init		= bfin_musb_init,
	.exit		= bfin_musb_exit,

	.enable		= bfin_musb_enable,
	.disable	= bfin_musb_disable,

	.set_mode	= bfin_musb_set_mode,
	.try_idle	= bfin_musb_try_idle,

	.vbus_status	= bfin_musb_vbus_status,
	.set_vbus	= bfin_musb_set_vbus,
};

static u64 bfin_dmamask = DMA_BIT_MASK(32);

static int __init bfin_probe(struct platform_device *pdev)
{
	struct musb_hdrc_platform_data	*pdata = pdev->dev.platform_data;
	struct platform_device		*musb;

	int				ret = -ENOMEM;

	musb = platform_device_alloc("musb-hdrc", -1);
	if (!musb) {
		dev_err(&pdev->dev, "failed to allocate musb device\n");
		goto err0;
	}

	musb->dev.parent		= &pdev->dev;
	musb->dev.dma_mask		= &bfin_dmamask;
	musb->dev.coherent_dma_mask	= bfin_dmamask;

	platform_set_drvdata(pdev, musb);

	ret = platform_device_add_resources(musb, pdev->resource,
			pdev->num_resources);
	if (ret) {
		dev_err(&pdev->dev, "failed to add resources\n");
		goto err1;
	}

	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	if (ret) {
		dev_err(&pdev->dev, "failed to add platform_data\n");
		goto err1;
	}

	ret = platform_device_add(musb);
	if (ret) {
		dev_err(&pdev->dev, "failed to register musb device\n");
		goto err1;
	}

	return 0;

err1:
	platform_device_put(musb);

err0:
	return ret;
}

static int __exit bfin_remove(struct platform_device *pdev)
{
	struct platform_device		*musb = platform_get_drvdata(pdev);

	platform_device_del(musb);
	platform_device_put(musb);

	return 0;
}

static struct platform_driver bfin_driver = {
	.remove		= __exit_p(bfin_remove),
	.driver		= {
		.name	= "musb-bfin",
	},
};

MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
MODULE_LICENSE("GPL v2");

static int __init bfin_init(void)
{
	return platform_driver_probe(&bfin_driver, bfin_probe);
}
subsys_initcall(bfin_init);

static void __exit bfin_exit(void)
{
	platform_driver_unregister(&bfin_driver);
}
module_exit(bfin_exit);
Commit	Line	Data
0c6a8818 BW	1	/*
	2	* MUSB OTG controller driver for Blackfin Processors
	3	*
	4	* Copyright 2006-2008 Analog Devices Inc.
	5	*
	6	* Enter bugs at http://blackfin.uclinux.org/
	7	*
	8	* Licensed under the GPL-2 or later.
	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/kernel.h>
	13	#include <linux/sched.h>
0c6a8818 BW	14	#include <linux/init.h>
0c6a8818 BW	15	#include <linux/list.h>
0c6a8818 BW	16	#include <linux/gpio.h>
0c6a8818 BW	17	#include <linux/io.h>
9cb0308e FB	18	#include <linux/platform_device.h>
9cb0308e FB	19	#include <linux/dma-mapping.h>
0c6a8818 BW	20
	21	#include <asm/cacheflush.h>
	22
	23	#include "musb_core.h"
	24	#include "blackfin.h"
	25
	26	/*
	27	* Load an endpoint's FIFO
	28	*/
	29	void musb_write_fifo(struct musb_hw_ep hw_ep, u16 len, const u8 src)
	30	{
	31	void __iomem *fifo = hw_ep->fifo;
	32	void __iomem *epio = hw_ep->regs;
1c4bdc01	33	u8 epnum = hw_ep->epnum;
0c6a8818 BW	34
	35	prefetch((u8 *)src);
	36
	37	musb_writew(epio, MUSB_TXCOUNT, len);
	38
	39	DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
	40	hw_ep->epnum, fifo, len, src, epio);
	41
	42	dump_fifo_data(src, len);
	43
1c4bdc01	44	if (!ANOMALY_05000380 && epnum != 0) {
1ca9e9ca BW	45	u16 dma_reg;
	46
	47	flush_dcache_range((unsigned long)src,
	48	(unsigned long)(src + len));
1c4bdc01 BW	49
1c4bdc01 BW	50	/* Setup DMA address register */
1ca9e9ca	51	dma_reg = (u32)src;
1c4bdc01 BW	52	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
	53	SSYNC();
	54
1ca9e9ca	55	dma_reg = (u32)src >> 16;
1c4bdc01 BW	56	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
	57	SSYNC();
	58
	59	/* Setup DMA count register */
	60	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
	61	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
	62	SSYNC();
	63
	64	/* Enable the DMA */
	65	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA \| DIRECTION;
	66	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
	67	SSYNC();
	68
	69	/* Wait for compelete */
	70	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
	71	cpu_relax();
	72
	73	/* acknowledge dma interrupt */
	74	bfin_write_USB_DMA_INTERRUPT(1 << epnum);
	75	SSYNC();
	76
	77	/* Reset DMA */
	78	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
	79	SSYNC();
	80	} else {
	81	SSYNC();
	82
	83	if (unlikely((unsigned long)src & 0x01))
1ca9e9ca	84	outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
1c4bdc01	85	else
1ca9e9ca	86	outsw((unsigned long)fifo, src, (len + 1) >> 1);
1c4bdc01	87	}
0c6a8818	88	}
0c6a8818 BW	89	/*
	90	* Unload an endpoint's FIFO
	91	*/
	92	void musb_read_fifo(struct musb_hw_ep hw_ep, u16 len, u8 dst)
	93	{
	94	void __iomem *fifo = hw_ep->fifo;
	95	u8 epnum = hw_ep->epnum;
0c6a8818	96
1c4bdc01	97	if (ANOMALY_05000467 && epnum != 0) {
1ca9e9ca	98	u16 dma_reg;
1c4bdc01	99
1ca9e9ca BW	100	invalidate_dcache_range((unsigned long)dst,
1ca9e9ca BW	101	(unsigned long)(dst + len));
1c4bdc01 BW	102
1c4bdc01 BW	103	/* Setup DMA address register */
1ca9e9ca	104	dma_reg = (u32)dst;
1c4bdc01 BW	105	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
	106	SSYNC();
	107
1ca9e9ca	108	dma_reg = (u32)dst >> 16;
1c4bdc01 BW	109	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
	110	SSYNC();
	111
	112	/* Setup DMA count register */
	113	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
	114	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
	115	SSYNC();
	116
	117	/* Enable the DMA */
	118	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA;
	119	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
	120	SSYNC();
	121
	122	/* Wait for compelete */
	123	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
	124	cpu_relax();
	125
	126	/* acknowledge dma interrupt */
	127	bfin_write_USB_DMA_INTERRUPT(1 << epnum);
	128	SSYNC();
	129
	130	/* Reset DMA */
	131	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
	132	SSYNC();
	133	} else {
	134	SSYNC();
	135	/* Read the last byte of packet with odd size from address fifo + 4
	136	* to trigger 1 byte access to EP0 FIFO.
	137	*/
	138	if (len == 1)
	139	*dst = (u8)inw((unsigned long)fifo + 4);
	140	else {
	141	if (unlikely((unsigned long)dst & 0x01))
	142	insw_8((unsigned long)fifo, dst, len >> 1);
	143	else
	144	insw((unsigned long)fifo, dst, len >> 1);
	145
	146	if (len & 0x01)
	147	*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
	148	}
	149	}
04f4086f MF	150	DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
	151	'R', hw_ep->epnum, fifo, len, dst);
	152
0c6a8818 BW	153	dump_fifo_data(dst, len);
	154	}
	155
	156	static irqreturn_t blackfin_interrupt(int irq, void *__hci)
	157	{
	158	unsigned long flags;
	159	irqreturn_t retval = IRQ_NONE;
	160	struct musb *musb = __hci;
	161
	162	spin_lock_irqsave(&musb->lock, flags);
	163
	164	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
	165	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
	166	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
	167
	168	if (musb->int_usb \|\| musb->int_tx \|\| musb->int_rx) {
	169	musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
	170	musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
	171	musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
	172	retval = musb_interrupt(musb);
	173	}
	174
ff927add CC	175	/* Start sampling ID pin, when plug is removed from MUSB */
	176	if (is_otg_enabled(musb) && (musb->xceiv->state == OTG_STATE_B_IDLE
	177	\|\| musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
	178	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	179	musb->a_wait_bcon = TIMER_DELAY;
	180	}
	181
0c6a8818 BW	182	spin_unlock_irqrestore(&musb->lock, flags);
0c6a8818 BW	183
2f831751	184	return retval;
0c6a8818 BW	185	}
	186
	187	static void musb_conn_timer_handler(unsigned long _musb)
	188	{
	189	struct musb musb = (void )_musb;
	190	unsigned long flags;
	191	u16 val;
ff927add	192	static u8 toggle;
0c6a8818 BW	193
0c6a8818 BW	194	spin_lock_irqsave(&musb->lock, flags);
84e250ff	195	switch (musb->xceiv->state) {
0c6a8818 BW	196	case OTG_STATE_A_IDLE:
	197	case OTG_STATE_A_WAIT_BCON:
	198	/* Start a new session */
	199	val = musb_readw(musb->mregs, MUSB_DEVCTL);
ff927add CC	200	val &= ~MUSB_DEVCTL_SESSION;
ff927add CC	201	musb_writew(musb->mregs, MUSB_DEVCTL, val);
0c6a8818 BW	202	val \|= MUSB_DEVCTL_SESSION;
0c6a8818 BW	203	musb_writew(musb->mregs, MUSB_DEVCTL, val);
ff927add CC	204	/* Check if musb is host or peripheral. */
	205	val = musb_readw(musb->mregs, MUSB_DEVCTL);
	206
	207	if (!(val & MUSB_DEVCTL_BDEVICE)) {
	208	gpio_set_value(musb->config->gpio_vrsel, 1);
	209	musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
	210	} else {
	211	gpio_set_value(musb->config->gpio_vrsel, 0);
	212	/* Ignore VBUSERROR and SUSPEND IRQ */
	213	val = musb_readb(musb->mregs, MUSB_INTRUSBE);
	214	val &= ~MUSB_INTR_VBUSERROR;
	215	musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
	216
	217	val = MUSB_INTR_SUSPEND \| MUSB_INTR_VBUSERROR;
	218	musb_writeb(musb->mregs, MUSB_INTRUSB, val);
	219	if (is_otg_enabled(musb))
	220	musb->xceiv->state = OTG_STATE_B_IDLE;
	221	else
	222	musb_writeb(musb->mregs, MUSB_POWER, MUSB_POWER_HSENAB);
	223	}
	224	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	225	break;
	226	case OTG_STATE_B_IDLE:
0c6a8818	227
ff927add CC	228	if (!is_peripheral_enabled(musb))
	229	break;
	230	/* Start a new session. It seems that MUSB needs taking
	231	* some time to recognize the type of the plug inserted?
	232	*/
	233	val = musb_readw(musb->mregs, MUSB_DEVCTL);
	234	val \|= MUSB_DEVCTL_SESSION;
	235	musb_writew(musb->mregs, MUSB_DEVCTL, val);
0c6a8818	236	val = musb_readw(musb->mregs, MUSB_DEVCTL);
ff927add	237
0c6a8818 BW	238	if (!(val & MUSB_DEVCTL_BDEVICE)) {
0c6a8818 BW	239	gpio_set_value(musb->config->gpio_vrsel, 1);
84e250ff	240	musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
0c6a8818 BW	241	} else {
	242	gpio_set_value(musb->config->gpio_vrsel, 0);
	243
	244	/* Ignore VBUSERROR and SUSPEND IRQ */
	245	val = musb_readb(musb->mregs, MUSB_INTRUSBE);
	246	val &= ~MUSB_INTR_VBUSERROR;
	247	musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
	248
	249	val = MUSB_INTR_SUSPEND \| MUSB_INTR_VBUSERROR;
	250	musb_writeb(musb->mregs, MUSB_INTRUSB, val);
	251
ff927add CC	252	/* Toggle the Soft Conn bit, so that we can response to
	253	* the inserting of either A-plug or B-plug.
	254	*/
	255	if (toggle) {
	256	val = musb_readb(musb->mregs, MUSB_POWER);
	257	val &= ~MUSB_POWER_SOFTCONN;
	258	musb_writeb(musb->mregs, MUSB_POWER, val);
	259	toggle = 0;
	260	} else {
	261	val = musb_readb(musb->mregs, MUSB_POWER);
	262	val \|= MUSB_POWER_SOFTCONN;
	263	musb_writeb(musb->mregs, MUSB_POWER, val);
	264	toggle = 1;
	265	}
	266	/* The delay time is set to 1/4 second by default,
	267	* shortening it, if accelerating A-plug detection
	268	* is needed in OTG mode.
	269	*/
	270	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
0c6a8818	271	}
0c6a8818	272	break;
0c6a8818 BW	273	default:
	274	DBG(1, "%s state not handled\n", otg_state_string(musb));
	275	break;
	276	}
	277	spin_unlock_irqrestore(&musb->lock, flags);
	278
	279	DBG(4, "state is %s\n", otg_state_string(musb));
	280	}
	281
743411b3	282	static void bfin_musb_enable(struct musb *musb)
0c6a8818	283	{
ff927add	284	if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
0c6a8818 BW	285	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	286	musb->a_wait_bcon = TIMER_DELAY;
	287	}
	288	}
	289
743411b3	290	static void bfin_musb_disable(struct musb *musb)
0c6a8818 BW	291	{
	292	}
	293
743411b3	294	static void bfin_musb_set_vbus(struct musb *musb, int is_on)
0c6a8818	295	{
6ddc6dae CC	296	int value = musb->config->gpio_vrsel_active;
	297	if (!is_on)
	298	value = !value;
	299	gpio_set_value(musb->config->gpio_vrsel, value);
0c6a8818 BW	300
	301	DBG(1, "VBUS %s, devctl %02x "
	302	/* otg %3x conf %08x prcm %08x */ "\n",
	303	otg_state_string(musb),
	304	musb_readb(musb->mregs, MUSB_DEVCTL));
	305	}
	306
743411b3	307	static int bfin_musb_set_power(struct otg_transceiver *x, unsigned mA)
0c6a8818 BW	308	{
	309	return 0;
	310	}
	311
743411b3	312	static void bfin_musb_try_idle(struct musb *musb, unsigned long timeout)
0c6a8818	313	{
ff927add	314	if (!is_otg_enabled(musb) && is_host_enabled(musb))
0c6a8818 BW	315	mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
	316	}
	317
743411b3	318	static int bfin_musb_get_vbus_status(struct musb *musb)
0c6a8818 BW	319	{
	320	return 0;
	321	}
	322
743411b3	323	static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
0c6a8818	324	{
2002e768	325	return -EIO;
0c6a8818 BW	326	}
0c6a8818 BW	327
743411b3	328	static void bfin_musb_reg_init(struct musb *musb)
0c6a8818	329	{
d426e60d RG	330	if (ANOMALY_05000346) {
	331	bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
	332	SSYNC();
	333	}
0c6a8818	334
d426e60d RG	335	if (ANOMALY_05000347) {
	336	bfin_write_USB_APHY_CNTRL(0x0);
	337	SSYNC();
	338	}
0c6a8818	339
0c6a8818 BW	340	/* Configure PLL oscillator register */
	341	bfin_write_USB_PLLOSC_CTRL(0x30a8);
	342	SSYNC();
	343
	344	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
	345	SSYNC();
	346
	347	bfin_write_USB_EP_NI0_RXMAXP(64);
	348	SSYNC();
	349
	350	bfin_write_USB_EP_NI0_TXMAXP(64);
	351	SSYNC();
	352
	353	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
	354	bfin_write_USB_GLOBINTR(0x7);
	355	SSYNC();
	356
	357	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA \| EP1_TX_ENA \| EP2_TX_ENA \|
	358	EP3_TX_ENA \| EP4_TX_ENA \| EP5_TX_ENA \|
	359	EP6_TX_ENA \| EP7_TX_ENA \| EP1_RX_ENA \|
	360	EP2_RX_ENA \| EP3_RX_ENA \| EP4_RX_ENA \|
	361	EP5_RX_ENA \| EP6_RX_ENA \| EP7_RX_ENA);
	362	SSYNC();
743411b3 FB	363	}
	364
	365	static int bfin_musb_init(struct musb *musb)
	366	{
	367
	368	/*
	369	* Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
	370	* and OTG HOST modes, while rev 1.1 and greater require PE7 to
	371	* be low for DEVICE mode and high for HOST mode. We set it high
	372	* here because we are in host mode
	373	*/
	374
	375	if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
	376	printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
	377	musb->config->gpio_vrsel);
	378	return -ENODEV;
	379	}
	380	gpio_direction_output(musb->config->gpio_vrsel, 0);
	381
	382	usb_nop_xceiv_register();
	383	musb->xceiv = otg_get_transceiver();
	384	if (!musb->xceiv) {
	385	gpio_free(musb->config->gpio_vrsel);
	386	return -ENODEV;
	387	}
	388
	389	bfin_musb_reg_init(musb);
0c6a8818 BW	390
0c6a8818 BW	391	if (is_host_enabled(musb)) {
743411b3	392	musb->board_set_vbus = bfin_musb_set_vbus;
0c6a8818 BW	393	setup_timer(&musb_conn_timer,
	394	musb_conn_timer_handler, (unsigned long) musb);
	395	}
	396	if (is_peripheral_enabled(musb))
743411b3	397	musb->xceiv->set_power = bfin_musb_set_power;
0c6a8818 BW	398
	399	musb->isr = blackfin_interrupt;
	400
	401	return 0;
	402	}
	403
743411b3 FB	404	#ifdef CONFIG_PM
	405	void musb_platform_save_context(struct musb *musb,
	406	struct musb_context_registers *musb_context)
	407	{
	408	if (is_host_active(musb))
	409	/*
	410	* During hibernate gpio_vrsel will change from high to low
	411	* low which will generate wakeup event resume the system
	412	* immediately. Set it to 0 before hibernate to avoid this
	413	* wakeup event.
	414	*/
	415	gpio_set_value(musb->config->gpio_vrsel, 0);
	416	}
	417
	418	void musb_platform_restore_context(struct musb *musb,
	419	struct musb_context_registers *musb_context)
	420	{
	421	bfin_musb_reg_init(musb);
	422	}
	423	#endif
	424
	425	static int bfin_musb_exit(struct musb *musb)
0c6a8818	426	{
0c6a8818	427	gpio_free(musb->config->gpio_vrsel);
0c6a8818	428
f4053874	429	otg_put_transceiver(musb->xceiv);
3daad24d	430	usb_nop_xceiv_unregister();
0c6a8818 BW	431	return 0;
0c6a8818 BW	432	}
743411b3 FB	433
	434	const struct musb_platform_ops musb_ops = {
	435	.init = bfin_musb_init,
	436	.exit = bfin_musb_exit,
	437
	438	.enable = bfin_musb_enable,
	439	.disable = bfin_musb_disable,
	440
	441	.set_mode = bfin_musb_set_mode,
	442	.try_idle = bfin_musb_try_idle,
	443
	444	.vbus_status = bfin_musb_vbus_status,
	445	.set_vbus = bfin_musb_set_vbus,
	446	};
9cb0308e FB	447
	448	static u64 bfin_dmamask = DMA_BIT_MASK(32);
	449
	450	static int __init bfin_probe(struct platform_device *pdev)
	451	{
	452	struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
	453	struct platform_device *musb;
	454
	455	int ret = -ENOMEM;
	456
	457	musb = platform_device_alloc("musb-hdrc", -1);
	458	if (!musb) {
	459	dev_err(&pdev->dev, "failed to allocate musb device\n");
	460	goto err0;
	461	}
	462
	463	musb->dev.parent = &pdev->dev;
	464	musb->dev.dma_mask = &bfin_dmamask;
	465	musb->dev.coherent_dma_mask = bfin_dmamask;
	466
	467	platform_set_drvdata(pdev, musb);
	468
	469	ret = platform_device_add_resources(musb, pdev->resource,
	470	pdev->num_resources);
	471	if (ret) {
	472	dev_err(&pdev->dev, "failed to add resources\n");
	473	goto err1;
	474	}
	475
	476	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	477	if (ret) {
	478	dev_err(&pdev->dev, "failed to add platform_data\n");
	479	goto err1;
	480	}
	481
	482	ret = platform_device_add(musb);
	483	if (ret) {
	484	dev_err(&pdev->dev, "failed to register musb device\n");
	485	goto err1;
	486	}
	487
	488	return 0;
	489
	490	err1:
	491	platform_device_put(musb);
	492
	493	err0:
	494	return ret;
	495	}
	496
	497	static int __exit bfin_remove(struct platform_device *pdev)
	498	{
	499	struct platform_device *musb = platform_get_drvdata(pdev);
	500
	501	platform_device_del(musb);
	502	platform_device_put(musb);
	503
	504	return 0;
	505	}
	506
	507	static struct platform_driver bfin_driver = {
	508	.remove = __exit_p(bfin_remove),
	509	.driver = {
	510	.name = "musb-bfin",
511	},
512	};
513
514	MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
515	MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
516	MODULE_LICENSE("GPL v2");
517
518	static int __init bfin_init(void)
519	{
520	return platform_driver_probe(&bfin_driver, bfin_probe);
521	}
522	subsys_initcall(bfin_init);
523
524	static void __exit bfin_exit(void)
525	{
526	platform_driver_unregister(&bfin_driver);
527	}
528	module_exit(bfin_exit);