[deliverable/linux.git] / drivers / usb / musb / da8xx.c

/*
 * Texas Instruments DA8xx/OMAP-L1x "glue layer"
 *
 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
 *
 * Based on the DaVinci "glue layer" code.
 * Copyright (C) 2005-2006 by Texas Instruments
 *
 * This file is part of the Inventra Controller Driver for Linux.
 *
 * The Inventra Controller Driver for Linux is free software; you
 * can redistribute it and/or modify it under the terms of the GNU
 * General Public License version 2 as published by the Free Software
 * Foundation.
 *
 * The Inventra Controller Driver for Linux is distributed in
 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
 * without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
 * License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with The Inventra Controller Driver for Linux ; if not,
 * write to the Free Software Foundation, Inc., 59 Temple Place,
 * Suite 330, Boston, MA  02111-1307  USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>

#include <mach/da8xx.h>
#include <linux/platform_data/usb-davinci.h>

#include "musb_core.h"

/*
 * DA8XX specific definitions
 */

/* USB 2.0 OTG module registers */
#define DA8XX_USB_REVISION_REG	0x00
#define DA8XX_USB_CTRL_REG	0x04
#define DA8XX_USB_STAT_REG	0x08
#define DA8XX_USB_EMULATION_REG 0x0c
#define DA8XX_USB_MODE_REG	0x10	/* Transparent, CDC, [Generic] RNDIS */
#define DA8XX_USB_AUTOREQ_REG	0x14
#define DA8XX_USB_SRP_FIX_TIME_REG 0x18
#define DA8XX_USB_TEARDOWN_REG	0x1c
#define DA8XX_USB_INTR_SRC_REG	0x20
#define DA8XX_USB_INTR_SRC_SET_REG 0x24
#define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
#define DA8XX_USB_INTR_MASK_REG 0x2c
#define DA8XX_USB_INTR_MASK_SET_REG 0x30
#define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
#define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
#define DA8XX_USB_END_OF_INTR_REG 0x3c
#define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))

/* Control register bits */
#define DA8XX_SOFT_RESET_MASK	1

#define DA8XX_USB_TX_EP_MASK	0x1f		/* EP0 + 4 Tx EPs */
#define DA8XX_USB_RX_EP_MASK	0x1e		/* 4 Rx EPs */

/* USB interrupt register bits */
#define DA8XX_INTR_USB_SHIFT	16
#define DA8XX_INTR_USB_MASK	(0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
					/* interrupts and DRVVBUS interrupt */
#define DA8XX_INTR_DRVVBUS	0x100
#define DA8XX_INTR_RX_SHIFT	8
#define DA8XX_INTR_RX_MASK	(DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
#define DA8XX_INTR_TX_SHIFT	0
#define DA8XX_INTR_TX_MASK	(DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)

#define DA8XX_MENTOR_CORE_OFFSET 0x400

#define CFGCHIP2	IO_ADDRESS(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG)

struct da8xx_glue {
	struct device		*dev;
	struct platform_device	*musb;
	struct clk		*clk;
};

/*
 * REVISIT (PM): we should be able to keep the PHY in low power mode most
 * of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0
 * and, when in host mode, autosuspending idle root ports... PHY_PLLON
 * (overriding SUSPENDM?) then likely needs to stay off.
 */

static inline void phy_on(void)
{
	u32 cfgchip2 = __raw_readl(CFGCHIP2);

	/*
	 * Start the on-chip PHY and its PLL.
	 */
	cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);
	cfgchip2 |= CFGCHIP2_PHY_PLLON;
	__raw_writel(cfgchip2, CFGCHIP2);

	pr_info("Waiting for USB PHY clock good...\n");
	while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
		cpu_relax();
}

static inline void phy_off(void)
{
	u32 cfgchip2 = __raw_readl(CFGCHIP2);

	/*
	 * Ensure that USB 1.1 reference clock is not being sourced from
	 * USB 2.0 PHY.  Otherwise do not power down the PHY.
	 */
	if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX) &&
	     (cfgchip2 & CFGCHIP2_USB1SUSPENDM)) {
		pr_warning("USB 1.1 clocked from USB 2.0 PHY -- "
			   "can't power it down\n");
		return;
	}

	/*
	 * Power down the on-chip PHY.
	 */
	cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
	__raw_writel(cfgchip2, CFGCHIP2);
}

/*
 * Because we don't set CTRL.UINT, it's "important" to:
 *	- not read/write INTRUSB/INTRUSBE (except during
 *	  initial setup, as a workaround);
 *	- use INTSET/INTCLR instead.
 */

/**
 * da8xx_musb_enable - enable interrupts
 */
static void da8xx_musb_enable(struct musb *musb)
{
	void __iomem *reg_base = musb->ctrl_base;
	u32 mask;

	/* Workaround: setup IRQs through both register sets. */
	mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) |
	       ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) |
	       DA8XX_INTR_USB_MASK;
	musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);

	/* Force the DRVVBUS IRQ so we can start polling for ID change. */
	if (is_otg_enabled(musb))
		musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
			    DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
}

/**
 * da8xx_musb_disable - disable HDRC and flush interrupts
 */
static void da8xx_musb_disable(struct musb *musb)
{
	void __iomem *reg_base = musb->ctrl_base;

	musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
		    DA8XX_INTR_USB_MASK |
		    DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK);
	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
	musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
}

#define portstate(stmt)		stmt

static void da8xx_musb_set_vbus(struct musb *musb, int is_on)
{
	WARN_ON(is_on && is_peripheral_active(musb));
}

#define	POLL_SECONDS	2

static struct timer_list otg_workaround;

static void otg_timer(unsigned long _musb)
{
	struct musb		*musb = (void *)_musb;
	void __iomem		*mregs = musb->mregs;
	u8			devctl;
	unsigned long		flags;

	/*
	 * We poll because DaVinci's won't expose several OTG-critical
	 * status change events (from the transceiver) otherwise.
	 */
	devctl = musb_readb(mregs, MUSB_DEVCTL);
	dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
		otg_state_string(musb->xceiv->state));

	spin_lock_irqsave(&musb->lock, flags);
	switch (musb->xceiv->state) {
	case OTG_STATE_A_WAIT_BCON:
		devctl &= ~MUSB_DEVCTL_SESSION;
		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);

		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
		if (devctl & MUSB_DEVCTL_BDEVICE) {
			musb->xceiv->state = OTG_STATE_B_IDLE;
			MUSB_DEV_MODE(musb);
		} else {
			musb->xceiv->state = OTG_STATE_A_IDLE;
			MUSB_HST_MODE(musb);
		}
		break;
	case OTG_STATE_A_WAIT_VFALL:
		/*
		 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
		 * RTL seems to mis-handle session "start" otherwise (or in
		 * our case "recover"), in routine "VBUS was valid by the time
		 * VBUSERR got reported during enumeration" cases.
		 */
		if (devctl & MUSB_DEVCTL_VBUS) {
			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
			break;
		}
		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
		musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG,
			    MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT);
		break;
	case OTG_STATE_B_IDLE:
		if (!is_peripheral_enabled(musb))
			break;

		/*
		 * There's no ID-changed IRQ, so we have no good way to tell
		 * when to switch to the A-Default state machine (by setting
		 * the DEVCTL.Session bit).
		 *
		 * Workaround:  whenever we're in B_IDLE, try setting the
		 * session flag every few seconds.  If it works, ID was
		 * grounded and we're now in the A-Default state machine.
		 *
		 * NOTE: setting the session flag is _supposed_ to trigger
		 * SRP but clearly it doesn't.
		 */
		musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION);
		devctl = musb_readb(mregs, MUSB_DEVCTL);
		if (devctl & MUSB_DEVCTL_BDEVICE)
			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
		else
			musb->xceiv->state = OTG_STATE_A_IDLE;
		break;
	default:
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);
}

static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout)
{
	static unsigned long last_timer;

	if (!is_otg_enabled(musb))
		return;

	if (timeout == 0)
		timeout = jiffies + msecs_to_jiffies(3);

	/* Never idle if active, or when VBUS timeout is not set as host */
	if (musb->is_active || (musb->a_wait_bcon == 0 &&
				musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
		dev_dbg(musb->controller, "%s active, deleting timer\n",
			otg_state_string(musb->xceiv->state));
		del_timer(&otg_workaround);
		last_timer = jiffies;
		return;
	}

	if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
		dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
		return;
	}
	last_timer = timeout;

	dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
		otg_state_string(musb->xceiv->state),
		jiffies_to_msecs(timeout - jiffies));
	mod_timer(&otg_workaround, timeout);
}

static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
{
	struct musb		*musb = hci;
	void __iomem		*reg_base = musb->ctrl_base;
	struct usb_otg		*otg = musb->xceiv->otg;
	unsigned long		flags;
	irqreturn_t		ret = IRQ_NONE;
	u32			status;

	spin_lock_irqsave(&musb->lock, flags);

	/*
	 * NOTE: DA8XX shadows the Mentor IRQs.  Don't manage them through
	 * the Mentor registers (except for setup), use the TI ones and EOI.
	 */

	/* Acknowledge and handle non-CPPI interrupts */
	status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
	if (!status)
		goto eoi;

	musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
	dev_dbg(musb->controller, "USB IRQ %08x\n", status);

	musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
	musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
	musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;

	/*
	 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
	 * DA8xx's missing ID change IRQ.  We need an ID change IRQ to
	 * switch appropriately between halves of the OTG state machine.
	 * Managing DEVCTL.Session per Mentor docs requires that we know its
	 * value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
	 * Also, DRVVBUS pulses for SRP (but not at 5 V)...
	 */
	if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
		int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
		void __iomem *mregs = musb->mregs;
		u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
		int err;

		err = is_host_enabled(musb) && (musb->int_usb &
						MUSB_INTR_VBUSERROR);
		if (err) {
			/*
			 * The Mentor core doesn't debounce VBUS as needed
			 * to cope with device connect current spikes. This
			 * means it's not uncommon for bus-powered devices
			 * to get VBUS errors during enumeration.
			 *
			 * This is a workaround, but newer RTL from Mentor
			 * seems to allow a better one: "re"-starting sessions
			 * without waiting for VBUS to stop registering in
			 * devctl.
			 */
			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
			WARNING("VBUS error workaround (delay coming)\n");
		} else if (is_host_enabled(musb) && drvvbus) {
			MUSB_HST_MODE(musb);
			otg->default_a = 1;
			musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
			portstate(musb->port1_status |= USB_PORT_STAT_POWER);
			del_timer(&otg_workaround);
		} else {
			musb->is_active = 0;
			MUSB_DEV_MODE(musb);
			otg->default_a = 0;
			musb->xceiv->state = OTG_STATE_B_IDLE;
			portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
		}

		dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
				drvvbus ? "on" : "off",
				otg_state_string(musb->xceiv->state),
				err ? " ERROR" : "",
				devctl);
		ret = IRQ_HANDLED;
	}

	if (musb->int_tx || musb->int_rx || musb->int_usb)
		ret |= musb_interrupt(musb);

 eoi:
	/* EOI needs to be written for the IRQ to be re-asserted. */
	if (ret == IRQ_HANDLED || status)
		musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);

	/* Poll for ID change */
	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
		mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);

	spin_unlock_irqrestore(&musb->lock, flags);

	return ret;
}

static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode)
{
	u32 cfgchip2 = __raw_readl(CFGCHIP2);

	cfgchip2 &= ~CFGCHIP2_OTGMODE;
	switch (musb_mode) {
	case MUSB_HOST:		/* Force VBUS valid, ID = 0 */
		cfgchip2 |= CFGCHIP2_FORCE_HOST;
		break;
	case MUSB_PERIPHERAL:	/* Force VBUS valid, ID = 1 */
		cfgchip2 |= CFGCHIP2_FORCE_DEVICE;
		break;
	case MUSB_OTG:		/* Don't override the VBUS/ID comparators */
		cfgchip2 |= CFGCHIP2_NO_OVERRIDE;
		break;
	default:
		dev_dbg(musb->controller, "Trying to set unsupported mode %u\n", musb_mode);
	}

	__raw_writel(cfgchip2, CFGCHIP2);
	return 0;
}

static int da8xx_musb_init(struct musb *musb)
{
	void __iomem *reg_base = musb->ctrl_base;
	u32 rev;

	musb->mregs += DA8XX_MENTOR_CORE_OFFSET;

	/* Returns zero if e.g. not clocked */
	rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG);
	if (!rev)
		goto fail;

	usb_nop_xceiv_register();
	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
	if (IS_ERR_OR_NULL(musb->xceiv))
		goto fail;

	if (is_host_enabled(musb))
		setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);

	/* Reset the controller */
	musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);

	/* Start the on-chip PHY and its PLL. */
	phy_on();

	msleep(5);

	/* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
	pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n",
		 rev, __raw_readl(CFGCHIP2),
		 musb_readb(reg_base, DA8XX_USB_CTRL_REG));

	musb->isr = da8xx_musb_interrupt;
	return 0;
fail:
	return -ENODEV;
}

static int da8xx_musb_exit(struct musb *musb)
{
	if (is_host_enabled(musb))
		del_timer_sync(&otg_workaround);

	phy_off();

	usb_put_phy(musb->xceiv);
	usb_nop_xceiv_unregister();

	return 0;
}

static const struct musb_platform_ops da8xx_ops = {
	.init		= da8xx_musb_init,
	.exit		= da8xx_musb_exit,

	.enable		= da8xx_musb_enable,
	.disable	= da8xx_musb_disable,

	.set_mode	= da8xx_musb_set_mode,
	.try_idle	= da8xx_musb_try_idle,

	.set_vbus	= da8xx_musb_set_vbus,
};

static u64 da8xx_dmamask = DMA_BIT_MASK(32);

static int __devinit da8xx_probe(struct platform_device *pdev)
{
	struct musb_hdrc_platform_data	*pdata = pdev->dev.platform_data;
	struct platform_device		*musb;
	struct da8xx_glue		*glue;

	struct clk			*clk;

	int				ret = -ENOMEM;

	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
	if (!glue) {
		dev_err(&pdev->dev, "failed to allocate glue context\n");
		goto err0;
	}

	musb = platform_device_alloc("musb-hdrc", -1);
	if (!musb) {
		dev_err(&pdev->dev, "failed to allocate musb device\n");
		goto err1;
	}

	clk = clk_get(&pdev->dev, "usb20");
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "failed to get clock\n");
		ret = PTR_ERR(clk);
		goto err2;
	}

	ret = clk_enable(clk);
	if (ret) {
		dev_err(&pdev->dev, "failed to enable clock\n");
		goto err3;
	}

	musb->dev.parent		= &pdev->dev;
	musb->dev.dma_mask		= &da8xx_dmamask;
	musb->dev.coherent_dma_mask	= da8xx_dmamask;

	glue->dev			= &pdev->dev;
	glue->musb			= musb;
	glue->clk			= clk;

	pdata->platform_ops		= &da8xx_ops;

	platform_set_drvdata(pdev, glue);

	ret = platform_device_add_resources(musb, pdev->resource,
			pdev->num_resources);
	if (ret) {
		dev_err(&pdev->dev, "failed to add resources\n");
		goto err4;
	}

	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	if (ret) {
		dev_err(&pdev->dev, "failed to add platform_data\n");
		goto err4;
	}

	ret = platform_device_add(musb);
	if (ret) {
		dev_err(&pdev->dev, "failed to register musb device\n");
		goto err4;
	}

	return 0;

err4:
	clk_disable(clk);

err3:
	clk_put(clk);

err2:
	platform_device_put(musb);

err1:
	kfree(glue);

err0:
	return ret;
}

static int __devexit da8xx_remove(struct platform_device *pdev)
{
	struct da8xx_glue		*glue = platform_get_drvdata(pdev);

	platform_device_del(glue->musb);
	platform_device_put(glue->musb);
	clk_disable(glue->clk);
	clk_put(glue->clk);
	kfree(glue);

	return 0;
}

static struct platform_driver da8xx_driver = {
	.probe		= da8xx_probe,
	.remove		= __devexit_p(da8xx_remove),
	.driver		= {
		.name	= "musb-da8xx",
	},
};

MODULE_DESCRIPTION("DA8xx/OMAP-L1x MUSB Glue Layer");
MODULE_AUTHOR("Sergei Shtylyov <sshtylyov@ru.mvista.com>");
MODULE_LICENSE("GPL v2");

static int __init da8xx_init(void)
{
	return platform_driver_register(&da8xx_driver);
}
module_init(da8xx_init);

static void __exit da8xx_exit(void)
{
	platform_driver_unregister(&da8xx_driver);
}
module_exit(da8xx_exit);
Commit	Line	Data
3ee076de SS	1	/*
	2	* Texas Instruments DA8xx/OMAP-L1x "glue layer"
	3	*
	4	* Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
	5	*
	6	* Based on the DaVinci "glue layer" code.
	7	* Copyright (C) 2005-2006 by Texas Instruments
	8	*
	9	* This file is part of the Inventra Controller Driver for Linux.
	10	*
	11	* The Inventra Controller Driver for Linux is free software; you
	12	* can redistribute it and/or modify it under the terms of the GNU
	13	* General Public License version 2 as published by the Free Software
	14	* Foundation.
	15	*
	16	* The Inventra Controller Driver for Linux is distributed in
	17	* the hope that it will be useful, but WITHOUT ANY WARRANTY;
	18	* without even the implied warranty of MERCHANTABILITY or
	19	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	20	* License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with The Inventra Controller Driver for Linux ; if not,
	24	* write to the Free Software Foundation, Inc., 59 Temple Place,
	25	* Suite 330, Boston, MA 02111-1307 USA
	26	*
	27	*/
	28
	29	#include <linux/init.h>
ab570da2	30	#include <linux/module.h>
3ee076de	31	#include <linux/clk.h>
ded017ee	32	#include <linux/err.h>
3ee076de	33	#include <linux/io.h>
8ceae51e FB	34	#include <linux/platform_device.h>
8ceae51e FB	35	#include <linux/dma-mapping.h>
3ee076de SS	36
3ee076de SS	37	#include <mach/da8xx.h>
ec2a0833	38	#include <linux/platform_data/usb-davinci.h>
3ee076de SS	39
	40	#include "musb_core.h"
	41
	42	/*
	43	* DA8XX specific definitions
	44	*/
	45
	46	/* USB 2.0 OTG module registers */
	47	#define DA8XX_USB_REVISION_REG 0x00
	48	#define DA8XX_USB_CTRL_REG 0x04
	49	#define DA8XX_USB_STAT_REG 0x08
	50	#define DA8XX_USB_EMULATION_REG 0x0c
	51	#define DA8XX_USB_MODE_REG 0x10 /* Transparent, CDC, [Generic] RNDIS */
	52	#define DA8XX_USB_AUTOREQ_REG 0x14
	53	#define DA8XX_USB_SRP_FIX_TIME_REG 0x18
	54	#define DA8XX_USB_TEARDOWN_REG 0x1c
	55	#define DA8XX_USB_INTR_SRC_REG 0x20
	56	#define DA8XX_USB_INTR_SRC_SET_REG 0x24
	57	#define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
	58	#define DA8XX_USB_INTR_MASK_REG 0x2c
	59	#define DA8XX_USB_INTR_MASK_SET_REG 0x30
	60	#define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
	61	#define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
	62	#define DA8XX_USB_END_OF_INTR_REG 0x3c
	63	#define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
	64
	65	/* Control register bits */
	66	#define DA8XX_SOFT_RESET_MASK 1
	67
	68	#define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */
	69	#define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */
	70
	71	/* USB interrupt register bits */
	72	#define DA8XX_INTR_USB_SHIFT 16
	73	#define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
	74	/* interrupts and DRVVBUS interrupt */
	75	#define DA8XX_INTR_DRVVBUS 0x100
	76	#define DA8XX_INTR_RX_SHIFT 8
	77	#define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
	78	#define DA8XX_INTR_TX_SHIFT 0
	79	#define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)
	80
	81	#define DA8XX_MENTOR_CORE_OFFSET 0x400
	82
	83	#define CFGCHIP2 IO_ADDRESS(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG)
	84
e6480faa FB	85	struct da8xx_glue {
	86	struct device *dev;
	87	struct platform_device *musb;
03491761	88	struct clk *clk;
e6480faa FB	89	};
e6480faa FB	90
3ee076de SS	91	/*
	92	* REVISIT (PM): we should be able to keep the PHY in low power mode most
	93	* of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0
	94	* and, when in host mode, autosuspending idle root ports... PHY_PLLON
	95	* (overriding SUSPENDM?) then likely needs to stay off.
	96	*/
	97
	98	static inline void phy_on(void)
	99	{
	100	u32 cfgchip2 = __raw_readl(CFGCHIP2);
	101
	102	/*
	103	* Start the on-chip PHY and its PLL.
	104	*/
	105	cfgchip2 &= ~(CFGCHIP2_RESET \| CFGCHIP2_PHYPWRDN \| CFGCHIP2_OTGPWRDN);
	106	cfgchip2 \|= CFGCHIP2_PHY_PLLON;
	107	__raw_writel(cfgchip2, CFGCHIP2);
	108
	109	pr_info("Waiting for USB PHY clock good...\n");
	110	while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
	111	cpu_relax();
	112	}
	113
	114	static inline void phy_off(void)
	115	{
	116	u32 cfgchip2 = __raw_readl(CFGCHIP2);
	117
	118	/*
	119	* Ensure that USB 1.1 reference clock is not being sourced from
	120	* USB 2.0 PHY. Otherwise do not power down the PHY.
	121	*/
	122	if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX) &&
	123	(cfgchip2 & CFGCHIP2_USB1SUSPENDM)) {
	124	pr_warning("USB 1.1 clocked from USB 2.0 PHY -- "
	125	"can't power it down\n");
	126	return;
	127	}
	128
	129	/*
	130	* Power down the on-chip PHY.
	131	*/
	132	cfgchip2 \|= CFGCHIP2_PHYPWRDN \| CFGCHIP2_OTGPWRDN;
	133	__raw_writel(cfgchip2, CFGCHIP2);
	134	}
	135
	136	/*
	137	* Because we don't set CTRL.UINT, it's "important" to:
	138	* - not read/write INTRUSB/INTRUSBE (except during
	139	* initial setup, as a workaround);
	140	* - use INTSET/INTCLR instead.
	141	*/
	142
	143	/**
743411b3	144	* da8xx_musb_enable - enable interrupts
3ee076de	145	*/
743411b3	146	static void da8xx_musb_enable(struct musb *musb)
3ee076de SS	147	{
	148	void __iomem *reg_base = musb->ctrl_base;
	149	u32 mask;
	150
	151	/* Workaround: setup IRQs through both register sets. */
	152	mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) \|
	153	((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) \|
	154	DA8XX_INTR_USB_MASK;
	155	musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
	156
	157	/* Force the DRVVBUS IRQ so we can start polling for ID change. */
	158	if (is_otg_enabled(musb))
	159	musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
	160	DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
	161	}
	162
	163	/**
743411b3	164	* da8xx_musb_disable - disable HDRC and flush interrupts
3ee076de	165	*/
743411b3	166	static void da8xx_musb_disable(struct musb *musb)
3ee076de SS	167	{
	168	void __iomem *reg_base = musb->ctrl_base;
	169
	170	musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
	171	DA8XX_INTR_USB_MASK \|
	172	DA8XX_INTR_TX_MASK \| DA8XX_INTR_RX_MASK);
	173	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
	174	musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
	175	}
	176
62285963	177	#define portstate(stmt) stmt
3ee076de	178
743411b3	179	static void da8xx_musb_set_vbus(struct musb *musb, int is_on)
3ee076de SS	180	{
	181	WARN_ON(is_on && is_peripheral_active(musb));
	182	}
	183
	184	#define POLL_SECONDS 2
	185
	186	static struct timer_list otg_workaround;
	187
	188	static void otg_timer(unsigned long _musb)
	189	{
	190	struct musb musb = (void )_musb;
	191	void __iomem *mregs = musb->mregs;
	192	u8 devctl;
	193	unsigned long flags;
	194
	195	/*
	196	* We poll because DaVinci's won't expose several OTG-critical
	197	* status change events (from the transceiver) otherwise.
	198	*/
	199	devctl = musb_readb(mregs, MUSB_DEVCTL);
5c8a86e1	200	dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
3df00453	201	otg_state_string(musb->xceiv->state));
3ee076de SS	202
	203	spin_lock_irqsave(&musb->lock, flags);
	204	switch (musb->xceiv->state) {
	205	case OTG_STATE_A_WAIT_BCON:
	206	devctl &= ~MUSB_DEVCTL_SESSION;
	207	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
	208
	209	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
	210	if (devctl & MUSB_DEVCTL_BDEVICE) {
	211	musb->xceiv->state = OTG_STATE_B_IDLE;
	212	MUSB_DEV_MODE(musb);
	213	} else {
	214	musb->xceiv->state = OTG_STATE_A_IDLE;
	215	MUSB_HST_MODE(musb);
	216	}
	217	break;
	218	case OTG_STATE_A_WAIT_VFALL:
	219	/*
	220	* Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
	221	* RTL seems to mis-handle session "start" otherwise (or in
	222	* our case "recover"), in routine "VBUS was valid by the time
	223	* VBUSERR got reported during enumeration" cases.
	224	*/
	225	if (devctl & MUSB_DEVCTL_VBUS) {
	226	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	227	break;
	228	}
	229	musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
	230	musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG,
	231	MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT);
	232	break;
	233	case OTG_STATE_B_IDLE:
	234	if (!is_peripheral_enabled(musb))
	235	break;
	236
	237	/*
	238	* There's no ID-changed IRQ, so we have no good way to tell
	239	* when to switch to the A-Default state machine (by setting
	240	* the DEVCTL.Session bit).
	241	*
	242	* Workaround: whenever we're in B_IDLE, try setting the
	243	* session flag every few seconds. If it works, ID was
	244	* grounded and we're now in the A-Default state machine.
	245	*
	246	* NOTE: setting the session flag is _supposed_ to trigger
	247	* SRP but clearly it doesn't.
	248	*/
	249	musb_writeb(mregs, MUSB_DEVCTL, devctl \| MUSB_DEVCTL_SESSION);
	250	devctl = musb_readb(mregs, MUSB_DEVCTL);
	251	if (devctl & MUSB_DEVCTL_BDEVICE)
	252	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	253	else
	254	musb->xceiv->state = OTG_STATE_A_IDLE;
	255	break;
	256	default:
	257	break;
	258	}
	259	spin_unlock_irqrestore(&musb->lock, flags);
	260	}
	261
743411b3	262	static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout)
3ee076de SS	263	{
	264	static unsigned long last_timer;
	265
	266	if (!is_otg_enabled(musb))
	267	return;
	268
	269	if (timeout == 0)
	270	timeout = jiffies + msecs_to_jiffies(3);
	271
	272	/* Never idle if active, or when VBUS timeout is not set as host */
	273	if (musb->is_active \|\| (musb->a_wait_bcon == 0 &&
	274	musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
5c8a86e1	275	dev_dbg(musb->controller, "%s active, deleting timer\n",
3df00453	276	otg_state_string(musb->xceiv->state));
3ee076de SS	277	del_timer(&otg_workaround);
	278	last_timer = jiffies;
	279	return;
	280	}
	281
	282	if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
5c8a86e1	283	dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
3ee076de SS	284	return;
	285	}
	286	last_timer = timeout;
	287
5c8a86e1	288	dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
3df00453 AG	289	otg_state_string(musb->xceiv->state),
3df00453 AG	290	jiffies_to_msecs(timeout - jiffies));
3ee076de SS	291	mod_timer(&otg_workaround, timeout);
	292	}
	293
743411b3	294	static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
3ee076de SS	295	{
	296	struct musb *musb = hci;
	297	void __iomem *reg_base = musb->ctrl_base;
d445b6da	298	struct usb_otg *otg = musb->xceiv->otg;
3ee076de SS	299	unsigned long flags;
	300	irqreturn_t ret = IRQ_NONE;
	301	u32 status;
	302
	303	spin_lock_irqsave(&musb->lock, flags);
	304
	305	/*
	306	* NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through
	307	* the Mentor registers (except for setup), use the TI ones and EOI.
	308	*/
	309
	310	/* Acknowledge and handle non-CPPI interrupts */
	311	status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
	312	if (!status)
	313	goto eoi;
	314
	315	musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
5c8a86e1	316	dev_dbg(musb->controller, "USB IRQ %08x\n", status);
3ee076de SS	317
	318	musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
	319	musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
	320	musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
	321
	322	/*
	323	* DRVVBUS IRQs are the only proxy we have (a very poor one!) for
	324	* DA8xx's missing ID change IRQ. We need an ID change IRQ to
	325	* switch appropriately between halves of the OTG state machine.
	326	* Managing DEVCTL.Session per Mentor docs requires that we know its
	327	* value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
	328	* Also, DRVVBUS pulses for SRP (but not at 5 V)...
	329	*/
	330	if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
	331	int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
	332	void __iomem *mregs = musb->mregs;
	333	u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
	334	int err;
	335
	336	err = is_host_enabled(musb) && (musb->int_usb &
	337	MUSB_INTR_VBUSERROR);
	338	if (err) {
	339	/*
	340	* The Mentor core doesn't debounce VBUS as needed
	341	* to cope with device connect current spikes. This
	342	* means it's not uncommon for bus-powered devices
	343	* to get VBUS errors during enumeration.
	344	*
	345	* This is a workaround, but newer RTL from Mentor
	346	* seems to allow a better one: "re"-starting sessions
	347	* without waiting for VBUS to stop registering in
	348	* devctl.
	349	*/
	350	musb->int_usb &= ~MUSB_INTR_VBUSERROR;
	351	musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
	352	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	353	WARNING("VBUS error workaround (delay coming)\n");
	354	} else if (is_host_enabled(musb) && drvvbus) {
	355	MUSB_HST_MODE(musb);
d445b6da	356	otg->default_a = 1;
3ee076de SS	357	musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
	358	portstate(musb->port1_status \|= USB_PORT_STAT_POWER);
	359	del_timer(&otg_workaround);
	360	} else {
	361	musb->is_active = 0;
	362	MUSB_DEV_MODE(musb);
d445b6da	363	otg->default_a = 0;
3ee076de SS	364	musb->xceiv->state = OTG_STATE_B_IDLE;
	365	portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
	366	}
	367
5c8a86e1	368	dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
3ee076de	369	drvvbus ? "on" : "off",
3df00453	370	otg_state_string(musb->xceiv->state),
3ee076de SS	371	err ? " ERROR" : "",
	372	devctl);
	373	ret = IRQ_HANDLED;
	374	}
	375
	376	if (musb->int_tx \|\| musb->int_rx \|\| musb->int_usb)
	377	ret \|= musb_interrupt(musb);
	378
	379	eoi:
	380	/* EOI needs to be written for the IRQ to be re-asserted. */
	381	if (ret == IRQ_HANDLED \|\| status)
	382	musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
	383
	384	/* Poll for ID change */
	385	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
	386	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	387
	388	spin_unlock_irqrestore(&musb->lock, flags);
	389
	390	return ret;
	391	}
	392
743411b3	393	static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode)
3ee076de SS	394	{
	395	u32 cfgchip2 = __raw_readl(CFGCHIP2);
	396
	397	cfgchip2 &= ~CFGCHIP2_OTGMODE;
	398	switch (musb_mode) {
3ee076de SS	399	case MUSB_HOST: /* Force VBUS valid, ID = 0 */
	400	cfgchip2 \|= CFGCHIP2_FORCE_HOST;
	401	break;
3ee076de SS	402	case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
	403	cfgchip2 \|= CFGCHIP2_FORCE_DEVICE;
	404	break;
3ee076de SS	405	case MUSB_OTG: /* Don't override the VBUS/ID comparators */
	406	cfgchip2 \|= CFGCHIP2_NO_OVERRIDE;
	407	break;
3ee076de	408	default:
5c8a86e1	409	dev_dbg(musb->controller, "Trying to set unsupported mode %u\n", musb_mode);
3ee076de SS	410	}
	411
	412	__raw_writel(cfgchip2, CFGCHIP2);
	413	return 0;
	414	}
	415
743411b3	416	static int da8xx_musb_init(struct musb *musb)
3ee076de SS	417	{
	418	void __iomem *reg_base = musb->ctrl_base;
	419	u32 rev;
	420
	421	musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
	422
3ee076de SS	423	/* Returns zero if e.g. not clocked */
	424	rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG);
	425	if (!rev)
	426	goto fail;
	427
	428	usb_nop_xceiv_register();
662dca54	429	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
ded017ee	430	if (IS_ERR_OR_NULL(musb->xceiv))
3ee076de SS	431	goto fail;
	432
	433	if (is_host_enabled(musb))
	434	setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);
	435
3ee076de SS	436	/* Reset the controller */
	437	musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
	438
	439	/* Start the on-chip PHY and its PLL. */
	440	phy_on();
	441
	442	msleep(5);
	443
	444	/* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
	445	pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n",
	446	rev, __raw_readl(CFGCHIP2),
	447	musb_readb(reg_base, DA8XX_USB_CTRL_REG));
	448
743411b3	449	musb->isr = da8xx_musb_interrupt;
3ee076de SS	450	return 0;
3ee076de SS	451	fail:
3ee076de SS	452	return -ENODEV;
	453	}
	454
743411b3	455	static int da8xx_musb_exit(struct musb *musb)
3ee076de SS	456	{
	457	if (is_host_enabled(musb))
	458	del_timer_sync(&otg_workaround);
	459
	460	phy_off();
	461
721002ec	462	usb_put_phy(musb->xceiv);
3ee076de SS	463	usb_nop_xceiv_unregister();
3ee076de SS	464
3ee076de SS	465	return 0;
3ee076de SS	466	}
743411b3	467
f7ec9437	468	static const struct musb_platform_ops da8xx_ops = {
743411b3 FB	469	.init = da8xx_musb_init,
	470	.exit = da8xx_musb_exit,
	471
	472	.enable = da8xx_musb_enable,
	473	.disable = da8xx_musb_disable,
	474
	475	.set_mode = da8xx_musb_set_mode,
	476	.try_idle = da8xx_musb_try_idle,
	477
	478	.set_vbus = da8xx_musb_set_vbus,
	479	};
8ceae51e FB	480
	481	static u64 da8xx_dmamask = DMA_BIT_MASK(32);
	482
e9e8c85e	483	static int __devinit da8xx_probe(struct platform_device *pdev)
8ceae51e FB	484	{
	485	struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
	486	struct platform_device *musb;
e6480faa	487	struct da8xx_glue *glue;
8ceae51e	488
03491761 FB	489	struct clk *clk;
03491761 FB	490
8ceae51e FB	491	int ret = -ENOMEM;
8ceae51e FB	492
e6480faa FB	493	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
	494	if (!glue) {
	495	dev_err(&pdev->dev, "failed to allocate glue context\n");
	496	goto err0;
	497	}
	498
8ceae51e FB	499	musb = platform_device_alloc("musb-hdrc", -1);
	500	if (!musb) {
	501	dev_err(&pdev->dev, "failed to allocate musb device\n");
e6480faa	502	goto err1;
8ceae51e FB	503	}
8ceae51e FB	504
03491761 FB	505	clk = clk_get(&pdev->dev, "usb20");
	506	if (IS_ERR(clk)) {
	507	dev_err(&pdev->dev, "failed to get clock\n");
	508	ret = PTR_ERR(clk);
	509	goto err2;
	510	}
	511
	512	ret = clk_enable(clk);
	513	if (ret) {
	514	dev_err(&pdev->dev, "failed to enable clock\n");
	515	goto err3;
	516	}
	517
8ceae51e FB	518	musb->dev.parent = &pdev->dev;
	519	musb->dev.dma_mask = &da8xx_dmamask;
	520	musb->dev.coherent_dma_mask = da8xx_dmamask;
	521
e6480faa FB	522	glue->dev = &pdev->dev;
e6480faa FB	523	glue->musb = musb;
03491761	524	glue->clk = clk;
e6480faa	525
f7ec9437 FB	526	pdata->platform_ops = &da8xx_ops;
f7ec9437 FB	527
e6480faa	528	platform_set_drvdata(pdev, glue);
8ceae51e FB	529
	530	ret = platform_device_add_resources(musb, pdev->resource,
	531	pdev->num_resources);
	532	if (ret) {
	533	dev_err(&pdev->dev, "failed to add resources\n");
03491761	534	goto err4;
8ceae51e FB	535	}
	536
	537	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	538	if (ret) {
	539	dev_err(&pdev->dev, "failed to add platform_data\n");
03491761	540	goto err4;
8ceae51e FB	541	}
	542
	543	ret = platform_device_add(musb);
	544	if (ret) {
	545	dev_err(&pdev->dev, "failed to register musb device\n");
03491761	546	goto err4;
8ceae51e FB	547	}
	548
	549	return 0;
	550
03491761 FB	551	err4:
	552	clk_disable(clk);
	553
	554	err3:
	555	clk_put(clk);
	556
e6480faa	557	err2:
8ceae51e FB	558	platform_device_put(musb);
8ceae51e FB	559
e6480faa FB	560	err1:
	561	kfree(glue);
	562
8ceae51e FB	563	err0:
	564	return ret;
	565	}
	566
e9e8c85e	567	static int __devexit da8xx_remove(struct platform_device *pdev)
8ceae51e	568	{
e6480faa	569	struct da8xx_glue *glue = platform_get_drvdata(pdev);
8ceae51e	570
e6480faa FB	571	platform_device_del(glue->musb);
e6480faa FB	572	platform_device_put(glue->musb);
03491761 FB	573	clk_disable(glue->clk);
03491761 FB	574	clk_put(glue->clk);
e6480faa	575	kfree(glue);
8ceae51e FB	576
	577	return 0;
	578	}
	579
	580	static struct platform_driver da8xx_driver = {
e9e8c85e FB	581	.probe = da8xx_probe,
e9e8c85e FB	582	.remove = __devexit_p(da8xx_remove),
8ceae51e FB	583	.driver = {
	584	.name = "musb-da8xx",
	585	},
	586	};
	587
	588	MODULE_DESCRIPTION("DA8xx/OMAP-L1x MUSB Glue Layer");
	589	MODULE_AUTHOR("Sergei Shtylyov <sshtylyov@ru.mvista.com>");
	590	MODULE_LICENSE("GPL v2");
	591
	592	static int __init da8xx_init(void)
	593	{
e9e8c85e	594	return platform_driver_register(&da8xx_driver);
8ceae51e	595	}
e9e8c85e	596	module_init(da8xx_init);
8ceae51e FB	597
	598	static void __exit da8xx_exit(void)
	599	{
	600	platform_driver_unregister(&da8xx_driver);
	601	}
	602	module_exit(da8xx_exit);