[deliverable/linux.git] / drivers / usb / musb / davinci.c

/*
 * Copyright (C) 2005-2006 by Texas Instruments
 *
 * This file is part of the Inventra Controller Driver for Linux.
 *
 * The Inventra Controller Driver for Linux is free software; you
 * can redistribute it and/or modify it under the terms of the GNU
 * General Public License version 2 as published by the Free Software
 * Foundation.
 *
 * The Inventra Controller Driver for Linux is distributed in
 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
 * without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
 * License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with The Inventra Controller Driver for Linux ; if not,
 * write to the Free Software Foundation, Inc., 59 Temple Place,
 * Suite 330, Boston, MA  02111-1307  USA
 *
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/list.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/usb/usb_phy_generic.h>

#include <mach/cputype.h>
#include <mach/hardware.h>

#include <asm/mach-types.h>

#include "musb_core.h"

#ifdef CONFIG_MACH_DAVINCI_EVM
#define GPIO_nVBUS_DRV		160
#endif

#include "davinci.h"
#include "cppi_dma.h"


#define USB_PHY_CTRL	IO_ADDRESS(USBPHY_CTL_PADDR)
#define DM355_DEEPSLEEP	IO_ADDRESS(DM355_DEEPSLEEP_PADDR)

struct davinci_glue {
	struct device		*dev;
	struct platform_device	*musb;
	struct clk		*clk;
};

/* REVISIT (PM) we should be able to keep the PHY in low power mode most
 * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
 * and, when in host mode, autosuspending idle root ports... PHYPLLON
 * (overriding SUSPENDM?) then likely needs to stay off.
 */

static inline void phy_on(void)
{
	u32	phy_ctrl = __raw_readl(USB_PHY_CTRL);

	/* power everything up; start the on-chip PHY and its PLL */
	phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN);
	phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON;
	__raw_writel(phy_ctrl, USB_PHY_CTRL);

	/* wait for PLL to lock before proceeding */
	while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0)
		cpu_relax();
}

static inline void phy_off(void)
{
	u32	phy_ctrl = __raw_readl(USB_PHY_CTRL);

	/* powerdown the on-chip PHY, its PLL, and the OTG block */
	phy_ctrl &= ~(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON);
	phy_ctrl |= USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN;
	__raw_writel(phy_ctrl, USB_PHY_CTRL);
}

static int dma_off = 1;

static void davinci_musb_enable(struct musb *musb)
{
	u32	tmp, old, val;

	/* workaround:  setup irqs through both register sets */
	tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
			<< DAVINCI_USB_TXINT_SHIFT;
	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
	old = tmp;
	tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
			<< DAVINCI_USB_RXINT_SHIFT;
	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
	tmp |= old;

	val = ~MUSB_INTR_SOF;
	tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);

	if (is_dma_capable() && !dma_off)
		printk(KERN_WARNING "%s %s: dma not reactivated\n",
				__FILE__, __func__);
	else
		dma_off = 0;

	/* force a DRVVBUS irq so we can start polling for ID change */
	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
			DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
}

/*
 * Disable the HDRC and flush interrupts
 */
static void davinci_musb_disable(struct musb *musb)
{
	/* because we don't set CTRLR.UINT, "important" to:
	 *  - not read/write INTRUSB/INTRUSBE
	 *  - (except during initial setup, as workaround)
	 *  - use INTSETR/INTCLRR instead
	 */
	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
			  DAVINCI_USB_USBINT_MASK
			| DAVINCI_USB_TXINT_MASK
			| DAVINCI_USB_RXINT_MASK);
	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
	musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);

	if (is_dma_capable() && !dma_off)
		WARNING("dma still active\n");
}


#define	portstate(stmt)		stmt

/*
 * VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM,
 * which doesn't wire DRVVBUS to the FET that switches it.  Unclear
 * if that's a problem with the DM6446 chip or just with that board.
 *
 * In either case, the DM355 EVM automates DRVVBUS the normal way,
 * when J10 is out, and TI documents it as handling OTG.
 */

#ifdef CONFIG_MACH_DAVINCI_EVM

static int vbus_state = -1;

/* I2C operations are always synchronous, and require a task context.
 * With unloaded systems, using the shared workqueue seems to suffice
 * to satisfy the 100msec A_WAIT_VRISE timeout...
 */
static void evm_deferred_drvvbus(struct work_struct *ignored)
{
	gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
	vbus_state = !vbus_state;
}

#endif	/* EVM */

static void davinci_musb_source_power(struct musb *musb, int is_on, int immediate)
{
#ifdef CONFIG_MACH_DAVINCI_EVM
	if (is_on)
		is_on = 1;

	if (vbus_state == is_on)
		return;
	vbus_state = !is_on;		/* 0/1 vs "-1 == unknown/init" */

	if (machine_is_davinci_evm()) {
		static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);

		if (immediate)
			gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
		else
			schedule_work(&evm_vbus_work);
	}
	if (immediate)
		vbus_state = is_on;
#endif
}

static void davinci_musb_set_vbus(struct musb *musb, int is_on)
{
	WARN_ON(is_on && is_peripheral_active(musb));
	davinci_musb_source_power(musb, is_on, 0);
}


#define	POLL_SECONDS	2

static struct timer_list otg_workaround;

static void otg_timer(unsigned long _musb)
{
	struct musb		*musb = (void *)_musb;
	void __iomem		*mregs = musb->mregs;
	u8			devctl;
	unsigned long		flags;

	/* We poll because DaVinci's won't expose several OTG-critical
	* status change events (from the transceiver) otherwise.
	 */
	devctl = musb_readb(mregs, MUSB_DEVCTL);
	dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl,
		usb_otg_state_string(musb->xceiv->state));

	spin_lock_irqsave(&musb->lock, flags);
	switch (musb->xceiv->state) {
	case OTG_STATE_A_WAIT_VFALL:
		/* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
		 * seems to mis-handle session "start" otherwise (or in our
		 * case "recover"), in routine "VBUS was valid by the time
		 * VBUSERR got reported during enumeration" cases.
		 */
		if (devctl & MUSB_DEVCTL_VBUS) {
			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
			break;
		}
		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
		musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
			MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
		break;
	case OTG_STATE_B_IDLE:
		/*
		 * There's no ID-changed IRQ, so we have no good way to tell
		 * when to switch to the A-Default state machine (by setting
		 * the DEVCTL.SESSION flag).
		 *
		 * Workaround:  whenever we're in B_IDLE, try setting the
		 * session flag every few seconds.  If it works, ID was
		 * grounded and we're now in the A-Default state machine.
		 *
		 * NOTE setting the session flag is _supposed_ to trigger
		 * SRP, but clearly it doesn't.
		 */
		musb_writeb(mregs, MUSB_DEVCTL,
				devctl | MUSB_DEVCTL_SESSION);
		devctl = musb_readb(mregs, MUSB_DEVCTL);
		if (devctl & MUSB_DEVCTL_BDEVICE)
			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
		else
			musb->xceiv->state = OTG_STATE_A_IDLE;
		break;
	default:
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);
}

static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
{
	unsigned long	flags;
	irqreturn_t	retval = IRQ_NONE;
	struct musb	*musb = __hci;
	struct usb_otg	*otg = musb->xceiv->otg;
	void __iomem	*tibase = musb->ctrl_base;
	struct cppi	*cppi;
	u32		tmp;

	spin_lock_irqsave(&musb->lock, flags);

	/* NOTE: DaVinci shadows the Mentor IRQs.  Don't manage them through
	 * the Mentor registers (except for setup), use the TI ones and EOI.
	 *
	 * Docs describe irq "vector" registers associated with the CPPI and
	 * USB EOI registers.  These hold a bitmask corresponding to the
	 * current IRQ, not an irq handler address.  Would using those bits
	 * resolve some of the races observed in this dispatch code??
	 */

	/* CPPI interrupts share the same IRQ line, but have their own
	 * mask, state, "vector", and EOI registers.
	 */
	cppi = container_of(musb->dma_controller, struct cppi, controller);
	if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
		retval = cppi_interrupt(irq, __hci);

	/* ack and handle non-CPPI interrupts */
	tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
	musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
	dev_dbg(musb->controller, "IRQ %08x\n", tmp);

	musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
			>> DAVINCI_USB_RXINT_SHIFT;
	musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
			>> DAVINCI_USB_TXINT_SHIFT;
	musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
			>> DAVINCI_USB_USBINT_SHIFT;

	/* DRVVBUS irqs are the only proxy we have (a very poor one!) for
	 * DaVinci's missing ID change IRQ.  We need an ID change IRQ to
	 * switch appropriately between halves of the OTG state machine.
	 * Managing DEVCTL.SESSION per Mentor docs requires we know its
	 * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
	 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
	 */
	if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
		int	drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
		void __iomem *mregs = musb->mregs;
		u8	devctl = musb_readb(mregs, MUSB_DEVCTL);
		int	err = musb->int_usb & MUSB_INTR_VBUSERROR;

		err = musb->int_usb & MUSB_INTR_VBUSERROR;
		if (err) {
			/* The Mentor core doesn't debounce VBUS as needed
			 * to cope with device connect current spikes. This
			 * means it's not uncommon for bus-powered devices
			 * to get VBUS errors during enumeration.
			 *
			 * This is a workaround, but newer RTL from Mentor
			 * seems to allow a better one: "re"starting sessions
			 * without waiting (on EVM, a **long** time) for VBUS
			 * to stop registering in devctl.
			 */
			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
			WARNING("VBUS error workaround (delay coming)\n");
		} else if (drvvbus) {
			MUSB_HST_MODE(musb);
			otg->default_a = 1;
			musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
			portstate(musb->port1_status |= USB_PORT_STAT_POWER);
			del_timer(&otg_workaround);
		} else {
			musb->is_active = 0;
			MUSB_DEV_MODE(musb);
			otg->default_a = 0;
			musb->xceiv->state = OTG_STATE_B_IDLE;
			portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
		}

		/* NOTE:  this must complete poweron within 100 msec
		 * (OTG_TIME_A_WAIT_VRISE) but we don't check for that.
		 */
		davinci_musb_source_power(musb, drvvbus, 0);
		dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
				drvvbus ? "on" : "off",
				usb_otg_state_string(musb->xceiv->state),
				err ? " ERROR" : "",
				devctl);
		retval = IRQ_HANDLED;
	}

	if (musb->int_tx || musb->int_rx || musb->int_usb)
		retval |= musb_interrupt(musb);

	/* irq stays asserted until EOI is written */
	musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);

	/* poll for ID change */
	if (musb->xceiv->state == OTG_STATE_B_IDLE)
		mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);

	spin_unlock_irqrestore(&musb->lock, flags);

	return retval;
}

static int davinci_musb_set_mode(struct musb *musb, u8 mode)
{
	/* EVM can't do this (right?) */
	return -EIO;
}

static int davinci_musb_init(struct musb *musb)
{
	void __iomem	*tibase = musb->ctrl_base;
	u32		revision;
	int 		ret = -ENODEV;

	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
	if (IS_ERR_OR_NULL(musb->xceiv)) {
		ret = -EPROBE_DEFER;
		goto unregister;
	}

	musb->mregs += DAVINCI_BASE_OFFSET;

	/* returns zero if e.g. not clocked */
	revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
	if (revision == 0)
		goto fail;

	setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);

	davinci_musb_source_power(musb, 0, 1);

	/* dm355 EVM swaps D+/D- for signal integrity, and
	 * is clocked from the main 24 MHz crystal.
	 */
	if (machine_is_davinci_dm355_evm()) {
		u32	phy_ctrl = __raw_readl(USB_PHY_CTRL);

		phy_ctrl &= ~(3 << 9);
		phy_ctrl |= USBPHY_DATAPOL;
		__raw_writel(phy_ctrl, USB_PHY_CTRL);
	}

	/* On dm355, the default-A state machine needs DRVVBUS control.
	 * If we won't be a host, there's no need to turn it on.
	 */
	if (cpu_is_davinci_dm355()) {
		u32	deepsleep = __raw_readl(DM355_DEEPSLEEP);

		deepsleep &= ~DRVVBUS_FORCE;
		__raw_writel(deepsleep, DM355_DEEPSLEEP);
	}

	/* reset the controller */
	musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);

	/* start the on-chip PHY and its PLL */
	phy_on();

	msleep(5);

	/* NOTE:  irqs are in mixed mode, not bypass to pure-musb */
	pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
		revision, __raw_readl(USB_PHY_CTRL),
		musb_readb(tibase, DAVINCI_USB_CTRL_REG));

	musb->isr = davinci_musb_interrupt;
	return 0;

fail:
	usb_put_phy(musb->xceiv);
unregister:
	usb_phy_generic_unregister();
	return ret;
}

static int davinci_musb_exit(struct musb *musb)
{
	del_timer_sync(&otg_workaround);

	/* force VBUS off */
	if (cpu_is_davinci_dm355()) {
		u32	deepsleep = __raw_readl(DM355_DEEPSLEEP);

		deepsleep &= ~DRVVBUS_FORCE;
		deepsleep |= DRVVBUS_OVERRIDE;
		__raw_writel(deepsleep, DM355_DEEPSLEEP);
	}

	davinci_musb_source_power(musb, 0 /*off*/, 1);

	/* delay, to avoid problems with module reload */
	if (musb->xceiv->otg->default_a) {
		int	maxdelay = 30;
		u8	devctl, warn = 0;

		/* if there's no peripheral connected, this can take a
		 * long time to fall, especially on EVM with huge C133.
		 */
		do {
			devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
			if (!(devctl & MUSB_DEVCTL_VBUS))
				break;
			if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
				warn = devctl & MUSB_DEVCTL_VBUS;
				dev_dbg(musb->controller, "VBUS %d\n",
					warn >> MUSB_DEVCTL_VBUS_SHIFT);
			}
			msleep(1000);
			maxdelay--;
		} while (maxdelay > 0);

		/* in OTG mode, another host might be connected */
		if (devctl & MUSB_DEVCTL_VBUS)
			dev_dbg(musb->controller, "VBUS off timeout (devctl %02x)\n", devctl);
	}

	phy_off();

	usb_put_phy(musb->xceiv);

	return 0;
}

static const struct musb_platform_ops davinci_ops = {
	.init		= davinci_musb_init,
	.exit		= davinci_musb_exit,

	.enable		= davinci_musb_enable,
	.disable	= davinci_musb_disable,

	.set_mode	= davinci_musb_set_mode,

	.set_vbus	= davinci_musb_set_vbus,
};

static const struct platform_device_info davinci_dev_info = {
	.name		= "musb-hdrc",
	.id		= PLATFORM_DEVID_AUTO,
	.dma_mask	= DMA_BIT_MASK(32),
};

static int davinci_probe(struct platform_device *pdev)
{
	struct resource			musb_resources[3];
	struct musb_hdrc_platform_data	*pdata = dev_get_platdata(&pdev->dev);
	struct platform_device		*musb;
	struct davinci_glue		*glue;
	struct platform_device_info	pinfo;
	struct clk			*clk;

	int				ret = -ENOMEM;

	glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
	if (!glue)
		goto err0;

	clk = devm_clk_get(&pdev->dev, "usb");
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "failed to get clock\n");
		ret = PTR_ERR(clk);
		goto err0;
	}

	ret = clk_enable(clk);
	if (ret) {
		dev_err(&pdev->dev, "failed to enable clock\n");
		goto err0;
	}

	glue->dev			= &pdev->dev;
	glue->clk			= clk;

	pdata->platform_ops		= &davinci_ops;

	usb_phy_generic_register();
	platform_set_drvdata(pdev, glue);

	memset(musb_resources, 0x00, sizeof(*musb_resources) *
			ARRAY_SIZE(musb_resources));

	musb_resources[0].name = pdev->resource[0].name;
	musb_resources[0].start = pdev->resource[0].start;
	musb_resources[0].end = pdev->resource[0].end;
	musb_resources[0].flags = pdev->resource[0].flags;

	musb_resources[1].name = pdev->resource[1].name;
	musb_resources[1].start = pdev->resource[1].start;
	musb_resources[1].end = pdev->resource[1].end;
	musb_resources[1].flags = pdev->resource[1].flags;

	/*
	 * For DM6467 3 resources are passed. A placeholder for the 3rd
	 * resource is always there, so it's safe to always copy it...
	 */
	musb_resources[2].name = pdev->resource[2].name;
	musb_resources[2].start = pdev->resource[2].start;
	musb_resources[2].end = pdev->resource[2].end;
	musb_resources[2].flags = pdev->resource[2].flags;

	pinfo = davinci_dev_info;
	pinfo.parent = &pdev->dev;
	pinfo.res = musb_resources;
	pinfo.num_res = ARRAY_SIZE(musb_resources);
	pinfo.data = pdata;
	pinfo.size_data = sizeof(*pdata);

	glue->musb = musb = platform_device_register_full(&pinfo);
	if (IS_ERR(musb)) {
		ret = PTR_ERR(musb);
		dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
		goto err1;
	}

	return 0;

err1:
	clk_disable(clk);

err0:
	return ret;
}

static int davinci_remove(struct platform_device *pdev)
{
	struct davinci_glue		*glue = platform_get_drvdata(pdev);

	platform_device_unregister(glue->musb);
	usb_phy_generic_unregister();
	clk_disable(glue->clk);

	return 0;
}

static struct platform_driver davinci_driver = {
	.probe		= davinci_probe,
	.remove		= davinci_remove,
	.driver		= {
		.name	= "musb-davinci",
	},
};

MODULE_DESCRIPTION("DaVinci MUSB Glue Layer");
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
MODULE_LICENSE("GPL v2");
module_platform_driver(davinci_driver);
Commit	Line	Data
550a7375 FB	1	/*
	2	* Copyright (C) 2005-2006 by Texas Instruments
	3	*
	4	* This file is part of the Inventra Controller Driver for Linux.
	5	*
	6	* The Inventra Controller Driver for Linux is free software; you
	7	* can redistribute it and/or modify it under the terms of the GNU
	8	* General Public License version 2 as published by the Free Software
	9	* Foundation.
	10	*
	11	* The Inventra Controller Driver for Linux is distributed in
	12	* the hope that it will be useful, but WITHOUT ANY WARRANTY;
	13	* without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	* License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with The Inventra Controller Driver for Linux ; if not,
	19	* write to the Free Software Foundation, Inc., 59 Temple Place,
	20	* Suite 330, Boston, MA 02111-1307 USA
	21	*
	22	*/
	23
	24	#include <linux/module.h>
	25	#include <linux/kernel.h>
	26	#include <linux/sched.h>
550a7375 FB	27	#include <linux/list.h>
	28	#include <linux/delay.h>
	29	#include <linux/clk.h>
ded017ee	30	#include <linux/err.h>
550a7375	31	#include <linux/io.h>
c767c1c6	32	#include <linux/gpio.h>
73b089b0 FB	33	#include <linux/platform_device.h>
73b089b0 FB	34	#include <linux/dma-mapping.h>
d7078df6	35	#include <linux/usb/usb_phy_generic.h>
550a7375	36
d163ef24	37	#include <mach/cputype.h>
6594b2d7	38	#include <mach/hardware.h>
10b4eade	39
550a7375 FB	40	#include <asm/mach-types.h>
	41
	42	#include "musb_core.h"
	43
	44	#ifdef CONFIG_MACH_DAVINCI_EVM
a2396a32	45	#define GPIO_nVBUS_DRV 160
550a7375 FB	46	#endif
	47
	48	#include "davinci.h"
	49	#include "cppi_dma.h"
	50
	51
a227fd7d DB	52	#define USB_PHY_CTRL IO_ADDRESS(USBPHY_CTL_PADDR)
	53	#define DM355_DEEPSLEEP IO_ADDRESS(DM355_DEEPSLEEP_PADDR)
	54
e110de4d FB	55	struct davinci_glue {
	56	struct device *dev;
	57	struct platform_device *musb;
03491761	58	struct clk *clk;
e110de4d FB	59	};
e110de4d FB	60
550a7375 FB	61	/* REVISIT (PM) we should be able to keep the PHY in low power mode most
	62	* of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
	63	* and, when in host mode, autosuspending idle root ports... PHYPLLON
	64	* (overriding SUSPENDM?) then likely needs to stay off.
	65	*/
	66
	67	static inline void phy_on(void)
	68	{
a227fd7d DB	69	u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
	70
	71	/* power everything up; start the on-chip PHY and its PLL */
	72	phy_ctrl &= ~(USBPHY_OSCPDWN \| USBPHY_OTGPDWN \| USBPHY_PHYPDWN);
	73	phy_ctrl \|= USBPHY_SESNDEN \| USBPHY_VBDTCTEN \| USBPHY_PHYPLLON;
	74	__raw_writel(phy_ctrl, USB_PHY_CTRL);
	75
	76	/* wait for PLL to lock before proceeding */
	77	while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0)
550a7375 FB	78	cpu_relax();
	79	}
	80
	81	static inline void phy_off(void)
	82	{
a227fd7d DB	83	u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
	84
	85	/* powerdown the on-chip PHY, its PLL, and the OTG block */
	86	phy_ctrl &= ~(USBPHY_SESNDEN \| USBPHY_VBDTCTEN \| USBPHY_PHYPLLON);
	87	phy_ctrl \|= USBPHY_OSCPDWN \| USBPHY_OTGPDWN \| USBPHY_PHYPDWN;
	88	__raw_writel(phy_ctrl, USB_PHY_CTRL);
550a7375 FB	89	}
	90
	91	static int dma_off = 1;
	92
743411b3	93	static void davinci_musb_enable(struct musb *musb)
550a7375 FB	94	{
	95	u32 tmp, old, val;
	96
	97	/* workaround: setup irqs through both register sets */
	98	tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
	99	<< DAVINCI_USB_TXINT_SHIFT;
	100	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
	101	old = tmp;
	102	tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
	103	<< DAVINCI_USB_RXINT_SHIFT;
	104	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
	105	tmp \|= old;
	106
	107	val = ~MUSB_INTR_SOF;
	108	tmp \|= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
	109	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
	110
	111	if (is_dma_capable() && !dma_off)
	112	printk(KERN_WARNING "%s %s: dma not reactivated\n",
	113	__FILE__, __func__);
	114	else
	115	dma_off = 0;
	116
	117	/* force a DRVVBUS irq so we can start polling for ID change */
032ec49f	118	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
550a7375 FB	119	DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
	120	}
	121
	122	/*
	123	* Disable the HDRC and flush interrupts
	124	*/
743411b3	125	static void davinci_musb_disable(struct musb *musb)
550a7375 FB	126	{
	127	/* because we don't set CTRLR.UINT, "important" to:
	128	* - not read/write INTRUSB/INTRUSBE
	129	* - (except during initial setup, as workaround)
	130	* - use INTSETR/INTCLRR instead
	131	*/
	132	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
	133	DAVINCI_USB_USBINT_MASK
	134	\| DAVINCI_USB_TXINT_MASK
	135	\| DAVINCI_USB_RXINT_MASK);
	136	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
	137	musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
	138
	139	if (is_dma_capable() && !dma_off)
	140	WARNING("dma still active\n");
	141	}
	142
	143
550a7375	144	#define portstate(stmt) stmt
550a7375	145
a227fd7d DB	146	/*
	147	* VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM,
	148	* which doesn't wire DRVVBUS to the FET that switches it. Unclear
	149	* if that's a problem with the DM6446 chip or just with that board.
	150	*
	151	* In either case, the DM355 EVM automates DRVVBUS the normal way,
	152	* when J10 is out, and TI documents it as handling OTG.
	153	*/
550a7375 FB	154
550a7375 FB	155	#ifdef CONFIG_MACH_DAVINCI_EVM
550a7375	156
a227fd7d DB	157	static int vbus_state = -1;
a227fd7d DB	158
550a7375 FB	159	/* I2C operations are always synchronous, and require a task context.
	160	* With unloaded systems, using the shared workqueue seems to suffice
	161	* to satisfy the 100msec A_WAIT_VRISE timeout...
	162	*/
	163	static void evm_deferred_drvvbus(struct work_struct *ignored)
	164	{
c767c1c6	165	gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
550a7375 FB	166	vbus_state = !vbus_state;
550a7375 FB	167	}
550a7375	168
550a7375 FB	169	#endif /* EVM */
550a7375 FB	170
743411b3	171	static void davinci_musb_source_power(struct musb *musb, int is_on, int immediate)
550a7375	172	{
a227fd7d	173	#ifdef CONFIG_MACH_DAVINCI_EVM
550a7375 FB	174	if (is_on)
	175	is_on = 1;
	176
	177	if (vbus_state == is_on)
	178	return;
	179	vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */
	180
550a7375	181	if (machine_is_davinci_evm()) {
a227fd7d DB	182	static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
a227fd7d DB	183
550a7375	184	if (immediate)
c767c1c6	185	gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
550a7375 FB	186	else
550a7375 FB	187	schedule_work(&evm_vbus_work);
550a7375	188	}
550a7375 FB	189	if (immediate)
550a7375 FB	190	vbus_state = is_on;
a227fd7d	191	#endif
550a7375 FB	192	}
550a7375 FB	193
743411b3	194	static void davinci_musb_set_vbus(struct musb *musb, int is_on)
550a7375 FB	195	{
550a7375 FB	196	WARN_ON(is_on && is_peripheral_active(musb));
743411b3	197	davinci_musb_source_power(musb, is_on, 0);
550a7375 FB	198	}
	199
	200
	201	#define POLL_SECONDS 2
	202
	203	static struct timer_list otg_workaround;
	204
	205	static void otg_timer(unsigned long _musb)
	206	{
	207	struct musb musb = (void )_musb;
	208	void __iomem *mregs = musb->mregs;
	209	u8 devctl;
	210	unsigned long flags;
	211
	212	/* We poll because DaVinci's won't expose several OTG-critical
	213	* status change events (from the transceiver) otherwise.
	214	*/
	215	devctl = musb_readb(mregs, MUSB_DEVCTL);
5c8a86e1	216	dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl,
42c0bf1c	217	usb_otg_state_string(musb->xceiv->state));
550a7375 FB	218
550a7375 FB	219	spin_lock_irqsave(&musb->lock, flags);
84e250ff	220	switch (musb->xceiv->state) {
550a7375 FB	221	case OTG_STATE_A_WAIT_VFALL:
	222	/* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
	223	* seems to mis-handle session "start" otherwise (or in our
	224	* case "recover"), in routine "VBUS was valid by the time
	225	* VBUSERR got reported during enumeration" cases.
	226	*/
	227	if (devctl & MUSB_DEVCTL_VBUS) {
	228	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	229	break;
	230	}
84e250ff	231	musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
550a7375 FB	232	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
	233	MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
	234	break;
	235	case OTG_STATE_B_IDLE:
032ec49f FB	236	/*
032ec49f FB	237	* There's no ID-changed IRQ, so we have no good way to tell
550a7375 FB	238	* when to switch to the A-Default state machine (by setting
	239	* the DEVCTL.SESSION flag).
	240	*
	241	* Workaround: whenever we're in B_IDLE, try setting the
	242	* session flag every few seconds. If it works, ID was
	243	* grounded and we're now in the A-Default state machine.
	244	*
	245	* NOTE setting the session flag is _supposed_ to trigger
	246	* SRP, but clearly it doesn't.
	247	*/
	248	musb_writeb(mregs, MUSB_DEVCTL,
	249	devctl \| MUSB_DEVCTL_SESSION);
	250	devctl = musb_readb(mregs, MUSB_DEVCTL);
	251	if (devctl & MUSB_DEVCTL_BDEVICE)
	252	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	253	else
84e250ff	254	musb->xceiv->state = OTG_STATE_A_IDLE;
550a7375 FB	255	break;
	256	default:
	257	break;
	258	}
	259	spin_unlock_irqrestore(&musb->lock, flags);
	260	}
	261
743411b3	262	static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
550a7375 FB	263	{
	264	unsigned long flags;
	265	irqreturn_t retval = IRQ_NONE;
	266	struct musb *musb = __hci;
d445b6da	267	struct usb_otg *otg = musb->xceiv->otg;
550a7375	268	void __iomem *tibase = musb->ctrl_base;
91e9c4fe	269	struct cppi *cppi;
550a7375 FB	270	u32 tmp;
	271
	272	spin_lock_irqsave(&musb->lock, flags);
	273
	274	/* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
	275	* the Mentor registers (except for setup), use the TI ones and EOI.
	276	*
dfff0615	277	* Docs describe irq "vector" registers associated with the CPPI and
550a7375 FB	278	* USB EOI registers. These hold a bitmask corresponding to the
	279	* current IRQ, not an irq handler address. Would using those bits
	280	* resolve some of the races observed in this dispatch code??
	281	*/
	282
	283	/* CPPI interrupts share the same IRQ line, but have their own
	284	* mask, state, "vector", and EOI registers.
	285	*/
91e9c4fe SS	286	cppi = container_of(musb->dma_controller, struct cppi, controller);
	287	if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
	288	retval = cppi_interrupt(irq, __hci);
550a7375 FB	289
	290	/* ack and handle non-CPPI interrupts */
	291	tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
	292	musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
5c8a86e1	293	dev_dbg(musb->controller, "IRQ %08x\n", tmp);
550a7375 FB	294
	295	musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
	296	>> DAVINCI_USB_RXINT_SHIFT;
	297	musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
	298	>> DAVINCI_USB_TXINT_SHIFT;
	299	musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
	300	>> DAVINCI_USB_USBINT_SHIFT;
	301
	302	/* DRVVBUS irqs are the only proxy we have (a very poor one!) for
	303	* DaVinci's missing ID change IRQ. We need an ID change IRQ to
	304	* switch appropriately between halves of the OTG state machine.
	305	* Managing DEVCTL.SESSION per Mentor docs requires we know its
	306	* value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
	307	* Also, DRVVBUS pulses for SRP (but not at 5V) ...
	308	*/
	309	if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
	310	int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
	311	void __iomem *mregs = musb->mregs;
	312	u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
	313	int err = musb->int_usb & MUSB_INTR_VBUSERROR;
	314
032ec49f	315	err = musb->int_usb & MUSB_INTR_VBUSERROR;
550a7375 FB	316	if (err) {
	317	/* The Mentor core doesn't debounce VBUS as needed
	318	* to cope with device connect current spikes. This
	319	* means it's not uncommon for bus-powered devices
	320	* to get VBUS errors during enumeration.
	321	*
	322	* This is a workaround, but newer RTL from Mentor
	323	* seems to allow a better one: "re"starting sessions
	324	* without waiting (on EVM, a long time) for VBUS
	325	* to stop registering in devctl.
	326	*/
	327	musb->int_usb &= ~MUSB_INTR_VBUSERROR;
84e250ff	328	musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
550a7375 FB	329	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
550a7375 FB	330	WARNING("VBUS error workaround (delay coming)\n");
032ec49f	331	} else if (drvvbus) {
550a7375	332	MUSB_HST_MODE(musb);
d445b6da	333	otg->default_a = 1;
84e250ff	334	musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
550a7375 FB	335	portstate(musb->port1_status \|= USB_PORT_STAT_POWER);
	336	del_timer(&otg_workaround);
	337	} else {
	338	musb->is_active = 0;
	339	MUSB_DEV_MODE(musb);
d445b6da	340	otg->default_a = 0;
84e250ff	341	musb->xceiv->state = OTG_STATE_B_IDLE;
550a7375 FB	342	portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
	343	}
	344
89368d3d DB	345	/* NOTE: this must complete poweron within 100 msec
	346	* (OTG_TIME_A_WAIT_VRISE) but we don't check for that.
	347	*/
743411b3	348	davinci_musb_source_power(musb, drvvbus, 0);
5c8a86e1	349	dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
550a7375	350	drvvbus ? "on" : "off",
42c0bf1c	351	usb_otg_state_string(musb->xceiv->state),
550a7375 FB	352	err ? " ERROR" : "",
	353	devctl);
	354	retval = IRQ_HANDLED;
	355	}
	356
	357	if (musb->int_tx \|\| musb->int_rx \|\| musb->int_usb)
	358	retval \|= musb_interrupt(musb);
	359
	360	/* irq stays asserted until EOI is written */
	361	musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
	362
	363	/* poll for ID change */
032ec49f	364	if (musb->xceiv->state == OTG_STATE_B_IDLE)
550a7375 FB	365	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	366
	367	spin_unlock_irqrestore(&musb->lock, flags);
	368
a5073b52	369	return retval;
550a7375 FB	370	}
550a7375 FB	371
743411b3	372	static int davinci_musb_set_mode(struct musb *musb, u8 mode)
96a274d1 DB	373	{
	374	/* EVM can't do this (right?) */
	375	return -EIO;
	376	}
	377
743411b3	378	static int davinci_musb_init(struct musb *musb)
550a7375 FB	379	{
	380	void __iomem *tibase = musb->ctrl_base;
	381	u32 revision;
25736e0c	382	int ret = -ENODEV;
550a7375	383
662dca54	384	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
25736e0c ML	385	if (IS_ERR_OR_NULL(musb->xceiv)) {
25736e0c ML	386	ret = -EPROBE_DEFER;
c67dd31c	387	goto unregister;
25736e0c	388	}
84e250ff	389
550a7375	390	musb->mregs += DAVINCI_BASE_OFFSET;
550a7375	391
550a7375 FB	392	/* returns zero if e.g. not clocked */
	393	revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
	394	if (revision == 0)
84e250ff	395	goto fail;
550a7375	396
032ec49f	397	setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
550a7375	398
743411b3	399	davinci_musb_source_power(musb, 0, 1);
550a7375	400
a227fd7d DB	401	/* dm355 EVM swaps D+/D- for signal integrity, and
	402	* is clocked from the main 24 MHz crystal.
	403	*/
	404	if (machine_is_davinci_dm355_evm()) {
	405	u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
	406
	407	phy_ctrl &= ~(3 << 9);
	408	phy_ctrl \|= USBPHY_DATAPOL;
	409	__raw_writel(phy_ctrl, USB_PHY_CTRL);
	410	}
	411
d163ef24 DB	412	/* On dm355, the default-A state machine needs DRVVBUS control.
	413	* If we won't be a host, there's no need to turn it on.
	414	*/
	415	if (cpu_is_davinci_dm355()) {
	416	u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
	417
032ec49f	418	deepsleep &= ~DRVVBUS_FORCE;
d163ef24 DB	419	__raw_writel(deepsleep, DM355_DEEPSLEEP);
	420	}
	421
550a7375 FB	422	/* reset the controller */
	423	musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
	424
	425	/* start the on-chip PHY and its PLL */
	426	phy_on();
	427
	428	msleep(5);
	429
	430	/* NOTE: irqs are in mixed mode, not bypass to pure-musb */
	431	pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
a227fd7d	432	revision, __raw_readl(USB_PHY_CTRL),
550a7375 FB	433	musb_readb(tibase, DAVINCI_USB_CTRL_REG));
550a7375 FB	434
743411b3	435	musb->isr = davinci_musb_interrupt;
550a7375	436	return 0;
84e250ff DB	437
84e250ff DB	438	fail:
721002ec	439	usb_put_phy(musb->xceiv);
c67dd31c	440	unregister:
4525beeb	441	usb_phy_generic_unregister();
25736e0c	442	return ret;
550a7375 FB	443	}
550a7375 FB	444
743411b3	445	static int davinci_musb_exit(struct musb *musb)
550a7375	446	{
032ec49f	447	del_timer_sync(&otg_workaround);
550a7375	448
d163ef24 DB	449	/* force VBUS off */
	450	if (cpu_is_davinci_dm355()) {
	451	u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
	452
	453	deepsleep &= ~DRVVBUS_FORCE;
	454	deepsleep \|= DRVVBUS_OVERRIDE;
	455	__raw_writel(deepsleep, DM355_DEEPSLEEP);
	456	}
	457
743411b3	458	davinci_musb_source_power(musb, 0 /off/, 1);
550a7375 FB	459
550a7375 FB	460	/* delay, to avoid problems with module reload */
032ec49f	461	if (musb->xceiv->otg->default_a) {
550a7375 FB	462	int maxdelay = 30;
	463	u8 devctl, warn = 0;
	464
	465	/* if there's no peripheral connected, this can take a
	466	* long time to fall, especially on EVM with huge C133.
	467	*/
	468	do {
	469	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
	470	if (!(devctl & MUSB_DEVCTL_VBUS))
	471	break;
	472	if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
	473	warn = devctl & MUSB_DEVCTL_VBUS;
5c8a86e1	474	dev_dbg(musb->controller, "VBUS %d\n",
550a7375 FB	475	warn >> MUSB_DEVCTL_VBUS_SHIFT);
	476	}
	477	msleep(1000);
	478	maxdelay--;
	479	} while (maxdelay > 0);
	480
	481	/* in OTG mode, another host might be connected */
	482	if (devctl & MUSB_DEVCTL_VBUS)
5c8a86e1	483	dev_dbg(musb->controller, "VBUS off timeout (devctl %02x)\n", devctl);
550a7375 FB	484	}
	485
	486	phy_off();
34f32c97	487
721002ec	488	usb_put_phy(musb->xceiv);
84e250ff	489
550a7375 FB	490	return 0;
550a7375 FB	491	}
743411b3	492
f7ec9437	493	static const struct musb_platform_ops davinci_ops = {
743411b3 FB	494	.init = davinci_musb_init,
	495	.exit = davinci_musb_exit,
	496
	497	.enable = davinci_musb_enable,
	498	.disable = davinci_musb_disable,
	499
	500	.set_mode = davinci_musb_set_mode,
	501
	502	.set_vbus = davinci_musb_set_vbus,
	503	};
73b089b0	504
af384875 RK	505	static const struct platform_device_info davinci_dev_info = {
	506	.name = "musb-hdrc",
	507	.id = PLATFORM_DEVID_AUTO,
	508	.dma_mask = DMA_BIT_MASK(32),
	509	};
73b089b0	510
41ac7b3a	511	static int davinci_probe(struct platform_device *pdev)
73b089b0	512	{
ea78201e	513	struct resource musb_resources[3];
c1a7d67c	514	struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
73b089b0	515	struct platform_device *musb;
e110de4d	516	struct davinci_glue *glue;
af384875	517	struct platform_device_info pinfo;
03491761	518	struct clk *clk;
73b089b0 FB	519
	520	int ret = -ENOMEM;
	521
276f146a	522	glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
26c07010	523	if (!glue)
e110de4d	524	goto err0;
e110de4d	525
276f146a	526	clk = devm_clk_get(&pdev->dev, "usb");
03491761 FB	527	if (IS_ERR(clk)) {
	528	dev_err(&pdev->dev, "failed to get clock\n");
	529	ret = PTR_ERR(clk);
276f146a	530	goto err0;
03491761 FB	531	}
	532
	533	ret = clk_enable(clk);
	534	if (ret) {
	535	dev_err(&pdev->dev, "failed to enable clock\n");
276f146a	536	goto err0;
03491761 FB	537	}
03491761 FB	538
e110de4d	539	glue->dev = &pdev->dev;
03491761	540	glue->clk = clk;
e110de4d	541
f7ec9437 FB	542	pdata->platform_ops = &davinci_ops;
f7ec9437 FB	543
e741e637	544	usb_phy_generic_register();
e110de4d	545	platform_set_drvdata(pdev, glue);
73b089b0	546
09fc7d22 FB	547	memset(musb_resources, 0x00, sizeof(musb_resources)
	548	ARRAY_SIZE(musb_resources));
	549
	550	musb_resources[0].name = pdev->resource[0].name;
	551	musb_resources[0].start = pdev->resource[0].start;
	552	musb_resources[0].end = pdev->resource[0].end;
	553	musb_resources[0].flags = pdev->resource[0].flags;
	554
	555	musb_resources[1].name = pdev->resource[1].name;
	556	musb_resources[1].start = pdev->resource[1].start;
	557	musb_resources[1].end = pdev->resource[1].end;
	558	musb_resources[1].flags = pdev->resource[1].flags;
ea78201e SS	559
	560	/*
	561	* For DM6467 3 resources are passed. A placeholder for the 3rd
	562	* resource is always there, so it's safe to always copy it...
	563	*/
	564	musb_resources[2].name = pdev->resource[2].name;
	565	musb_resources[2].start = pdev->resource[2].start;
	566	musb_resources[2].end = pdev->resource[2].end;
	567	musb_resources[2].flags = pdev->resource[2].flags;
09fc7d22	568
af384875 RK	569	pinfo = davinci_dev_info;
	570	pinfo.parent = &pdev->dev;
	571	pinfo.res = musb_resources;
	572	pinfo.num_res = ARRAY_SIZE(musb_resources);
	573	pinfo.data = pdata;
	574	pinfo.size_data = sizeof(*pdata);
	575
	576	glue->musb = musb = platform_device_register_full(&pinfo);
	577	if (IS_ERR(musb)) {
	578	ret = PTR_ERR(musb);
	579	dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
276f146a	580	goto err1;
73b089b0 FB	581	}
	582
	583	return 0;
	584
276f146a	585	err1:
03491761 FB	586	clk_disable(clk);
03491761 FB	587
73b089b0 FB	588	err0:
	589	return ret;
	590	}
	591
fb4e98ab	592	static int davinci_remove(struct platform_device *pdev)
73b089b0	593	{
e110de4d	594	struct davinci_glue *glue = platform_get_drvdata(pdev);
73b089b0	595
12a71f5b	596	platform_device_unregister(glue->musb);
e741e637	597	usb_phy_generic_unregister();
03491761	598	clk_disable(glue->clk);
73b089b0 FB	599
	600	return 0;
	601	}
	602
	603	static struct platform_driver davinci_driver = {
e9e8c85e	604	.probe = davinci_probe,
7690417d	605	.remove = davinci_remove,
73b089b0 FB	606	.driver = {
	607	.name = "musb-davinci",
	608	},
	609	};
	610
	611	MODULE_DESCRIPTION("DaVinci MUSB Glue Layer");
	612	MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
	613	MODULE_LICENSE("GPL v2");
8d92f6d4	614	module_platform_driver(davinci_driver);