Commit | Line | Data |
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550a7375 FB |
1 | /* |
2 | * Copyright (C) 2005-2006 by Texas Instruments | |
3 | * | |
4 | * This file is part of the Inventra Controller Driver for Linux. | |
5 | * | |
6 | * The Inventra Controller Driver for Linux is free software; you | |
7 | * can redistribute it and/or modify it under the terms of the GNU | |
8 | * General Public License version 2 as published by the Free Software | |
9 | * Foundation. | |
10 | * | |
11 | * The Inventra Controller Driver for Linux is distributed in | |
12 | * the hope that it will be useful, but WITHOUT ANY WARRANTY; | |
13 | * without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | * License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with The Inventra Controller Driver for Linux ; if not, | |
19 | * write to the Free Software Foundation, Inc., 59 Temple Place, | |
20 | * Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/sched.h> | |
550a7375 FB |
27 | #include <linux/init.h> |
28 | #include <linux/list.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/clk.h> | |
31 | #include <linux/io.h> | |
c767c1c6 | 32 | #include <linux/gpio.h> |
73b089b0 FB |
33 | #include <linux/platform_device.h> |
34 | #include <linux/dma-mapping.h> | |
550a7375 | 35 | |
d163ef24 | 36 | #include <mach/cputype.h> |
6594b2d7 | 37 | #include <mach/hardware.h> |
10b4eade | 38 | |
550a7375 FB |
39 | #include <asm/mach-types.h> |
40 | ||
41 | #include "musb_core.h" | |
42 | ||
43 | #ifdef CONFIG_MACH_DAVINCI_EVM | |
a2396a32 | 44 | #define GPIO_nVBUS_DRV 160 |
550a7375 FB |
45 | #endif |
46 | ||
47 | #include "davinci.h" | |
48 | #include "cppi_dma.h" | |
49 | ||
50 | ||
a227fd7d DB |
51 | #define USB_PHY_CTRL IO_ADDRESS(USBPHY_CTL_PADDR) |
52 | #define DM355_DEEPSLEEP IO_ADDRESS(DM355_DEEPSLEEP_PADDR) | |
53 | ||
e110de4d FB |
54 | struct davinci_glue { |
55 | struct device *dev; | |
56 | struct platform_device *musb; | |
03491761 | 57 | struct clk *clk; |
e110de4d FB |
58 | }; |
59 | ||
550a7375 FB |
60 | /* REVISIT (PM) we should be able to keep the PHY in low power mode most |
61 | * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0 | |
62 | * and, when in host mode, autosuspending idle root ports... PHYPLLON | |
63 | * (overriding SUSPENDM?) then likely needs to stay off. | |
64 | */ | |
65 | ||
66 | static inline void phy_on(void) | |
67 | { | |
a227fd7d DB |
68 | u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); |
69 | ||
70 | /* power everything up; start the on-chip PHY and its PLL */ | |
71 | phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN); | |
72 | phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON; | |
73 | __raw_writel(phy_ctrl, USB_PHY_CTRL); | |
74 | ||
75 | /* wait for PLL to lock before proceeding */ | |
76 | while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0) | |
550a7375 FB |
77 | cpu_relax(); |
78 | } | |
79 | ||
80 | static inline void phy_off(void) | |
81 | { | |
a227fd7d DB |
82 | u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); |
83 | ||
84 | /* powerdown the on-chip PHY, its PLL, and the OTG block */ | |
85 | phy_ctrl &= ~(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON); | |
86 | phy_ctrl |= USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN; | |
87 | __raw_writel(phy_ctrl, USB_PHY_CTRL); | |
550a7375 FB |
88 | } |
89 | ||
90 | static int dma_off = 1; | |
91 | ||
743411b3 | 92 | static void davinci_musb_enable(struct musb *musb) |
550a7375 FB |
93 | { |
94 | u32 tmp, old, val; | |
95 | ||
96 | /* workaround: setup irqs through both register sets */ | |
97 | tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK) | |
98 | << DAVINCI_USB_TXINT_SHIFT; | |
99 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); | |
100 | old = tmp; | |
101 | tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK)) | |
102 | << DAVINCI_USB_RXINT_SHIFT; | |
103 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); | |
104 | tmp |= old; | |
105 | ||
106 | val = ~MUSB_INTR_SOF; | |
107 | tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT); | |
108 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); | |
109 | ||
110 | if (is_dma_capable() && !dma_off) | |
111 | printk(KERN_WARNING "%s %s: dma not reactivated\n", | |
112 | __FILE__, __func__); | |
113 | else | |
114 | dma_off = 0; | |
115 | ||
116 | /* force a DRVVBUS irq so we can start polling for ID change */ | |
117 | if (is_otg_enabled(musb)) | |
118 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG, | |
119 | DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT); | |
120 | } | |
121 | ||
122 | /* | |
123 | * Disable the HDRC and flush interrupts | |
124 | */ | |
743411b3 | 125 | static void davinci_musb_disable(struct musb *musb) |
550a7375 FB |
126 | { |
127 | /* because we don't set CTRLR.UINT, "important" to: | |
128 | * - not read/write INTRUSB/INTRUSBE | |
129 | * - (except during initial setup, as workaround) | |
130 | * - use INTSETR/INTCLRR instead | |
131 | */ | |
132 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG, | |
133 | DAVINCI_USB_USBINT_MASK | |
134 | | DAVINCI_USB_TXINT_MASK | |
135 | | DAVINCI_USB_RXINT_MASK); | |
136 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
137 | musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0); | |
138 | ||
139 | if (is_dma_capable() && !dma_off) | |
140 | WARNING("dma still active\n"); | |
141 | } | |
142 | ||
143 | ||
550a7375 | 144 | #define portstate(stmt) stmt |
550a7375 | 145 | |
a227fd7d DB |
146 | /* |
147 | * VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM, | |
148 | * which doesn't wire DRVVBUS to the FET that switches it. Unclear | |
149 | * if that's a problem with the DM6446 chip or just with that board. | |
150 | * | |
151 | * In either case, the DM355 EVM automates DRVVBUS the normal way, | |
152 | * when J10 is out, and TI documents it as handling OTG. | |
153 | */ | |
550a7375 FB |
154 | |
155 | #ifdef CONFIG_MACH_DAVINCI_EVM | |
550a7375 | 156 | |
a227fd7d DB |
157 | static int vbus_state = -1; |
158 | ||
550a7375 FB |
159 | /* I2C operations are always synchronous, and require a task context. |
160 | * With unloaded systems, using the shared workqueue seems to suffice | |
161 | * to satisfy the 100msec A_WAIT_VRISE timeout... | |
162 | */ | |
163 | static void evm_deferred_drvvbus(struct work_struct *ignored) | |
164 | { | |
c767c1c6 | 165 | gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state); |
550a7375 FB |
166 | vbus_state = !vbus_state; |
167 | } | |
550a7375 | 168 | |
550a7375 FB |
169 | #endif /* EVM */ |
170 | ||
743411b3 | 171 | static void davinci_musb_source_power(struct musb *musb, int is_on, int immediate) |
550a7375 | 172 | { |
a227fd7d | 173 | #ifdef CONFIG_MACH_DAVINCI_EVM |
550a7375 FB |
174 | if (is_on) |
175 | is_on = 1; | |
176 | ||
177 | if (vbus_state == is_on) | |
178 | return; | |
179 | vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */ | |
180 | ||
550a7375 | 181 | if (machine_is_davinci_evm()) { |
a227fd7d DB |
182 | static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus); |
183 | ||
550a7375 | 184 | if (immediate) |
c767c1c6 | 185 | gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state); |
550a7375 FB |
186 | else |
187 | schedule_work(&evm_vbus_work); | |
550a7375 | 188 | } |
550a7375 FB |
189 | if (immediate) |
190 | vbus_state = is_on; | |
a227fd7d | 191 | #endif |
550a7375 FB |
192 | } |
193 | ||
743411b3 | 194 | static void davinci_musb_set_vbus(struct musb *musb, int is_on) |
550a7375 FB |
195 | { |
196 | WARN_ON(is_on && is_peripheral_active(musb)); | |
743411b3 | 197 | davinci_musb_source_power(musb, is_on, 0); |
550a7375 FB |
198 | } |
199 | ||
200 | ||
201 | #define POLL_SECONDS 2 | |
202 | ||
203 | static struct timer_list otg_workaround; | |
204 | ||
205 | static void otg_timer(unsigned long _musb) | |
206 | { | |
207 | struct musb *musb = (void *)_musb; | |
208 | void __iomem *mregs = musb->mregs; | |
209 | u8 devctl; | |
210 | unsigned long flags; | |
211 | ||
212 | /* We poll because DaVinci's won't expose several OTG-critical | |
213 | * status change events (from the transceiver) otherwise. | |
214 | */ | |
215 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
5c8a86e1 | 216 | dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl, |
3df00453 | 217 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
218 | |
219 | spin_lock_irqsave(&musb->lock, flags); | |
84e250ff | 220 | switch (musb->xceiv->state) { |
550a7375 FB |
221 | case OTG_STATE_A_WAIT_VFALL: |
222 | /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL | |
223 | * seems to mis-handle session "start" otherwise (or in our | |
224 | * case "recover"), in routine "VBUS was valid by the time | |
225 | * VBUSERR got reported during enumeration" cases. | |
226 | */ | |
227 | if (devctl & MUSB_DEVCTL_VBUS) { | |
228 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
229 | break; | |
230 | } | |
84e250ff | 231 | musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; |
550a7375 FB |
232 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG, |
233 | MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT); | |
234 | break; | |
235 | case OTG_STATE_B_IDLE: | |
236 | if (!is_peripheral_enabled(musb)) | |
237 | break; | |
238 | ||
239 | /* There's no ID-changed IRQ, so we have no good way to tell | |
240 | * when to switch to the A-Default state machine (by setting | |
241 | * the DEVCTL.SESSION flag). | |
242 | * | |
243 | * Workaround: whenever we're in B_IDLE, try setting the | |
244 | * session flag every few seconds. If it works, ID was | |
245 | * grounded and we're now in the A-Default state machine. | |
246 | * | |
247 | * NOTE setting the session flag is _supposed_ to trigger | |
248 | * SRP, but clearly it doesn't. | |
249 | */ | |
250 | musb_writeb(mregs, MUSB_DEVCTL, | |
251 | devctl | MUSB_DEVCTL_SESSION); | |
252 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
253 | if (devctl & MUSB_DEVCTL_BDEVICE) | |
254 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
255 | else | |
84e250ff | 256 | musb->xceiv->state = OTG_STATE_A_IDLE; |
550a7375 FB |
257 | break; |
258 | default: | |
259 | break; | |
260 | } | |
261 | spin_unlock_irqrestore(&musb->lock, flags); | |
262 | } | |
263 | ||
743411b3 | 264 | static irqreturn_t davinci_musb_interrupt(int irq, void *__hci) |
550a7375 FB |
265 | { |
266 | unsigned long flags; | |
267 | irqreturn_t retval = IRQ_NONE; | |
268 | struct musb *musb = __hci; | |
d445b6da | 269 | struct usb_otg *otg = musb->xceiv->otg; |
550a7375 | 270 | void __iomem *tibase = musb->ctrl_base; |
91e9c4fe | 271 | struct cppi *cppi; |
550a7375 FB |
272 | u32 tmp; |
273 | ||
274 | spin_lock_irqsave(&musb->lock, flags); | |
275 | ||
276 | /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through | |
277 | * the Mentor registers (except for setup), use the TI ones and EOI. | |
278 | * | |
dfff0615 | 279 | * Docs describe irq "vector" registers associated with the CPPI and |
550a7375 FB |
280 | * USB EOI registers. These hold a bitmask corresponding to the |
281 | * current IRQ, not an irq handler address. Would using those bits | |
282 | * resolve some of the races observed in this dispatch code?? | |
283 | */ | |
284 | ||
285 | /* CPPI interrupts share the same IRQ line, but have their own | |
286 | * mask, state, "vector", and EOI registers. | |
287 | */ | |
91e9c4fe SS |
288 | cppi = container_of(musb->dma_controller, struct cppi, controller); |
289 | if (is_cppi_enabled() && musb->dma_controller && !cppi->irq) | |
290 | retval = cppi_interrupt(irq, __hci); | |
550a7375 FB |
291 | |
292 | /* ack and handle non-CPPI interrupts */ | |
293 | tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG); | |
294 | musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp); | |
5c8a86e1 | 295 | dev_dbg(musb->controller, "IRQ %08x\n", tmp); |
550a7375 FB |
296 | |
297 | musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK) | |
298 | >> DAVINCI_USB_RXINT_SHIFT; | |
299 | musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK) | |
300 | >> DAVINCI_USB_TXINT_SHIFT; | |
301 | musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK) | |
302 | >> DAVINCI_USB_USBINT_SHIFT; | |
303 | ||
304 | /* DRVVBUS irqs are the only proxy we have (a very poor one!) for | |
305 | * DaVinci's missing ID change IRQ. We need an ID change IRQ to | |
306 | * switch appropriately between halves of the OTG state machine. | |
307 | * Managing DEVCTL.SESSION per Mentor docs requires we know its | |
308 | * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set. | |
309 | * Also, DRVVBUS pulses for SRP (but not at 5V) ... | |
310 | */ | |
311 | if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) { | |
312 | int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG); | |
313 | void __iomem *mregs = musb->mregs; | |
314 | u8 devctl = musb_readb(mregs, MUSB_DEVCTL); | |
315 | int err = musb->int_usb & MUSB_INTR_VBUSERROR; | |
316 | ||
317 | err = is_host_enabled(musb) | |
318 | && (musb->int_usb & MUSB_INTR_VBUSERROR); | |
319 | if (err) { | |
320 | /* The Mentor core doesn't debounce VBUS as needed | |
321 | * to cope with device connect current spikes. This | |
322 | * means it's not uncommon for bus-powered devices | |
323 | * to get VBUS errors during enumeration. | |
324 | * | |
325 | * This is a workaround, but newer RTL from Mentor | |
326 | * seems to allow a better one: "re"starting sessions | |
327 | * without waiting (on EVM, a **long** time) for VBUS | |
328 | * to stop registering in devctl. | |
329 | */ | |
330 | musb->int_usb &= ~MUSB_INTR_VBUSERROR; | |
84e250ff | 331 | musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; |
550a7375 FB |
332 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); |
333 | WARNING("VBUS error workaround (delay coming)\n"); | |
334 | } else if (is_host_enabled(musb) && drvvbus) { | |
550a7375 | 335 | MUSB_HST_MODE(musb); |
d445b6da | 336 | otg->default_a = 1; |
84e250ff | 337 | musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; |
550a7375 FB |
338 | portstate(musb->port1_status |= USB_PORT_STAT_POWER); |
339 | del_timer(&otg_workaround); | |
340 | } else { | |
341 | musb->is_active = 0; | |
342 | MUSB_DEV_MODE(musb); | |
d445b6da | 343 | otg->default_a = 0; |
84e250ff | 344 | musb->xceiv->state = OTG_STATE_B_IDLE; |
550a7375 FB |
345 | portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); |
346 | } | |
347 | ||
89368d3d DB |
348 | /* NOTE: this must complete poweron within 100 msec |
349 | * (OTG_TIME_A_WAIT_VRISE) but we don't check for that. | |
350 | */ | |
743411b3 | 351 | davinci_musb_source_power(musb, drvvbus, 0); |
5c8a86e1 | 352 | dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n", |
550a7375 | 353 | drvvbus ? "on" : "off", |
3df00453 | 354 | otg_state_string(musb->xceiv->state), |
550a7375 FB |
355 | err ? " ERROR" : "", |
356 | devctl); | |
357 | retval = IRQ_HANDLED; | |
358 | } | |
359 | ||
360 | if (musb->int_tx || musb->int_rx || musb->int_usb) | |
361 | retval |= musb_interrupt(musb); | |
362 | ||
363 | /* irq stays asserted until EOI is written */ | |
364 | musb_writel(tibase, DAVINCI_USB_EOI_REG, 0); | |
365 | ||
366 | /* poll for ID change */ | |
367 | if (is_otg_enabled(musb) | |
84e250ff | 368 | && musb->xceiv->state == OTG_STATE_B_IDLE) |
550a7375 FB |
369 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); |
370 | ||
371 | spin_unlock_irqrestore(&musb->lock, flags); | |
372 | ||
a5073b52 | 373 | return retval; |
550a7375 FB |
374 | } |
375 | ||
743411b3 | 376 | static int davinci_musb_set_mode(struct musb *musb, u8 mode) |
96a274d1 DB |
377 | { |
378 | /* EVM can't do this (right?) */ | |
379 | return -EIO; | |
380 | } | |
381 | ||
743411b3 | 382 | static int davinci_musb_init(struct musb *musb) |
550a7375 FB |
383 | { |
384 | void __iomem *tibase = musb->ctrl_base; | |
385 | u32 revision; | |
386 | ||
84e250ff | 387 | usb_nop_xceiv_register(); |
b96d3b08 | 388 | musb->xceiv = usb_get_transceiver(); |
84e250ff | 389 | if (!musb->xceiv) |
c67dd31c | 390 | goto unregister; |
84e250ff | 391 | |
550a7375 | 392 | musb->mregs += DAVINCI_BASE_OFFSET; |
550a7375 | 393 | |
550a7375 FB |
394 | /* returns zero if e.g. not clocked */ |
395 | revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG); | |
396 | if (revision == 0) | |
84e250ff | 397 | goto fail; |
550a7375 FB |
398 | |
399 | if (is_host_enabled(musb)) | |
400 | setup_timer(&otg_workaround, otg_timer, (unsigned long) musb); | |
401 | ||
743411b3 | 402 | davinci_musb_source_power(musb, 0, 1); |
550a7375 | 403 | |
a227fd7d DB |
404 | /* dm355 EVM swaps D+/D- for signal integrity, and |
405 | * is clocked from the main 24 MHz crystal. | |
406 | */ | |
407 | if (machine_is_davinci_dm355_evm()) { | |
408 | u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); | |
409 | ||
410 | phy_ctrl &= ~(3 << 9); | |
411 | phy_ctrl |= USBPHY_DATAPOL; | |
412 | __raw_writel(phy_ctrl, USB_PHY_CTRL); | |
413 | } | |
414 | ||
d163ef24 DB |
415 | /* On dm355, the default-A state machine needs DRVVBUS control. |
416 | * If we won't be a host, there's no need to turn it on. | |
417 | */ | |
418 | if (cpu_is_davinci_dm355()) { | |
419 | u32 deepsleep = __raw_readl(DM355_DEEPSLEEP); | |
420 | ||
421 | if (is_host_enabled(musb)) { | |
422 | deepsleep &= ~DRVVBUS_OVERRIDE; | |
423 | } else { | |
424 | deepsleep &= ~DRVVBUS_FORCE; | |
425 | deepsleep |= DRVVBUS_OVERRIDE; | |
426 | } | |
427 | __raw_writel(deepsleep, DM355_DEEPSLEEP); | |
428 | } | |
429 | ||
550a7375 FB |
430 | /* reset the controller */ |
431 | musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1); | |
432 | ||
433 | /* start the on-chip PHY and its PLL */ | |
434 | phy_on(); | |
435 | ||
436 | msleep(5); | |
437 | ||
438 | /* NOTE: irqs are in mixed mode, not bypass to pure-musb */ | |
439 | pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n", | |
a227fd7d | 440 | revision, __raw_readl(USB_PHY_CTRL), |
550a7375 FB |
441 | musb_readb(tibase, DAVINCI_USB_CTRL_REG)); |
442 | ||
743411b3 | 443 | musb->isr = davinci_musb_interrupt; |
550a7375 | 444 | return 0; |
84e250ff DB |
445 | |
446 | fail: | |
b96d3b08 | 447 | usb_put_transceiver(musb->xceiv); |
c67dd31c | 448 | unregister: |
84e250ff DB |
449 | usb_nop_xceiv_unregister(); |
450 | return -ENODEV; | |
550a7375 FB |
451 | } |
452 | ||
743411b3 | 453 | static int davinci_musb_exit(struct musb *musb) |
550a7375 FB |
454 | { |
455 | if (is_host_enabled(musb)) | |
456 | del_timer_sync(&otg_workaround); | |
457 | ||
d163ef24 DB |
458 | /* force VBUS off */ |
459 | if (cpu_is_davinci_dm355()) { | |
460 | u32 deepsleep = __raw_readl(DM355_DEEPSLEEP); | |
461 | ||
462 | deepsleep &= ~DRVVBUS_FORCE; | |
463 | deepsleep |= DRVVBUS_OVERRIDE; | |
464 | __raw_writel(deepsleep, DM355_DEEPSLEEP); | |
465 | } | |
466 | ||
743411b3 | 467 | davinci_musb_source_power(musb, 0 /*off*/, 1); |
550a7375 FB |
468 | |
469 | /* delay, to avoid problems with module reload */ | |
d445b6da | 470 | if (is_host_enabled(musb) && musb->xceiv->otg->default_a) { |
550a7375 FB |
471 | int maxdelay = 30; |
472 | u8 devctl, warn = 0; | |
473 | ||
474 | /* if there's no peripheral connected, this can take a | |
475 | * long time to fall, especially on EVM with huge C133. | |
476 | */ | |
477 | do { | |
478 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
479 | if (!(devctl & MUSB_DEVCTL_VBUS)) | |
480 | break; | |
481 | if ((devctl & MUSB_DEVCTL_VBUS) != warn) { | |
482 | warn = devctl & MUSB_DEVCTL_VBUS; | |
5c8a86e1 | 483 | dev_dbg(musb->controller, "VBUS %d\n", |
550a7375 FB |
484 | warn >> MUSB_DEVCTL_VBUS_SHIFT); |
485 | } | |
486 | msleep(1000); | |
487 | maxdelay--; | |
488 | } while (maxdelay > 0); | |
489 | ||
490 | /* in OTG mode, another host might be connected */ | |
491 | if (devctl & MUSB_DEVCTL_VBUS) | |
5c8a86e1 | 492 | dev_dbg(musb->controller, "VBUS off timeout (devctl %02x)\n", devctl); |
550a7375 FB |
493 | } |
494 | ||
495 | phy_off(); | |
34f32c97 | 496 | |
b96d3b08 | 497 | usb_put_transceiver(musb->xceiv); |
84e250ff DB |
498 | usb_nop_xceiv_unregister(); |
499 | ||
550a7375 FB |
500 | return 0; |
501 | } | |
743411b3 | 502 | |
f7ec9437 | 503 | static const struct musb_platform_ops davinci_ops = { |
743411b3 FB |
504 | .init = davinci_musb_init, |
505 | .exit = davinci_musb_exit, | |
506 | ||
507 | .enable = davinci_musb_enable, | |
508 | .disable = davinci_musb_disable, | |
509 | ||
510 | .set_mode = davinci_musb_set_mode, | |
511 | ||
512 | .set_vbus = davinci_musb_set_vbus, | |
513 | }; | |
73b089b0 FB |
514 | |
515 | static u64 davinci_dmamask = DMA_BIT_MASK(32); | |
516 | ||
e9e8c85e | 517 | static int __devinit davinci_probe(struct platform_device *pdev) |
73b089b0 FB |
518 | { |
519 | struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data; | |
520 | struct platform_device *musb; | |
e110de4d | 521 | struct davinci_glue *glue; |
03491761 | 522 | struct clk *clk; |
73b089b0 FB |
523 | |
524 | int ret = -ENOMEM; | |
525 | ||
e110de4d FB |
526 | glue = kzalloc(sizeof(*glue), GFP_KERNEL); |
527 | if (!glue) { | |
528 | dev_err(&pdev->dev, "failed to allocate glue context\n"); | |
529 | goto err0; | |
530 | } | |
531 | ||
73b089b0 FB |
532 | musb = platform_device_alloc("musb-hdrc", -1); |
533 | if (!musb) { | |
534 | dev_err(&pdev->dev, "failed to allocate musb device\n"); | |
e110de4d | 535 | goto err1; |
73b089b0 FB |
536 | } |
537 | ||
03491761 FB |
538 | clk = clk_get(&pdev->dev, "usb"); |
539 | if (IS_ERR(clk)) { | |
540 | dev_err(&pdev->dev, "failed to get clock\n"); | |
541 | ret = PTR_ERR(clk); | |
542 | goto err2; | |
543 | } | |
544 | ||
545 | ret = clk_enable(clk); | |
546 | if (ret) { | |
547 | dev_err(&pdev->dev, "failed to enable clock\n"); | |
548 | goto err3; | |
549 | } | |
550 | ||
73b089b0 FB |
551 | musb->dev.parent = &pdev->dev; |
552 | musb->dev.dma_mask = &davinci_dmamask; | |
553 | musb->dev.coherent_dma_mask = davinci_dmamask; | |
554 | ||
e110de4d FB |
555 | glue->dev = &pdev->dev; |
556 | glue->musb = musb; | |
03491761 | 557 | glue->clk = clk; |
e110de4d | 558 | |
f7ec9437 FB |
559 | pdata->platform_ops = &davinci_ops; |
560 | ||
e110de4d | 561 | platform_set_drvdata(pdev, glue); |
73b089b0 FB |
562 | |
563 | ret = platform_device_add_resources(musb, pdev->resource, | |
564 | pdev->num_resources); | |
565 | if (ret) { | |
566 | dev_err(&pdev->dev, "failed to add resources\n"); | |
03491761 | 567 | goto err4; |
73b089b0 FB |
568 | } |
569 | ||
570 | ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); | |
571 | if (ret) { | |
572 | dev_err(&pdev->dev, "failed to add platform_data\n"); | |
03491761 | 573 | goto err4; |
73b089b0 FB |
574 | } |
575 | ||
576 | ret = platform_device_add(musb); | |
577 | if (ret) { | |
578 | dev_err(&pdev->dev, "failed to register musb device\n"); | |
03491761 | 579 | goto err4; |
73b089b0 FB |
580 | } |
581 | ||
582 | return 0; | |
583 | ||
03491761 FB |
584 | err4: |
585 | clk_disable(clk); | |
586 | ||
587 | err3: | |
588 | clk_put(clk); | |
589 | ||
e110de4d | 590 | err2: |
73b089b0 FB |
591 | platform_device_put(musb); |
592 | ||
e110de4d FB |
593 | err1: |
594 | kfree(glue); | |
595 | ||
73b089b0 FB |
596 | err0: |
597 | return ret; | |
598 | } | |
599 | ||
e9e8c85e | 600 | static int __devexit davinci_remove(struct platform_device *pdev) |
73b089b0 | 601 | { |
e110de4d | 602 | struct davinci_glue *glue = platform_get_drvdata(pdev); |
73b089b0 | 603 | |
e110de4d FB |
604 | platform_device_del(glue->musb); |
605 | platform_device_put(glue->musb); | |
03491761 FB |
606 | clk_disable(glue->clk); |
607 | clk_put(glue->clk); | |
e110de4d | 608 | kfree(glue); |
73b089b0 FB |
609 | |
610 | return 0; | |
611 | } | |
612 | ||
613 | static struct platform_driver davinci_driver = { | |
e9e8c85e FB |
614 | .probe = davinci_probe, |
615 | .remove = __devexit_p(davinci_remove), | |
73b089b0 FB |
616 | .driver = { |
617 | .name = "musb-davinci", | |
618 | }, | |
619 | }; | |
620 | ||
621 | MODULE_DESCRIPTION("DaVinci MUSB Glue Layer"); | |
622 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); | |
623 | MODULE_LICENSE("GPL v2"); | |
624 | ||
625 | static int __init davinci_init(void) | |
626 | { | |
e9e8c85e | 627 | return platform_driver_register(&davinci_driver); |
73b089b0 | 628 | } |
e9e8c85e | 629 | module_init(davinci_init); |
73b089b0 FB |
630 | |
631 | static void __exit davinci_exit(void) | |
632 | { | |
633 | platform_driver_unregister(&davinci_driver); | |
634 | } | |
635 | module_exit(davinci_exit); |