[deliverable/linux.git] / drivers / usb / musb / davinci.c

/*
 * Copyright (C) 2005-2006 by Texas Instruments
 *
 * This file is part of the Inventra Controller Driver for Linux.
 *
 * The Inventra Controller Driver for Linux is free software; you
 * can redistribute it and/or modify it under the terms of the GNU
 * General Public License version 2 as published by the Free Software
 * Foundation.
 *
 * The Inventra Controller Driver for Linux is distributed in
 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
 * without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
 * License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with The Inventra Controller Driver for Linux ; if not,
 * write to the Free Software Foundation, Inc., 59 Temple Place,
 * Suite 330, Boston, MA  02111-1307  USA
 *
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/gpio.h>

#include <asm/arch/hardware.h>
#include <asm/arch/memory.h>
#include <asm/arch/gpio.h>
#include <asm/mach-types.h>

#include "musb_core.h"

#ifdef CONFIG_MACH_DAVINCI_EVM
#define GPIO_nVBUS_DRV		87
#endif

#include "davinci.h"
#include "cppi_dma.h"


/* REVISIT (PM) we should be able to keep the PHY in low power mode most
 * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
 * and, when in host mode, autosuspending idle root ports... PHYPLLON
 * (overriding SUSPENDM?) then likely needs to stay off.
 */

static inline void phy_on(void)
{
	/* start the on-chip PHY and its PLL */
	__raw_writel(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON,
			(void __force __iomem *) IO_ADDRESS(USBPHY_CTL_PADDR));
	while ((__raw_readl((void __force __iomem *)
				IO_ADDRESS(USBPHY_CTL_PADDR))
			& USBPHY_PHYCLKGD) == 0)
		cpu_relax();
}

static inline void phy_off(void)
{
	/* powerdown the on-chip PHY and its oscillator */
	__raw_writel(USBPHY_OSCPDWN | USBPHY_PHYPDWN, (void __force __iomem *)
			IO_ADDRESS(USBPHY_CTL_PADDR));
}

static int dma_off = 1;

void musb_platform_enable(struct musb *musb)
{
	u32	tmp, old, val;

	/* workaround:  setup irqs through both register sets */
	tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
			<< DAVINCI_USB_TXINT_SHIFT;
	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
	old = tmp;
	tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
			<< DAVINCI_USB_RXINT_SHIFT;
	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
	tmp |= old;

	val = ~MUSB_INTR_SOF;
	tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);

	if (is_dma_capable() && !dma_off)
		printk(KERN_WARNING "%s %s: dma not reactivated\n",
				__FILE__, __func__);
	else
		dma_off = 0;

	/* force a DRVVBUS irq so we can start polling for ID change */
	if (is_otg_enabled(musb))
		musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
			DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
}

/*
 * Disable the HDRC and flush interrupts
 */
void musb_platform_disable(struct musb *musb)
{
	/* because we don't set CTRLR.UINT, "important" to:
	 *  - not read/write INTRUSB/INTRUSBE
	 *  - (except during initial setup, as workaround)
	 *  - use INTSETR/INTCLRR instead
	 */
	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
			  DAVINCI_USB_USBINT_MASK
			| DAVINCI_USB_TXINT_MASK
			| DAVINCI_USB_RXINT_MASK);
	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
	musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);

	if (is_dma_capable() && !dma_off)
		WARNING("dma still active\n");
}


/* REVISIT it's not clear whether DaVinci can support full OTG.  */

static int vbus_state = -1;

#ifdef CONFIG_USB_MUSB_HDRC_HCD
#define	portstate(stmt)		stmt
#else
#define	portstate(stmt)
#endif


/* VBUS SWITCHING IS BOARD-SPECIFIC */

#ifdef CONFIG_MACH_DAVINCI_EVM

/* I2C operations are always synchronous, and require a task context.
 * With unloaded systems, using the shared workqueue seems to suffice
 * to satisfy the 100msec A_WAIT_VRISE timeout...
 */
static void evm_deferred_drvvbus(struct work_struct *ignored)
{
	gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
	vbus_state = !vbus_state;
}
static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);

#endif	/* EVM */

static void davinci_source_power(struct musb *musb, int is_on, int immediate)
{
	if (is_on)
		is_on = 1;

	if (vbus_state == is_on)
		return;
	vbus_state = !is_on;		/* 0/1 vs "-1 == unknown/init" */

#ifdef CONFIG_MACH_DAVINCI_EVM
	if (machine_is_davinci_evm()) {
		if (immediate)
			gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
		else
			schedule_work(&evm_vbus_work);
	}
#endif
	if (immediate)
		vbus_state = is_on;
}

static void davinci_set_vbus(struct musb *musb, int is_on)
{
	WARN_ON(is_on && is_peripheral_active(musb));
	davinci_source_power(musb, is_on, 0);
}


#define	POLL_SECONDS	2

static struct timer_list otg_workaround;

static void otg_timer(unsigned long _musb)
{
	struct musb		*musb = (void *)_musb;
	void __iomem		*mregs = musb->mregs;
	u8			devctl;
	unsigned long		flags;

	/* We poll because DaVinci's won't expose several OTG-critical
	* status change events (from the transceiver) otherwise.
	 */
	devctl = musb_readb(mregs, MUSB_DEVCTL);
	DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));

	spin_lock_irqsave(&musb->lock, flags);
	switch (musb->xceiv.state) {
	case OTG_STATE_A_WAIT_VFALL:
		/* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
		 * seems to mis-handle session "start" otherwise (or in our
		 * case "recover"), in routine "VBUS was valid by the time
		 * VBUSERR got reported during enumeration" cases.
		 */
		if (devctl & MUSB_DEVCTL_VBUS) {
			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
			break;
		}
		musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
		musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
			MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
		break;
	case OTG_STATE_B_IDLE:
		if (!is_peripheral_enabled(musb))
			break;

		/* There's no ID-changed IRQ, so we have no good way to tell
		 * when to switch to the A-Default state machine (by setting
		 * the DEVCTL.SESSION flag).
		 *
		 * Workaround:  whenever we're in B_IDLE, try setting the
		 * session flag every few seconds.  If it works, ID was
		 * grounded and we're now in the A-Default state machine.
		 *
		 * NOTE setting the session flag is _supposed_ to trigger
		 * SRP, but clearly it doesn't.
		 */
		musb_writeb(mregs, MUSB_DEVCTL,
				devctl | MUSB_DEVCTL_SESSION);
		devctl = musb_readb(mregs, MUSB_DEVCTL);
		if (devctl & MUSB_DEVCTL_BDEVICE)
			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
		else
			musb->xceiv.state = OTG_STATE_A_IDLE;
		break;
	default:
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);
}

static irqreturn_t davinci_interrupt(int irq, void *__hci)
{
	unsigned long	flags;
	irqreturn_t	retval = IRQ_NONE;
	struct musb	*musb = __hci;
	void __iomem	*tibase = musb->ctrl_base;
	u32		tmp;

	spin_lock_irqsave(&musb->lock, flags);

	/* NOTE: DaVinci shadows the Mentor IRQs.  Don't manage them through
	 * the Mentor registers (except for setup), use the TI ones and EOI.
	 *
	 * Docs describe irq "vector" registers asociated with the CPPI and
	 * USB EOI registers.  These hold a bitmask corresponding to the
	 * current IRQ, not an irq handler address.  Would using those bits
	 * resolve some of the races observed in this dispatch code??
	 */

	/* CPPI interrupts share the same IRQ line, but have their own
	 * mask, state, "vector", and EOI registers.
	 */
	if (is_cppi_enabled()) {
		u32 cppi_tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
		u32 cppi_rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);

		if (cppi_tx || cppi_rx) {
			DBG(4, "CPPI IRQ t%x r%x\n", cppi_tx, cppi_rx);
			cppi_completion(musb, cppi_rx, cppi_tx);
			retval = IRQ_HANDLED;
		}
	}

	/* ack and handle non-CPPI interrupts */
	tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
	musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
	DBG(4, "IRQ %08x\n", tmp);

	musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
			>> DAVINCI_USB_RXINT_SHIFT;
	musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
			>> DAVINCI_USB_TXINT_SHIFT;
	musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
			>> DAVINCI_USB_USBINT_SHIFT;

	/* DRVVBUS irqs are the only proxy we have (a very poor one!) for
	 * DaVinci's missing ID change IRQ.  We need an ID change IRQ to
	 * switch appropriately between halves of the OTG state machine.
	 * Managing DEVCTL.SESSION per Mentor docs requires we know its
	 * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
	 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
	 */
	if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
		int	drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
		void __iomem *mregs = musb->mregs;
		u8	devctl = musb_readb(mregs, MUSB_DEVCTL);
		int	err = musb->int_usb & MUSB_INTR_VBUSERROR;

		err = is_host_enabled(musb)
				&& (musb->int_usb & MUSB_INTR_VBUSERROR);
		if (err) {
			/* The Mentor core doesn't debounce VBUS as needed
			 * to cope with device connect current spikes. This
			 * means it's not uncommon for bus-powered devices
			 * to get VBUS errors during enumeration.
			 *
			 * This is a workaround, but newer RTL from Mentor
			 * seems to allow a better one: "re"starting sessions
			 * without waiting (on EVM, a **long** time) for VBUS
			 * to stop registering in devctl.
			 */
			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
			musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
			WARNING("VBUS error workaround (delay coming)\n");
		} else if (is_host_enabled(musb) && drvvbus) {
			musb->is_active = 1;
			MUSB_HST_MODE(musb);
			musb->xceiv.default_a = 1;
			musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
			portstate(musb->port1_status |= USB_PORT_STAT_POWER);
			del_timer(&otg_workaround);
		} else {
			musb->is_active = 0;
			MUSB_DEV_MODE(musb);
			musb->xceiv.default_a = 0;
			musb->xceiv.state = OTG_STATE_B_IDLE;
			portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
		}

		/* NOTE:  this must complete poweron within 100 msec */
		davinci_source_power(musb, drvvbus, 0);
		DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
				drvvbus ? "on" : "off",
				otg_state_string(musb),
				err ? " ERROR" : "",
				devctl);
		retval = IRQ_HANDLED;
	}

	if (musb->int_tx || musb->int_rx || musb->int_usb)
		retval |= musb_interrupt(musb);

	/* irq stays asserted until EOI is written */
	musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);

	/* poll for ID change */
	if (is_otg_enabled(musb)
			&& musb->xceiv.state == OTG_STATE_B_IDLE)
		mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);

	spin_unlock_irqrestore(&musb->lock, flags);

	/* REVISIT we sometimes get unhandled IRQs
	 * (e.g. ep0).  not clear why...
	 */
	if (retval != IRQ_HANDLED)
		DBG(5, "unhandled? %08x\n", tmp);
	return IRQ_HANDLED;
}

int __init musb_platform_init(struct musb *musb)
{
	void __iomem	*tibase = musb->ctrl_base;
	u32		revision;

	musb->mregs += DAVINCI_BASE_OFFSET;
#if 0
	/* REVISIT there's something odd about clocking, this
	 * didn't appear do the job ...
	 */
	musb->clock = clk_get(pDevice, "usb");
	if (IS_ERR(musb->clock))
		return PTR_ERR(musb->clock);

	status = clk_enable(musb->clock);
	if (status < 0)
		return -ENODEV;
#endif

	/* returns zero if e.g. not clocked */
	revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
	if (revision == 0)
		return -ENODEV;

	if (is_host_enabled(musb))
		setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);

	musb->board_set_vbus = davinci_set_vbus;
	davinci_source_power(musb, 0, 1);

	/* reset the controller */
	musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);

	/* start the on-chip PHY and its PLL */
	phy_on();

	msleep(5);

	/* NOTE:  irqs are in mixed mode, not bypass to pure-musb */
	pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
		revision, __raw_readl((void __force __iomem *)
				IO_ADDRESS(USBPHY_CTL_PADDR)),
		musb_readb(tibase, DAVINCI_USB_CTRL_REG));

	musb->isr = davinci_interrupt;
	return 0;
}

int musb_platform_exit(struct musb *musb)
{
	if (is_host_enabled(musb))
		del_timer_sync(&otg_workaround);

	davinci_source_power(musb, 0 /*off*/, 1);

	/* delay, to avoid problems with module reload */
	if (is_host_enabled(musb) && musb->xceiv.default_a) {
		int	maxdelay = 30;
		u8	devctl, warn = 0;

		/* if there's no peripheral connected, this can take a
		 * long time to fall, especially on EVM with huge C133.
		 */
		do {
			devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
			if (!(devctl & MUSB_DEVCTL_VBUS))
				break;
			if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
				warn = devctl & MUSB_DEVCTL_VBUS;
				DBG(1, "VBUS %d\n",
					warn >> MUSB_DEVCTL_VBUS_SHIFT);
			}
			msleep(1000);
			maxdelay--;
		} while (maxdelay > 0);

		/* in OTG mode, another host might be connected */
		if (devctl & MUSB_DEVCTL_VBUS)
			DBG(1, "VBUS off timeout (devctl %02x)\n", devctl);
	}

	phy_off();
	return 0;
}
Commit	Line	Data
550a7375 FB	1	/*
	2	* Copyright (C) 2005-2006 by Texas Instruments
	3	*
	4	* This file is part of the Inventra Controller Driver for Linux.
	5	*
	6	* The Inventra Controller Driver for Linux is free software; you
	7	* can redistribute it and/or modify it under the terms of the GNU
	8	* General Public License version 2 as published by the Free Software
	9	* Foundation.
	10	*
	11	* The Inventra Controller Driver for Linux is distributed in
	12	* the hope that it will be useful, but WITHOUT ANY WARRANTY;
	13	* without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	* License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with The Inventra Controller Driver for Linux ; if not,
	19	* write to the Free Software Foundation, Inc., 59 Temple Place,
	20	* Suite 330, Boston, MA 02111-1307 USA
	21	*
	22	*/
	23
	24	#include <linux/module.h>
	25	#include <linux/kernel.h>
	26	#include <linux/sched.h>
	27	#include <linux/slab.h>
	28	#include <linux/init.h>
	29	#include <linux/list.h>
	30	#include <linux/delay.h>
	31	#include <linux/clk.h>
	32	#include <linux/io.h>
c767c1c6	33	#include <linux/gpio.h>
550a7375 FB	34
	35	#include <asm/arch/hardware.h>
	36	#include <asm/arch/memory.h>
	37	#include <asm/arch/gpio.h>
	38	#include <asm/mach-types.h>
	39
	40	#include "musb_core.h"
	41
	42	#ifdef CONFIG_MACH_DAVINCI_EVM
c767c1c6	43	#define GPIO_nVBUS_DRV 87
550a7375 FB	44	#endif
	45
	46	#include "davinci.h"
	47	#include "cppi_dma.h"
	48
	49
	50	/* REVISIT (PM) we should be able to keep the PHY in low power mode most
	51	* of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
	52	* and, when in host mode, autosuspending idle root ports... PHYPLLON
	53	* (overriding SUSPENDM?) then likely needs to stay off.
	54	*/
	55
	56	static inline void phy_on(void)
	57	{
	58	/* start the on-chip PHY and its PLL */
	59	__raw_writel(USBPHY_SESNDEN \| USBPHY_VBDTCTEN \| USBPHY_PHYPLLON,
	60	(void __force __iomem *) IO_ADDRESS(USBPHY_CTL_PADDR));
	61	while ((__raw_readl((void __force __iomem *)
	62	IO_ADDRESS(USBPHY_CTL_PADDR))
	63	& USBPHY_PHYCLKGD) == 0)
	64	cpu_relax();
	65	}
	66
	67	static inline void phy_off(void)
	68	{
	69	/* powerdown the on-chip PHY and its oscillator */
	70	__raw_writel(USBPHY_OSCPDWN \| USBPHY_PHYPDWN, (void __force __iomem *)
	71	IO_ADDRESS(USBPHY_CTL_PADDR));
	72	}
	73
	74	static int dma_off = 1;
	75
	76	void musb_platform_enable(struct musb *musb)
	77	{
	78	u32 tmp, old, val;
	79
	80	/* workaround: setup irqs through both register sets */
	81	tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
	82	<< DAVINCI_USB_TXINT_SHIFT;
	83	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
	84	old = tmp;
	85	tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
	86	<< DAVINCI_USB_RXINT_SHIFT;
	87	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
	88	tmp \|= old;
	89
	90	val = ~MUSB_INTR_SOF;
	91	tmp \|= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
	92	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
	93
	94	if (is_dma_capable() && !dma_off)
	95	printk(KERN_WARNING "%s %s: dma not reactivated\n",
	96	__FILE__, __func__);
	97	else
	98	dma_off = 0;
	99
	100	/* force a DRVVBUS irq so we can start polling for ID change */
	101	if (is_otg_enabled(musb))
	102	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
	103	DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
	104	}
	105
	106	/*
	107	* Disable the HDRC and flush interrupts
108	*/
109	void musb_platform_disable(struct musb *musb)
110	{
111	/* because we don't set CTRLR.UINT, "important" to:
112	* - not read/write INTRUSB/INTRUSBE
113	* - (except during initial setup, as workaround)
114	* - use INTSETR/INTCLRR instead
115	*/
116	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
117	DAVINCI_USB_USBINT_MASK
118	\| DAVINCI_USB_TXINT_MASK
119	\| DAVINCI_USB_RXINT_MASK);
120	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
121	musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
122
123	if (is_dma_capable() && !dma_off)
124	WARNING("dma still active\n");
125	}
126
127
128	/* REVISIT it's not clear whether DaVinci can support full OTG. */
129
130	static int vbus_state = -1;
131
132	#ifdef CONFIG_USB_MUSB_HDRC_HCD
133	#define portstate(stmt) stmt
134	#else
135	#define portstate(stmt)
136	#endif
137
138
139	/* VBUS SWITCHING IS BOARD-SPECIFIC */
140
141	#ifdef CONFIG_MACH_DAVINCI_EVM
550a7375 FB	142
	143	/* I2C operations are always synchronous, and require a task context.
	144	* With unloaded systems, using the shared workqueue seems to suffice
	145	* to satisfy the 100msec A_WAIT_VRISE timeout...
	146	*/
	147	static void evm_deferred_drvvbus(struct work_struct *ignored)
	148	{
c767c1c6	149	gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
550a7375 FB	150	vbus_state = !vbus_state;
	151	}
	152	static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
	153
550a7375 FB	154	#endif /* EVM */
	155
	156	static void davinci_source_power(struct musb *musb, int is_on, int immediate)
	157	{
	158	if (is_on)
	159	is_on = 1;
	160
	161	if (vbus_state == is_on)
	162	return;
	163	vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */
	164
	165	#ifdef CONFIG_MACH_DAVINCI_EVM
	166	if (machine_is_davinci_evm()) {
550a7375	167	if (immediate)
c767c1c6	168	gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
550a7375 FB	169	else
550a7375 FB	170	schedule_work(&evm_vbus_work);
550a7375 FB	171	}
	172	#endif
	173	if (immediate)
	174	vbus_state = is_on;
	175	}
	176
	177	static void davinci_set_vbus(struct musb *musb, int is_on)
	178	{
	179	WARN_ON(is_on && is_peripheral_active(musb));
	180	davinci_source_power(musb, is_on, 0);
	181	}
	182
	183
	184	#define POLL_SECONDS 2
	185
	186	static struct timer_list otg_workaround;
	187
	188	static void otg_timer(unsigned long _musb)
	189	{
	190	struct musb musb = (void )_musb;
	191	void __iomem *mregs = musb->mregs;
	192	u8 devctl;
	193	unsigned long flags;
	194
	195	/* We poll because DaVinci's won't expose several OTG-critical
	196	* status change events (from the transceiver) otherwise.
	197	*/
	198	devctl = musb_readb(mregs, MUSB_DEVCTL);
	199	DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
	200
	201	spin_lock_irqsave(&musb->lock, flags);
	202	switch (musb->xceiv.state) {
	203	case OTG_STATE_A_WAIT_VFALL:
	204	/* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
	205	* seems to mis-handle session "start" otherwise (or in our
	206	* case "recover"), in routine "VBUS was valid by the time
	207	* VBUSERR got reported during enumeration" cases.
	208	*/
	209	if (devctl & MUSB_DEVCTL_VBUS) {
	210	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	211	break;
	212	}
	213	musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
	214	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
	215	MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
	216	break;
	217	case OTG_STATE_B_IDLE:
	218	if (!is_peripheral_enabled(musb))
	219	break;
	220
	221	/* There's no ID-changed IRQ, so we have no good way to tell
	222	* when to switch to the A-Default state machine (by setting
	223	* the DEVCTL.SESSION flag).
	224	*
	225	* Workaround: whenever we're in B_IDLE, try setting the
	226	* session flag every few seconds. If it works, ID was
	227	* grounded and we're now in the A-Default state machine.
	228	*
	229	* NOTE setting the session flag is _supposed_ to trigger
	230	* SRP, but clearly it doesn't.
	231	*/
	232	musb_writeb(mregs, MUSB_DEVCTL,
	233	devctl \| MUSB_DEVCTL_SESSION);
	234	devctl = musb_readb(mregs, MUSB_DEVCTL);
235	if (devctl & MUSB_DEVCTL_BDEVICE)
236	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
237	else
238	musb->xceiv.state = OTG_STATE_A_IDLE;
239	break;
240	default:
241	break;
242	}
243	spin_unlock_irqrestore(&musb->lock, flags);
244	}
245
246	static irqreturn_t davinci_interrupt(int irq, void *__hci)
247	{
248	unsigned long flags;
249	irqreturn_t retval = IRQ_NONE;
250	struct musb *musb = __hci;
251	void __iomem *tibase = musb->ctrl_base;
252	u32 tmp;
253
254	spin_lock_irqsave(&musb->lock, flags);
255
256	/* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
257	* the Mentor registers (except for setup), use the TI ones and EOI.
258	*
259	* Docs describe irq "vector" registers asociated with the CPPI and
260	* USB EOI registers. These hold a bitmask corresponding to the
261	* current IRQ, not an irq handler address. Would using those bits
262	* resolve some of the races observed in this dispatch code??
263	*/
264
265	/* CPPI interrupts share the same IRQ line, but have their own
266	* mask, state, "vector", and EOI registers.
267	*/
268	if (is_cppi_enabled()) {
269	u32 cppi_tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
270	u32 cppi_rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
271
272	if (cppi_tx \|\| cppi_rx) {
273	DBG(4, "CPPI IRQ t%x r%x\n", cppi_tx, cppi_rx);
274	cppi_completion(musb, cppi_rx, cppi_tx);
275	retval = IRQ_HANDLED;
276	}
277	}
278
279	/* ack and handle non-CPPI interrupts */
280	tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
281	musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
282	DBG(4, "IRQ %08x\n", tmp);
283
284	musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
285	>> DAVINCI_USB_RXINT_SHIFT;
286	musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
287	>> DAVINCI_USB_TXINT_SHIFT;
288	musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
289	>> DAVINCI_USB_USBINT_SHIFT;
290
291	/* DRVVBUS irqs are the only proxy we have (a very poor one!) for
292	* DaVinci's missing ID change IRQ. We need an ID change IRQ to
293	* switch appropriately between halves of the OTG state machine.
294	* Managing DEVCTL.SESSION per Mentor docs requires we know its
295	* value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
296	* Also, DRVVBUS pulses for SRP (but not at 5V) ...
297	*/
298	if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
299	int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
300	void __iomem *mregs = musb->mregs;
301	u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
302	int err = musb->int_usb & MUSB_INTR_VBUSERROR;
303
304	err = is_host_enabled(musb)
305	&& (musb->int_usb & MUSB_INTR_VBUSERROR);
306	if (err) {
307	/* The Mentor core doesn't debounce VBUS as needed
308	* to cope with device connect current spikes. This
309	* means it's not uncommon for bus-powered devices
310	* to get VBUS errors during enumeration.
311	*
312	* This is a workaround, but newer RTL from Mentor
313	* seems to allow a better one: "re"starting sessions
314	* without waiting (on EVM, a long time) for VBUS
315	* to stop registering in devctl.
316	*/
317	musb->int_usb &= ~MUSB_INTR_VBUSERROR;
318	musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
319	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
320	WARNING("VBUS error workaround (delay coming)\n");
321	} else if (is_host_enabled(musb) && drvvbus) {
322	musb->is_active = 1;
323	MUSB_HST_MODE(musb);
324	musb->xceiv.default_a = 1;
325	musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
326	portstate(musb->port1_status \|= USB_PORT_STAT_POWER);
327	del_timer(&otg_workaround);
328	} else {
329	musb->is_active = 0;
330	MUSB_DEV_MODE(musb);
331	musb->xceiv.default_a = 0;
332	musb->xceiv.state = OTG_STATE_B_IDLE;
333	portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
334	}
335
336	/* NOTE: this must complete poweron within 100 msec */
337	davinci_source_power(musb, drvvbus, 0);
338	DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
339	drvvbus ? "on" : "off",
340	otg_state_string(musb),
341	err ? " ERROR" : "",
342	devctl);
343	retval = IRQ_HANDLED;
344	}
345
346	if (musb->int_tx \|\| musb->int_rx \|\| musb->int_usb)
347	retval \|= musb_interrupt(musb);
348
349	/* irq stays asserted until EOI is written */
350	musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
351
352	/* poll for ID change */
353	if (is_otg_enabled(musb)
354	&& musb->xceiv.state == OTG_STATE_B_IDLE)
355	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
356
357	spin_unlock_irqrestore(&musb->lock, flags);
358
359	/* REVISIT we sometimes get unhandled IRQs
360	* (e.g. ep0). not clear why...
361	*/
362	if (retval != IRQ_HANDLED)
363	DBG(5, "unhandled? %08x\n", tmp);
364	return IRQ_HANDLED;
365	}
366
367	int __init musb_platform_init(struct musb *musb)
368	{
369	void __iomem *tibase = musb->ctrl_base;
370	u32 revision;
371
372	musb->mregs += DAVINCI_BASE_OFFSET;
373	#if 0
374	/* REVISIT there's something odd about clocking, this
375	* didn't appear do the job ...
376	*/
377	musb->clock = clk_get(pDevice, "usb");
378	if (IS_ERR(musb->clock))
379	return PTR_ERR(musb->clock);
380
381	status = clk_enable(musb->clock);
382	if (status < 0)
383	return -ENODEV;
384	#endif
385
386	/* returns zero if e.g. not clocked */
387	revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
388	if (revision == 0)
389	return -ENODEV;
390
391	if (is_host_enabled(musb))
392	setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
393
394	musb->board_set_vbus = davinci_set_vbus;
395	davinci_source_power(musb, 0, 1);
396
397	/* reset the controller */
398	musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
399
400	/* start the on-chip PHY and its PLL */
401	phy_on();
402
403	msleep(5);
404
405	/* NOTE: irqs are in mixed mode, not bypass to pure-musb */
406	pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
407	revision, __raw_readl((void __force __iomem *)
408	IO_ADDRESS(USBPHY_CTL_PADDR)),
409	musb_readb(tibase, DAVINCI_USB_CTRL_REG));
410
411	musb->isr = davinci_interrupt;
412	return 0;
413	}
414
415	int musb_platform_exit(struct musb *musb)
416	{
417	if (is_host_enabled(musb))
418	del_timer_sync(&otg_workaround);
419
420	davinci_source_power(musb, 0 /off/, 1);
421
422	/* delay, to avoid problems with module reload */
423	if (is_host_enabled(musb) && musb->xceiv.default_a) {
424	int maxdelay = 30;
425	u8 devctl, warn = 0;
426
427	/* if there's no peripheral connected, this can take a
428	* long time to fall, especially on EVM with huge C133.
429	*/
430	do {
431	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
432	if (!(devctl & MUSB_DEVCTL_VBUS))
433	break;
434	if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
435	warn = devctl & MUSB_DEVCTL_VBUS;
436	DBG(1, "VBUS %d\n",
437	warn >> MUSB_DEVCTL_VBUS_SHIFT);
438	}
439	msleep(1000);
440	maxdelay--;
441	} while (maxdelay > 0);
442
443	/* in OTG mode, another host might be connected */
444	if (devctl & MUSB_DEVCTL_VBUS)
445	DBG(1, "VBUS off timeout (devctl %02x)\n", devctl);
446	}
447
448	phy_off();
449	return 0;
450	}