Commit | Line | Data |
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550a7375 FB |
1 | /* |
2 | * Copyright (C) 2005-2006 by Texas Instruments | |
3 | * | |
4 | * This file is part of the Inventra Controller Driver for Linux. | |
5 | * | |
6 | * The Inventra Controller Driver for Linux is free software; you | |
7 | * can redistribute it and/or modify it under the terms of the GNU | |
8 | * General Public License version 2 as published by the Free Software | |
9 | * Foundation. | |
10 | * | |
11 | * The Inventra Controller Driver for Linux is distributed in | |
12 | * the hope that it will be useful, but WITHOUT ANY WARRANTY; | |
13 | * without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | * License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with The Inventra Controller Driver for Linux ; if not, | |
19 | * write to the Free Software Foundation, Inc., 59 Temple Place, | |
20 | * Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/list.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/clk.h> | |
32 | #include <linux/io.h> | |
c767c1c6 | 33 | #include <linux/gpio.h> |
550a7375 | 34 | |
10b4eade DB |
35 | #include <mach/hardware.h> |
36 | #include <mach/memory.h> | |
37 | #include <mach/gpio.h> | |
d163ef24 | 38 | #include <mach/cputype.h> |
10b4eade | 39 | |
550a7375 FB |
40 | #include <asm/mach-types.h> |
41 | ||
42 | #include "musb_core.h" | |
43 | ||
44 | #ifdef CONFIG_MACH_DAVINCI_EVM | |
30899ca7 | 45 | #define GPIO_nVBUS_DRV 144 |
550a7375 FB |
46 | #endif |
47 | ||
48 | #include "davinci.h" | |
49 | #include "cppi_dma.h" | |
50 | ||
51 | ||
a227fd7d DB |
52 | #define USB_PHY_CTRL IO_ADDRESS(USBPHY_CTL_PADDR) |
53 | #define DM355_DEEPSLEEP IO_ADDRESS(DM355_DEEPSLEEP_PADDR) | |
54 | ||
550a7375 FB |
55 | /* REVISIT (PM) we should be able to keep the PHY in low power mode most |
56 | * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0 | |
57 | * and, when in host mode, autosuspending idle root ports... PHYPLLON | |
58 | * (overriding SUSPENDM?) then likely needs to stay off. | |
59 | */ | |
60 | ||
61 | static inline void phy_on(void) | |
62 | { | |
a227fd7d DB |
63 | u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); |
64 | ||
65 | /* power everything up; start the on-chip PHY and its PLL */ | |
66 | phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN); | |
67 | phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON; | |
68 | __raw_writel(phy_ctrl, USB_PHY_CTRL); | |
69 | ||
70 | /* wait for PLL to lock before proceeding */ | |
71 | while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0) | |
550a7375 FB |
72 | cpu_relax(); |
73 | } | |
74 | ||
75 | static inline void phy_off(void) | |
76 | { | |
a227fd7d DB |
77 | u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); |
78 | ||
79 | /* powerdown the on-chip PHY, its PLL, and the OTG block */ | |
80 | phy_ctrl &= ~(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON); | |
81 | phy_ctrl |= USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN; | |
82 | __raw_writel(phy_ctrl, USB_PHY_CTRL); | |
550a7375 FB |
83 | } |
84 | ||
85 | static int dma_off = 1; | |
86 | ||
87 | void musb_platform_enable(struct musb *musb) | |
88 | { | |
89 | u32 tmp, old, val; | |
90 | ||
91 | /* workaround: setup irqs through both register sets */ | |
92 | tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK) | |
93 | << DAVINCI_USB_TXINT_SHIFT; | |
94 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); | |
95 | old = tmp; | |
96 | tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK)) | |
97 | << DAVINCI_USB_RXINT_SHIFT; | |
98 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); | |
99 | tmp |= old; | |
100 | ||
101 | val = ~MUSB_INTR_SOF; | |
102 | tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT); | |
103 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); | |
104 | ||
105 | if (is_dma_capable() && !dma_off) | |
106 | printk(KERN_WARNING "%s %s: dma not reactivated\n", | |
107 | __FILE__, __func__); | |
108 | else | |
109 | dma_off = 0; | |
110 | ||
111 | /* force a DRVVBUS irq so we can start polling for ID change */ | |
112 | if (is_otg_enabled(musb)) | |
113 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG, | |
114 | DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT); | |
115 | } | |
116 | ||
117 | /* | |
118 | * Disable the HDRC and flush interrupts | |
119 | */ | |
120 | void musb_platform_disable(struct musb *musb) | |
121 | { | |
122 | /* because we don't set CTRLR.UINT, "important" to: | |
123 | * - not read/write INTRUSB/INTRUSBE | |
124 | * - (except during initial setup, as workaround) | |
125 | * - use INTSETR/INTCLRR instead | |
126 | */ | |
127 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG, | |
128 | DAVINCI_USB_USBINT_MASK | |
129 | | DAVINCI_USB_TXINT_MASK | |
130 | | DAVINCI_USB_RXINT_MASK); | |
131 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
132 | musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0); | |
133 | ||
134 | if (is_dma_capable() && !dma_off) | |
135 | WARNING("dma still active\n"); | |
136 | } | |
137 | ||
138 | ||
550a7375 FB |
139 | #ifdef CONFIG_USB_MUSB_HDRC_HCD |
140 | #define portstate(stmt) stmt | |
141 | #else | |
142 | #define portstate(stmt) | |
143 | #endif | |
144 | ||
145 | ||
a227fd7d DB |
146 | /* |
147 | * VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM, | |
148 | * which doesn't wire DRVVBUS to the FET that switches it. Unclear | |
149 | * if that's a problem with the DM6446 chip or just with that board. | |
150 | * | |
151 | * In either case, the DM355 EVM automates DRVVBUS the normal way, | |
152 | * when J10 is out, and TI documents it as handling OTG. | |
153 | */ | |
550a7375 FB |
154 | |
155 | #ifdef CONFIG_MACH_DAVINCI_EVM | |
550a7375 | 156 | |
a227fd7d DB |
157 | static int vbus_state = -1; |
158 | ||
550a7375 FB |
159 | /* I2C operations are always synchronous, and require a task context. |
160 | * With unloaded systems, using the shared workqueue seems to suffice | |
161 | * to satisfy the 100msec A_WAIT_VRISE timeout... | |
162 | */ | |
163 | static void evm_deferred_drvvbus(struct work_struct *ignored) | |
164 | { | |
c767c1c6 | 165 | gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state); |
550a7375 FB |
166 | vbus_state = !vbus_state; |
167 | } | |
550a7375 | 168 | |
550a7375 FB |
169 | #endif /* EVM */ |
170 | ||
171 | static void davinci_source_power(struct musb *musb, int is_on, int immediate) | |
172 | { | |
a227fd7d | 173 | #ifdef CONFIG_MACH_DAVINCI_EVM |
550a7375 FB |
174 | if (is_on) |
175 | is_on = 1; | |
176 | ||
177 | if (vbus_state == is_on) | |
178 | return; | |
179 | vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */ | |
180 | ||
550a7375 | 181 | if (machine_is_davinci_evm()) { |
a227fd7d DB |
182 | static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus); |
183 | ||
550a7375 | 184 | if (immediate) |
c767c1c6 | 185 | gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state); |
550a7375 FB |
186 | else |
187 | schedule_work(&evm_vbus_work); | |
550a7375 | 188 | } |
550a7375 FB |
189 | if (immediate) |
190 | vbus_state = is_on; | |
a227fd7d | 191 | #endif |
550a7375 FB |
192 | } |
193 | ||
194 | static void davinci_set_vbus(struct musb *musb, int is_on) | |
195 | { | |
196 | WARN_ON(is_on && is_peripheral_active(musb)); | |
197 | davinci_source_power(musb, is_on, 0); | |
198 | } | |
199 | ||
200 | ||
201 | #define POLL_SECONDS 2 | |
202 | ||
203 | static struct timer_list otg_workaround; | |
204 | ||
205 | static void otg_timer(unsigned long _musb) | |
206 | { | |
207 | struct musb *musb = (void *)_musb; | |
208 | void __iomem *mregs = musb->mregs; | |
209 | u8 devctl; | |
210 | unsigned long flags; | |
211 | ||
212 | /* We poll because DaVinci's won't expose several OTG-critical | |
213 | * status change events (from the transceiver) otherwise. | |
214 | */ | |
215 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
216 | DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb)); | |
217 | ||
218 | spin_lock_irqsave(&musb->lock, flags); | |
84e250ff | 219 | switch (musb->xceiv->state) { |
550a7375 FB |
220 | case OTG_STATE_A_WAIT_VFALL: |
221 | /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL | |
222 | * seems to mis-handle session "start" otherwise (or in our | |
223 | * case "recover"), in routine "VBUS was valid by the time | |
224 | * VBUSERR got reported during enumeration" cases. | |
225 | */ | |
226 | if (devctl & MUSB_DEVCTL_VBUS) { | |
227 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
228 | break; | |
229 | } | |
84e250ff | 230 | musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; |
550a7375 FB |
231 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG, |
232 | MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT); | |
233 | break; | |
234 | case OTG_STATE_B_IDLE: | |
235 | if (!is_peripheral_enabled(musb)) | |
236 | break; | |
237 | ||
238 | /* There's no ID-changed IRQ, so we have no good way to tell | |
239 | * when to switch to the A-Default state machine (by setting | |
240 | * the DEVCTL.SESSION flag). | |
241 | * | |
242 | * Workaround: whenever we're in B_IDLE, try setting the | |
243 | * session flag every few seconds. If it works, ID was | |
244 | * grounded and we're now in the A-Default state machine. | |
245 | * | |
246 | * NOTE setting the session flag is _supposed_ to trigger | |
247 | * SRP, but clearly it doesn't. | |
248 | */ | |
249 | musb_writeb(mregs, MUSB_DEVCTL, | |
250 | devctl | MUSB_DEVCTL_SESSION); | |
251 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
252 | if (devctl & MUSB_DEVCTL_BDEVICE) | |
253 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
254 | else | |
84e250ff | 255 | musb->xceiv->state = OTG_STATE_A_IDLE; |
550a7375 FB |
256 | break; |
257 | default: | |
258 | break; | |
259 | } | |
260 | spin_unlock_irqrestore(&musb->lock, flags); | |
261 | } | |
262 | ||
263 | static irqreturn_t davinci_interrupt(int irq, void *__hci) | |
264 | { | |
265 | unsigned long flags; | |
266 | irqreturn_t retval = IRQ_NONE; | |
267 | struct musb *musb = __hci; | |
268 | void __iomem *tibase = musb->ctrl_base; | |
91e9c4fe | 269 | struct cppi *cppi; |
550a7375 FB |
270 | u32 tmp; |
271 | ||
272 | spin_lock_irqsave(&musb->lock, flags); | |
273 | ||
274 | /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through | |
275 | * the Mentor registers (except for setup), use the TI ones and EOI. | |
276 | * | |
277 | * Docs describe irq "vector" registers asociated with the CPPI and | |
278 | * USB EOI registers. These hold a bitmask corresponding to the | |
279 | * current IRQ, not an irq handler address. Would using those bits | |
280 | * resolve some of the races observed in this dispatch code?? | |
281 | */ | |
282 | ||
283 | /* CPPI interrupts share the same IRQ line, but have their own | |
284 | * mask, state, "vector", and EOI registers. | |
285 | */ | |
91e9c4fe SS |
286 | cppi = container_of(musb->dma_controller, struct cppi, controller); |
287 | if (is_cppi_enabled() && musb->dma_controller && !cppi->irq) | |
288 | retval = cppi_interrupt(irq, __hci); | |
550a7375 FB |
289 | |
290 | /* ack and handle non-CPPI interrupts */ | |
291 | tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG); | |
292 | musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp); | |
293 | DBG(4, "IRQ %08x\n", tmp); | |
294 | ||
295 | musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK) | |
296 | >> DAVINCI_USB_RXINT_SHIFT; | |
297 | musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK) | |
298 | >> DAVINCI_USB_TXINT_SHIFT; | |
299 | musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK) | |
300 | >> DAVINCI_USB_USBINT_SHIFT; | |
301 | ||
302 | /* DRVVBUS irqs are the only proxy we have (a very poor one!) for | |
303 | * DaVinci's missing ID change IRQ. We need an ID change IRQ to | |
304 | * switch appropriately between halves of the OTG state machine. | |
305 | * Managing DEVCTL.SESSION per Mentor docs requires we know its | |
306 | * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set. | |
307 | * Also, DRVVBUS pulses for SRP (but not at 5V) ... | |
308 | */ | |
309 | if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) { | |
310 | int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG); | |
311 | void __iomem *mregs = musb->mregs; | |
312 | u8 devctl = musb_readb(mregs, MUSB_DEVCTL); | |
313 | int err = musb->int_usb & MUSB_INTR_VBUSERROR; | |
314 | ||
315 | err = is_host_enabled(musb) | |
316 | && (musb->int_usb & MUSB_INTR_VBUSERROR); | |
317 | if (err) { | |
318 | /* The Mentor core doesn't debounce VBUS as needed | |
319 | * to cope with device connect current spikes. This | |
320 | * means it's not uncommon for bus-powered devices | |
321 | * to get VBUS errors during enumeration. | |
322 | * | |
323 | * This is a workaround, but newer RTL from Mentor | |
324 | * seems to allow a better one: "re"starting sessions | |
325 | * without waiting (on EVM, a **long** time) for VBUS | |
326 | * to stop registering in devctl. | |
327 | */ | |
328 | musb->int_usb &= ~MUSB_INTR_VBUSERROR; | |
84e250ff | 329 | musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; |
550a7375 FB |
330 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); |
331 | WARNING("VBUS error workaround (delay coming)\n"); | |
332 | } else if (is_host_enabled(musb) && drvvbus) { | |
550a7375 | 333 | MUSB_HST_MODE(musb); |
84e250ff DB |
334 | musb->xceiv->default_a = 1; |
335 | musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; | |
550a7375 FB |
336 | portstate(musb->port1_status |= USB_PORT_STAT_POWER); |
337 | del_timer(&otg_workaround); | |
338 | } else { | |
339 | musb->is_active = 0; | |
340 | MUSB_DEV_MODE(musb); | |
84e250ff DB |
341 | musb->xceiv->default_a = 0; |
342 | musb->xceiv->state = OTG_STATE_B_IDLE; | |
550a7375 FB |
343 | portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); |
344 | } | |
345 | ||
89368d3d DB |
346 | /* NOTE: this must complete poweron within 100 msec |
347 | * (OTG_TIME_A_WAIT_VRISE) but we don't check for that. | |
348 | */ | |
550a7375 FB |
349 | davinci_source_power(musb, drvvbus, 0); |
350 | DBG(2, "VBUS %s (%s)%s, devctl %02x\n", | |
351 | drvvbus ? "on" : "off", | |
352 | otg_state_string(musb), | |
353 | err ? " ERROR" : "", | |
354 | devctl); | |
355 | retval = IRQ_HANDLED; | |
356 | } | |
357 | ||
358 | if (musb->int_tx || musb->int_rx || musb->int_usb) | |
359 | retval |= musb_interrupt(musb); | |
360 | ||
361 | /* irq stays asserted until EOI is written */ | |
362 | musb_writel(tibase, DAVINCI_USB_EOI_REG, 0); | |
363 | ||
364 | /* poll for ID change */ | |
365 | if (is_otg_enabled(musb) | |
84e250ff | 366 | && musb->xceiv->state == OTG_STATE_B_IDLE) |
550a7375 FB |
367 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); |
368 | ||
369 | spin_unlock_irqrestore(&musb->lock, flags); | |
370 | ||
a5073b52 | 371 | return retval; |
550a7375 FB |
372 | } |
373 | ||
96a274d1 DB |
374 | int musb_platform_set_mode(struct musb *musb, u8 mode) |
375 | { | |
376 | /* EVM can't do this (right?) */ | |
377 | return -EIO; | |
378 | } | |
379 | ||
550a7375 FB |
380 | int __init musb_platform_init(struct musb *musb) |
381 | { | |
382 | void __iomem *tibase = musb->ctrl_base; | |
383 | u32 revision; | |
384 | ||
84e250ff DB |
385 | usb_nop_xceiv_register(); |
386 | musb->xceiv = otg_get_transceiver(); | |
387 | if (!musb->xceiv) | |
388 | return -ENODEV; | |
389 | ||
550a7375 | 390 | musb->mregs += DAVINCI_BASE_OFFSET; |
550a7375 | 391 | |
34f32c97 | 392 | clk_enable(musb->clock); |
550a7375 FB |
393 | |
394 | /* returns zero if e.g. not clocked */ | |
395 | revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG); | |
396 | if (revision == 0) | |
84e250ff | 397 | goto fail; |
550a7375 FB |
398 | |
399 | if (is_host_enabled(musb)) | |
400 | setup_timer(&otg_workaround, otg_timer, (unsigned long) musb); | |
401 | ||
402 | musb->board_set_vbus = davinci_set_vbus; | |
403 | davinci_source_power(musb, 0, 1); | |
404 | ||
a227fd7d DB |
405 | /* dm355 EVM swaps D+/D- for signal integrity, and |
406 | * is clocked from the main 24 MHz crystal. | |
407 | */ | |
408 | if (machine_is_davinci_dm355_evm()) { | |
409 | u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); | |
410 | ||
411 | phy_ctrl &= ~(3 << 9); | |
412 | phy_ctrl |= USBPHY_DATAPOL; | |
413 | __raw_writel(phy_ctrl, USB_PHY_CTRL); | |
414 | } | |
415 | ||
d163ef24 DB |
416 | /* On dm355, the default-A state machine needs DRVVBUS control. |
417 | * If we won't be a host, there's no need to turn it on. | |
418 | */ | |
419 | if (cpu_is_davinci_dm355()) { | |
420 | u32 deepsleep = __raw_readl(DM355_DEEPSLEEP); | |
421 | ||
422 | if (is_host_enabled(musb)) { | |
423 | deepsleep &= ~DRVVBUS_OVERRIDE; | |
424 | } else { | |
425 | deepsleep &= ~DRVVBUS_FORCE; | |
426 | deepsleep |= DRVVBUS_OVERRIDE; | |
427 | } | |
428 | __raw_writel(deepsleep, DM355_DEEPSLEEP); | |
429 | } | |
430 | ||
550a7375 FB |
431 | /* reset the controller */ |
432 | musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1); | |
433 | ||
434 | /* start the on-chip PHY and its PLL */ | |
435 | phy_on(); | |
436 | ||
437 | msleep(5); | |
438 | ||
439 | /* NOTE: irqs are in mixed mode, not bypass to pure-musb */ | |
440 | pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n", | |
a227fd7d | 441 | revision, __raw_readl(USB_PHY_CTRL), |
550a7375 FB |
442 | musb_readb(tibase, DAVINCI_USB_CTRL_REG)); |
443 | ||
444 | musb->isr = davinci_interrupt; | |
445 | return 0; | |
84e250ff DB |
446 | |
447 | fail: | |
448 | usb_nop_xceiv_unregister(); | |
449 | return -ENODEV; | |
550a7375 FB |
450 | } |
451 | ||
452 | int musb_platform_exit(struct musb *musb) | |
453 | { | |
454 | if (is_host_enabled(musb)) | |
455 | del_timer_sync(&otg_workaround); | |
456 | ||
d163ef24 DB |
457 | /* force VBUS off */ |
458 | if (cpu_is_davinci_dm355()) { | |
459 | u32 deepsleep = __raw_readl(DM355_DEEPSLEEP); | |
460 | ||
461 | deepsleep &= ~DRVVBUS_FORCE; | |
462 | deepsleep |= DRVVBUS_OVERRIDE; | |
463 | __raw_writel(deepsleep, DM355_DEEPSLEEP); | |
464 | } | |
465 | ||
550a7375 FB |
466 | davinci_source_power(musb, 0 /*off*/, 1); |
467 | ||
468 | /* delay, to avoid problems with module reload */ | |
84e250ff | 469 | if (is_host_enabled(musb) && musb->xceiv->default_a) { |
550a7375 FB |
470 | int maxdelay = 30; |
471 | u8 devctl, warn = 0; | |
472 | ||
473 | /* if there's no peripheral connected, this can take a | |
474 | * long time to fall, especially on EVM with huge C133. | |
475 | */ | |
476 | do { | |
477 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
478 | if (!(devctl & MUSB_DEVCTL_VBUS)) | |
479 | break; | |
480 | if ((devctl & MUSB_DEVCTL_VBUS) != warn) { | |
481 | warn = devctl & MUSB_DEVCTL_VBUS; | |
482 | DBG(1, "VBUS %d\n", | |
483 | warn >> MUSB_DEVCTL_VBUS_SHIFT); | |
484 | } | |
485 | msleep(1000); | |
486 | maxdelay--; | |
487 | } while (maxdelay > 0); | |
488 | ||
489 | /* in OTG mode, another host might be connected */ | |
490 | if (devctl & MUSB_DEVCTL_VBUS) | |
491 | DBG(1, "VBUS off timeout (devctl %02x)\n", devctl); | |
492 | } | |
493 | ||
494 | phy_off(); | |
34f32c97 DB |
495 | |
496 | clk_disable(musb->clock); | |
497 | ||
84e250ff DB |
498 | usb_nop_xceiv_unregister(); |
499 | ||
550a7375 FB |
500 | return 0; |
501 | } |