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550a7375 FB |
1 | /* |
2 | * MUSB OTG driver core code | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
23 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
25 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
26 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
27 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
28 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | */ | |
34 | ||
35 | /* | |
36 | * Inventra (Multipoint) Dual-Role Controller Driver for Linux. | |
37 | * | |
38 | * This consists of a Host Controller Driver (HCD) and a peripheral | |
39 | * controller driver implementing the "Gadget" API; OTG support is | |
40 | * in the works. These are normal Linux-USB controller drivers which | |
41 | * use IRQs and have no dedicated thread. | |
42 | * | |
43 | * This version of the driver has only been used with products from | |
44 | * Texas Instruments. Those products integrate the Inventra logic | |
45 | * with other DMA, IRQ, and bus modules, as well as other logic that | |
46 | * needs to be reflected in this driver. | |
47 | * | |
48 | * | |
49 | * NOTE: the original Mentor code here was pretty much a collection | |
50 | * of mechanisms that don't seem to have been fully integrated/working | |
51 | * for *any* Linux kernel version. This version aims at Linux 2.6.now, | |
52 | * Key open issues include: | |
53 | * | |
54 | * - Lack of host-side transaction scheduling, for all transfer types. | |
55 | * The hardware doesn't do it; instead, software must. | |
56 | * | |
57 | * This is not an issue for OTG devices that don't support external | |
58 | * hubs, but for more "normal" USB hosts it's a user issue that the | |
59 | * "multipoint" support doesn't scale in the expected ways. That | |
60 | * includes DaVinci EVM in a common non-OTG mode. | |
61 | * | |
62 | * * Control and bulk use dedicated endpoints, and there's as | |
63 | * yet no mechanism to either (a) reclaim the hardware when | |
64 | * peripherals are NAKing, which gets complicated with bulk | |
65 | * endpoints, or (b) use more than a single bulk endpoint in | |
66 | * each direction. | |
67 | * | |
68 | * RESULT: one device may be perceived as blocking another one. | |
69 | * | |
70 | * * Interrupt and isochronous will dynamically allocate endpoint | |
71 | * hardware, but (a) there's no record keeping for bandwidth; | |
72 | * (b) in the common case that few endpoints are available, there | |
73 | * is no mechanism to reuse endpoints to talk to multiple devices. | |
74 | * | |
75 | * RESULT: At one extreme, bandwidth can be overcommitted in | |
76 | * some hardware configurations, no faults will be reported. | |
77 | * At the other extreme, the bandwidth capabilities which do | |
78 | * exist tend to be severely undercommitted. You can't yet hook | |
79 | * up both a keyboard and a mouse to an external USB hub. | |
80 | */ | |
81 | ||
82 | /* | |
83 | * This gets many kinds of configuration information: | |
84 | * - Kconfig for everything user-configurable | |
550a7375 FB |
85 | * - platform_device for addressing, irq, and platform_data |
86 | * - platform_data is mostly for board-specific informarion | |
c767c1c6 | 87 | * (plus recentrly, SOC or family details) |
550a7375 FB |
88 | * |
89 | * Most of the conditional compilation will (someday) vanish. | |
90 | */ | |
91 | ||
92 | #include <linux/module.h> | |
93 | #include <linux/kernel.h> | |
94 | #include <linux/sched.h> | |
95 | #include <linux/slab.h> | |
96 | #include <linux/init.h> | |
97 | #include <linux/list.h> | |
98 | #include <linux/kobject.h> | |
99 | #include <linux/platform_device.h> | |
100 | #include <linux/io.h> | |
101 | ||
102 | #ifdef CONFIG_ARM | |
0590d587 FB |
103 | #include <mach/hardware.h> |
104 | #include <mach/memory.h> | |
550a7375 FB |
105 | #include <asm/mach-types.h> |
106 | #endif | |
107 | ||
108 | #include "musb_core.h" | |
109 | ||
110 | ||
111 | #ifdef CONFIG_ARCH_DAVINCI | |
112 | #include "davinci.h" | |
113 | #endif | |
114 | ||
115 | ||
116 | ||
b60c72ab FB |
117 | unsigned musb_debug; |
118 | module_param(musb_debug, uint, S_IRUGO | S_IWUSR); | |
e8164f64 | 119 | MODULE_PARM_DESC(debug, "Debug message level. Default = 0"); |
550a7375 FB |
120 | |
121 | #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" | |
122 | #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" | |
123 | ||
e8164f64 | 124 | #define MUSB_VERSION "6.0" |
550a7375 FB |
125 | |
126 | #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION | |
127 | ||
128 | #define MUSB_DRIVER_NAME "musb_hdrc" | |
129 | const char musb_driver_name[] = MUSB_DRIVER_NAME; | |
130 | ||
131 | MODULE_DESCRIPTION(DRIVER_INFO); | |
132 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
133 | MODULE_LICENSE("GPL"); | |
134 | MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); | |
135 | ||
136 | ||
137 | /*-------------------------------------------------------------------------*/ | |
138 | ||
139 | static inline struct musb *dev_to_musb(struct device *dev) | |
140 | { | |
141 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
142 | /* usbcore insists dev->driver_data is a "struct hcd *" */ | |
143 | return hcd_to_musb(dev_get_drvdata(dev)); | |
144 | #else | |
145 | return dev_get_drvdata(dev); | |
146 | #endif | |
147 | } | |
148 | ||
149 | /*-------------------------------------------------------------------------*/ | |
150 | ||
c6cf8b00 BW |
151 | #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN) |
152 | ||
550a7375 FB |
153 | /* |
154 | * Load an endpoint's FIFO | |
155 | */ | |
156 | void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) | |
157 | { | |
158 | void __iomem *fifo = hw_ep->fifo; | |
159 | ||
160 | prefetch((u8 *)src); | |
161 | ||
162 | DBG(4, "%cX ep%d fifo %p count %d buf %p\n", | |
163 | 'T', hw_ep->epnum, fifo, len, src); | |
164 | ||
165 | /* we can't assume unaligned reads work */ | |
166 | if (likely((0x01 & (unsigned long) src) == 0)) { | |
167 | u16 index = 0; | |
168 | ||
169 | /* best case is 32bit-aligned source address */ | |
170 | if ((0x02 & (unsigned long) src) == 0) { | |
171 | if (len >= 4) { | |
172 | writesl(fifo, src + index, len >> 2); | |
173 | index += len & ~0x03; | |
174 | } | |
175 | if (len & 0x02) { | |
176 | musb_writew(fifo, 0, *(u16 *)&src[index]); | |
177 | index += 2; | |
178 | } | |
179 | } else { | |
180 | if (len >= 2) { | |
181 | writesw(fifo, src + index, len >> 1); | |
182 | index += len & ~0x01; | |
183 | } | |
184 | } | |
185 | if (len & 0x01) | |
186 | musb_writeb(fifo, 0, src[index]); | |
187 | } else { | |
188 | /* byte aligned */ | |
189 | writesb(fifo, src, len); | |
190 | } | |
191 | } | |
192 | ||
193 | /* | |
194 | * Unload an endpoint's FIFO | |
195 | */ | |
196 | void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) | |
197 | { | |
198 | void __iomem *fifo = hw_ep->fifo; | |
199 | ||
200 | DBG(4, "%cX ep%d fifo %p count %d buf %p\n", | |
201 | 'R', hw_ep->epnum, fifo, len, dst); | |
202 | ||
203 | /* we can't assume unaligned writes work */ | |
204 | if (likely((0x01 & (unsigned long) dst) == 0)) { | |
205 | u16 index = 0; | |
206 | ||
207 | /* best case is 32bit-aligned destination address */ | |
208 | if ((0x02 & (unsigned long) dst) == 0) { | |
209 | if (len >= 4) { | |
210 | readsl(fifo, dst, len >> 2); | |
211 | index = len & ~0x03; | |
212 | } | |
213 | if (len & 0x02) { | |
214 | *(u16 *)&dst[index] = musb_readw(fifo, 0); | |
215 | index += 2; | |
216 | } | |
217 | } else { | |
218 | if (len >= 2) { | |
219 | readsw(fifo, dst, len >> 1); | |
220 | index = len & ~0x01; | |
221 | } | |
222 | } | |
223 | if (len & 0x01) | |
224 | dst[index] = musb_readb(fifo, 0); | |
225 | } else { | |
226 | /* byte aligned */ | |
227 | readsb(fifo, dst, len); | |
228 | } | |
229 | } | |
230 | ||
231 | #endif /* normal PIO */ | |
232 | ||
233 | ||
234 | /*-------------------------------------------------------------------------*/ | |
235 | ||
236 | /* for high speed test mode; see USB 2.0 spec 7.1.20 */ | |
237 | static const u8 musb_test_packet[53] = { | |
238 | /* implicit SYNC then DATA0 to start */ | |
239 | ||
240 | /* JKJKJKJK x9 */ | |
241 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
242 | /* JJKKJJKK x8 */ | |
243 | 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, | |
244 | /* JJJJKKKK x8 */ | |
245 | 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, | |
246 | /* JJJJJJJKKKKKKK x8 */ | |
247 | 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
248 | /* JJJJJJJK x8 */ | |
249 | 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, | |
250 | /* JKKKKKKK x10, JK */ | |
251 | 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e | |
252 | ||
253 | /* implicit CRC16 then EOP to end */ | |
254 | }; | |
255 | ||
256 | void musb_load_testpacket(struct musb *musb) | |
257 | { | |
258 | void __iomem *regs = musb->endpoints[0].regs; | |
259 | ||
260 | musb_ep_select(musb->mregs, 0); | |
261 | musb_write_fifo(musb->control_ep, | |
262 | sizeof(musb_test_packet), musb_test_packet); | |
263 | musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); | |
264 | } | |
265 | ||
266 | /*-------------------------------------------------------------------------*/ | |
267 | ||
268 | const char *otg_state_string(struct musb *musb) | |
269 | { | |
270 | switch (musb->xceiv.state) { | |
271 | case OTG_STATE_A_IDLE: return "a_idle"; | |
272 | case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise"; | |
273 | case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon"; | |
274 | case OTG_STATE_A_HOST: return "a_host"; | |
275 | case OTG_STATE_A_SUSPEND: return "a_suspend"; | |
276 | case OTG_STATE_A_PERIPHERAL: return "a_peripheral"; | |
277 | case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall"; | |
278 | case OTG_STATE_A_VBUS_ERR: return "a_vbus_err"; | |
279 | case OTG_STATE_B_IDLE: return "b_idle"; | |
280 | case OTG_STATE_B_SRP_INIT: return "b_srp_init"; | |
281 | case OTG_STATE_B_PERIPHERAL: return "b_peripheral"; | |
282 | case OTG_STATE_B_WAIT_ACON: return "b_wait_acon"; | |
283 | case OTG_STATE_B_HOST: return "b_host"; | |
284 | default: return "UNDEFINED"; | |
285 | } | |
286 | } | |
287 | ||
288 | #ifdef CONFIG_USB_MUSB_OTG | |
289 | ||
290 | /* | |
291 | * See also USB_OTG_1-3.pdf 6.6.5 Timers | |
292 | * REVISIT: Are the other timers done in the hardware? | |
293 | */ | |
294 | #define TB_ASE0_BRST 100 /* Min 3.125 ms */ | |
295 | ||
296 | /* | |
297 | * Handles OTG hnp timeouts, such as b_ase0_brst | |
298 | */ | |
299 | void musb_otg_timer_func(unsigned long data) | |
300 | { | |
301 | struct musb *musb = (struct musb *)data; | |
302 | unsigned long flags; | |
303 | ||
304 | spin_lock_irqsave(&musb->lock, flags); | |
305 | switch (musb->xceiv.state) { | |
306 | case OTG_STATE_B_WAIT_ACON: | |
307 | DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n"); | |
308 | musb_g_disconnect(musb); | |
309 | musb->xceiv.state = OTG_STATE_B_PERIPHERAL; | |
310 | musb->is_active = 0; | |
311 | break; | |
312 | case OTG_STATE_A_WAIT_BCON: | |
313 | DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n"); | |
314 | musb_hnp_stop(musb); | |
315 | break; | |
316 | default: | |
317 | DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb)); | |
318 | } | |
319 | musb->ignore_disconnect = 0; | |
320 | spin_unlock_irqrestore(&musb->lock, flags); | |
321 | } | |
322 | ||
323 | static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0); | |
324 | ||
325 | /* | |
326 | * Stops the B-device HNP state. Caller must take care of locking. | |
327 | */ | |
328 | void musb_hnp_stop(struct musb *musb) | |
329 | { | |
330 | struct usb_hcd *hcd = musb_to_hcd(musb); | |
331 | void __iomem *mbase = musb->mregs; | |
332 | u8 reg; | |
333 | ||
334 | switch (musb->xceiv.state) { | |
335 | case OTG_STATE_A_PERIPHERAL: | |
336 | case OTG_STATE_A_WAIT_VFALL: | |
337 | case OTG_STATE_A_WAIT_BCON: | |
338 | DBG(1, "HNP: Switching back to A-host\n"); | |
339 | musb_g_disconnect(musb); | |
340 | musb->xceiv.state = OTG_STATE_A_IDLE; | |
341 | MUSB_HST_MODE(musb); | |
342 | musb->is_active = 0; | |
343 | break; | |
344 | case OTG_STATE_B_HOST: | |
345 | DBG(1, "HNP: Disabling HR\n"); | |
346 | hcd->self.is_b_host = 0; | |
347 | musb->xceiv.state = OTG_STATE_B_PERIPHERAL; | |
348 | MUSB_DEV_MODE(musb); | |
349 | reg = musb_readb(mbase, MUSB_POWER); | |
350 | reg |= MUSB_POWER_SUSPENDM; | |
351 | musb_writeb(mbase, MUSB_POWER, reg); | |
352 | /* REVISIT: Start SESSION_REQUEST here? */ | |
353 | break; | |
354 | default: | |
355 | DBG(1, "HNP: Stopping in unknown state %s\n", | |
356 | otg_state_string(musb)); | |
357 | } | |
358 | ||
359 | /* | |
360 | * When returning to A state after HNP, avoid hub_port_rebounce(), | |
361 | * which cause occasional OPT A "Did not receive reset after connect" | |
362 | * errors. | |
363 | */ | |
364 | musb->port1_status &= | |
365 | ~(1 << USB_PORT_FEAT_C_CONNECTION); | |
366 | } | |
367 | ||
368 | #endif | |
369 | ||
370 | /* | |
371 | * Interrupt Service Routine to record USB "global" interrupts. | |
372 | * Since these do not happen often and signify things of | |
373 | * paramount importance, it seems OK to check them individually; | |
374 | * the order of the tests is specified in the manual | |
375 | * | |
376 | * @param musb instance pointer | |
377 | * @param int_usb register contents | |
378 | * @param devctl | |
379 | * @param power | |
380 | */ | |
381 | ||
382 | #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \ | |
383 | | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \ | |
384 | | MUSB_INTR_RESET) | |
385 | ||
386 | static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, | |
387 | u8 devctl, u8 power) | |
388 | { | |
389 | irqreturn_t handled = IRQ_NONE; | |
390 | void __iomem *mbase = musb->mregs; | |
391 | ||
392 | DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, | |
393 | int_usb); | |
394 | ||
395 | /* in host mode, the peripheral may issue remote wakeup. | |
396 | * in peripheral mode, the host may resume the link. | |
397 | * spurious RESUME irqs happen too, paired with SUSPEND. | |
398 | */ | |
399 | if (int_usb & MUSB_INTR_RESUME) { | |
400 | handled = IRQ_HANDLED; | |
401 | DBG(3, "RESUME (%s)\n", otg_state_string(musb)); | |
402 | ||
403 | if (devctl & MUSB_DEVCTL_HM) { | |
404 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
405 | switch (musb->xceiv.state) { | |
406 | case OTG_STATE_A_SUSPEND: | |
407 | /* remote wakeup? later, GetPortStatus | |
408 | * will stop RESUME signaling | |
409 | */ | |
410 | ||
411 | if (power & MUSB_POWER_SUSPENDM) { | |
412 | /* spurious */ | |
413 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
414 | DBG(2, "Spurious SUSPENDM\n"); | |
415 | break; | |
416 | } | |
417 | ||
418 | power &= ~MUSB_POWER_SUSPENDM; | |
419 | musb_writeb(mbase, MUSB_POWER, | |
420 | power | MUSB_POWER_RESUME); | |
421 | ||
422 | musb->port1_status |= | |
423 | (USB_PORT_STAT_C_SUSPEND << 16) | |
424 | | MUSB_PORT_STAT_RESUME; | |
425 | musb->rh_timer = jiffies | |
426 | + msecs_to_jiffies(20); | |
427 | ||
428 | musb->xceiv.state = OTG_STATE_A_HOST; | |
429 | musb->is_active = 1; | |
430 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
431 | break; | |
432 | case OTG_STATE_B_WAIT_ACON: | |
433 | musb->xceiv.state = OTG_STATE_B_PERIPHERAL; | |
434 | musb->is_active = 1; | |
435 | MUSB_DEV_MODE(musb); | |
436 | break; | |
437 | default: | |
438 | WARNING("bogus %s RESUME (%s)\n", | |
439 | "host", | |
440 | otg_state_string(musb)); | |
441 | } | |
442 | #endif | |
443 | } else { | |
444 | switch (musb->xceiv.state) { | |
445 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
446 | case OTG_STATE_A_SUSPEND: | |
447 | /* possibly DISCONNECT is upcoming */ | |
448 | musb->xceiv.state = OTG_STATE_A_HOST; | |
449 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
450 | break; | |
451 | #endif | |
452 | #ifdef CONFIG_USB_GADGET_MUSB_HDRC | |
453 | case OTG_STATE_B_WAIT_ACON: | |
454 | case OTG_STATE_B_PERIPHERAL: | |
455 | /* disconnect while suspended? we may | |
456 | * not get a disconnect irq... | |
457 | */ | |
458 | if ((devctl & MUSB_DEVCTL_VBUS) | |
459 | != (3 << MUSB_DEVCTL_VBUS_SHIFT) | |
460 | ) { | |
461 | musb->int_usb |= MUSB_INTR_DISCONNECT; | |
462 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
463 | break; | |
464 | } | |
465 | musb_g_resume(musb); | |
466 | break; | |
467 | case OTG_STATE_B_IDLE: | |
468 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
469 | break; | |
470 | #endif | |
471 | default: | |
472 | WARNING("bogus %s RESUME (%s)\n", | |
473 | "peripheral", | |
474 | otg_state_string(musb)); | |
475 | } | |
476 | } | |
477 | } | |
478 | ||
479 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
480 | /* see manual for the order of the tests */ | |
481 | if (int_usb & MUSB_INTR_SESSREQ) { | |
482 | DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb)); | |
483 | ||
484 | /* IRQ arrives from ID pin sense or (later, if VBUS power | |
485 | * is removed) SRP. responses are time critical: | |
486 | * - turn on VBUS (with silicon-specific mechanism) | |
487 | * - go through A_WAIT_VRISE | |
488 | * - ... to A_WAIT_BCON. | |
489 | * a_wait_vrise_tmout triggers VBUS_ERROR transitions | |
490 | */ | |
491 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
492 | musb->ep0_stage = MUSB_EP0_START; | |
493 | musb->xceiv.state = OTG_STATE_A_IDLE; | |
494 | MUSB_HST_MODE(musb); | |
495 | musb_set_vbus(musb, 1); | |
496 | ||
497 | handled = IRQ_HANDLED; | |
498 | } | |
499 | ||
500 | if (int_usb & MUSB_INTR_VBUSERROR) { | |
501 | int ignore = 0; | |
502 | ||
503 | /* During connection as an A-Device, we may see a short | |
504 | * current spikes causing voltage drop, because of cable | |
505 | * and peripheral capacitance combined with vbus draw. | |
506 | * (So: less common with truly self-powered devices, where | |
507 | * vbus doesn't act like a power supply.) | |
508 | * | |
509 | * Such spikes are short; usually less than ~500 usec, max | |
510 | * of ~2 msec. That is, they're not sustained overcurrent | |
511 | * errors, though they're reported using VBUSERROR irqs. | |
512 | * | |
513 | * Workarounds: (a) hardware: use self powered devices. | |
514 | * (b) software: ignore non-repeated VBUS errors. | |
515 | * | |
516 | * REVISIT: do delays from lots of DEBUG_KERNEL checks | |
517 | * make trouble here, keeping VBUS < 4.4V ? | |
518 | */ | |
519 | switch (musb->xceiv.state) { | |
520 | case OTG_STATE_A_HOST: | |
521 | /* recovery is dicey once we've gotten past the | |
522 | * initial stages of enumeration, but if VBUS | |
523 | * stayed ok at the other end of the link, and | |
524 | * another reset is due (at least for high speed, | |
525 | * to redo the chirp etc), it might work OK... | |
526 | */ | |
527 | case OTG_STATE_A_WAIT_BCON: | |
528 | case OTG_STATE_A_WAIT_VRISE: | |
529 | if (musb->vbuserr_retry) { | |
530 | musb->vbuserr_retry--; | |
531 | ignore = 1; | |
532 | devctl |= MUSB_DEVCTL_SESSION; | |
533 | musb_writeb(mbase, MUSB_DEVCTL, devctl); | |
534 | } else { | |
535 | musb->port1_status |= | |
536 | (1 << USB_PORT_FEAT_OVER_CURRENT) | |
537 | | (1 << USB_PORT_FEAT_C_OVER_CURRENT); | |
538 | } | |
539 | break; | |
540 | default: | |
541 | break; | |
542 | } | |
543 | ||
544 | DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", | |
545 | otg_state_string(musb), | |
546 | devctl, | |
547 | ({ char *s; | |
548 | switch (devctl & MUSB_DEVCTL_VBUS) { | |
549 | case 0 << MUSB_DEVCTL_VBUS_SHIFT: | |
550 | s = "<SessEnd"; break; | |
551 | case 1 << MUSB_DEVCTL_VBUS_SHIFT: | |
552 | s = "<AValid"; break; | |
553 | case 2 << MUSB_DEVCTL_VBUS_SHIFT: | |
554 | s = "<VBusValid"; break; | |
555 | /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ | |
556 | default: | |
557 | s = "VALID"; break; | |
558 | }; s; }), | |
559 | VBUSERR_RETRY_COUNT - musb->vbuserr_retry, | |
560 | musb->port1_status); | |
561 | ||
562 | /* go through A_WAIT_VFALL then start a new session */ | |
563 | if (!ignore) | |
564 | musb_set_vbus(musb, 0); | |
565 | handled = IRQ_HANDLED; | |
566 | } | |
567 | ||
568 | if (int_usb & MUSB_INTR_CONNECT) { | |
569 | struct usb_hcd *hcd = musb_to_hcd(musb); | |
570 | ||
571 | handled = IRQ_HANDLED; | |
572 | musb->is_active = 1; | |
573 | set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags); | |
574 | ||
575 | musb->ep0_stage = MUSB_EP0_START; | |
576 | ||
577 | #ifdef CONFIG_USB_MUSB_OTG | |
578 | /* flush endpoints when transitioning from Device Mode */ | |
579 | if (is_peripheral_active(musb)) { | |
580 | /* REVISIT HNP; just force disconnect */ | |
581 | } | |
582 | musb_writew(mbase, MUSB_INTRTXE, musb->epmask); | |
583 | musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe); | |
584 | musb_writeb(mbase, MUSB_INTRUSBE, 0xf7); | |
585 | #endif | |
586 | musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED | |
587 | |USB_PORT_STAT_HIGH_SPEED | |
588 | |USB_PORT_STAT_ENABLE | |
589 | ); | |
590 | musb->port1_status |= USB_PORT_STAT_CONNECTION | |
591 | |(USB_PORT_STAT_C_CONNECTION << 16); | |
592 | ||
593 | /* high vs full speed is just a guess until after reset */ | |
594 | if (devctl & MUSB_DEVCTL_LSDEV) | |
595 | musb->port1_status |= USB_PORT_STAT_LOW_SPEED; | |
596 | ||
597 | if (hcd->status_urb) | |
598 | usb_hcd_poll_rh_status(hcd); | |
599 | else | |
600 | usb_hcd_resume_root_hub(hcd); | |
601 | ||
602 | MUSB_HST_MODE(musb); | |
603 | ||
604 | /* indicate new connection to OTG machine */ | |
605 | switch (musb->xceiv.state) { | |
606 | case OTG_STATE_B_PERIPHERAL: | |
607 | if (int_usb & MUSB_INTR_SUSPEND) { | |
608 | DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n"); | |
609 | musb->xceiv.state = OTG_STATE_B_HOST; | |
610 | hcd->self.is_b_host = 1; | |
611 | int_usb &= ~MUSB_INTR_SUSPEND; | |
612 | } else | |
613 | DBG(1, "CONNECT as b_peripheral???\n"); | |
614 | break; | |
615 | case OTG_STATE_B_WAIT_ACON: | |
616 | DBG(1, "HNP: Waiting to switch to b_host state\n"); | |
617 | musb->xceiv.state = OTG_STATE_B_HOST; | |
618 | hcd->self.is_b_host = 1; | |
619 | break; | |
620 | default: | |
621 | if ((devctl & MUSB_DEVCTL_VBUS) | |
622 | == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { | |
623 | musb->xceiv.state = OTG_STATE_A_HOST; | |
624 | hcd->self.is_b_host = 0; | |
625 | } | |
626 | break; | |
627 | } | |
628 | DBG(1, "CONNECT (%s) devctl %02x\n", | |
629 | otg_state_string(musb), devctl); | |
630 | } | |
631 | #endif /* CONFIG_USB_MUSB_HDRC_HCD */ | |
632 | ||
633 | /* mentor saves a bit: bus reset and babble share the same irq. | |
634 | * only host sees babble; only peripheral sees bus reset. | |
635 | */ | |
636 | if (int_usb & MUSB_INTR_RESET) { | |
637 | if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { | |
638 | /* | |
639 | * Looks like non-HS BABBLE can be ignored, but | |
640 | * HS BABBLE is an error condition. For HS the solution | |
641 | * is to avoid babble in the first place and fix what | |
642 | * caused BABBLE. When HS BABBLE happens we can only | |
643 | * stop the session. | |
644 | */ | |
645 | if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) | |
646 | DBG(1, "BABBLE devctl: %02x\n", devctl); | |
647 | else { | |
648 | ERR("Stopping host session -- babble\n"); | |
649 | musb_writeb(mbase, MUSB_DEVCTL, 0); | |
650 | } | |
651 | } else if (is_peripheral_capable()) { | |
652 | DBG(1, "BUS RESET as %s\n", otg_state_string(musb)); | |
653 | switch (musb->xceiv.state) { | |
654 | #ifdef CONFIG_USB_OTG | |
655 | case OTG_STATE_A_SUSPEND: | |
656 | /* We need to ignore disconnect on suspend | |
657 | * otherwise tusb 2.0 won't reconnect after a | |
658 | * power cycle, which breaks otg compliance. | |
659 | */ | |
660 | musb->ignore_disconnect = 1; | |
661 | musb_g_reset(musb); | |
662 | /* FALLTHROUGH */ | |
663 | case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ | |
664 | DBG(1, "HNP: Setting timer as %s\n", | |
665 | otg_state_string(musb)); | |
666 | musb_otg_timer.data = (unsigned long)musb; | |
667 | mod_timer(&musb_otg_timer, jiffies | |
668 | + msecs_to_jiffies(100)); | |
669 | break; | |
670 | case OTG_STATE_A_PERIPHERAL: | |
671 | musb_hnp_stop(musb); | |
672 | break; | |
673 | case OTG_STATE_B_WAIT_ACON: | |
674 | DBG(1, "HNP: RESET (%s), to b_peripheral\n", | |
675 | otg_state_string(musb)); | |
676 | musb->xceiv.state = OTG_STATE_B_PERIPHERAL; | |
677 | musb_g_reset(musb); | |
678 | break; | |
679 | #endif | |
680 | case OTG_STATE_B_IDLE: | |
681 | musb->xceiv.state = OTG_STATE_B_PERIPHERAL; | |
682 | /* FALLTHROUGH */ | |
683 | case OTG_STATE_B_PERIPHERAL: | |
684 | musb_g_reset(musb); | |
685 | break; | |
686 | default: | |
687 | DBG(1, "Unhandled BUS RESET as %s\n", | |
688 | otg_state_string(musb)); | |
689 | } | |
690 | } | |
691 | ||
692 | handled = IRQ_HANDLED; | |
693 | } | |
694 | schedule_work(&musb->irq_work); | |
695 | ||
696 | return handled; | |
697 | } | |
698 | ||
699 | /* | |
700 | * Interrupt Service Routine to record USB "global" interrupts. | |
701 | * Since these do not happen often and signify things of | |
702 | * paramount importance, it seems OK to check them individually; | |
703 | * the order of the tests is specified in the manual | |
704 | * | |
705 | * @param musb instance pointer | |
706 | * @param int_usb register contents | |
707 | * @param devctl | |
708 | * @param power | |
709 | */ | |
710 | static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb, | |
711 | u8 devctl, u8 power) | |
712 | { | |
713 | irqreturn_t handled = IRQ_NONE; | |
714 | ||
715 | #if 0 | |
716 | /* REVISIT ... this would be for multiplexing periodic endpoints, or | |
717 | * supporting transfer phasing to prevent exceeding ISO bandwidth | |
718 | * limits of a given frame or microframe. | |
719 | * | |
720 | * It's not needed for peripheral side, which dedicates endpoints; | |
721 | * though it _might_ use SOF irqs for other purposes. | |
722 | * | |
723 | * And it's not currently needed for host side, which also dedicates | |
724 | * endpoints, relies on TX/RX interval registers, and isn't claimed | |
725 | * to support ISO transfers yet. | |
726 | */ | |
727 | if (int_usb & MUSB_INTR_SOF) { | |
728 | void __iomem *mbase = musb->mregs; | |
729 | struct musb_hw_ep *ep; | |
730 | u8 epnum; | |
731 | u16 frame; | |
732 | ||
733 | DBG(6, "START_OF_FRAME\n"); | |
734 | handled = IRQ_HANDLED; | |
735 | ||
736 | /* start any periodic Tx transfers waiting for current frame */ | |
737 | frame = musb_readw(mbase, MUSB_FRAME); | |
738 | ep = musb->endpoints; | |
739 | for (epnum = 1; (epnum < musb->nr_endpoints) | |
740 | && (musb->epmask >= (1 << epnum)); | |
741 | epnum++, ep++) { | |
742 | /* | |
743 | * FIXME handle framecounter wraps (12 bits) | |
744 | * eliminate duplicated StartUrb logic | |
745 | */ | |
746 | if (ep->dwWaitFrame >= frame) { | |
747 | ep->dwWaitFrame = 0; | |
748 | pr_debug("SOF --> periodic TX%s on %d\n", | |
749 | ep->tx_channel ? " DMA" : "", | |
750 | epnum); | |
751 | if (!ep->tx_channel) | |
752 | musb_h_tx_start(musb, epnum); | |
753 | else | |
754 | cppi_hostdma_start(musb, epnum); | |
755 | } | |
756 | } /* end of for loop */ | |
757 | } | |
758 | #endif | |
759 | ||
760 | if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { | |
761 | DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n", | |
762 | otg_state_string(musb), | |
763 | MUSB_MODE(musb), devctl); | |
764 | handled = IRQ_HANDLED; | |
765 | ||
766 | switch (musb->xceiv.state) { | |
767 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
768 | case OTG_STATE_A_HOST: | |
769 | case OTG_STATE_A_SUSPEND: | |
770 | musb_root_disconnect(musb); | |
771 | if (musb->a_wait_bcon != 0) | |
772 | musb_platform_try_idle(musb, jiffies | |
773 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
774 | break; | |
775 | #endif /* HOST */ | |
776 | #ifdef CONFIG_USB_MUSB_OTG | |
777 | case OTG_STATE_B_HOST: | |
778 | musb_hnp_stop(musb); | |
779 | break; | |
780 | case OTG_STATE_A_PERIPHERAL: | |
781 | musb_hnp_stop(musb); | |
782 | musb_root_disconnect(musb); | |
783 | /* FALLTHROUGH */ | |
784 | case OTG_STATE_B_WAIT_ACON: | |
785 | /* FALLTHROUGH */ | |
786 | #endif /* OTG */ | |
787 | #ifdef CONFIG_USB_GADGET_MUSB_HDRC | |
788 | case OTG_STATE_B_PERIPHERAL: | |
789 | case OTG_STATE_B_IDLE: | |
790 | musb_g_disconnect(musb); | |
791 | break; | |
792 | #endif /* GADGET */ | |
793 | default: | |
794 | WARNING("unhandled DISCONNECT transition (%s)\n", | |
795 | otg_state_string(musb)); | |
796 | break; | |
797 | } | |
798 | ||
799 | schedule_work(&musb->irq_work); | |
800 | } | |
801 | ||
802 | if (int_usb & MUSB_INTR_SUSPEND) { | |
803 | DBG(1, "SUSPEND (%s) devctl %02x power %02x\n", | |
804 | otg_state_string(musb), devctl, power); | |
805 | handled = IRQ_HANDLED; | |
806 | ||
807 | switch (musb->xceiv.state) { | |
808 | #ifdef CONFIG_USB_MUSB_OTG | |
809 | case OTG_STATE_A_PERIPHERAL: | |
810 | /* | |
811 | * We cannot stop HNP here, devctl BDEVICE might be | |
812 | * still set. | |
813 | */ | |
814 | break; | |
815 | #endif | |
816 | case OTG_STATE_B_PERIPHERAL: | |
817 | musb_g_suspend(musb); | |
818 | musb->is_active = is_otg_enabled(musb) | |
819 | && musb->xceiv.gadget->b_hnp_enable; | |
820 | if (musb->is_active) { | |
821 | #ifdef CONFIG_USB_MUSB_OTG | |
822 | musb->xceiv.state = OTG_STATE_B_WAIT_ACON; | |
823 | DBG(1, "HNP: Setting timer for b_ase0_brst\n"); | |
824 | musb_otg_timer.data = (unsigned long)musb; | |
825 | mod_timer(&musb_otg_timer, jiffies | |
826 | + msecs_to_jiffies(TB_ASE0_BRST)); | |
827 | #endif | |
828 | } | |
829 | break; | |
830 | case OTG_STATE_A_WAIT_BCON: | |
831 | if (musb->a_wait_bcon != 0) | |
832 | musb_platform_try_idle(musb, jiffies | |
833 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
834 | break; | |
835 | case OTG_STATE_A_HOST: | |
836 | musb->xceiv.state = OTG_STATE_A_SUSPEND; | |
837 | musb->is_active = is_otg_enabled(musb) | |
838 | && musb->xceiv.host->b_hnp_enable; | |
839 | break; | |
840 | case OTG_STATE_B_HOST: | |
841 | /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ | |
842 | DBG(1, "REVISIT: SUSPEND as B_HOST\n"); | |
843 | break; | |
844 | default: | |
845 | /* "should not happen" */ | |
846 | musb->is_active = 0; | |
847 | break; | |
848 | } | |
849 | schedule_work(&musb->irq_work); | |
850 | } | |
851 | ||
852 | ||
853 | return handled; | |
854 | } | |
855 | ||
856 | /*-------------------------------------------------------------------------*/ | |
857 | ||
858 | /* | |
859 | * Program the HDRC to start (enable interrupts, dma, etc.). | |
860 | */ | |
861 | void musb_start(struct musb *musb) | |
862 | { | |
863 | void __iomem *regs = musb->mregs; | |
864 | u8 devctl = musb_readb(regs, MUSB_DEVCTL); | |
865 | ||
866 | DBG(2, "<== devctl %02x\n", devctl); | |
867 | ||
868 | /* Set INT enable registers, enable interrupts */ | |
869 | musb_writew(regs, MUSB_INTRTXE, musb->epmask); | |
870 | musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); | |
871 | musb_writeb(regs, MUSB_INTRUSBE, 0xf7); | |
872 | ||
873 | musb_writeb(regs, MUSB_TESTMODE, 0); | |
874 | ||
875 | /* put into basic highspeed mode and start session */ | |
876 | musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE | |
877 | | MUSB_POWER_SOFTCONN | |
878 | | MUSB_POWER_HSENAB | |
879 | /* ENSUSPEND wedges tusb */ | |
880 | /* | MUSB_POWER_ENSUSPEND */ | |
881 | ); | |
882 | ||
883 | musb->is_active = 0; | |
884 | devctl = musb_readb(regs, MUSB_DEVCTL); | |
885 | devctl &= ~MUSB_DEVCTL_SESSION; | |
886 | ||
887 | if (is_otg_enabled(musb)) { | |
888 | /* session started after: | |
889 | * (a) ID-grounded irq, host mode; | |
890 | * (b) vbus present/connect IRQ, peripheral mode; | |
891 | * (c) peripheral initiates, using SRP | |
892 | */ | |
893 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
894 | musb->is_active = 1; | |
895 | else | |
896 | devctl |= MUSB_DEVCTL_SESSION; | |
897 | ||
898 | } else if (is_host_enabled(musb)) { | |
899 | /* assume ID pin is hard-wired to ground */ | |
900 | devctl |= MUSB_DEVCTL_SESSION; | |
901 | ||
902 | } else /* peripheral is enabled */ { | |
903 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
904 | musb->is_active = 1; | |
905 | } | |
906 | musb_platform_enable(musb); | |
907 | musb_writeb(regs, MUSB_DEVCTL, devctl); | |
908 | } | |
909 | ||
910 | ||
911 | static void musb_generic_disable(struct musb *musb) | |
912 | { | |
913 | void __iomem *mbase = musb->mregs; | |
914 | u16 temp; | |
915 | ||
916 | /* disable interrupts */ | |
917 | musb_writeb(mbase, MUSB_INTRUSBE, 0); | |
918 | musb_writew(mbase, MUSB_INTRTXE, 0); | |
919 | musb_writew(mbase, MUSB_INTRRXE, 0); | |
920 | ||
921 | /* off */ | |
922 | musb_writeb(mbase, MUSB_DEVCTL, 0); | |
923 | ||
924 | /* flush pending interrupts */ | |
925 | temp = musb_readb(mbase, MUSB_INTRUSB); | |
926 | temp = musb_readw(mbase, MUSB_INTRTX); | |
927 | temp = musb_readw(mbase, MUSB_INTRRX); | |
928 | ||
929 | } | |
930 | ||
931 | /* | |
932 | * Make the HDRC stop (disable interrupts, etc.); | |
933 | * reversible by musb_start | |
934 | * called on gadget driver unregister | |
935 | * with controller locked, irqs blocked | |
936 | * acts as a NOP unless some role activated the hardware | |
937 | */ | |
938 | void musb_stop(struct musb *musb) | |
939 | { | |
940 | /* stop IRQs, timers, ... */ | |
941 | musb_platform_disable(musb); | |
942 | musb_generic_disable(musb); | |
943 | DBG(3, "HDRC disabled\n"); | |
944 | ||
945 | /* FIXME | |
946 | * - mark host and/or peripheral drivers unusable/inactive | |
947 | * - disable DMA (and enable it in HdrcStart) | |
948 | * - make sure we can musb_start() after musb_stop(); with | |
949 | * OTG mode, gadget driver module rmmod/modprobe cycles that | |
950 | * - ... | |
951 | */ | |
952 | musb_platform_try_idle(musb, 0); | |
953 | } | |
954 | ||
955 | static void musb_shutdown(struct platform_device *pdev) | |
956 | { | |
957 | struct musb *musb = dev_to_musb(&pdev->dev); | |
958 | unsigned long flags; | |
959 | ||
960 | spin_lock_irqsave(&musb->lock, flags); | |
961 | musb_platform_disable(musb); | |
962 | musb_generic_disable(musb); | |
963 | if (musb->clock) { | |
964 | clk_put(musb->clock); | |
965 | musb->clock = NULL; | |
966 | } | |
967 | spin_unlock_irqrestore(&musb->lock, flags); | |
968 | ||
969 | /* FIXME power down */ | |
970 | } | |
971 | ||
972 | ||
973 | /*-------------------------------------------------------------------------*/ | |
974 | ||
975 | /* | |
976 | * The silicon either has hard-wired endpoint configurations, or else | |
977 | * "dynamic fifo" sizing. The driver has support for both, though at this | |
c767c1c6 DB |
978 | * writing only the dynamic sizing is very well tested. Since we switched |
979 | * away from compile-time hardware parameters, we can no longer rely on | |
980 | * dead code elimination to leave only the relevant one in the object file. | |
550a7375 FB |
981 | * |
982 | * We don't currently use dynamic fifo setup capability to do anything | |
983 | * more than selecting one of a bunch of predefined configurations. | |
984 | */ | |
550a7375 FB |
985 | #if defined(CONFIG_USB_TUSB6010) || \ |
986 | defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) | |
987 | static ushort __initdata fifo_mode = 4; | |
988 | #else | |
989 | static ushort __initdata fifo_mode = 2; | |
990 | #endif | |
991 | ||
992 | /* "modprobe ... fifo_mode=1" etc */ | |
993 | module_param(fifo_mode, ushort, 0); | |
994 | MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); | |
995 | ||
996 | ||
550a7375 FB |
997 | enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed)); |
998 | enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed)); | |
999 | ||
1000 | struct fifo_cfg { | |
1001 | u8 hw_ep_num; | |
1002 | enum fifo_style style; | |
1003 | enum buf_mode mode; | |
1004 | u16 maxpacket; | |
1005 | }; | |
1006 | ||
1007 | /* | |
1008 | * tables defining fifo_mode values. define more if you like. | |
1009 | * for host side, make sure both halves of ep1 are set up. | |
1010 | */ | |
1011 | ||
1012 | /* mode 0 - fits in 2KB */ | |
1013 | static struct fifo_cfg __initdata mode_0_cfg[] = { | |
1014 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, | |
1015 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1016 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1017 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1018 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1019 | }; | |
1020 | ||
1021 | /* mode 1 - fits in 4KB */ | |
1022 | static struct fifo_cfg __initdata mode_1_cfg[] = { | |
1023 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1024 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1025 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1026 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1027 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1028 | }; | |
1029 | ||
1030 | /* mode 2 - fits in 4KB */ | |
1031 | static struct fifo_cfg __initdata mode_2_cfg[] = { | |
1032 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, | |
1033 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1034 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1035 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1036 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1037 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1038 | }; | |
1039 | ||
1040 | /* mode 3 - fits in 4KB */ | |
1041 | static struct fifo_cfg __initdata mode_3_cfg[] = { | |
1042 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1043 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1044 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1045 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1046 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1047 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1048 | }; | |
1049 | ||
1050 | /* mode 4 - fits in 16KB */ | |
1051 | static struct fifo_cfg __initdata mode_4_cfg[] = { | |
1052 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, | |
1053 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1054 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1055 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1056 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1057 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1058 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1059 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1060 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1061 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1062 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, | |
1063 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, | |
1064 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, | |
1065 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, | |
1066 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, | |
1067 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, | |
1068 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, | |
1069 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, | |
1070 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, }, | |
1071 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, }, | |
1072 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, }, | |
1073 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, }, | |
1074 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, }, | |
1075 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, }, | |
1076 | { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, }, | |
1077 | { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, }, | |
1078 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1079 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1080 | }; | |
1081 | ||
1082 | ||
1083 | /* | |
1084 | * configure a fifo; for non-shared endpoints, this may be called | |
1085 | * once for a tx fifo and once for an rx fifo. | |
1086 | * | |
1087 | * returns negative errno or offset for next fifo. | |
1088 | */ | |
1089 | static int __init | |
1090 | fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, | |
1091 | const struct fifo_cfg *cfg, u16 offset) | |
1092 | { | |
1093 | void __iomem *mbase = musb->mregs; | |
1094 | int size = 0; | |
1095 | u16 maxpacket = cfg->maxpacket; | |
1096 | u16 c_off = offset >> 3; | |
1097 | u8 c_size; | |
1098 | ||
1099 | /* expect hw_ep has already been zero-initialized */ | |
1100 | ||
1101 | size = ffs(max(maxpacket, (u16) 8)) - 1; | |
1102 | maxpacket = 1 << size; | |
1103 | ||
1104 | c_size = size - 3; | |
1105 | if (cfg->mode == BUF_DOUBLE) { | |
ca6d1b13 FB |
1106 | if ((offset + (maxpacket << 1)) > |
1107 | (1 << (musb->config->ram_bits + 2))) | |
550a7375 FB |
1108 | return -EMSGSIZE; |
1109 | c_size |= MUSB_FIFOSZ_DPB; | |
1110 | } else { | |
ca6d1b13 | 1111 | if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) |
550a7375 FB |
1112 | return -EMSGSIZE; |
1113 | } | |
1114 | ||
1115 | /* configure the FIFO */ | |
1116 | musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); | |
1117 | ||
1118 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
1119 | /* EP0 reserved endpoint for control, bidirectional; | |
1120 | * EP1 reserved for bulk, two unidirection halves. | |
1121 | */ | |
1122 | if (hw_ep->epnum == 1) | |
1123 | musb->bulk_ep = hw_ep; | |
1124 | /* REVISIT error check: be sure ep0 can both rx and tx ... */ | |
1125 | #endif | |
1126 | switch (cfg->style) { | |
1127 | case FIFO_TX: | |
c6cf8b00 BW |
1128 | musb_write_txfifosz(mbase, c_size); |
1129 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1130 | hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1131 | hw_ep->max_packet_sz_tx = maxpacket; | |
1132 | break; | |
1133 | case FIFO_RX: | |
c6cf8b00 BW |
1134 | musb_write_rxfifosz(mbase, c_size); |
1135 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1136 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1137 | hw_ep->max_packet_sz_rx = maxpacket; | |
1138 | break; | |
1139 | case FIFO_RXTX: | |
c6cf8b00 BW |
1140 | musb_write_txfifosz(mbase, c_size); |
1141 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1142 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1143 | hw_ep->max_packet_sz_rx = maxpacket; | |
1144 | ||
c6cf8b00 BW |
1145 | musb_write_rxfifosz(mbase, c_size); |
1146 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1147 | hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; |
1148 | hw_ep->max_packet_sz_tx = maxpacket; | |
1149 | ||
1150 | hw_ep->is_shared_fifo = true; | |
1151 | break; | |
1152 | } | |
1153 | ||
1154 | /* NOTE rx and tx endpoint irqs aren't managed separately, | |
1155 | * which happens to be ok | |
1156 | */ | |
1157 | musb->epmask |= (1 << hw_ep->epnum); | |
1158 | ||
1159 | return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); | |
1160 | } | |
1161 | ||
1162 | static struct fifo_cfg __initdata ep0_cfg = { | |
1163 | .style = FIFO_RXTX, .maxpacket = 64, | |
1164 | }; | |
1165 | ||
1166 | static int __init ep_config_from_table(struct musb *musb) | |
1167 | { | |
1168 | const struct fifo_cfg *cfg; | |
1169 | unsigned i, n; | |
1170 | int offset; | |
1171 | struct musb_hw_ep *hw_ep = musb->endpoints; | |
1172 | ||
1173 | switch (fifo_mode) { | |
1174 | default: | |
1175 | fifo_mode = 0; | |
1176 | /* FALLTHROUGH */ | |
1177 | case 0: | |
1178 | cfg = mode_0_cfg; | |
1179 | n = ARRAY_SIZE(mode_0_cfg); | |
1180 | break; | |
1181 | case 1: | |
1182 | cfg = mode_1_cfg; | |
1183 | n = ARRAY_SIZE(mode_1_cfg); | |
1184 | break; | |
1185 | case 2: | |
1186 | cfg = mode_2_cfg; | |
1187 | n = ARRAY_SIZE(mode_2_cfg); | |
1188 | break; | |
1189 | case 3: | |
1190 | cfg = mode_3_cfg; | |
1191 | n = ARRAY_SIZE(mode_3_cfg); | |
1192 | break; | |
1193 | case 4: | |
1194 | cfg = mode_4_cfg; | |
1195 | n = ARRAY_SIZE(mode_4_cfg); | |
1196 | break; | |
1197 | } | |
1198 | ||
1199 | printk(KERN_DEBUG "%s: setup fifo_mode %d\n", | |
1200 | musb_driver_name, fifo_mode); | |
1201 | ||
1202 | ||
1203 | offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); | |
1204 | /* assert(offset > 0) */ | |
1205 | ||
1206 | /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would | |
ca6d1b13 | 1207 | * be better than static musb->config->num_eps and DYN_FIFO_SIZE... |
550a7375 FB |
1208 | */ |
1209 | ||
1210 | for (i = 0; i < n; i++) { | |
1211 | u8 epn = cfg->hw_ep_num; | |
1212 | ||
ca6d1b13 | 1213 | if (epn >= musb->config->num_eps) { |
550a7375 FB |
1214 | pr_debug("%s: invalid ep %d\n", |
1215 | musb_driver_name, epn); | |
bb1c9ef1 | 1216 | return -EINVAL; |
550a7375 FB |
1217 | } |
1218 | offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); | |
1219 | if (offset < 0) { | |
1220 | pr_debug("%s: mem overrun, ep %d\n", | |
1221 | musb_driver_name, epn); | |
1222 | return -EINVAL; | |
1223 | } | |
1224 | epn++; | |
1225 | musb->nr_endpoints = max(epn, musb->nr_endpoints); | |
1226 | } | |
1227 | ||
1228 | printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", | |
1229 | musb_driver_name, | |
ca6d1b13 FB |
1230 | n + 1, musb->config->num_eps * 2 - 1, |
1231 | offset, (1 << (musb->config->ram_bits + 2))); | |
550a7375 FB |
1232 | |
1233 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
1234 | if (!musb->bulk_ep) { | |
1235 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1236 | return -EINVAL; | |
1237 | } | |
1238 | #endif | |
1239 | ||
1240 | return 0; | |
1241 | } | |
1242 | ||
1243 | ||
1244 | /* | |
1245 | * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false | |
1246 | * @param musb the controller | |
1247 | */ | |
1248 | static int __init ep_config_from_hw(struct musb *musb) | |
1249 | { | |
c6cf8b00 | 1250 | u8 epnum = 0; |
550a7375 FB |
1251 | struct musb_hw_ep *hw_ep; |
1252 | void *mbase = musb->mregs; | |
c6cf8b00 | 1253 | int ret = 0; |
550a7375 FB |
1254 | |
1255 | DBG(2, "<== static silicon ep config\n"); | |
1256 | ||
1257 | /* FIXME pick up ep0 maxpacket size */ | |
1258 | ||
ca6d1b13 | 1259 | for (epnum = 1; epnum < musb->config->num_eps; epnum++) { |
550a7375 FB |
1260 | musb_ep_select(mbase, epnum); |
1261 | hw_ep = musb->endpoints + epnum; | |
1262 | ||
c6cf8b00 BW |
1263 | ret = musb_read_fifosize(musb, hw_ep, epnum); |
1264 | if (ret < 0) | |
550a7375 | 1265 | break; |
550a7375 FB |
1266 | |
1267 | /* FIXME set up hw_ep->{rx,tx}_double_buffered */ | |
1268 | ||
1269 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
1270 | /* pick an RX/TX endpoint for bulk */ | |
1271 | if (hw_ep->max_packet_sz_tx < 512 | |
1272 | || hw_ep->max_packet_sz_rx < 512) | |
1273 | continue; | |
1274 | ||
1275 | /* REVISIT: this algorithm is lazy, we should at least | |
1276 | * try to pick a double buffered endpoint. | |
1277 | */ | |
1278 | if (musb->bulk_ep) | |
1279 | continue; | |
1280 | musb->bulk_ep = hw_ep; | |
1281 | #endif | |
1282 | } | |
1283 | ||
1284 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
1285 | if (!musb->bulk_ep) { | |
1286 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1287 | return -EINVAL; | |
1288 | } | |
1289 | #endif | |
1290 | ||
1291 | return 0; | |
1292 | } | |
1293 | ||
1294 | enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; | |
1295 | ||
1296 | /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; | |
1297 | * configure endpoints, or take their config from silicon | |
1298 | */ | |
1299 | static int __init musb_core_init(u16 musb_type, struct musb *musb) | |
1300 | { | |
1301 | #ifdef MUSB_AHB_ID | |
1302 | u32 data; | |
1303 | #endif | |
1304 | u8 reg; | |
1305 | char *type; | |
1306 | u16 hwvers, rev_major, rev_minor; | |
1307 | char aInfo[78], aRevision[32], aDate[12]; | |
1308 | void __iomem *mbase = musb->mregs; | |
1309 | int status = 0; | |
1310 | int i; | |
1311 | ||
1312 | /* log core options (read using indexed model) */ | |
1313 | musb_ep_select(mbase, 0); | |
c6cf8b00 | 1314 | reg = musb_read_configdata(mbase); |
550a7375 FB |
1315 | |
1316 | strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); | |
1317 | if (reg & MUSB_CONFIGDATA_DYNFIFO) | |
1318 | strcat(aInfo, ", dyn FIFOs"); | |
1319 | if (reg & MUSB_CONFIGDATA_MPRXE) { | |
1320 | strcat(aInfo, ", bulk combine"); | |
1321 | #ifdef C_MP_RX | |
1322 | musb->bulk_combine = true; | |
1323 | #else | |
1324 | strcat(aInfo, " (X)"); /* no driver support */ | |
1325 | #endif | |
1326 | } | |
1327 | if (reg & MUSB_CONFIGDATA_MPTXE) { | |
1328 | strcat(aInfo, ", bulk split"); | |
1329 | #ifdef C_MP_TX | |
1330 | musb->bulk_split = true; | |
1331 | #else | |
1332 | strcat(aInfo, " (X)"); /* no driver support */ | |
1333 | #endif | |
1334 | } | |
1335 | if (reg & MUSB_CONFIGDATA_HBRXE) { | |
1336 | strcat(aInfo, ", HB-ISO Rx"); | |
1337 | strcat(aInfo, " (X)"); /* no driver support */ | |
1338 | } | |
1339 | if (reg & MUSB_CONFIGDATA_HBTXE) { | |
1340 | strcat(aInfo, ", HB-ISO Tx"); | |
1341 | strcat(aInfo, " (X)"); /* no driver support */ | |
1342 | } | |
1343 | if (reg & MUSB_CONFIGDATA_SOFTCONE) | |
1344 | strcat(aInfo, ", SoftConn"); | |
1345 | ||
1346 | printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", | |
1347 | musb_driver_name, reg, aInfo); | |
1348 | ||
1349 | #ifdef MUSB_AHB_ID | |
1350 | data = musb_readl(mbase, 0x404); | |
1351 | sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff), | |
1352 | (data >> 16) & 0xff, (data >> 24) & 0xff); | |
1353 | /* FIXME ID2 and ID3 are unused */ | |
1354 | data = musb_readl(mbase, 0x408); | |
1355 | printk(KERN_DEBUG "ID2=%lx\n", (long unsigned)data); | |
1356 | data = musb_readl(mbase, 0x40c); | |
1357 | printk(KERN_DEBUG "ID3=%lx\n", (long unsigned)data); | |
1358 | reg = musb_readb(mbase, 0x400); | |
1359 | musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC; | |
1360 | #else | |
1361 | aDate[0] = 0; | |
1362 | #endif | |
1363 | if (MUSB_CONTROLLER_MHDRC == musb_type) { | |
1364 | musb->is_multipoint = 1; | |
1365 | type = "M"; | |
1366 | } else { | |
1367 | musb->is_multipoint = 0; | |
1368 | type = ""; | |
1369 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
1370 | #ifndef CONFIG_USB_OTG_BLACKLIST_HUB | |
1371 | printk(KERN_ERR | |
1372 | "%s: kernel must blacklist external hubs\n", | |
1373 | musb_driver_name); | |
1374 | #endif | |
1375 | #endif | |
1376 | } | |
1377 | ||
1378 | /* log release info */ | |
c6cf8b00 | 1379 | hwvers = musb_read_hwvers(mbase); |
550a7375 FB |
1380 | rev_major = (hwvers >> 10) & 0x1f; |
1381 | rev_minor = hwvers & 0x3ff; | |
1382 | snprintf(aRevision, 32, "%d.%d%s", rev_major, | |
1383 | rev_minor, (hwvers & 0x8000) ? "RC" : ""); | |
1384 | printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", | |
1385 | musb_driver_name, type, aRevision, aDate); | |
1386 | ||
1387 | /* configure ep0 */ | |
c6cf8b00 | 1388 | musb_configure_ep0(musb); |
550a7375 FB |
1389 | |
1390 | /* discover endpoint configuration */ | |
1391 | musb->nr_endpoints = 1; | |
1392 | musb->epmask = 1; | |
1393 | ||
1394 | if (reg & MUSB_CONFIGDATA_DYNFIFO) { | |
ca6d1b13 | 1395 | if (musb->config->dyn_fifo) |
550a7375 FB |
1396 | status = ep_config_from_table(musb); |
1397 | else { | |
1398 | ERR("reconfigure software for Dynamic FIFOs\n"); | |
1399 | status = -ENODEV; | |
1400 | } | |
1401 | } else { | |
ca6d1b13 | 1402 | if (!musb->config->dyn_fifo) |
550a7375 FB |
1403 | status = ep_config_from_hw(musb); |
1404 | else { | |
1405 | ERR("reconfigure software for static FIFOs\n"); | |
1406 | return -ENODEV; | |
1407 | } | |
1408 | } | |
1409 | ||
1410 | if (status < 0) | |
1411 | return status; | |
1412 | ||
1413 | /* finish init, and print endpoint config */ | |
1414 | for (i = 0; i < musb->nr_endpoints; i++) { | |
1415 | struct musb_hw_ep *hw_ep = musb->endpoints + i; | |
1416 | ||
1417 | hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; | |
1418 | #ifdef CONFIG_USB_TUSB6010 | |
1419 | hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); | |
1420 | hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); | |
1421 | hw_ep->fifo_sync_va = | |
1422 | musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); | |
1423 | ||
1424 | if (i == 0) | |
1425 | hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; | |
1426 | else | |
1427 | hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); | |
1428 | #endif | |
1429 | ||
1430 | hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; | |
1431 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
c6cf8b00 | 1432 | hw_ep->target_regs = musb_read_target_reg_base(i, mbase); |
550a7375 FB |
1433 | hw_ep->rx_reinit = 1; |
1434 | hw_ep->tx_reinit = 1; | |
1435 | #endif | |
1436 | ||
1437 | if (hw_ep->max_packet_sz_tx) { | |
1438 | printk(KERN_DEBUG | |
1439 | "%s: hw_ep %d%s, %smax %d\n", | |
1440 | musb_driver_name, i, | |
1441 | hw_ep->is_shared_fifo ? "shared" : "tx", | |
1442 | hw_ep->tx_double_buffered | |
1443 | ? "doublebuffer, " : "", | |
1444 | hw_ep->max_packet_sz_tx); | |
1445 | } | |
1446 | if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { | |
1447 | printk(KERN_DEBUG | |
1448 | "%s: hw_ep %d%s, %smax %d\n", | |
1449 | musb_driver_name, i, | |
1450 | "rx", | |
1451 | hw_ep->rx_double_buffered | |
1452 | ? "doublebuffer, " : "", | |
1453 | hw_ep->max_packet_sz_rx); | |
1454 | } | |
1455 | if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) | |
1456 | DBG(1, "hw_ep %d not configured\n", i); | |
1457 | } | |
1458 | ||
1459 | return 0; | |
1460 | } | |
1461 | ||
1462 | /*-------------------------------------------------------------------------*/ | |
1463 | ||
1464 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) | |
1465 | ||
1466 | static irqreturn_t generic_interrupt(int irq, void *__hci) | |
1467 | { | |
1468 | unsigned long flags; | |
1469 | irqreturn_t retval = IRQ_NONE; | |
1470 | struct musb *musb = __hci; | |
1471 | ||
1472 | spin_lock_irqsave(&musb->lock, flags); | |
1473 | ||
1474 | musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); | |
1475 | musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); | |
1476 | musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); | |
1477 | ||
1478 | if (musb->int_usb || musb->int_tx || musb->int_rx) | |
1479 | retval = musb_interrupt(musb); | |
1480 | ||
1481 | spin_unlock_irqrestore(&musb->lock, flags); | |
1482 | ||
1483 | /* REVISIT we sometimes get spurious IRQs on g_ep0 | |
1484 | * not clear why... | |
1485 | */ | |
1486 | if (retval != IRQ_HANDLED) | |
1487 | DBG(5, "spurious?\n"); | |
1488 | ||
1489 | return IRQ_HANDLED; | |
1490 | } | |
1491 | ||
1492 | #else | |
1493 | #define generic_interrupt NULL | |
1494 | #endif | |
1495 | ||
1496 | /* | |
1497 | * handle all the irqs defined by the HDRC core. for now we expect: other | |
1498 | * irq sources (phy, dma, etc) will be handled first, musb->int_* values | |
1499 | * will be assigned, and the irq will already have been acked. | |
1500 | * | |
1501 | * called in irq context with spinlock held, irqs blocked | |
1502 | */ | |
1503 | irqreturn_t musb_interrupt(struct musb *musb) | |
1504 | { | |
1505 | irqreturn_t retval = IRQ_NONE; | |
1506 | u8 devctl, power; | |
1507 | int ep_num; | |
1508 | u32 reg; | |
1509 | ||
1510 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1511 | power = musb_readb(musb->mregs, MUSB_POWER); | |
1512 | ||
1513 | DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n", | |
1514 | (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", | |
1515 | musb->int_usb, musb->int_tx, musb->int_rx); | |
1516 | ||
1517 | /* the core can interrupt us for multiple reasons; docs have | |
1518 | * a generic interrupt flowchart to follow | |
1519 | */ | |
1520 | if (musb->int_usb & STAGE0_MASK) | |
1521 | retval |= musb_stage0_irq(musb, musb->int_usb, | |
1522 | devctl, power); | |
1523 | ||
1524 | /* "stage 1" is handling endpoint irqs */ | |
1525 | ||
1526 | /* handle endpoint 0 first */ | |
1527 | if (musb->int_tx & 1) { | |
1528 | if (devctl & MUSB_DEVCTL_HM) | |
1529 | retval |= musb_h_ep0_irq(musb); | |
1530 | else | |
1531 | retval |= musb_g_ep0_irq(musb); | |
1532 | } | |
1533 | ||
1534 | /* RX on endpoints 1-15 */ | |
1535 | reg = musb->int_rx >> 1; | |
1536 | ep_num = 1; | |
1537 | while (reg) { | |
1538 | if (reg & 1) { | |
1539 | /* musb_ep_select(musb->mregs, ep_num); */ | |
1540 | /* REVISIT just retval = ep->rx_irq(...) */ | |
1541 | retval = IRQ_HANDLED; | |
1542 | if (devctl & MUSB_DEVCTL_HM) { | |
1543 | if (is_host_capable()) | |
1544 | musb_host_rx(musb, ep_num); | |
1545 | } else { | |
1546 | if (is_peripheral_capable()) | |
1547 | musb_g_rx(musb, ep_num); | |
1548 | } | |
1549 | } | |
1550 | ||
1551 | reg >>= 1; | |
1552 | ep_num++; | |
1553 | } | |
1554 | ||
1555 | /* TX on endpoints 1-15 */ | |
1556 | reg = musb->int_tx >> 1; | |
1557 | ep_num = 1; | |
1558 | while (reg) { | |
1559 | if (reg & 1) { | |
1560 | /* musb_ep_select(musb->mregs, ep_num); */ | |
1561 | /* REVISIT just retval |= ep->tx_irq(...) */ | |
1562 | retval = IRQ_HANDLED; | |
1563 | if (devctl & MUSB_DEVCTL_HM) { | |
1564 | if (is_host_capable()) | |
1565 | musb_host_tx(musb, ep_num); | |
1566 | } else { | |
1567 | if (is_peripheral_capable()) | |
1568 | musb_g_tx(musb, ep_num); | |
1569 | } | |
1570 | } | |
1571 | reg >>= 1; | |
1572 | ep_num++; | |
1573 | } | |
1574 | ||
1575 | /* finish handling "global" interrupts after handling fifos */ | |
1576 | if (musb->int_usb) | |
1577 | retval |= musb_stage2_irq(musb, | |
1578 | musb->int_usb, devctl, power); | |
1579 | ||
1580 | return retval; | |
1581 | } | |
1582 | ||
1583 | ||
1584 | #ifndef CONFIG_MUSB_PIO_ONLY | |
1585 | static int __initdata use_dma = 1; | |
1586 | ||
1587 | /* "modprobe ... use_dma=0" etc */ | |
1588 | module_param(use_dma, bool, 0); | |
1589 | MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); | |
1590 | ||
1591 | void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) | |
1592 | { | |
1593 | u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1594 | ||
1595 | /* called with controller lock already held */ | |
1596 | ||
1597 | if (!epnum) { | |
1598 | #ifndef CONFIG_USB_TUSB_OMAP_DMA | |
1599 | if (!is_cppi_enabled()) { | |
1600 | /* endpoint 0 */ | |
1601 | if (devctl & MUSB_DEVCTL_HM) | |
1602 | musb_h_ep0_irq(musb); | |
1603 | else | |
1604 | musb_g_ep0_irq(musb); | |
1605 | } | |
1606 | #endif | |
1607 | } else { | |
1608 | /* endpoints 1..15 */ | |
1609 | if (transmit) { | |
1610 | if (devctl & MUSB_DEVCTL_HM) { | |
1611 | if (is_host_capable()) | |
1612 | musb_host_tx(musb, epnum); | |
1613 | } else { | |
1614 | if (is_peripheral_capable()) | |
1615 | musb_g_tx(musb, epnum); | |
1616 | } | |
1617 | } else { | |
1618 | /* receive */ | |
1619 | if (devctl & MUSB_DEVCTL_HM) { | |
1620 | if (is_host_capable()) | |
1621 | musb_host_rx(musb, epnum); | |
1622 | } else { | |
1623 | if (is_peripheral_capable()) | |
1624 | musb_g_rx(musb, epnum); | |
1625 | } | |
1626 | } | |
1627 | } | |
1628 | } | |
1629 | ||
1630 | #else | |
1631 | #define use_dma 0 | |
1632 | #endif | |
1633 | ||
1634 | /*-------------------------------------------------------------------------*/ | |
1635 | ||
1636 | #ifdef CONFIG_SYSFS | |
1637 | ||
1638 | static ssize_t | |
1639 | musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1640 | { | |
1641 | struct musb *musb = dev_to_musb(dev); | |
1642 | unsigned long flags; | |
1643 | int ret = -EINVAL; | |
1644 | ||
1645 | spin_lock_irqsave(&musb->lock, flags); | |
1646 | ret = sprintf(buf, "%s\n", otg_state_string(musb)); | |
1647 | spin_unlock_irqrestore(&musb->lock, flags); | |
1648 | ||
1649 | return ret; | |
1650 | } | |
1651 | ||
1652 | static ssize_t | |
1653 | musb_mode_store(struct device *dev, struct device_attribute *attr, | |
1654 | const char *buf, size_t n) | |
1655 | { | |
1656 | struct musb *musb = dev_to_musb(dev); | |
1657 | unsigned long flags; | |
96a274d1 | 1658 | int status; |
550a7375 FB |
1659 | |
1660 | spin_lock_irqsave(&musb->lock, flags); | |
96a274d1 DB |
1661 | if (sysfs_streq(buf, "host")) |
1662 | status = musb_platform_set_mode(musb, MUSB_HOST); | |
1663 | else if (sysfs_streq(buf, "peripheral")) | |
1664 | status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); | |
1665 | else if (sysfs_streq(buf, "otg")) | |
1666 | status = musb_platform_set_mode(musb, MUSB_OTG); | |
1667 | else | |
1668 | status = -EINVAL; | |
550a7375 FB |
1669 | spin_unlock_irqrestore(&musb->lock, flags); |
1670 | ||
96a274d1 | 1671 | return (status == 0) ? n : status; |
550a7375 FB |
1672 | } |
1673 | static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); | |
1674 | ||
1675 | static ssize_t | |
1676 | musb_vbus_store(struct device *dev, struct device_attribute *attr, | |
1677 | const char *buf, size_t n) | |
1678 | { | |
1679 | struct musb *musb = dev_to_musb(dev); | |
1680 | unsigned long flags; | |
1681 | unsigned long val; | |
1682 | ||
1683 | if (sscanf(buf, "%lu", &val) < 1) { | |
1684 | printk(KERN_ERR "Invalid VBUS timeout ms value\n"); | |
1685 | return -EINVAL; | |
1686 | } | |
1687 | ||
1688 | spin_lock_irqsave(&musb->lock, flags); | |
1689 | musb->a_wait_bcon = val; | |
1690 | if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON) | |
1691 | musb->is_active = 0; | |
1692 | musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); | |
1693 | spin_unlock_irqrestore(&musb->lock, flags); | |
1694 | ||
1695 | return n; | |
1696 | } | |
1697 | ||
1698 | static ssize_t | |
1699 | musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1700 | { | |
1701 | struct musb *musb = dev_to_musb(dev); | |
1702 | unsigned long flags; | |
1703 | unsigned long val; | |
1704 | int vbus; | |
1705 | ||
1706 | spin_lock_irqsave(&musb->lock, flags); | |
1707 | val = musb->a_wait_bcon; | |
1708 | vbus = musb_platform_get_vbus_status(musb); | |
1709 | spin_unlock_irqrestore(&musb->lock, flags); | |
1710 | ||
1711 | return sprintf(buf, "Vbus %s, timeout %lu\n", | |
1712 | vbus ? "on" : "off", val); | |
1713 | } | |
1714 | static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); | |
1715 | ||
1716 | #ifdef CONFIG_USB_GADGET_MUSB_HDRC | |
1717 | ||
1718 | /* Gadget drivers can't know that a host is connected so they might want | |
1719 | * to start SRP, but users can. This allows userspace to trigger SRP. | |
1720 | */ | |
1721 | static ssize_t | |
1722 | musb_srp_store(struct device *dev, struct device_attribute *attr, | |
1723 | const char *buf, size_t n) | |
1724 | { | |
1725 | struct musb *musb = dev_to_musb(dev); | |
1726 | unsigned short srp; | |
1727 | ||
1728 | if (sscanf(buf, "%hu", &srp) != 1 | |
1729 | || (srp != 1)) { | |
1730 | printk(KERN_ERR "SRP: Value must be 1\n"); | |
1731 | return -EINVAL; | |
1732 | } | |
1733 | ||
1734 | if (srp == 1) | |
1735 | musb_g_wakeup(musb); | |
1736 | ||
1737 | return n; | |
1738 | } | |
1739 | static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); | |
1740 | ||
1741 | #endif /* CONFIG_USB_GADGET_MUSB_HDRC */ | |
1742 | ||
1743 | #endif /* sysfs */ | |
1744 | ||
1745 | /* Only used to provide driver mode change events */ | |
1746 | static void musb_irq_work(struct work_struct *data) | |
1747 | { | |
1748 | struct musb *musb = container_of(data, struct musb, irq_work); | |
1749 | static int old_state; | |
1750 | ||
1751 | if (musb->xceiv.state != old_state) { | |
1752 | old_state = musb->xceiv.state; | |
1753 | sysfs_notify(&musb->controller->kobj, NULL, "mode"); | |
1754 | } | |
1755 | } | |
1756 | ||
1757 | /* -------------------------------------------------------------------------- | |
1758 | * Init support | |
1759 | */ | |
1760 | ||
1761 | static struct musb *__init | |
ca6d1b13 FB |
1762 | allocate_instance(struct device *dev, |
1763 | struct musb_hdrc_config *config, void __iomem *mbase) | |
550a7375 FB |
1764 | { |
1765 | struct musb *musb; | |
1766 | struct musb_hw_ep *ep; | |
1767 | int epnum; | |
1768 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
1769 | struct usb_hcd *hcd; | |
1770 | ||
427c4f33 | 1771 | hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); |
550a7375 FB |
1772 | if (!hcd) |
1773 | return NULL; | |
1774 | /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ | |
1775 | ||
1776 | musb = hcd_to_musb(hcd); | |
1777 | INIT_LIST_HEAD(&musb->control); | |
1778 | INIT_LIST_HEAD(&musb->in_bulk); | |
1779 | INIT_LIST_HEAD(&musb->out_bulk); | |
1780 | ||
1781 | hcd->uses_new_polling = 1; | |
1782 | ||
1783 | musb->vbuserr_retry = VBUSERR_RETRY_COUNT; | |
1784 | #else | |
1785 | musb = kzalloc(sizeof *musb, GFP_KERNEL); | |
1786 | if (!musb) | |
1787 | return NULL; | |
1788 | dev_set_drvdata(dev, musb); | |
1789 | ||
1790 | #endif | |
1791 | ||
1792 | musb->mregs = mbase; | |
1793 | musb->ctrl_base = mbase; | |
1794 | musb->nIrq = -ENODEV; | |
ca6d1b13 | 1795 | musb->config = config; |
02582b92 | 1796 | BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); |
550a7375 | 1797 | for (epnum = 0, ep = musb->endpoints; |
ca6d1b13 | 1798 | epnum < musb->config->num_eps; |
550a7375 | 1799 | epnum++, ep++) { |
550a7375 FB |
1800 | ep->musb = musb; |
1801 | ep->epnum = epnum; | |
1802 | } | |
1803 | ||
1804 | musb->controller = dev; | |
1805 | return musb; | |
1806 | } | |
1807 | ||
1808 | static void musb_free(struct musb *musb) | |
1809 | { | |
1810 | /* this has multiple entry modes. it handles fault cleanup after | |
1811 | * probe(), where things may be partially set up, as well as rmmod | |
1812 | * cleanup after everything's been de-activated. | |
1813 | */ | |
1814 | ||
1815 | #ifdef CONFIG_SYSFS | |
1816 | device_remove_file(musb->controller, &dev_attr_mode); | |
1817 | device_remove_file(musb->controller, &dev_attr_vbus); | |
1818 | #ifdef CONFIG_USB_MUSB_OTG | |
1819 | device_remove_file(musb->controller, &dev_attr_srp); | |
1820 | #endif | |
1821 | #endif | |
1822 | ||
1823 | #ifdef CONFIG_USB_GADGET_MUSB_HDRC | |
1824 | musb_gadget_cleanup(musb); | |
1825 | #endif | |
1826 | ||
97a39896 AKG |
1827 | if (musb->nIrq >= 0) { |
1828 | if (musb->irq_wake) | |
1829 | disable_irq_wake(musb->nIrq); | |
550a7375 FB |
1830 | free_irq(musb->nIrq, musb); |
1831 | } | |
1832 | if (is_dma_capable() && musb->dma_controller) { | |
1833 | struct dma_controller *c = musb->dma_controller; | |
1834 | ||
1835 | (void) c->stop(c); | |
1836 | dma_controller_destroy(c); | |
1837 | } | |
1838 | ||
1839 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
1840 | musb_platform_exit(musb); | |
1841 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
1842 | ||
1843 | if (musb->clock) { | |
1844 | clk_disable(musb->clock); | |
1845 | clk_put(musb->clock); | |
1846 | } | |
1847 | ||
1848 | #ifdef CONFIG_USB_MUSB_OTG | |
1849 | put_device(musb->xceiv.dev); | |
1850 | #endif | |
1851 | ||
1852 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
1853 | usb_put_hcd(musb_to_hcd(musb)); | |
1854 | #else | |
1855 | kfree(musb); | |
1856 | #endif | |
1857 | } | |
1858 | ||
1859 | /* | |
1860 | * Perform generic per-controller initialization. | |
1861 | * | |
1862 | * @pDevice: the controller (already clocked, etc) | |
1863 | * @nIrq: irq | |
1864 | * @mregs: virtual address of controller registers, | |
1865 | * not yet corrected for platform-specific offsets | |
1866 | */ | |
1867 | static int __init | |
1868 | musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) | |
1869 | { | |
1870 | int status; | |
1871 | struct musb *musb; | |
1872 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
1873 | ||
1874 | /* The driver might handle more features than the board; OK. | |
1875 | * Fail when the board needs a feature that's not enabled. | |
1876 | */ | |
1877 | if (!plat) { | |
1878 | dev_dbg(dev, "no platform_data?\n"); | |
1879 | return -ENODEV; | |
1880 | } | |
1881 | switch (plat->mode) { | |
1882 | case MUSB_HOST: | |
1883 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
1884 | break; | |
1885 | #else | |
1886 | goto bad_config; | |
1887 | #endif | |
1888 | case MUSB_PERIPHERAL: | |
1889 | #ifdef CONFIG_USB_GADGET_MUSB_HDRC | |
1890 | break; | |
1891 | #else | |
1892 | goto bad_config; | |
1893 | #endif | |
1894 | case MUSB_OTG: | |
1895 | #ifdef CONFIG_USB_MUSB_OTG | |
1896 | break; | |
1897 | #else | |
1898 | bad_config: | |
1899 | #endif | |
1900 | default: | |
1901 | dev_err(dev, "incompatible Kconfig role setting\n"); | |
1902 | return -EINVAL; | |
1903 | } | |
1904 | ||
1905 | /* allocate */ | |
ca6d1b13 | 1906 | musb = allocate_instance(dev, plat->config, ctrl); |
550a7375 FB |
1907 | if (!musb) |
1908 | return -ENOMEM; | |
1909 | ||
1910 | spin_lock_init(&musb->lock); | |
1911 | musb->board_mode = plat->mode; | |
1912 | musb->board_set_power = plat->set_power; | |
1913 | musb->set_clock = plat->set_clock; | |
1914 | musb->min_power = plat->min_power; | |
1915 | ||
1916 | /* Clock usage is chip-specific ... functional clock (DaVinci, | |
1917 | * OMAP2430), or PHY ref (some TUSB6010 boards). All this core | |
1918 | * code does is make sure a clock handle is available; platform | |
1919 | * code manages it during start/stop and suspend/resume. | |
1920 | */ | |
1921 | if (plat->clock) { | |
1922 | musb->clock = clk_get(dev, plat->clock); | |
1923 | if (IS_ERR(musb->clock)) { | |
1924 | status = PTR_ERR(musb->clock); | |
1925 | musb->clock = NULL; | |
1926 | goto fail; | |
1927 | } | |
1928 | } | |
1929 | ||
1930 | /* assume vbus is off */ | |
1931 | ||
1932 | /* platform adjusts musb->mregs and musb->isr if needed, | |
1933 | * and activates clocks | |
1934 | */ | |
1935 | musb->isr = generic_interrupt; | |
1936 | status = musb_platform_init(musb); | |
1937 | ||
1938 | if (status < 0) | |
1939 | goto fail; | |
1940 | if (!musb->isr) { | |
1941 | status = -ENODEV; | |
1942 | goto fail2; | |
1943 | } | |
1944 | ||
1945 | #ifndef CONFIG_MUSB_PIO_ONLY | |
1946 | if (use_dma && dev->dma_mask) { | |
1947 | struct dma_controller *c; | |
1948 | ||
1949 | c = dma_controller_create(musb, musb->mregs); | |
1950 | musb->dma_controller = c; | |
1951 | if (c) | |
1952 | (void) c->start(c); | |
1953 | } | |
1954 | #endif | |
1955 | /* ideally this would be abstracted in platform setup */ | |
1956 | if (!is_dma_capable() || !musb->dma_controller) | |
1957 | dev->dma_mask = NULL; | |
1958 | ||
1959 | /* be sure interrupts are disabled before connecting ISR */ | |
1960 | musb_platform_disable(musb); | |
1961 | musb_generic_disable(musb); | |
1962 | ||
1963 | /* setup musb parts of the core (especially endpoints) */ | |
ca6d1b13 | 1964 | status = musb_core_init(plat->config->multipoint |
550a7375 FB |
1965 | ? MUSB_CONTROLLER_MHDRC |
1966 | : MUSB_CONTROLLER_HDRC, musb); | |
1967 | if (status < 0) | |
1968 | goto fail2; | |
1969 | ||
1970 | /* Init IRQ workqueue before request_irq */ | |
1971 | INIT_WORK(&musb->irq_work, musb_irq_work); | |
1972 | ||
1973 | /* attach to the IRQ */ | |
427c4f33 | 1974 | if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { |
550a7375 FB |
1975 | dev_err(dev, "request_irq %d failed!\n", nIrq); |
1976 | status = -ENODEV; | |
1977 | goto fail2; | |
1978 | } | |
1979 | musb->nIrq = nIrq; | |
1980 | /* FIXME this handles wakeup irqs wrong */ | |
c48a5155 FB |
1981 | if (enable_irq_wake(nIrq) == 0) { |
1982 | musb->irq_wake = 1; | |
550a7375 | 1983 | device_init_wakeup(dev, 1); |
c48a5155 FB |
1984 | } else { |
1985 | musb->irq_wake = 0; | |
1986 | } | |
550a7375 FB |
1987 | |
1988 | pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n", | |
1989 | musb_driver_name, | |
1990 | ({char *s; | |
1991 | switch (musb->board_mode) { | |
1992 | case MUSB_HOST: s = "Host"; break; | |
1993 | case MUSB_PERIPHERAL: s = "Peripheral"; break; | |
1994 | default: s = "OTG"; break; | |
1995 | }; s; }), | |
1996 | ctrl, | |
1997 | (is_dma_capable() && musb->dma_controller) | |
1998 | ? "DMA" : "PIO", | |
1999 | musb->nIrq); | |
2000 | ||
2001 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
2002 | /* host side needs more setup, except for no-host modes */ | |
2003 | if (musb->board_mode != MUSB_PERIPHERAL) { | |
2004 | struct usb_hcd *hcd = musb_to_hcd(musb); | |
2005 | ||
2006 | if (musb->board_mode == MUSB_OTG) | |
2007 | hcd->self.otg_port = 1; | |
2008 | musb->xceiv.host = &hcd->self; | |
2009 | hcd->power_budget = 2 * (plat->power ? : 250); | |
2010 | } | |
2011 | #endif /* CONFIG_USB_MUSB_HDRC_HCD */ | |
2012 | ||
2013 | /* For the host-only role, we can activate right away. | |
2014 | * (We expect the ID pin to be forcibly grounded!!) | |
2015 | * Otherwise, wait till the gadget driver hooks up. | |
2016 | */ | |
2017 | if (!is_otg_enabled(musb) && is_host_enabled(musb)) { | |
2018 | MUSB_HST_MODE(musb); | |
2019 | musb->xceiv.default_a = 1; | |
2020 | musb->xceiv.state = OTG_STATE_A_IDLE; | |
2021 | ||
2022 | status = usb_add_hcd(musb_to_hcd(musb), -1, 0); | |
746cdd0b FB |
2023 | if (status) |
2024 | goto fail; | |
550a7375 FB |
2025 | |
2026 | DBG(1, "%s mode, status %d, devctl %02x %c\n", | |
2027 | "HOST", status, | |
2028 | musb_readb(musb->mregs, MUSB_DEVCTL), | |
2029 | (musb_readb(musb->mregs, MUSB_DEVCTL) | |
2030 | & MUSB_DEVCTL_BDEVICE | |
2031 | ? 'B' : 'A')); | |
2032 | ||
2033 | } else /* peripheral is enabled */ { | |
2034 | MUSB_DEV_MODE(musb); | |
2035 | musb->xceiv.default_a = 0; | |
2036 | musb->xceiv.state = OTG_STATE_B_IDLE; | |
2037 | ||
2038 | status = musb_gadget_setup(musb); | |
746cdd0b FB |
2039 | if (status) |
2040 | goto fail; | |
550a7375 FB |
2041 | |
2042 | DBG(1, "%s mode, status %d, dev%02x\n", | |
2043 | is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", | |
2044 | status, | |
2045 | musb_readb(musb->mregs, MUSB_DEVCTL)); | |
2046 | ||
2047 | } | |
2048 | ||
550a7375 FB |
2049 | #ifdef CONFIG_SYSFS |
2050 | status = device_create_file(dev, &dev_attr_mode); | |
2051 | status = device_create_file(dev, &dev_attr_vbus); | |
2052 | #ifdef CONFIG_USB_GADGET_MUSB_HDRC | |
2053 | status = device_create_file(dev, &dev_attr_srp); | |
2054 | #endif /* CONFIG_USB_GADGET_MUSB_HDRC */ | |
2055 | status = 0; | |
2056 | #endif | |
28c2c51c FB |
2057 | if (status) |
2058 | goto fail2; | |
550a7375 | 2059 | |
28c2c51c | 2060 | return 0; |
550a7375 FB |
2061 | |
2062 | fail2: | |
28c2c51c FB |
2063 | #ifdef CONFIG_SYSFS |
2064 | device_remove_file(musb->controller, &dev_attr_mode); | |
2065 | device_remove_file(musb->controller, &dev_attr_vbus); | |
2066 | #ifdef CONFIG_USB_MUSB_OTG | |
2067 | device_remove_file(musb->controller, &dev_attr_srp); | |
2068 | #endif | |
2069 | #endif | |
550a7375 | 2070 | musb_platform_exit(musb); |
28c2c51c FB |
2071 | fail: |
2072 | dev_err(musb->controller, | |
2073 | "musb_init_controller failed with status %d\n", status); | |
2074 | ||
2075 | if (musb->clock) | |
2076 | clk_put(musb->clock); | |
2077 | device_init_wakeup(dev, 0); | |
2078 | musb_free(musb); | |
2079 | ||
2080 | return status; | |
2081 | ||
550a7375 FB |
2082 | } |
2083 | ||
2084 | /*-------------------------------------------------------------------------*/ | |
2085 | ||
2086 | /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just | |
2087 | * bridge to a platform device; this driver then suffices. | |
2088 | */ | |
2089 | ||
2090 | #ifndef CONFIG_MUSB_PIO_ONLY | |
2091 | static u64 *orig_dma_mask; | |
2092 | #endif | |
2093 | ||
2094 | static int __init musb_probe(struct platform_device *pdev) | |
2095 | { | |
2096 | struct device *dev = &pdev->dev; | |
2097 | int irq = platform_get_irq(pdev, 0); | |
2098 | struct resource *iomem; | |
2099 | void __iomem *base; | |
2100 | ||
2101 | iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2102 | if (!iomem || irq == 0) | |
2103 | return -ENODEV; | |
2104 | ||
2105 | base = ioremap(iomem->start, iomem->end - iomem->start + 1); | |
2106 | if (!base) { | |
2107 | dev_err(dev, "ioremap failed\n"); | |
2108 | return -ENOMEM; | |
2109 | } | |
2110 | ||
2111 | #ifndef CONFIG_MUSB_PIO_ONLY | |
2112 | /* clobbered by use_dma=n */ | |
2113 | orig_dma_mask = dev->dma_mask; | |
2114 | #endif | |
2115 | return musb_init_controller(dev, irq, base); | |
2116 | } | |
2117 | ||
2118 | static int __devexit musb_remove(struct platform_device *pdev) | |
2119 | { | |
2120 | struct musb *musb = dev_to_musb(&pdev->dev); | |
2121 | void __iomem *ctrl_base = musb->ctrl_base; | |
2122 | ||
2123 | /* this gets called on rmmod. | |
2124 | * - Host mode: host may still be active | |
2125 | * - Peripheral mode: peripheral is deactivated (or never-activated) | |
2126 | * - OTG mode: both roles are deactivated (or never-activated) | |
2127 | */ | |
2128 | musb_shutdown(pdev); | |
550a7375 FB |
2129 | #ifdef CONFIG_USB_MUSB_HDRC_HCD |
2130 | if (musb->board_mode == MUSB_HOST) | |
2131 | usb_remove_hcd(musb_to_hcd(musb)); | |
2132 | #endif | |
2133 | musb_free(musb); | |
2134 | iounmap(ctrl_base); | |
2135 | device_init_wakeup(&pdev->dev, 0); | |
2136 | #ifndef CONFIG_MUSB_PIO_ONLY | |
2137 | pdev->dev.dma_mask = orig_dma_mask; | |
2138 | #endif | |
2139 | return 0; | |
2140 | } | |
2141 | ||
2142 | #ifdef CONFIG_PM | |
2143 | ||
2144 | static int musb_suspend(struct platform_device *pdev, pm_message_t message) | |
2145 | { | |
2146 | unsigned long flags; | |
2147 | struct musb *musb = dev_to_musb(&pdev->dev); | |
2148 | ||
2149 | if (!musb->clock) | |
2150 | return 0; | |
2151 | ||
2152 | spin_lock_irqsave(&musb->lock, flags); | |
2153 | ||
2154 | if (is_peripheral_active(musb)) { | |
2155 | /* FIXME force disconnect unless we know USB will wake | |
2156 | * the system up quickly enough to respond ... | |
2157 | */ | |
2158 | } else if (is_host_active(musb)) { | |
2159 | /* we know all the children are suspended; sometimes | |
2160 | * they will even be wakeup-enabled. | |
2161 | */ | |
2162 | } | |
2163 | ||
2164 | if (musb->set_clock) | |
2165 | musb->set_clock(musb->clock, 0); | |
2166 | else | |
2167 | clk_disable(musb->clock); | |
2168 | spin_unlock_irqrestore(&musb->lock, flags); | |
2169 | return 0; | |
2170 | } | |
2171 | ||
2172 | static int musb_resume(struct platform_device *pdev) | |
2173 | { | |
2174 | unsigned long flags; | |
2175 | struct musb *musb = dev_to_musb(&pdev->dev); | |
2176 | ||
2177 | if (!musb->clock) | |
2178 | return 0; | |
2179 | ||
2180 | spin_lock_irqsave(&musb->lock, flags); | |
2181 | ||
2182 | if (musb->set_clock) | |
2183 | musb->set_clock(musb->clock, 1); | |
2184 | else | |
2185 | clk_enable(musb->clock); | |
2186 | ||
2187 | /* for static cmos like DaVinci, register values were preserved | |
2188 | * unless for some reason the whole soc powered down and we're | |
2189 | * not treating that as a whole-system restart (e.g. swsusp) | |
2190 | */ | |
2191 | spin_unlock_irqrestore(&musb->lock, flags); | |
2192 | return 0; | |
2193 | } | |
2194 | ||
2195 | #else | |
2196 | #define musb_suspend NULL | |
2197 | #define musb_resume NULL | |
2198 | #endif | |
2199 | ||
2200 | static struct platform_driver musb_driver = { | |
2201 | .driver = { | |
2202 | .name = (char *)musb_driver_name, | |
2203 | .bus = &platform_bus_type, | |
2204 | .owner = THIS_MODULE, | |
2205 | }, | |
2206 | .remove = __devexit_p(musb_remove), | |
2207 | .shutdown = musb_shutdown, | |
2208 | .suspend = musb_suspend, | |
2209 | .resume = musb_resume, | |
2210 | }; | |
2211 | ||
2212 | /*-------------------------------------------------------------------------*/ | |
2213 | ||
2214 | static int __init musb_init(void) | |
2215 | { | |
2216 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
2217 | if (usb_disabled()) | |
2218 | return 0; | |
2219 | #endif | |
2220 | ||
2221 | pr_info("%s: version " MUSB_VERSION ", " | |
2222 | #ifdef CONFIG_MUSB_PIO_ONLY | |
2223 | "pio" | |
2224 | #elif defined(CONFIG_USB_TI_CPPI_DMA) | |
2225 | "cppi-dma" | |
2226 | #elif defined(CONFIG_USB_INVENTRA_DMA) | |
2227 | "musb-dma" | |
2228 | #elif defined(CONFIG_USB_TUSB_OMAP_DMA) | |
2229 | "tusb-omap-dma" | |
2230 | #else | |
2231 | "?dma?" | |
2232 | #endif | |
2233 | ", " | |
2234 | #ifdef CONFIG_USB_MUSB_OTG | |
2235 | "otg (peripheral+host)" | |
2236 | #elif defined(CONFIG_USB_GADGET_MUSB_HDRC) | |
2237 | "peripheral" | |
2238 | #elif defined(CONFIG_USB_MUSB_HDRC_HCD) | |
2239 | "host" | |
2240 | #endif | |
2241 | ", debug=%d\n", | |
b60c72ab | 2242 | musb_driver_name, musb_debug); |
550a7375 FB |
2243 | return platform_driver_probe(&musb_driver, musb_probe); |
2244 | } | |
2245 | ||
2246 | /* make us init after usbcore and before usb | |
2247 | * gadget and host-side drivers start to register | |
2248 | */ | |
2249 | subsys_initcall(musb_init); | |
2250 | ||
2251 | static void __exit musb_cleanup(void) | |
2252 | { | |
2253 | platform_driver_unregister(&musb_driver); | |
2254 | } | |
2255 | module_exit(musb_cleanup); |