Commit | Line | Data |
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550a7375 FB |
1 | /* |
2 | * MUSB OTG driver core code | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
23 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
25 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
26 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
27 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
28 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | */ | |
34 | ||
35 | /* | |
36 | * Inventra (Multipoint) Dual-Role Controller Driver for Linux. | |
37 | * | |
38 | * This consists of a Host Controller Driver (HCD) and a peripheral | |
39 | * controller driver implementing the "Gadget" API; OTG support is | |
40 | * in the works. These are normal Linux-USB controller drivers which | |
41 | * use IRQs and have no dedicated thread. | |
42 | * | |
43 | * This version of the driver has only been used with products from | |
44 | * Texas Instruments. Those products integrate the Inventra logic | |
45 | * with other DMA, IRQ, and bus modules, as well as other logic that | |
46 | * needs to be reflected in this driver. | |
47 | * | |
48 | * | |
49 | * NOTE: the original Mentor code here was pretty much a collection | |
50 | * of mechanisms that don't seem to have been fully integrated/working | |
51 | * for *any* Linux kernel version. This version aims at Linux 2.6.now, | |
52 | * Key open issues include: | |
53 | * | |
54 | * - Lack of host-side transaction scheduling, for all transfer types. | |
55 | * The hardware doesn't do it; instead, software must. | |
56 | * | |
57 | * This is not an issue for OTG devices that don't support external | |
58 | * hubs, but for more "normal" USB hosts it's a user issue that the | |
59 | * "multipoint" support doesn't scale in the expected ways. That | |
60 | * includes DaVinci EVM in a common non-OTG mode. | |
61 | * | |
62 | * * Control and bulk use dedicated endpoints, and there's as | |
63 | * yet no mechanism to either (a) reclaim the hardware when | |
64 | * peripherals are NAKing, which gets complicated with bulk | |
65 | * endpoints, or (b) use more than a single bulk endpoint in | |
66 | * each direction. | |
67 | * | |
68 | * RESULT: one device may be perceived as blocking another one. | |
69 | * | |
70 | * * Interrupt and isochronous will dynamically allocate endpoint | |
71 | * hardware, but (a) there's no record keeping for bandwidth; | |
72 | * (b) in the common case that few endpoints are available, there | |
73 | * is no mechanism to reuse endpoints to talk to multiple devices. | |
74 | * | |
75 | * RESULT: At one extreme, bandwidth can be overcommitted in | |
76 | * some hardware configurations, no faults will be reported. | |
77 | * At the other extreme, the bandwidth capabilities which do | |
78 | * exist tend to be severely undercommitted. You can't yet hook | |
79 | * up both a keyboard and a mouse to an external USB hub. | |
80 | */ | |
81 | ||
82 | /* | |
83 | * This gets many kinds of configuration information: | |
84 | * - Kconfig for everything user-configurable | |
550a7375 FB |
85 | * - platform_device for addressing, irq, and platform_data |
86 | * - platform_data is mostly for board-specific informarion | |
c767c1c6 | 87 | * (plus recentrly, SOC or family details) |
550a7375 FB |
88 | * |
89 | * Most of the conditional compilation will (someday) vanish. | |
90 | */ | |
91 | ||
92 | #include <linux/module.h> | |
93 | #include <linux/kernel.h> | |
94 | #include <linux/sched.h> | |
95 | #include <linux/slab.h> | |
96 | #include <linux/init.h> | |
97 | #include <linux/list.h> | |
98 | #include <linux/kobject.h> | |
9303961f | 99 | #include <linux/prefetch.h> |
550a7375 FB |
100 | #include <linux/platform_device.h> |
101 | #include <linux/io.h> | |
8d2421e6 | 102 | #include <linux/dma-mapping.h> |
550a7375 | 103 | |
550a7375 FB |
104 | #include "musb_core.h" |
105 | ||
f7f9d63e | 106 | #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) |
550a7375 FB |
107 | |
108 | ||
550a7375 FB |
109 | #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" |
110 | #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" | |
111 | ||
e8164f64 | 112 | #define MUSB_VERSION "6.0" |
550a7375 FB |
113 | |
114 | #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION | |
115 | ||
05ac10dd | 116 | #define MUSB_DRIVER_NAME "musb-hdrc" |
550a7375 FB |
117 | const char musb_driver_name[] = MUSB_DRIVER_NAME; |
118 | ||
119 | MODULE_DESCRIPTION(DRIVER_INFO); | |
120 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
121 | MODULE_LICENSE("GPL"); | |
122 | MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); | |
123 | ||
124 | ||
125 | /*-------------------------------------------------------------------------*/ | |
126 | ||
127 | static inline struct musb *dev_to_musb(struct device *dev) | |
128 | { | |
550a7375 | 129 | return dev_get_drvdata(dev); |
550a7375 FB |
130 | } |
131 | ||
132 | /*-------------------------------------------------------------------------*/ | |
133 | ||
ffb865b1 | 134 | #ifndef CONFIG_BLACKFIN |
b96d3b08 | 135 | static int musb_ulpi_read(struct usb_phy *phy, u32 offset) |
ffb865b1 | 136 | { |
b96d3b08 | 137 | void __iomem *addr = phy->io_priv; |
ffb865b1 HK |
138 | int i = 0; |
139 | u8 r; | |
140 | u8 power; | |
bf070bc1 GI |
141 | int ret; |
142 | ||
143 | pm_runtime_get_sync(phy->io_dev); | |
ffb865b1 HK |
144 | |
145 | /* Make sure the transceiver is not in low power mode */ | |
146 | power = musb_readb(addr, MUSB_POWER); | |
147 | power &= ~MUSB_POWER_SUSPENDM; | |
148 | musb_writeb(addr, MUSB_POWER, power); | |
149 | ||
150 | /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the | |
151 | * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. | |
152 | */ | |
153 | ||
154 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); | |
155 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, | |
156 | MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); | |
157 | ||
158 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) | |
159 | & MUSB_ULPI_REG_CMPLT)) { | |
160 | i++; | |
bf070bc1 GI |
161 | if (i == 10000) { |
162 | ret = -ETIMEDOUT; | |
163 | goto out; | |
164 | } | |
ffb865b1 HK |
165 | |
166 | } | |
167 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); | |
168 | r &= ~MUSB_ULPI_REG_CMPLT; | |
169 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); | |
170 | ||
bf070bc1 GI |
171 | ret = musb_readb(addr, MUSB_ULPI_REG_DATA); |
172 | ||
173 | out: | |
174 | pm_runtime_put(phy->io_dev); | |
175 | ||
176 | return ret; | |
ffb865b1 HK |
177 | } |
178 | ||
b96d3b08 | 179 | static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) |
ffb865b1 | 180 | { |
b96d3b08 | 181 | void __iomem *addr = phy->io_priv; |
ffb865b1 HK |
182 | int i = 0; |
183 | u8 r = 0; | |
184 | u8 power; | |
bf070bc1 GI |
185 | int ret = 0; |
186 | ||
187 | pm_runtime_get_sync(phy->io_dev); | |
ffb865b1 HK |
188 | |
189 | /* Make sure the transceiver is not in low power mode */ | |
190 | power = musb_readb(addr, MUSB_POWER); | |
191 | power &= ~MUSB_POWER_SUSPENDM; | |
192 | musb_writeb(addr, MUSB_POWER, power); | |
193 | ||
194 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); | |
195 | musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); | |
196 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); | |
197 | ||
198 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) | |
199 | & MUSB_ULPI_REG_CMPLT)) { | |
200 | i++; | |
bf070bc1 GI |
201 | if (i == 10000) { |
202 | ret = -ETIMEDOUT; | |
203 | goto out; | |
204 | } | |
ffb865b1 HK |
205 | } |
206 | ||
207 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); | |
208 | r &= ~MUSB_ULPI_REG_CMPLT; | |
209 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); | |
210 | ||
bf070bc1 GI |
211 | out: |
212 | pm_runtime_put(phy->io_dev); | |
213 | ||
214 | return ret; | |
ffb865b1 HK |
215 | } |
216 | #else | |
f2263db7 MF |
217 | #define musb_ulpi_read NULL |
218 | #define musb_ulpi_write NULL | |
ffb865b1 HK |
219 | #endif |
220 | ||
b96d3b08 | 221 | static struct usb_phy_io_ops musb_ulpi_access = { |
ffb865b1 HK |
222 | .read = musb_ulpi_read, |
223 | .write = musb_ulpi_write, | |
224 | }; | |
225 | ||
226 | /*-------------------------------------------------------------------------*/ | |
227 | ||
7c925546 | 228 | #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) |
c6cf8b00 | 229 | |
550a7375 FB |
230 | /* |
231 | * Load an endpoint's FIFO | |
232 | */ | |
233 | void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) | |
234 | { | |
5c8a86e1 | 235 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
236 | void __iomem *fifo = hw_ep->fifo; |
237 | ||
603fe2b2 AKG |
238 | if (unlikely(len == 0)) |
239 | return; | |
240 | ||
550a7375 FB |
241 | prefetch((u8 *)src); |
242 | ||
5c8a86e1 | 243 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
244 | 'T', hw_ep->epnum, fifo, len, src); |
245 | ||
246 | /* we can't assume unaligned reads work */ | |
247 | if (likely((0x01 & (unsigned long) src) == 0)) { | |
248 | u16 index = 0; | |
249 | ||
250 | /* best case is 32bit-aligned source address */ | |
251 | if ((0x02 & (unsigned long) src) == 0) { | |
252 | if (len >= 4) { | |
2bf0a8f6 | 253 | iowrite32_rep(fifo, src + index, len >> 2); |
550a7375 FB |
254 | index += len & ~0x03; |
255 | } | |
256 | if (len & 0x02) { | |
257 | musb_writew(fifo, 0, *(u16 *)&src[index]); | |
258 | index += 2; | |
259 | } | |
260 | } else { | |
261 | if (len >= 2) { | |
2bf0a8f6 | 262 | iowrite16_rep(fifo, src + index, len >> 1); |
550a7375 FB |
263 | index += len & ~0x01; |
264 | } | |
265 | } | |
266 | if (len & 0x01) | |
267 | musb_writeb(fifo, 0, src[index]); | |
268 | } else { | |
269 | /* byte aligned */ | |
2bf0a8f6 | 270 | iowrite8_rep(fifo, src, len); |
550a7375 FB |
271 | } |
272 | } | |
273 | ||
843bb1d0 | 274 | #if !defined(CONFIG_USB_MUSB_AM35X) |
550a7375 FB |
275 | /* |
276 | * Unload an endpoint's FIFO | |
277 | */ | |
278 | void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) | |
279 | { | |
5c8a86e1 | 280 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
281 | void __iomem *fifo = hw_ep->fifo; |
282 | ||
603fe2b2 AKG |
283 | if (unlikely(len == 0)) |
284 | return; | |
285 | ||
5c8a86e1 | 286 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
287 | 'R', hw_ep->epnum, fifo, len, dst); |
288 | ||
289 | /* we can't assume unaligned writes work */ | |
290 | if (likely((0x01 & (unsigned long) dst) == 0)) { | |
291 | u16 index = 0; | |
292 | ||
293 | /* best case is 32bit-aligned destination address */ | |
294 | if ((0x02 & (unsigned long) dst) == 0) { | |
295 | if (len >= 4) { | |
2bf0a8f6 | 296 | ioread32_rep(fifo, dst, len >> 2); |
550a7375 FB |
297 | index = len & ~0x03; |
298 | } | |
299 | if (len & 0x02) { | |
300 | *(u16 *)&dst[index] = musb_readw(fifo, 0); | |
301 | index += 2; | |
302 | } | |
303 | } else { | |
304 | if (len >= 2) { | |
2bf0a8f6 | 305 | ioread16_rep(fifo, dst, len >> 1); |
550a7375 FB |
306 | index = len & ~0x01; |
307 | } | |
308 | } | |
309 | if (len & 0x01) | |
310 | dst[index] = musb_readb(fifo, 0); | |
311 | } else { | |
312 | /* byte aligned */ | |
2bf0a8f6 | 313 | ioread8_rep(fifo, dst, len); |
550a7375 FB |
314 | } |
315 | } | |
843bb1d0 | 316 | #endif |
550a7375 FB |
317 | |
318 | #endif /* normal PIO */ | |
319 | ||
320 | ||
321 | /*-------------------------------------------------------------------------*/ | |
322 | ||
323 | /* for high speed test mode; see USB 2.0 spec 7.1.20 */ | |
324 | static const u8 musb_test_packet[53] = { | |
325 | /* implicit SYNC then DATA0 to start */ | |
326 | ||
327 | /* JKJKJKJK x9 */ | |
328 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
329 | /* JJKKJJKK x8 */ | |
330 | 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, | |
331 | /* JJJJKKKK x8 */ | |
332 | 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, | |
333 | /* JJJJJJJKKKKKKK x8 */ | |
334 | 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
335 | /* JJJJJJJK x8 */ | |
336 | 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, | |
337 | /* JKKKKKKK x10, JK */ | |
338 | 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e | |
339 | ||
340 | /* implicit CRC16 then EOP to end */ | |
341 | }; | |
342 | ||
343 | void musb_load_testpacket(struct musb *musb) | |
344 | { | |
345 | void __iomem *regs = musb->endpoints[0].regs; | |
346 | ||
347 | musb_ep_select(musb->mregs, 0); | |
348 | musb_write_fifo(musb->control_ep, | |
349 | sizeof(musb_test_packet), musb_test_packet); | |
350 | musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); | |
351 | } | |
352 | ||
353 | /*-------------------------------------------------------------------------*/ | |
354 | ||
550a7375 FB |
355 | /* |
356 | * Handles OTG hnp timeouts, such as b_ase0_brst | |
357 | */ | |
a156544b | 358 | static void musb_otg_timer_func(unsigned long data) |
550a7375 FB |
359 | { |
360 | struct musb *musb = (struct musb *)data; | |
361 | unsigned long flags; | |
362 | ||
363 | spin_lock_irqsave(&musb->lock, flags); | |
84e250ff | 364 | switch (musb->xceiv->state) { |
550a7375 | 365 | case OTG_STATE_B_WAIT_ACON: |
5c8a86e1 | 366 | dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); |
550a7375 | 367 | musb_g_disconnect(musb); |
84e250ff | 368 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
369 | musb->is_active = 0; |
370 | break; | |
ab983f2a | 371 | case OTG_STATE_A_SUSPEND: |
550a7375 | 372 | case OTG_STATE_A_WAIT_BCON: |
5c8a86e1 | 373 | dev_dbg(musb->controller, "HNP: %s timeout\n", |
42c0bf1c | 374 | usb_otg_state_string(musb->xceiv->state)); |
743411b3 | 375 | musb_platform_set_vbus(musb, 0); |
ab983f2a | 376 | musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; |
550a7375 FB |
377 | break; |
378 | default: | |
5c8a86e1 | 379 | dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", |
42c0bf1c | 380 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 | 381 | } |
550a7375 FB |
382 | spin_unlock_irqrestore(&musb->lock, flags); |
383 | } | |
384 | ||
550a7375 | 385 | /* |
f7f9d63e | 386 | * Stops the HNP transition. Caller must take care of locking. |
550a7375 FB |
387 | */ |
388 | void musb_hnp_stop(struct musb *musb) | |
389 | { | |
8b125df5 | 390 | struct usb_hcd *hcd = musb->hcd; |
550a7375 FB |
391 | void __iomem *mbase = musb->mregs; |
392 | u8 reg; | |
393 | ||
42c0bf1c FB |
394 | dev_dbg(musb->controller, "HNP: stop from %s\n", |
395 | usb_otg_state_string(musb->xceiv->state)); | |
ab983f2a | 396 | |
84e250ff | 397 | switch (musb->xceiv->state) { |
550a7375 | 398 | case OTG_STATE_A_PERIPHERAL: |
550a7375 | 399 | musb_g_disconnect(musb); |
5c8a86e1 | 400 | dev_dbg(musb->controller, "HNP: back to %s\n", |
42c0bf1c | 401 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
402 | break; |
403 | case OTG_STATE_B_HOST: | |
5c8a86e1 | 404 | dev_dbg(musb->controller, "HNP: Disabling HR\n"); |
74c2e936 DM |
405 | if (hcd) |
406 | hcd->self.is_b_host = 0; | |
84e250ff | 407 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
408 | MUSB_DEV_MODE(musb); |
409 | reg = musb_readb(mbase, MUSB_POWER); | |
410 | reg |= MUSB_POWER_SUSPENDM; | |
411 | musb_writeb(mbase, MUSB_POWER, reg); | |
412 | /* REVISIT: Start SESSION_REQUEST here? */ | |
413 | break; | |
414 | default: | |
5c8a86e1 | 415 | dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", |
42c0bf1c | 416 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
417 | } |
418 | ||
419 | /* | |
420 | * When returning to A state after HNP, avoid hub_port_rebounce(), | |
421 | * which cause occasional OPT A "Did not receive reset after connect" | |
422 | * errors. | |
423 | */ | |
749da5f8 | 424 | musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); |
550a7375 FB |
425 | } |
426 | ||
550a7375 FB |
427 | /* |
428 | * Interrupt Service Routine to record USB "global" interrupts. | |
429 | * Since these do not happen often and signify things of | |
430 | * paramount importance, it seems OK to check them individually; | |
431 | * the order of the tests is specified in the manual | |
432 | * | |
433 | * @param musb instance pointer | |
434 | * @param int_usb register contents | |
435 | * @param devctl | |
436 | * @param power | |
437 | */ | |
438 | ||
550a7375 | 439 | static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, |
b11e94d0 | 440 | u8 devctl) |
550a7375 | 441 | { |
d445b6da | 442 | struct usb_otg *otg = musb->xceiv->otg; |
550a7375 | 443 | irqreturn_t handled = IRQ_NONE; |
550a7375 | 444 | |
b11e94d0 | 445 | dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl, |
550a7375 FB |
446 | int_usb); |
447 | ||
448 | /* in host mode, the peripheral may issue remote wakeup. | |
449 | * in peripheral mode, the host may resume the link. | |
450 | * spurious RESUME irqs happen too, paired with SUSPEND. | |
451 | */ | |
452 | if (int_usb & MUSB_INTR_RESUME) { | |
453 | handled = IRQ_HANDLED; | |
42c0bf1c | 454 | dev_dbg(musb->controller, "RESUME (%s)\n", usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
455 | |
456 | if (devctl & MUSB_DEVCTL_HM) { | |
aa471456 | 457 | void __iomem *mbase = musb->mregs; |
b11e94d0 | 458 | u8 power; |
aa471456 | 459 | |
84e250ff | 460 | switch (musb->xceiv->state) { |
550a7375 FB |
461 | case OTG_STATE_A_SUSPEND: |
462 | /* remote wakeup? later, GetPortStatus | |
463 | * will stop RESUME signaling | |
464 | */ | |
465 | ||
b11e94d0 | 466 | power = musb_readb(musb->mregs, MUSB_POWER); |
550a7375 FB |
467 | if (power & MUSB_POWER_SUSPENDM) { |
468 | /* spurious */ | |
469 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
5c8a86e1 | 470 | dev_dbg(musb->controller, "Spurious SUSPENDM\n"); |
550a7375 FB |
471 | break; |
472 | } | |
473 | ||
474 | power &= ~MUSB_POWER_SUSPENDM; | |
475 | musb_writeb(mbase, MUSB_POWER, | |
476 | power | MUSB_POWER_RESUME); | |
477 | ||
478 | musb->port1_status |= | |
479 | (USB_PORT_STAT_C_SUSPEND << 16) | |
480 | | MUSB_PORT_STAT_RESUME; | |
481 | musb->rh_timer = jiffies | |
482 | + msecs_to_jiffies(20); | |
483 | ||
84e250ff | 484 | musb->xceiv->state = OTG_STATE_A_HOST; |
550a7375 | 485 | musb->is_active = 1; |
0b3eba44 | 486 | musb_host_resume_root_hub(musb); |
550a7375 FB |
487 | break; |
488 | case OTG_STATE_B_WAIT_ACON: | |
84e250ff | 489 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
490 | musb->is_active = 1; |
491 | MUSB_DEV_MODE(musb); | |
492 | break; | |
493 | default: | |
494 | WARNING("bogus %s RESUME (%s)\n", | |
495 | "host", | |
42c0bf1c | 496 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 | 497 | } |
550a7375 | 498 | } else { |
84e250ff | 499 | switch (musb->xceiv->state) { |
550a7375 FB |
500 | case OTG_STATE_A_SUSPEND: |
501 | /* possibly DISCONNECT is upcoming */ | |
84e250ff | 502 | musb->xceiv->state = OTG_STATE_A_HOST; |
0b3eba44 | 503 | musb_host_resume_root_hub(musb); |
550a7375 | 504 | break; |
550a7375 FB |
505 | case OTG_STATE_B_WAIT_ACON: |
506 | case OTG_STATE_B_PERIPHERAL: | |
507 | /* disconnect while suspended? we may | |
508 | * not get a disconnect irq... | |
509 | */ | |
510 | if ((devctl & MUSB_DEVCTL_VBUS) | |
511 | != (3 << MUSB_DEVCTL_VBUS_SHIFT) | |
512 | ) { | |
513 | musb->int_usb |= MUSB_INTR_DISCONNECT; | |
514 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
515 | break; | |
516 | } | |
517 | musb_g_resume(musb); | |
518 | break; | |
519 | case OTG_STATE_B_IDLE: | |
520 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
521 | break; | |
550a7375 FB |
522 | default: |
523 | WARNING("bogus %s RESUME (%s)\n", | |
524 | "peripheral", | |
42c0bf1c | 525 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
526 | } |
527 | } | |
528 | } | |
529 | ||
550a7375 FB |
530 | /* see manual for the order of the tests */ |
531 | if (int_usb & MUSB_INTR_SESSREQ) { | |
aa471456 FB |
532 | void __iomem *mbase = musb->mregs; |
533 | ||
19aab56c HK |
534 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS |
535 | && (devctl & MUSB_DEVCTL_BDEVICE)) { | |
5c8a86e1 | 536 | dev_dbg(musb->controller, "SessReq while on B state\n"); |
a6038ee7 HK |
537 | return IRQ_HANDLED; |
538 | } | |
539 | ||
5c8a86e1 | 540 | dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", |
42c0bf1c | 541 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
542 | |
543 | /* IRQ arrives from ID pin sense or (later, if VBUS power | |
544 | * is removed) SRP. responses are time critical: | |
545 | * - turn on VBUS (with silicon-specific mechanism) | |
546 | * - go through A_WAIT_VRISE | |
547 | * - ... to A_WAIT_BCON. | |
548 | * a_wait_vrise_tmout triggers VBUS_ERROR transitions | |
549 | */ | |
550 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
551 | musb->ep0_stage = MUSB_EP0_START; | |
84e250ff | 552 | musb->xceiv->state = OTG_STATE_A_IDLE; |
550a7375 | 553 | MUSB_HST_MODE(musb); |
743411b3 | 554 | musb_platform_set_vbus(musb, 1); |
550a7375 FB |
555 | |
556 | handled = IRQ_HANDLED; | |
557 | } | |
558 | ||
559 | if (int_usb & MUSB_INTR_VBUSERROR) { | |
560 | int ignore = 0; | |
561 | ||
562 | /* During connection as an A-Device, we may see a short | |
563 | * current spikes causing voltage drop, because of cable | |
564 | * and peripheral capacitance combined with vbus draw. | |
565 | * (So: less common with truly self-powered devices, where | |
566 | * vbus doesn't act like a power supply.) | |
567 | * | |
568 | * Such spikes are short; usually less than ~500 usec, max | |
569 | * of ~2 msec. That is, they're not sustained overcurrent | |
570 | * errors, though they're reported using VBUSERROR irqs. | |
571 | * | |
572 | * Workarounds: (a) hardware: use self powered devices. | |
573 | * (b) software: ignore non-repeated VBUS errors. | |
574 | * | |
575 | * REVISIT: do delays from lots of DEBUG_KERNEL checks | |
576 | * make trouble here, keeping VBUS < 4.4V ? | |
577 | */ | |
84e250ff | 578 | switch (musb->xceiv->state) { |
550a7375 FB |
579 | case OTG_STATE_A_HOST: |
580 | /* recovery is dicey once we've gotten past the | |
581 | * initial stages of enumeration, but if VBUS | |
582 | * stayed ok at the other end of the link, and | |
583 | * another reset is due (at least for high speed, | |
584 | * to redo the chirp etc), it might work OK... | |
585 | */ | |
586 | case OTG_STATE_A_WAIT_BCON: | |
587 | case OTG_STATE_A_WAIT_VRISE: | |
588 | if (musb->vbuserr_retry) { | |
aa471456 FB |
589 | void __iomem *mbase = musb->mregs; |
590 | ||
550a7375 FB |
591 | musb->vbuserr_retry--; |
592 | ignore = 1; | |
593 | devctl |= MUSB_DEVCTL_SESSION; | |
594 | musb_writeb(mbase, MUSB_DEVCTL, devctl); | |
595 | } else { | |
596 | musb->port1_status |= | |
749da5f8 AS |
597 | USB_PORT_STAT_OVERCURRENT |
598 | | (USB_PORT_STAT_C_OVERCURRENT << 16); | |
550a7375 FB |
599 | } |
600 | break; | |
601 | default: | |
602 | break; | |
603 | } | |
604 | ||
54485116 GI |
605 | dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller, |
606 | "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", | |
42c0bf1c | 607 | usb_otg_state_string(musb->xceiv->state), |
550a7375 FB |
608 | devctl, |
609 | ({ char *s; | |
610 | switch (devctl & MUSB_DEVCTL_VBUS) { | |
611 | case 0 << MUSB_DEVCTL_VBUS_SHIFT: | |
612 | s = "<SessEnd"; break; | |
613 | case 1 << MUSB_DEVCTL_VBUS_SHIFT: | |
614 | s = "<AValid"; break; | |
615 | case 2 << MUSB_DEVCTL_VBUS_SHIFT: | |
616 | s = "<VBusValid"; break; | |
617 | /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ | |
618 | default: | |
619 | s = "VALID"; break; | |
620 | }; s; }), | |
621 | VBUSERR_RETRY_COUNT - musb->vbuserr_retry, | |
622 | musb->port1_status); | |
623 | ||
624 | /* go through A_WAIT_VFALL then start a new session */ | |
625 | if (!ignore) | |
743411b3 | 626 | musb_platform_set_vbus(musb, 0); |
550a7375 FB |
627 | handled = IRQ_HANDLED; |
628 | } | |
629 | ||
1c25fda4 | 630 | if (int_usb & MUSB_INTR_SUSPEND) { |
b11e94d0 | 631 | dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n", |
42c0bf1c | 632 | usb_otg_state_string(musb->xceiv->state), devctl); |
1c25fda4 AM |
633 | handled = IRQ_HANDLED; |
634 | ||
635 | switch (musb->xceiv->state) { | |
1c25fda4 AM |
636 | case OTG_STATE_A_PERIPHERAL: |
637 | /* We also come here if the cable is removed, since | |
638 | * this silicon doesn't report ID-no-longer-grounded. | |
639 | * | |
640 | * We depend on T(a_wait_bcon) to shut us down, and | |
641 | * hope users don't do anything dicey during this | |
642 | * undesired detour through A_WAIT_BCON. | |
643 | */ | |
644 | musb_hnp_stop(musb); | |
0b3eba44 | 645 | musb_host_resume_root_hub(musb); |
1c25fda4 AM |
646 | musb_root_disconnect(musb); |
647 | musb_platform_try_idle(musb, jiffies | |
648 | + msecs_to_jiffies(musb->a_wait_bcon | |
649 | ? : OTG_TIME_A_WAIT_BCON)); | |
650 | ||
651 | break; | |
1c25fda4 AM |
652 | case OTG_STATE_B_IDLE: |
653 | if (!musb->is_active) | |
654 | break; | |
655 | case OTG_STATE_B_PERIPHERAL: | |
656 | musb_g_suspend(musb); | |
032ec49f | 657 | musb->is_active = otg->gadget->b_hnp_enable; |
1c25fda4 | 658 | if (musb->is_active) { |
1c25fda4 | 659 | musb->xceiv->state = OTG_STATE_B_WAIT_ACON; |
5c8a86e1 | 660 | dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); |
1c25fda4 AM |
661 | mod_timer(&musb->otg_timer, jiffies |
662 | + msecs_to_jiffies( | |
663 | OTG_TIME_B_ASE0_BRST)); | |
1c25fda4 AM |
664 | } |
665 | break; | |
666 | case OTG_STATE_A_WAIT_BCON: | |
667 | if (musb->a_wait_bcon != 0) | |
668 | musb_platform_try_idle(musb, jiffies | |
669 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
670 | break; | |
671 | case OTG_STATE_A_HOST: | |
672 | musb->xceiv->state = OTG_STATE_A_SUSPEND; | |
032ec49f | 673 | musb->is_active = otg->host->b_hnp_enable; |
1c25fda4 AM |
674 | break; |
675 | case OTG_STATE_B_HOST: | |
676 | /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ | |
5c8a86e1 | 677 | dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); |
1c25fda4 AM |
678 | break; |
679 | default: | |
680 | /* "should not happen" */ | |
681 | musb->is_active = 0; | |
682 | break; | |
683 | } | |
684 | } | |
685 | ||
550a7375 | 686 | if (int_usb & MUSB_INTR_CONNECT) { |
8b125df5 | 687 | struct usb_hcd *hcd = musb->hcd; |
550a7375 FB |
688 | |
689 | handled = IRQ_HANDLED; | |
690 | musb->is_active = 1; | |
550a7375 FB |
691 | |
692 | musb->ep0_stage = MUSB_EP0_START; | |
693 | ||
550a7375 FB |
694 | /* flush endpoints when transitioning from Device Mode */ |
695 | if (is_peripheral_active(musb)) { | |
696 | /* REVISIT HNP; just force disconnect */ | |
697 | } | |
b18d26f6 SAS |
698 | musb->intrtxe = musb->epmask; |
699 | musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe); | |
af5ec14d SAS |
700 | musb->intrrxe = musb->epmask & 0xfffe; |
701 | musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe); | |
d709d22e | 702 | musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); |
550a7375 FB |
703 | musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED |
704 | |USB_PORT_STAT_HIGH_SPEED | |
705 | |USB_PORT_STAT_ENABLE | |
706 | ); | |
707 | musb->port1_status |= USB_PORT_STAT_CONNECTION | |
708 | |(USB_PORT_STAT_C_CONNECTION << 16); | |
709 | ||
710 | /* high vs full speed is just a guess until after reset */ | |
711 | if (devctl & MUSB_DEVCTL_LSDEV) | |
712 | musb->port1_status |= USB_PORT_STAT_LOW_SPEED; | |
713 | ||
550a7375 | 714 | /* indicate new connection to OTG machine */ |
84e250ff | 715 | switch (musb->xceiv->state) { |
550a7375 FB |
716 | case OTG_STATE_B_PERIPHERAL: |
717 | if (int_usb & MUSB_INTR_SUSPEND) { | |
5c8a86e1 | 718 | dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); |
550a7375 | 719 | int_usb &= ~MUSB_INTR_SUSPEND; |
1de00dae | 720 | goto b_host; |
550a7375 | 721 | } else |
5c8a86e1 | 722 | dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); |
550a7375 FB |
723 | break; |
724 | case OTG_STATE_B_WAIT_ACON: | |
5c8a86e1 | 725 | dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); |
1de00dae | 726 | b_host: |
84e250ff | 727 | musb->xceiv->state = OTG_STATE_B_HOST; |
74c2e936 DM |
728 | if (musb->hcd) |
729 | musb->hcd->self.is_b_host = 1; | |
1de00dae | 730 | del_timer(&musb->otg_timer); |
550a7375 FB |
731 | break; |
732 | default: | |
733 | if ((devctl & MUSB_DEVCTL_VBUS) | |
734 | == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { | |
84e250ff | 735 | musb->xceiv->state = OTG_STATE_A_HOST; |
0b3eba44 DM |
736 | if (hcd) |
737 | hcd->self.is_b_host = 0; | |
550a7375 FB |
738 | } |
739 | break; | |
740 | } | |
1de00dae | 741 | |
0b3eba44 | 742 | musb_host_poke_root_hub(musb); |
1de00dae | 743 | |
5c8a86e1 | 744 | dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", |
42c0bf1c | 745 | usb_otg_state_string(musb->xceiv->state), devctl); |
550a7375 | 746 | } |
550a7375 | 747 | |
6d349671 | 748 | if (int_usb & MUSB_INTR_DISCONNECT) { |
5c8a86e1 | 749 | dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", |
42c0bf1c | 750 | usb_otg_state_string(musb->xceiv->state), |
1c25fda4 AM |
751 | MUSB_MODE(musb), devctl); |
752 | handled = IRQ_HANDLED; | |
753 | ||
754 | switch (musb->xceiv->state) { | |
1c25fda4 AM |
755 | case OTG_STATE_A_HOST: |
756 | case OTG_STATE_A_SUSPEND: | |
0b3eba44 | 757 | musb_host_resume_root_hub(musb); |
1c25fda4 | 758 | musb_root_disconnect(musb); |
032ec49f | 759 | if (musb->a_wait_bcon != 0) |
1c25fda4 AM |
760 | musb_platform_try_idle(musb, jiffies |
761 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
762 | break; | |
1c25fda4 AM |
763 | case OTG_STATE_B_HOST: |
764 | /* REVISIT this behaves for "real disconnect" | |
765 | * cases; make sure the other transitions from | |
766 | * from B_HOST act right too. The B_HOST code | |
767 | * in hnp_stop() is currently not used... | |
768 | */ | |
769 | musb_root_disconnect(musb); | |
74c2e936 DM |
770 | if (musb->hcd) |
771 | musb->hcd->self.is_b_host = 0; | |
1c25fda4 AM |
772 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
773 | MUSB_DEV_MODE(musb); | |
774 | musb_g_disconnect(musb); | |
775 | break; | |
776 | case OTG_STATE_A_PERIPHERAL: | |
777 | musb_hnp_stop(musb); | |
778 | musb_root_disconnect(musb); | |
779 | /* FALLTHROUGH */ | |
780 | case OTG_STATE_B_WAIT_ACON: | |
781 | /* FALLTHROUGH */ | |
1c25fda4 AM |
782 | case OTG_STATE_B_PERIPHERAL: |
783 | case OTG_STATE_B_IDLE: | |
784 | musb_g_disconnect(musb); | |
785 | break; | |
1c25fda4 AM |
786 | default: |
787 | WARNING("unhandled DISCONNECT transition (%s)\n", | |
42c0bf1c | 788 | usb_otg_state_string(musb->xceiv->state)); |
1c25fda4 AM |
789 | break; |
790 | } | |
791 | } | |
792 | ||
550a7375 FB |
793 | /* mentor saves a bit: bus reset and babble share the same irq. |
794 | * only host sees babble; only peripheral sees bus reset. | |
795 | */ | |
796 | if (int_usb & MUSB_INTR_RESET) { | |
1c25fda4 | 797 | handled = IRQ_HANDLED; |
a04d46d0 | 798 | if ((devctl & MUSB_DEVCTL_HM) != 0) { |
550a7375 FB |
799 | /* |
800 | * Looks like non-HS BABBLE can be ignored, but | |
801 | * HS BABBLE is an error condition. For HS the solution | |
802 | * is to avoid babble in the first place and fix what | |
803 | * caused BABBLE. When HS BABBLE happens we can only | |
804 | * stop the session. | |
805 | */ | |
806 | if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) | |
5c8a86e1 | 807 | dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl); |
550a7375 FB |
808 | else { |
809 | ERR("Stopping host session -- babble\n"); | |
1c25fda4 | 810 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); |
550a7375 | 811 | } |
a04d46d0 | 812 | } else { |
5c8a86e1 | 813 | dev_dbg(musb->controller, "BUS RESET as %s\n", |
42c0bf1c | 814 | usb_otg_state_string(musb->xceiv->state)); |
84e250ff | 815 | switch (musb->xceiv->state) { |
550a7375 | 816 | case OTG_STATE_A_SUSPEND: |
550a7375 FB |
817 | musb_g_reset(musb); |
818 | /* FALLTHROUGH */ | |
819 | case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ | |
f7f9d63e | 820 | /* never use invalid T(a_wait_bcon) */ |
5c8a86e1 | 821 | dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", |
42c0bf1c | 822 | usb_otg_state_string(musb->xceiv->state), |
3df00453 | 823 | TA_WAIT_BCON(musb)); |
f7f9d63e DB |
824 | mod_timer(&musb->otg_timer, jiffies |
825 | + msecs_to_jiffies(TA_WAIT_BCON(musb))); | |
550a7375 FB |
826 | break; |
827 | case OTG_STATE_A_PERIPHERAL: | |
1de00dae DB |
828 | del_timer(&musb->otg_timer); |
829 | musb_g_reset(musb); | |
550a7375 FB |
830 | break; |
831 | case OTG_STATE_B_WAIT_ACON: | |
5c8a86e1 | 832 | dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", |
42c0bf1c | 833 | usb_otg_state_string(musb->xceiv->state)); |
84e250ff | 834 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
835 | musb_g_reset(musb); |
836 | break; | |
550a7375 | 837 | case OTG_STATE_B_IDLE: |
84e250ff | 838 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
839 | /* FALLTHROUGH */ |
840 | case OTG_STATE_B_PERIPHERAL: | |
841 | musb_g_reset(musb); | |
842 | break; | |
843 | default: | |
5c8a86e1 | 844 | dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", |
42c0bf1c | 845 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
846 | } |
847 | } | |
550a7375 | 848 | } |
550a7375 FB |
849 | |
850 | #if 0 | |
851 | /* REVISIT ... this would be for multiplexing periodic endpoints, or | |
852 | * supporting transfer phasing to prevent exceeding ISO bandwidth | |
853 | * limits of a given frame or microframe. | |
854 | * | |
855 | * It's not needed for peripheral side, which dedicates endpoints; | |
856 | * though it _might_ use SOF irqs for other purposes. | |
857 | * | |
858 | * And it's not currently needed for host side, which also dedicates | |
859 | * endpoints, relies on TX/RX interval registers, and isn't claimed | |
860 | * to support ISO transfers yet. | |
861 | */ | |
862 | if (int_usb & MUSB_INTR_SOF) { | |
863 | void __iomem *mbase = musb->mregs; | |
864 | struct musb_hw_ep *ep; | |
865 | u8 epnum; | |
866 | u16 frame; | |
867 | ||
5c8a86e1 | 868 | dev_dbg(musb->controller, "START_OF_FRAME\n"); |
550a7375 FB |
869 | handled = IRQ_HANDLED; |
870 | ||
871 | /* start any periodic Tx transfers waiting for current frame */ | |
872 | frame = musb_readw(mbase, MUSB_FRAME); | |
873 | ep = musb->endpoints; | |
874 | for (epnum = 1; (epnum < musb->nr_endpoints) | |
875 | && (musb->epmask >= (1 << epnum)); | |
876 | epnum++, ep++) { | |
877 | /* | |
878 | * FIXME handle framecounter wraps (12 bits) | |
879 | * eliminate duplicated StartUrb logic | |
880 | */ | |
881 | if (ep->dwWaitFrame >= frame) { | |
882 | ep->dwWaitFrame = 0; | |
883 | pr_debug("SOF --> periodic TX%s on %d\n", | |
884 | ep->tx_channel ? " DMA" : "", | |
885 | epnum); | |
886 | if (!ep->tx_channel) | |
887 | musb_h_tx_start(musb, epnum); | |
888 | else | |
889 | cppi_hostdma_start(musb, epnum); | |
890 | } | |
891 | } /* end of for loop */ | |
892 | } | |
893 | #endif | |
894 | ||
1c25fda4 | 895 | schedule_work(&musb->irq_work); |
550a7375 FB |
896 | |
897 | return handled; | |
898 | } | |
899 | ||
900 | /*-------------------------------------------------------------------------*/ | |
901 | ||
550a7375 FB |
902 | static void musb_generic_disable(struct musb *musb) |
903 | { | |
904 | void __iomem *mbase = musb->mregs; | |
905 | u16 temp; | |
906 | ||
907 | /* disable interrupts */ | |
908 | musb_writeb(mbase, MUSB_INTRUSBE, 0); | |
b18d26f6 | 909 | musb->intrtxe = 0; |
550a7375 | 910 | musb_writew(mbase, MUSB_INTRTXE, 0); |
af5ec14d | 911 | musb->intrrxe = 0; |
550a7375 FB |
912 | musb_writew(mbase, MUSB_INTRRXE, 0); |
913 | ||
914 | /* off */ | |
915 | musb_writeb(mbase, MUSB_DEVCTL, 0); | |
916 | ||
917 | /* flush pending interrupts */ | |
918 | temp = musb_readb(mbase, MUSB_INTRUSB); | |
919 | temp = musb_readw(mbase, MUSB_INTRTX); | |
920 | temp = musb_readw(mbase, MUSB_INTRRX); | |
921 | ||
922 | } | |
923 | ||
001dd84a SAS |
924 | /* |
925 | * Program the HDRC to start (enable interrupts, dma, etc.). | |
926 | */ | |
927 | void musb_start(struct musb *musb) | |
928 | { | |
929 | void __iomem *regs = musb->mregs; | |
930 | u8 devctl = musb_readb(regs, MUSB_DEVCTL); | |
931 | ||
932 | dev_dbg(musb->controller, "<== devctl %02x\n", devctl); | |
933 | ||
934 | /* Set INT enable registers, enable interrupts */ | |
935 | musb->intrtxe = musb->epmask; | |
936 | musb_writew(regs, MUSB_INTRTXE, musb->intrtxe); | |
937 | musb->intrrxe = musb->epmask & 0xfffe; | |
938 | musb_writew(regs, MUSB_INTRRXE, musb->intrrxe); | |
939 | musb_writeb(regs, MUSB_INTRUSBE, 0xf7); | |
940 | ||
941 | musb_writeb(regs, MUSB_TESTMODE, 0); | |
942 | ||
943 | /* put into basic highspeed mode and start session */ | |
944 | musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE | |
945 | | MUSB_POWER_HSENAB | |
946 | /* ENSUSPEND wedges tusb */ | |
947 | /* | MUSB_POWER_ENSUSPEND */ | |
948 | ); | |
949 | ||
950 | musb->is_active = 0; | |
951 | devctl = musb_readb(regs, MUSB_DEVCTL); | |
952 | devctl &= ~MUSB_DEVCTL_SESSION; | |
953 | ||
954 | /* session started after: | |
955 | * (a) ID-grounded irq, host mode; | |
956 | * (b) vbus present/connect IRQ, peripheral mode; | |
957 | * (c) peripheral initiates, using SRP | |
958 | */ | |
959 | if (musb->port_mode != MUSB_PORT_MODE_HOST && | |
960 | (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) { | |
961 | musb->is_active = 1; | |
962 | } else { | |
963 | devctl |= MUSB_DEVCTL_SESSION; | |
964 | } | |
965 | ||
966 | musb_platform_enable(musb); | |
967 | musb_writeb(regs, MUSB_DEVCTL, devctl); | |
968 | } | |
969 | ||
550a7375 FB |
970 | /* |
971 | * Make the HDRC stop (disable interrupts, etc.); | |
972 | * reversible by musb_start | |
973 | * called on gadget driver unregister | |
974 | * with controller locked, irqs blocked | |
975 | * acts as a NOP unless some role activated the hardware | |
976 | */ | |
977 | void musb_stop(struct musb *musb) | |
978 | { | |
979 | /* stop IRQs, timers, ... */ | |
980 | musb_platform_disable(musb); | |
981 | musb_generic_disable(musb); | |
5c8a86e1 | 982 | dev_dbg(musb->controller, "HDRC disabled\n"); |
550a7375 FB |
983 | |
984 | /* FIXME | |
985 | * - mark host and/or peripheral drivers unusable/inactive | |
986 | * - disable DMA (and enable it in HdrcStart) | |
987 | * - make sure we can musb_start() after musb_stop(); with | |
988 | * OTG mode, gadget driver module rmmod/modprobe cycles that | |
989 | * - ... | |
990 | */ | |
991 | musb_platform_try_idle(musb, 0); | |
992 | } | |
993 | ||
994 | static void musb_shutdown(struct platform_device *pdev) | |
995 | { | |
996 | struct musb *musb = dev_to_musb(&pdev->dev); | |
997 | unsigned long flags; | |
998 | ||
4f9edd2d | 999 | pm_runtime_get_sync(musb->controller); |
24307cae | 1000 | |
2cc65fea | 1001 | musb_host_cleanup(musb); |
24307cae GI |
1002 | musb_gadget_cleanup(musb); |
1003 | ||
550a7375 FB |
1004 | spin_lock_irqsave(&musb->lock, flags); |
1005 | musb_platform_disable(musb); | |
1006 | musb_generic_disable(musb); | |
550a7375 FB |
1007 | spin_unlock_irqrestore(&musb->lock, flags); |
1008 | ||
120d074c GI |
1009 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); |
1010 | musb_platform_exit(musb); | |
120d074c | 1011 | |
4f9edd2d | 1012 | pm_runtime_put(musb->controller); |
550a7375 FB |
1013 | /* FIXME power down */ |
1014 | } | |
1015 | ||
1016 | ||
1017 | /*-------------------------------------------------------------------------*/ | |
1018 | ||
1019 | /* | |
1020 | * The silicon either has hard-wired endpoint configurations, or else | |
1021 | * "dynamic fifo" sizing. The driver has support for both, though at this | |
c767c1c6 DB |
1022 | * writing only the dynamic sizing is very well tested. Since we switched |
1023 | * away from compile-time hardware parameters, we can no longer rely on | |
1024 | * dead code elimination to leave only the relevant one in the object file. | |
550a7375 FB |
1025 | * |
1026 | * We don't currently use dynamic fifo setup capability to do anything | |
1027 | * more than selecting one of a bunch of predefined configurations. | |
1028 | */ | |
ee34e51a FB |
1029 | #if defined(CONFIG_USB_MUSB_TUSB6010) \ |
1030 | || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \ | |
1031 | || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ | |
1032 | || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \ | |
1033 | || defined(CONFIG_USB_MUSB_AM35X) \ | |
9ecb8875 AKG |
1034 | || defined(CONFIG_USB_MUSB_AM35X_MODULE) \ |
1035 | || defined(CONFIG_USB_MUSB_DSPS) \ | |
1036 | || defined(CONFIG_USB_MUSB_DSPS_MODULE) | |
d3608b6d | 1037 | static ushort fifo_mode = 4; |
ee34e51a FB |
1038 | #elif defined(CONFIG_USB_MUSB_UX500) \ |
1039 | || defined(CONFIG_USB_MUSB_UX500_MODULE) | |
d3608b6d | 1040 | static ushort fifo_mode = 5; |
550a7375 | 1041 | #else |
d3608b6d | 1042 | static ushort fifo_mode = 2; |
550a7375 FB |
1043 | #endif |
1044 | ||
1045 | /* "modprobe ... fifo_mode=1" etc */ | |
1046 | module_param(fifo_mode, ushort, 0); | |
1047 | MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); | |
1048 | ||
550a7375 FB |
1049 | /* |
1050 | * tables defining fifo_mode values. define more if you like. | |
1051 | * for host side, make sure both halves of ep1 are set up. | |
1052 | */ | |
1053 | ||
1054 | /* mode 0 - fits in 2KB */ | |
d3608b6d | 1055 | static struct musb_fifo_cfg mode_0_cfg[] = { |
550a7375 FB |
1056 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1057 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1058 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1059 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1060 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1061 | }; | |
1062 | ||
1063 | /* mode 1 - fits in 4KB */ | |
d3608b6d | 1064 | static struct musb_fifo_cfg mode_1_cfg[] = { |
550a7375 FB |
1065 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
1066 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1067 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1068 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1069 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1070 | }; | |
1071 | ||
1072 | /* mode 2 - fits in 4KB */ | |
d3608b6d | 1073 | static struct musb_fifo_cfg mode_2_cfg[] = { |
550a7375 FB |
1074 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1075 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1076 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1077 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1078 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1079 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1080 | }; | |
1081 | ||
1082 | /* mode 3 - fits in 4KB */ | |
d3608b6d | 1083 | static struct musb_fifo_cfg mode_3_cfg[] = { |
550a7375 FB |
1084 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
1085 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1086 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1087 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1088 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1089 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1090 | }; | |
1091 | ||
1092 | /* mode 4 - fits in 16KB */ | |
d3608b6d | 1093 | static struct musb_fifo_cfg mode_4_cfg[] = { |
550a7375 FB |
1094 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1095 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1096 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1097 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1098 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1099 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1100 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1101 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1102 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1103 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1104 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, | |
1105 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, | |
1106 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, | |
1107 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, | |
1108 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, | |
1109 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, | |
1110 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, | |
1111 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, | |
a483d706 AKG |
1112 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, |
1113 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, | |
1114 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, | |
1115 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, | |
1116 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, | |
1117 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, | |
1118 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, | |
550a7375 FB |
1119 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, |
1120 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1121 | }; | |
1122 | ||
3b151526 | 1123 | /* mode 5 - fits in 8KB */ |
d3608b6d | 1124 | static struct musb_fifo_cfg mode_5_cfg[] = { |
3b151526 AKG |
1125 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1126 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1127 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1128 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1129 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1130 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1131 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1132 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1133 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1134 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1135 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, | |
1136 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, | |
1137 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, | |
1138 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, | |
1139 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, | |
1140 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, | |
1141 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, | |
1142 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, | |
1143 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, | |
1144 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, | |
1145 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, | |
1146 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, | |
1147 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, | |
1148 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, | |
1149 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1150 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1151 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1152 | }; | |
550a7375 FB |
1153 | |
1154 | /* | |
1155 | * configure a fifo; for non-shared endpoints, this may be called | |
1156 | * once for a tx fifo and once for an rx fifo. | |
1157 | * | |
1158 | * returns negative errno or offset for next fifo. | |
1159 | */ | |
41ac7b3a | 1160 | static int |
550a7375 | 1161 | fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, |
e6c213b2 | 1162 | const struct musb_fifo_cfg *cfg, u16 offset) |
550a7375 FB |
1163 | { |
1164 | void __iomem *mbase = musb->mregs; | |
1165 | int size = 0; | |
1166 | u16 maxpacket = cfg->maxpacket; | |
1167 | u16 c_off = offset >> 3; | |
1168 | u8 c_size; | |
1169 | ||
1170 | /* expect hw_ep has already been zero-initialized */ | |
1171 | ||
1172 | size = ffs(max(maxpacket, (u16) 8)) - 1; | |
1173 | maxpacket = 1 << size; | |
1174 | ||
1175 | c_size = size - 3; | |
1176 | if (cfg->mode == BUF_DOUBLE) { | |
ca6d1b13 FB |
1177 | if ((offset + (maxpacket << 1)) > |
1178 | (1 << (musb->config->ram_bits + 2))) | |
550a7375 FB |
1179 | return -EMSGSIZE; |
1180 | c_size |= MUSB_FIFOSZ_DPB; | |
1181 | } else { | |
ca6d1b13 | 1182 | if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) |
550a7375 FB |
1183 | return -EMSGSIZE; |
1184 | } | |
1185 | ||
1186 | /* configure the FIFO */ | |
1187 | musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); | |
1188 | ||
550a7375 FB |
1189 | /* EP0 reserved endpoint for control, bidirectional; |
1190 | * EP1 reserved for bulk, two unidirection halves. | |
1191 | */ | |
1192 | if (hw_ep->epnum == 1) | |
1193 | musb->bulk_ep = hw_ep; | |
1194 | /* REVISIT error check: be sure ep0 can both rx and tx ... */ | |
550a7375 FB |
1195 | switch (cfg->style) { |
1196 | case FIFO_TX: | |
c6cf8b00 BW |
1197 | musb_write_txfifosz(mbase, c_size); |
1198 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1199 | hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1200 | hw_ep->max_packet_sz_tx = maxpacket; | |
1201 | break; | |
1202 | case FIFO_RX: | |
c6cf8b00 BW |
1203 | musb_write_rxfifosz(mbase, c_size); |
1204 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1205 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1206 | hw_ep->max_packet_sz_rx = maxpacket; | |
1207 | break; | |
1208 | case FIFO_RXTX: | |
c6cf8b00 BW |
1209 | musb_write_txfifosz(mbase, c_size); |
1210 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1211 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1212 | hw_ep->max_packet_sz_rx = maxpacket; | |
1213 | ||
c6cf8b00 BW |
1214 | musb_write_rxfifosz(mbase, c_size); |
1215 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1216 | hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; |
1217 | hw_ep->max_packet_sz_tx = maxpacket; | |
1218 | ||
1219 | hw_ep->is_shared_fifo = true; | |
1220 | break; | |
1221 | } | |
1222 | ||
1223 | /* NOTE rx and tx endpoint irqs aren't managed separately, | |
1224 | * which happens to be ok | |
1225 | */ | |
1226 | musb->epmask |= (1 << hw_ep->epnum); | |
1227 | ||
1228 | return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); | |
1229 | } | |
1230 | ||
d3608b6d | 1231 | static struct musb_fifo_cfg ep0_cfg = { |
550a7375 FB |
1232 | .style = FIFO_RXTX, .maxpacket = 64, |
1233 | }; | |
1234 | ||
41ac7b3a | 1235 | static int ep_config_from_table(struct musb *musb) |
550a7375 | 1236 | { |
e6c213b2 | 1237 | const struct musb_fifo_cfg *cfg; |
550a7375 FB |
1238 | unsigned i, n; |
1239 | int offset; | |
1240 | struct musb_hw_ep *hw_ep = musb->endpoints; | |
1241 | ||
e6c213b2 FB |
1242 | if (musb->config->fifo_cfg) { |
1243 | cfg = musb->config->fifo_cfg; | |
1244 | n = musb->config->fifo_cfg_size; | |
1245 | goto done; | |
1246 | } | |
1247 | ||
550a7375 FB |
1248 | switch (fifo_mode) { |
1249 | default: | |
1250 | fifo_mode = 0; | |
1251 | /* FALLTHROUGH */ | |
1252 | case 0: | |
1253 | cfg = mode_0_cfg; | |
1254 | n = ARRAY_SIZE(mode_0_cfg); | |
1255 | break; | |
1256 | case 1: | |
1257 | cfg = mode_1_cfg; | |
1258 | n = ARRAY_SIZE(mode_1_cfg); | |
1259 | break; | |
1260 | case 2: | |
1261 | cfg = mode_2_cfg; | |
1262 | n = ARRAY_SIZE(mode_2_cfg); | |
1263 | break; | |
1264 | case 3: | |
1265 | cfg = mode_3_cfg; | |
1266 | n = ARRAY_SIZE(mode_3_cfg); | |
1267 | break; | |
1268 | case 4: | |
1269 | cfg = mode_4_cfg; | |
1270 | n = ARRAY_SIZE(mode_4_cfg); | |
1271 | break; | |
3b151526 AKG |
1272 | case 5: |
1273 | cfg = mode_5_cfg; | |
1274 | n = ARRAY_SIZE(mode_5_cfg); | |
1275 | break; | |
550a7375 FB |
1276 | } |
1277 | ||
1278 | printk(KERN_DEBUG "%s: setup fifo_mode %d\n", | |
1279 | musb_driver_name, fifo_mode); | |
1280 | ||
1281 | ||
e6c213b2 | 1282 | done: |
550a7375 FB |
1283 | offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); |
1284 | /* assert(offset > 0) */ | |
1285 | ||
1286 | /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would | |
ca6d1b13 | 1287 | * be better than static musb->config->num_eps and DYN_FIFO_SIZE... |
550a7375 FB |
1288 | */ |
1289 | ||
1290 | for (i = 0; i < n; i++) { | |
1291 | u8 epn = cfg->hw_ep_num; | |
1292 | ||
ca6d1b13 | 1293 | if (epn >= musb->config->num_eps) { |
550a7375 FB |
1294 | pr_debug("%s: invalid ep %d\n", |
1295 | musb_driver_name, epn); | |
bb1c9ef1 | 1296 | return -EINVAL; |
550a7375 FB |
1297 | } |
1298 | offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); | |
1299 | if (offset < 0) { | |
1300 | pr_debug("%s: mem overrun, ep %d\n", | |
1301 | musb_driver_name, epn); | |
f69dfa1f | 1302 | return offset; |
550a7375 FB |
1303 | } |
1304 | epn++; | |
1305 | musb->nr_endpoints = max(epn, musb->nr_endpoints); | |
1306 | } | |
1307 | ||
1308 | printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", | |
1309 | musb_driver_name, | |
ca6d1b13 FB |
1310 | n + 1, musb->config->num_eps * 2 - 1, |
1311 | offset, (1 << (musb->config->ram_bits + 2))); | |
550a7375 | 1312 | |
550a7375 FB |
1313 | if (!musb->bulk_ep) { |
1314 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1315 | return -EINVAL; | |
1316 | } | |
550a7375 FB |
1317 | |
1318 | return 0; | |
1319 | } | |
1320 | ||
1321 | ||
1322 | /* | |
1323 | * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false | |
1324 | * @param musb the controller | |
1325 | */ | |
41ac7b3a | 1326 | static int ep_config_from_hw(struct musb *musb) |
550a7375 | 1327 | { |
c6cf8b00 | 1328 | u8 epnum = 0; |
550a7375 | 1329 | struct musb_hw_ep *hw_ep; |
a156544b | 1330 | void __iomem *mbase = musb->mregs; |
c6cf8b00 | 1331 | int ret = 0; |
550a7375 | 1332 | |
5c8a86e1 | 1333 | dev_dbg(musb->controller, "<== static silicon ep config\n"); |
550a7375 FB |
1334 | |
1335 | /* FIXME pick up ep0 maxpacket size */ | |
1336 | ||
ca6d1b13 | 1337 | for (epnum = 1; epnum < musb->config->num_eps; epnum++) { |
550a7375 FB |
1338 | musb_ep_select(mbase, epnum); |
1339 | hw_ep = musb->endpoints + epnum; | |
1340 | ||
c6cf8b00 BW |
1341 | ret = musb_read_fifosize(musb, hw_ep, epnum); |
1342 | if (ret < 0) | |
550a7375 | 1343 | break; |
550a7375 FB |
1344 | |
1345 | /* FIXME set up hw_ep->{rx,tx}_double_buffered */ | |
1346 | ||
550a7375 FB |
1347 | /* pick an RX/TX endpoint for bulk */ |
1348 | if (hw_ep->max_packet_sz_tx < 512 | |
1349 | || hw_ep->max_packet_sz_rx < 512) | |
1350 | continue; | |
1351 | ||
1352 | /* REVISIT: this algorithm is lazy, we should at least | |
1353 | * try to pick a double buffered endpoint. | |
1354 | */ | |
1355 | if (musb->bulk_ep) | |
1356 | continue; | |
1357 | musb->bulk_ep = hw_ep; | |
550a7375 FB |
1358 | } |
1359 | ||
550a7375 FB |
1360 | if (!musb->bulk_ep) { |
1361 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1362 | return -EINVAL; | |
1363 | } | |
550a7375 FB |
1364 | |
1365 | return 0; | |
1366 | } | |
1367 | ||
1368 | enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; | |
1369 | ||
1370 | /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; | |
1371 | * configure endpoints, or take their config from silicon | |
1372 | */ | |
41ac7b3a | 1373 | static int musb_core_init(u16 musb_type, struct musb *musb) |
550a7375 | 1374 | { |
550a7375 FB |
1375 | u8 reg; |
1376 | char *type; | |
0ea52ff4 | 1377 | char aInfo[90], aRevision[32], aDate[12]; |
550a7375 FB |
1378 | void __iomem *mbase = musb->mregs; |
1379 | int status = 0; | |
1380 | int i; | |
1381 | ||
1382 | /* log core options (read using indexed model) */ | |
c6cf8b00 | 1383 | reg = musb_read_configdata(mbase); |
550a7375 FB |
1384 | |
1385 | strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); | |
51bf0d0e | 1386 | if (reg & MUSB_CONFIGDATA_DYNFIFO) { |
550a7375 | 1387 | strcat(aInfo, ", dyn FIFOs"); |
51bf0d0e AKG |
1388 | musb->dyn_fifo = true; |
1389 | } | |
550a7375 FB |
1390 | if (reg & MUSB_CONFIGDATA_MPRXE) { |
1391 | strcat(aInfo, ", bulk combine"); | |
550a7375 | 1392 | musb->bulk_combine = true; |
550a7375 FB |
1393 | } |
1394 | if (reg & MUSB_CONFIGDATA_MPTXE) { | |
1395 | strcat(aInfo, ", bulk split"); | |
550a7375 | 1396 | musb->bulk_split = true; |
550a7375 FB |
1397 | } |
1398 | if (reg & MUSB_CONFIGDATA_HBRXE) { | |
1399 | strcat(aInfo, ", HB-ISO Rx"); | |
a483d706 | 1400 | musb->hb_iso_rx = true; |
550a7375 FB |
1401 | } |
1402 | if (reg & MUSB_CONFIGDATA_HBTXE) { | |
1403 | strcat(aInfo, ", HB-ISO Tx"); | |
a483d706 | 1404 | musb->hb_iso_tx = true; |
550a7375 FB |
1405 | } |
1406 | if (reg & MUSB_CONFIGDATA_SOFTCONE) | |
1407 | strcat(aInfo, ", SoftConn"); | |
1408 | ||
1409 | printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", | |
1410 | musb_driver_name, reg, aInfo); | |
1411 | ||
550a7375 | 1412 | aDate[0] = 0; |
550a7375 FB |
1413 | if (MUSB_CONTROLLER_MHDRC == musb_type) { |
1414 | musb->is_multipoint = 1; | |
1415 | type = "M"; | |
1416 | } else { | |
1417 | musb->is_multipoint = 0; | |
1418 | type = ""; | |
550a7375 FB |
1419 | #ifndef CONFIG_USB_OTG_BLACKLIST_HUB |
1420 | printk(KERN_ERR | |
1421 | "%s: kernel must blacklist external hubs\n", | |
1422 | musb_driver_name); | |
550a7375 FB |
1423 | #endif |
1424 | } | |
1425 | ||
1426 | /* log release info */ | |
32c3b94e AG |
1427 | musb->hwvers = musb_read_hwvers(mbase); |
1428 | snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), | |
1429 | MUSB_HWVERS_MINOR(musb->hwvers), | |
1430 | (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); | |
550a7375 FB |
1431 | printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", |
1432 | musb_driver_name, type, aRevision, aDate); | |
1433 | ||
1434 | /* configure ep0 */ | |
c6cf8b00 | 1435 | musb_configure_ep0(musb); |
550a7375 FB |
1436 | |
1437 | /* discover endpoint configuration */ | |
1438 | musb->nr_endpoints = 1; | |
1439 | musb->epmask = 1; | |
1440 | ||
ad517e9e FB |
1441 | if (musb->dyn_fifo) |
1442 | status = ep_config_from_table(musb); | |
1443 | else | |
1444 | status = ep_config_from_hw(musb); | |
550a7375 FB |
1445 | |
1446 | if (status < 0) | |
1447 | return status; | |
1448 | ||
1449 | /* finish init, and print endpoint config */ | |
1450 | for (i = 0; i < musb->nr_endpoints; i++) { | |
1451 | struct musb_hw_ep *hw_ep = musb->endpoints + i; | |
1452 | ||
1453 | hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; | |
9a35f876 | 1454 | #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE) |
550a7375 FB |
1455 | hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); |
1456 | hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); | |
1457 | hw_ep->fifo_sync_va = | |
1458 | musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); | |
1459 | ||
1460 | if (i == 0) | |
1461 | hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; | |
1462 | else | |
1463 | hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); | |
1464 | #endif | |
1465 | ||
1466 | hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; | |
c6cf8b00 | 1467 | hw_ep->target_regs = musb_read_target_reg_base(i, mbase); |
550a7375 FB |
1468 | hw_ep->rx_reinit = 1; |
1469 | hw_ep->tx_reinit = 1; | |
550a7375 FB |
1470 | |
1471 | if (hw_ep->max_packet_sz_tx) { | |
5c8a86e1 | 1472 | dev_dbg(musb->controller, |
550a7375 FB |
1473 | "%s: hw_ep %d%s, %smax %d\n", |
1474 | musb_driver_name, i, | |
1475 | hw_ep->is_shared_fifo ? "shared" : "tx", | |
1476 | hw_ep->tx_double_buffered | |
1477 | ? "doublebuffer, " : "", | |
1478 | hw_ep->max_packet_sz_tx); | |
1479 | } | |
1480 | if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { | |
5c8a86e1 | 1481 | dev_dbg(musb->controller, |
550a7375 FB |
1482 | "%s: hw_ep %d%s, %smax %d\n", |
1483 | musb_driver_name, i, | |
1484 | "rx", | |
1485 | hw_ep->rx_double_buffered | |
1486 | ? "doublebuffer, " : "", | |
1487 | hw_ep->max_packet_sz_rx); | |
1488 | } | |
1489 | if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) | |
5c8a86e1 | 1490 | dev_dbg(musb->controller, "hw_ep %d not configured\n", i); |
550a7375 FB |
1491 | } |
1492 | ||
1493 | return 0; | |
1494 | } | |
1495 | ||
1496 | /*-------------------------------------------------------------------------*/ | |
1497 | ||
550a7375 FB |
1498 | /* |
1499 | * handle all the irqs defined by the HDRC core. for now we expect: other | |
1500 | * irq sources (phy, dma, etc) will be handled first, musb->int_* values | |
1501 | * will be assigned, and the irq will already have been acked. | |
1502 | * | |
1503 | * called in irq context with spinlock held, irqs blocked | |
1504 | */ | |
1505 | irqreturn_t musb_interrupt(struct musb *musb) | |
1506 | { | |
1507 | irqreturn_t retval = IRQ_NONE; | |
b11e94d0 | 1508 | u8 devctl; |
550a7375 FB |
1509 | int ep_num; |
1510 | u32 reg; | |
1511 | ||
1512 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
550a7375 | 1513 | |
5c8a86e1 | 1514 | dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", |
550a7375 FB |
1515 | (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", |
1516 | musb->int_usb, musb->int_tx, musb->int_rx); | |
1517 | ||
1518 | /* the core can interrupt us for multiple reasons; docs have | |
1519 | * a generic interrupt flowchart to follow | |
1520 | */ | |
7d9645fd | 1521 | if (musb->int_usb) |
550a7375 | 1522 | retval |= musb_stage0_irq(musb, musb->int_usb, |
b11e94d0 | 1523 | devctl); |
550a7375 FB |
1524 | |
1525 | /* "stage 1" is handling endpoint irqs */ | |
1526 | ||
1527 | /* handle endpoint 0 first */ | |
1528 | if (musb->int_tx & 1) { | |
1529 | if (devctl & MUSB_DEVCTL_HM) | |
1530 | retval |= musb_h_ep0_irq(musb); | |
1531 | else | |
1532 | retval |= musb_g_ep0_irq(musb); | |
1533 | } | |
1534 | ||
1535 | /* RX on endpoints 1-15 */ | |
1536 | reg = musb->int_rx >> 1; | |
1537 | ep_num = 1; | |
1538 | while (reg) { | |
1539 | if (reg & 1) { | |
1540 | /* musb_ep_select(musb->mregs, ep_num); */ | |
1541 | /* REVISIT just retval = ep->rx_irq(...) */ | |
1542 | retval = IRQ_HANDLED; | |
a04d46d0 FB |
1543 | if (devctl & MUSB_DEVCTL_HM) |
1544 | musb_host_rx(musb, ep_num); | |
1545 | else | |
1546 | musb_g_rx(musb, ep_num); | |
550a7375 FB |
1547 | } |
1548 | ||
1549 | reg >>= 1; | |
1550 | ep_num++; | |
1551 | } | |
1552 | ||
1553 | /* TX on endpoints 1-15 */ | |
1554 | reg = musb->int_tx >> 1; | |
1555 | ep_num = 1; | |
1556 | while (reg) { | |
1557 | if (reg & 1) { | |
1558 | /* musb_ep_select(musb->mregs, ep_num); */ | |
1559 | /* REVISIT just retval |= ep->tx_irq(...) */ | |
1560 | retval = IRQ_HANDLED; | |
a04d46d0 FB |
1561 | if (devctl & MUSB_DEVCTL_HM) |
1562 | musb_host_tx(musb, ep_num); | |
1563 | else | |
1564 | musb_g_tx(musb, ep_num); | |
550a7375 FB |
1565 | } |
1566 | reg >>= 1; | |
1567 | ep_num++; | |
1568 | } | |
1569 | ||
550a7375 FB |
1570 | return retval; |
1571 | } | |
981430a1 | 1572 | EXPORT_SYMBOL_GPL(musb_interrupt); |
550a7375 FB |
1573 | |
1574 | #ifndef CONFIG_MUSB_PIO_ONLY | |
d3608b6d | 1575 | static bool use_dma = 1; |
550a7375 FB |
1576 | |
1577 | /* "modprobe ... use_dma=0" etc */ | |
1578 | module_param(use_dma, bool, 0); | |
1579 | MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); | |
1580 | ||
1581 | void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) | |
1582 | { | |
1583 | u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1584 | ||
1585 | /* called with controller lock already held */ | |
1586 | ||
1587 | if (!epnum) { | |
1588 | #ifndef CONFIG_USB_TUSB_OMAP_DMA | |
1589 | if (!is_cppi_enabled()) { | |
1590 | /* endpoint 0 */ | |
1591 | if (devctl & MUSB_DEVCTL_HM) | |
1592 | musb_h_ep0_irq(musb); | |
1593 | else | |
1594 | musb_g_ep0_irq(musb); | |
1595 | } | |
1596 | #endif | |
1597 | } else { | |
1598 | /* endpoints 1..15 */ | |
1599 | if (transmit) { | |
a04d46d0 FB |
1600 | if (devctl & MUSB_DEVCTL_HM) |
1601 | musb_host_tx(musb, epnum); | |
1602 | else | |
1603 | musb_g_tx(musb, epnum); | |
550a7375 FB |
1604 | } else { |
1605 | /* receive */ | |
a04d46d0 FB |
1606 | if (devctl & MUSB_DEVCTL_HM) |
1607 | musb_host_rx(musb, epnum); | |
1608 | else | |
1609 | musb_g_rx(musb, epnum); | |
550a7375 FB |
1610 | } |
1611 | } | |
1612 | } | |
9a35f876 | 1613 | EXPORT_SYMBOL_GPL(musb_dma_completion); |
550a7375 FB |
1614 | |
1615 | #else | |
1616 | #define use_dma 0 | |
1617 | #endif | |
1618 | ||
1619 | /*-------------------------------------------------------------------------*/ | |
1620 | ||
550a7375 FB |
1621 | static ssize_t |
1622 | musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1623 | { | |
1624 | struct musb *musb = dev_to_musb(dev); | |
1625 | unsigned long flags; | |
1626 | int ret = -EINVAL; | |
1627 | ||
1628 | spin_lock_irqsave(&musb->lock, flags); | |
42c0bf1c | 1629 | ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
1630 | spin_unlock_irqrestore(&musb->lock, flags); |
1631 | ||
1632 | return ret; | |
1633 | } | |
1634 | ||
1635 | static ssize_t | |
1636 | musb_mode_store(struct device *dev, struct device_attribute *attr, | |
1637 | const char *buf, size_t n) | |
1638 | { | |
1639 | struct musb *musb = dev_to_musb(dev); | |
1640 | unsigned long flags; | |
96a274d1 | 1641 | int status; |
550a7375 FB |
1642 | |
1643 | spin_lock_irqsave(&musb->lock, flags); | |
96a274d1 DB |
1644 | if (sysfs_streq(buf, "host")) |
1645 | status = musb_platform_set_mode(musb, MUSB_HOST); | |
1646 | else if (sysfs_streq(buf, "peripheral")) | |
1647 | status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); | |
1648 | else if (sysfs_streq(buf, "otg")) | |
1649 | status = musb_platform_set_mode(musb, MUSB_OTG); | |
1650 | else | |
1651 | status = -EINVAL; | |
550a7375 FB |
1652 | spin_unlock_irqrestore(&musb->lock, flags); |
1653 | ||
96a274d1 | 1654 | return (status == 0) ? n : status; |
550a7375 FB |
1655 | } |
1656 | static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); | |
1657 | ||
1658 | static ssize_t | |
1659 | musb_vbus_store(struct device *dev, struct device_attribute *attr, | |
1660 | const char *buf, size_t n) | |
1661 | { | |
1662 | struct musb *musb = dev_to_musb(dev); | |
1663 | unsigned long flags; | |
1664 | unsigned long val; | |
1665 | ||
1666 | if (sscanf(buf, "%lu", &val) < 1) { | |
b3b1cc3b | 1667 | dev_err(dev, "Invalid VBUS timeout ms value\n"); |
550a7375 FB |
1668 | return -EINVAL; |
1669 | } | |
1670 | ||
1671 | spin_lock_irqsave(&musb->lock, flags); | |
f7f9d63e DB |
1672 | /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ |
1673 | musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; | |
84e250ff | 1674 | if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) |
550a7375 FB |
1675 | musb->is_active = 0; |
1676 | musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); | |
1677 | spin_unlock_irqrestore(&musb->lock, flags); | |
1678 | ||
1679 | return n; | |
1680 | } | |
1681 | ||
1682 | static ssize_t | |
1683 | musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1684 | { | |
1685 | struct musb *musb = dev_to_musb(dev); | |
1686 | unsigned long flags; | |
1687 | unsigned long val; | |
1688 | int vbus; | |
1689 | ||
1690 | spin_lock_irqsave(&musb->lock, flags); | |
1691 | val = musb->a_wait_bcon; | |
f7f9d63e DB |
1692 | /* FIXME get_vbus_status() is normally #defined as false... |
1693 | * and is effectively TUSB-specific. | |
1694 | */ | |
550a7375 FB |
1695 | vbus = musb_platform_get_vbus_status(musb); |
1696 | spin_unlock_irqrestore(&musb->lock, flags); | |
1697 | ||
f7f9d63e | 1698 | return sprintf(buf, "Vbus %s, timeout %lu msec\n", |
550a7375 FB |
1699 | vbus ? "on" : "off", val); |
1700 | } | |
1701 | static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); | |
1702 | ||
550a7375 FB |
1703 | /* Gadget drivers can't know that a host is connected so they might want |
1704 | * to start SRP, but users can. This allows userspace to trigger SRP. | |
1705 | */ | |
1706 | static ssize_t | |
1707 | musb_srp_store(struct device *dev, struct device_attribute *attr, | |
1708 | const char *buf, size_t n) | |
1709 | { | |
1710 | struct musb *musb = dev_to_musb(dev); | |
1711 | unsigned short srp; | |
1712 | ||
1713 | if (sscanf(buf, "%hu", &srp) != 1 | |
1714 | || (srp != 1)) { | |
b3b1cc3b | 1715 | dev_err(dev, "SRP: Value must be 1\n"); |
550a7375 FB |
1716 | return -EINVAL; |
1717 | } | |
1718 | ||
1719 | if (srp == 1) | |
1720 | musb_g_wakeup(musb); | |
1721 | ||
1722 | return n; | |
1723 | } | |
1724 | static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); | |
1725 | ||
94375751 FB |
1726 | static struct attribute *musb_attributes[] = { |
1727 | &dev_attr_mode.attr, | |
1728 | &dev_attr_vbus.attr, | |
94375751 | 1729 | &dev_attr_srp.attr, |
94375751 FB |
1730 | NULL |
1731 | }; | |
1732 | ||
1733 | static const struct attribute_group musb_attr_group = { | |
1734 | .attrs = musb_attributes, | |
1735 | }; | |
1736 | ||
550a7375 FB |
1737 | /* Only used to provide driver mode change events */ |
1738 | static void musb_irq_work(struct work_struct *data) | |
1739 | { | |
1740 | struct musb *musb = container_of(data, struct musb, irq_work); | |
550a7375 | 1741 | |
8d2421e6 AKG |
1742 | if (musb->xceiv->state != musb->xceiv_old_state) { |
1743 | musb->xceiv_old_state = musb->xceiv->state; | |
550a7375 FB |
1744 | sysfs_notify(&musb->controller->kobj, NULL, "mode"); |
1745 | } | |
1746 | } | |
1747 | ||
1748 | /* -------------------------------------------------------------------------- | |
1749 | * Init support | |
1750 | */ | |
1751 | ||
41ac7b3a | 1752 | static struct musb *allocate_instance(struct device *dev, |
ca6d1b13 | 1753 | struct musb_hdrc_config *config, void __iomem *mbase) |
550a7375 FB |
1754 | { |
1755 | struct musb *musb; | |
1756 | struct musb_hw_ep *ep; | |
1757 | int epnum; | |
74c2e936 | 1758 | int ret; |
550a7375 | 1759 | |
74c2e936 DM |
1760 | musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL); |
1761 | if (!musb) | |
550a7375 | 1762 | return NULL; |
550a7375 | 1763 | |
550a7375 FB |
1764 | INIT_LIST_HEAD(&musb->control); |
1765 | INIT_LIST_HEAD(&musb->in_bulk); | |
1766 | INIT_LIST_HEAD(&musb->out_bulk); | |
1767 | ||
550a7375 | 1768 | musb->vbuserr_retry = VBUSERR_RETRY_COUNT; |
f7f9d63e | 1769 | musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; |
550a7375 FB |
1770 | musb->mregs = mbase; |
1771 | musb->ctrl_base = mbase; | |
1772 | musb->nIrq = -ENODEV; | |
ca6d1b13 | 1773 | musb->config = config; |
02582b92 | 1774 | BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); |
550a7375 | 1775 | for (epnum = 0, ep = musb->endpoints; |
ca6d1b13 | 1776 | epnum < musb->config->num_eps; |
550a7375 | 1777 | epnum++, ep++) { |
550a7375 FB |
1778 | ep->musb = musb; |
1779 | ep->epnum = epnum; | |
1780 | } | |
1781 | ||
1782 | musb->controller = dev; | |
743411b3 | 1783 | |
74c2e936 DM |
1784 | ret = musb_host_alloc(musb); |
1785 | if (ret < 0) | |
1786 | goto err_free; | |
1787 | ||
1788 | dev_set_drvdata(dev, musb); | |
1789 | ||
550a7375 | 1790 | return musb; |
74c2e936 DM |
1791 | |
1792 | err_free: | |
1793 | return NULL; | |
550a7375 FB |
1794 | } |
1795 | ||
1796 | static void musb_free(struct musb *musb) | |
1797 | { | |
1798 | /* this has multiple entry modes. it handles fault cleanup after | |
1799 | * probe(), where things may be partially set up, as well as rmmod | |
1800 | * cleanup after everything's been de-activated. | |
1801 | */ | |
1802 | ||
1803 | #ifdef CONFIG_SYSFS | |
94375751 | 1804 | sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); |
550a7375 FB |
1805 | #endif |
1806 | ||
97a39896 AKG |
1807 | if (musb->nIrq >= 0) { |
1808 | if (musb->irq_wake) | |
1809 | disable_irq_wake(musb->nIrq); | |
550a7375 FB |
1810 | free_irq(musb->nIrq, musb); |
1811 | } | |
6904b845 | 1812 | if (musb->dma_controller) |
66c01883 | 1813 | dma_controller_destroy(musb->dma_controller); |
550a7375 | 1814 | |
74c2e936 | 1815 | musb_host_free(musb); |
550a7375 FB |
1816 | } |
1817 | ||
1818 | /* | |
1819 | * Perform generic per-controller initialization. | |
1820 | * | |
28dd924a SS |
1821 | * @dev: the controller (already clocked, etc) |
1822 | * @nIrq: IRQ number | |
1823 | * @ctrl: virtual address of controller registers, | |
550a7375 FB |
1824 | * not yet corrected for platform-specific offsets |
1825 | */ | |
41ac7b3a | 1826 | static int |
550a7375 FB |
1827 | musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) |
1828 | { | |
1829 | int status; | |
1830 | struct musb *musb; | |
c1a7d67c | 1831 | struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); |
550a7375 FB |
1832 | |
1833 | /* The driver might handle more features than the board; OK. | |
1834 | * Fail when the board needs a feature that's not enabled. | |
1835 | */ | |
1836 | if (!plat) { | |
1837 | dev_dbg(dev, "no platform_data?\n"); | |
34e2beb2 SS |
1838 | status = -ENODEV; |
1839 | goto fail0; | |
550a7375 | 1840 | } |
34e2beb2 | 1841 | |
550a7375 | 1842 | /* allocate */ |
ca6d1b13 | 1843 | musb = allocate_instance(dev, plat->config, ctrl); |
34e2beb2 SS |
1844 | if (!musb) { |
1845 | status = -ENOMEM; | |
1846 | goto fail0; | |
1847 | } | |
550a7375 | 1848 | |
7acc6197 HH |
1849 | pm_runtime_use_autosuspend(musb->controller); |
1850 | pm_runtime_set_autosuspend_delay(musb->controller, 200); | |
1851 | pm_runtime_enable(musb->controller); | |
1852 | ||
550a7375 | 1853 | spin_lock_init(&musb->lock); |
550a7375 | 1854 | musb->board_set_power = plat->set_power; |
550a7375 | 1855 | musb->min_power = plat->min_power; |
f7ec9437 | 1856 | musb->ops = plat->platform_ops; |
9ad96e69 | 1857 | musb->port_mode = plat->mode; |
550a7375 | 1858 | |
84e250ff | 1859 | /* The musb_platform_init() call: |
baef653a PDS |
1860 | * - adjusts musb->mregs |
1861 | * - sets the musb->isr | |
84e250ff | 1862 | * - may initialize an integrated tranceiver |
721002ec | 1863 | * - initializes musb->xceiv, usually by otg_get_phy() |
84e250ff | 1864 | * - stops powering VBUS |
84e250ff | 1865 | * |
7c9d440e | 1866 | * There are various transceiver configurations. Blackfin, |
84e250ff DB |
1867 | * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses |
1868 | * external/discrete ones in various flavors (twl4030 family, | |
1869 | * isp1504, non-OTG, etc) mostly hooking up through ULPI. | |
550a7375 | 1870 | */ |
ea65df57 | 1871 | status = musb_platform_init(musb); |
550a7375 | 1872 | if (status < 0) |
03491761 | 1873 | goto fail1; |
34e2beb2 | 1874 | |
550a7375 FB |
1875 | if (!musb->isr) { |
1876 | status = -ENODEV; | |
c04352a5 | 1877 | goto fail2; |
550a7375 FB |
1878 | } |
1879 | ||
ffb865b1 | 1880 | if (!musb->xceiv->io_ops) { |
bf070bc1 | 1881 | musb->xceiv->io_dev = musb->controller; |
ffb865b1 HK |
1882 | musb->xceiv->io_priv = musb->mregs; |
1883 | musb->xceiv->io_ops = &musb_ulpi_access; | |
1884 | } | |
1885 | ||
c04352a5 GI |
1886 | pm_runtime_get_sync(musb->controller); |
1887 | ||
66c01883 SAS |
1888 | if (use_dma && dev->dma_mask) |
1889 | musb->dma_controller = dma_controller_create(musb, musb->mregs); | |
550a7375 FB |
1890 | |
1891 | /* be sure interrupts are disabled before connecting ISR */ | |
1892 | musb_platform_disable(musb); | |
1893 | musb_generic_disable(musb); | |
1894 | ||
1895 | /* setup musb parts of the core (especially endpoints) */ | |
ca6d1b13 | 1896 | status = musb_core_init(plat->config->multipoint |
550a7375 FB |
1897 | ? MUSB_CONTROLLER_MHDRC |
1898 | : MUSB_CONTROLLER_HDRC, musb); | |
1899 | if (status < 0) | |
34e2beb2 | 1900 | goto fail3; |
550a7375 | 1901 | |
f7f9d63e | 1902 | setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); |
f7f9d63e | 1903 | |
550a7375 FB |
1904 | /* Init IRQ workqueue before request_irq */ |
1905 | INIT_WORK(&musb->irq_work, musb_irq_work); | |
1906 | ||
1907 | /* attach to the IRQ */ | |
427c4f33 | 1908 | if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { |
550a7375 FB |
1909 | dev_err(dev, "request_irq %d failed!\n", nIrq); |
1910 | status = -ENODEV; | |
34e2beb2 | 1911 | goto fail3; |
550a7375 FB |
1912 | } |
1913 | musb->nIrq = nIrq; | |
032ec49f | 1914 | /* FIXME this handles wakeup irqs wrong */ |
c48a5155 FB |
1915 | if (enable_irq_wake(nIrq) == 0) { |
1916 | musb->irq_wake = 1; | |
550a7375 | 1917 | device_init_wakeup(dev, 1); |
c48a5155 FB |
1918 | } else { |
1919 | musb->irq_wake = 0; | |
1920 | } | |
550a7375 | 1921 | |
032ec49f FB |
1922 | /* program PHY to use external vBus if required */ |
1923 | if (plat->extvbus) { | |
1924 | u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); | |
1925 | busctl |= MUSB_ULPI_USE_EXTVBUS; | |
1926 | musb_write_ulpi_buscontrol(musb->mregs, busctl); | |
550a7375 | 1927 | } |
550a7375 | 1928 | |
e5615112 GI |
1929 | if (musb->xceiv->otg->default_a) { |
1930 | MUSB_HST_MODE(musb); | |
1931 | musb->xceiv->state = OTG_STATE_A_IDLE; | |
1932 | } else { | |
1933 | MUSB_DEV_MODE(musb); | |
1934 | musb->xceiv->state = OTG_STATE_B_IDLE; | |
1935 | } | |
550a7375 | 1936 | |
6c5f6a6f DM |
1937 | switch (musb->port_mode) { |
1938 | case MUSB_PORT_MODE_HOST: | |
1939 | status = musb_host_setup(musb, plat->power); | |
1940 | break; | |
1941 | case MUSB_PORT_MODE_GADGET: | |
1942 | status = musb_gadget_setup(musb); | |
1943 | break; | |
1944 | case MUSB_PORT_MODE_DUAL_ROLE: | |
1945 | status = musb_host_setup(musb, plat->power); | |
1946 | if (status < 0) | |
1947 | goto fail3; | |
1948 | status = musb_gadget_setup(musb); | |
1949 | break; | |
1950 | default: | |
1951 | dev_err(dev, "unsupported port mode %d\n", musb->port_mode); | |
1952 | break; | |
1953 | } | |
550a7375 | 1954 | |
461972d8 | 1955 | if (status < 0) |
34e2beb2 | 1956 | goto fail3; |
550a7375 | 1957 | |
7f7f9e2a FB |
1958 | status = musb_init_debugfs(musb); |
1959 | if (status < 0) | |
b0f9da7e | 1960 | goto fail4; |
7f7f9e2a | 1961 | |
94375751 | 1962 | status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); |
28c2c51c | 1963 | if (status) |
b0f9da7e | 1964 | goto fail5; |
550a7375 | 1965 | |
c04352a5 GI |
1966 | pm_runtime_put(musb->controller); |
1967 | ||
28c2c51c | 1968 | return 0; |
550a7375 | 1969 | |
b0f9da7e FB |
1970 | fail5: |
1971 | musb_exit_debugfs(musb); | |
1972 | ||
34e2beb2 | 1973 | fail4: |
032ec49f | 1974 | musb_gadget_cleanup(musb); |
34e2beb2 SS |
1975 | |
1976 | fail3: | |
f3ce4d5b SAS |
1977 | if (musb->dma_controller) |
1978 | dma_controller_destroy(musb->dma_controller); | |
c04352a5 GI |
1979 | pm_runtime_put_sync(musb->controller); |
1980 | ||
1981 | fail2: | |
34e2beb2 SS |
1982 | if (musb->irq_wake) |
1983 | device_init_wakeup(dev, 0); | |
550a7375 | 1984 | musb_platform_exit(musb); |
28c2c51c | 1985 | |
34e2beb2 | 1986 | fail1: |
681d1e87 | 1987 | pm_runtime_disable(musb->controller); |
34e2beb2 SS |
1988 | dev_err(musb->controller, |
1989 | "musb_init_controller failed with status %d\n", status); | |
1990 | ||
28c2c51c FB |
1991 | musb_free(musb); |
1992 | ||
34e2beb2 SS |
1993 | fail0: |
1994 | ||
28c2c51c FB |
1995 | return status; |
1996 | ||
550a7375 FB |
1997 | } |
1998 | ||
1999 | /*-------------------------------------------------------------------------*/ | |
2000 | ||
2001 | /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just | |
2002 | * bridge to a platform device; this driver then suffices. | |
2003 | */ | |
41ac7b3a | 2004 | static int musb_probe(struct platform_device *pdev) |
550a7375 FB |
2005 | { |
2006 | struct device *dev = &pdev->dev; | |
fcf173e4 | 2007 | int irq = platform_get_irq_byname(pdev, "mc"); |
550a7375 FB |
2008 | struct resource *iomem; |
2009 | void __iomem *base; | |
2010 | ||
2011 | iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
541079de | 2012 | if (!iomem || irq <= 0) |
550a7375 FB |
2013 | return -ENODEV; |
2014 | ||
b42f7f30 FB |
2015 | base = devm_ioremap_resource(dev, iomem); |
2016 | if (IS_ERR(base)) | |
2017 | return PTR_ERR(base); | |
550a7375 | 2018 | |
b42f7f30 | 2019 | return musb_init_controller(dev, irq, base); |
550a7375 FB |
2020 | } |
2021 | ||
fb4e98ab | 2022 | static int musb_remove(struct platform_device *pdev) |
550a7375 | 2023 | { |
8d2421e6 AKG |
2024 | struct device *dev = &pdev->dev; |
2025 | struct musb *musb = dev_to_musb(dev); | |
550a7375 FB |
2026 | |
2027 | /* this gets called on rmmod. | |
2028 | * - Host mode: host may still be active | |
2029 | * - Peripheral mode: peripheral is deactivated (or never-activated) | |
2030 | * - OTG mode: both roles are deactivated (or never-activated) | |
2031 | */ | |
7f7f9e2a | 2032 | musb_exit_debugfs(musb); |
550a7375 | 2033 | musb_shutdown(pdev); |
461972d8 | 2034 | |
550a7375 | 2035 | musb_free(musb); |
8d2421e6 | 2036 | device_init_wakeup(dev, 0); |
550a7375 FB |
2037 | return 0; |
2038 | } | |
2039 | ||
2040 | #ifdef CONFIG_PM | |
2041 | ||
3c8a5fcc | 2042 | static void musb_save_context(struct musb *musb) |
4f712e01 AKG |
2043 | { |
2044 | int i; | |
2045 | void __iomem *musb_base = musb->mregs; | |
ae9b2ad2 | 2046 | void __iomem *epio; |
4f712e01 | 2047 | |
032ec49f FB |
2048 | musb->context.frame = musb_readw(musb_base, MUSB_FRAME); |
2049 | musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); | |
2050 | musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); | |
7421107b | 2051 | musb->context.power = musb_readb(musb_base, MUSB_POWER); |
7421107b FB |
2052 | musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); |
2053 | musb->context.index = musb_readb(musb_base, MUSB_INDEX); | |
2054 | musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); | |
4f712e01 | 2055 | |
ae9b2ad2 | 2056 | for (i = 0; i < musb->config->num_eps; ++i) { |
e4e5b136 FB |
2057 | struct musb_hw_ep *hw_ep; |
2058 | ||
2059 | hw_ep = &musb->endpoints[i]; | |
2060 | if (!hw_ep) | |
2061 | continue; | |
2062 | ||
2063 | epio = hw_ep->regs; | |
2064 | if (!epio) | |
2065 | continue; | |
2066 | ||
ea737554 | 2067 | musb_writeb(musb_base, MUSB_INDEX, i); |
7421107b | 2068 | musb->context.index_regs[i].txmaxp = |
ae9b2ad2 | 2069 | musb_readw(epio, MUSB_TXMAXP); |
7421107b | 2070 | musb->context.index_regs[i].txcsr = |
ae9b2ad2 | 2071 | musb_readw(epio, MUSB_TXCSR); |
7421107b | 2072 | musb->context.index_regs[i].rxmaxp = |
ae9b2ad2 | 2073 | musb_readw(epio, MUSB_RXMAXP); |
7421107b | 2074 | musb->context.index_regs[i].rxcsr = |
ae9b2ad2 | 2075 | musb_readw(epio, MUSB_RXCSR); |
4f712e01 AKG |
2076 | |
2077 | if (musb->dyn_fifo) { | |
7421107b | 2078 | musb->context.index_regs[i].txfifoadd = |
4f712e01 | 2079 | musb_read_txfifoadd(musb_base); |
7421107b | 2080 | musb->context.index_regs[i].rxfifoadd = |
4f712e01 | 2081 | musb_read_rxfifoadd(musb_base); |
7421107b | 2082 | musb->context.index_regs[i].txfifosz = |
4f712e01 | 2083 | musb_read_txfifosz(musb_base); |
7421107b | 2084 | musb->context.index_regs[i].rxfifosz = |
4f712e01 AKG |
2085 | musb_read_rxfifosz(musb_base); |
2086 | } | |
032ec49f FB |
2087 | |
2088 | musb->context.index_regs[i].txtype = | |
2089 | musb_readb(epio, MUSB_TXTYPE); | |
2090 | musb->context.index_regs[i].txinterval = | |
2091 | musb_readb(epio, MUSB_TXINTERVAL); | |
2092 | musb->context.index_regs[i].rxtype = | |
2093 | musb_readb(epio, MUSB_RXTYPE); | |
2094 | musb->context.index_regs[i].rxinterval = | |
2095 | musb_readb(epio, MUSB_RXINTERVAL); | |
2096 | ||
2097 | musb->context.index_regs[i].txfunaddr = | |
2098 | musb_read_txfunaddr(musb_base, i); | |
2099 | musb->context.index_regs[i].txhubaddr = | |
2100 | musb_read_txhubaddr(musb_base, i); | |
2101 | musb->context.index_regs[i].txhubport = | |
2102 | musb_read_txhubport(musb_base, i); | |
2103 | ||
2104 | musb->context.index_regs[i].rxfunaddr = | |
2105 | musb_read_rxfunaddr(musb_base, i); | |
2106 | musb->context.index_regs[i].rxhubaddr = | |
2107 | musb_read_rxhubaddr(musb_base, i); | |
2108 | musb->context.index_regs[i].rxhubport = | |
2109 | musb_read_rxhubport(musb_base, i); | |
4f712e01 | 2110 | } |
4f712e01 AKG |
2111 | } |
2112 | ||
3c8a5fcc | 2113 | static void musb_restore_context(struct musb *musb) |
4f712e01 AKG |
2114 | { |
2115 | int i; | |
2116 | void __iomem *musb_base = musb->mregs; | |
2117 | void __iomem *ep_target_regs; | |
ae9b2ad2 | 2118 | void __iomem *epio; |
4f712e01 | 2119 | |
032ec49f FB |
2120 | musb_writew(musb_base, MUSB_FRAME, musb->context.frame); |
2121 | musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); | |
2122 | musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); | |
7421107b | 2123 | musb_writeb(musb_base, MUSB_POWER, musb->context.power); |
b18d26f6 | 2124 | musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe); |
af5ec14d | 2125 | musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe); |
7421107b FB |
2126 | musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); |
2127 | musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); | |
4f712e01 | 2128 | |
ae9b2ad2 | 2129 | for (i = 0; i < musb->config->num_eps; ++i) { |
e4e5b136 FB |
2130 | struct musb_hw_ep *hw_ep; |
2131 | ||
2132 | hw_ep = &musb->endpoints[i]; | |
2133 | if (!hw_ep) | |
2134 | continue; | |
2135 | ||
2136 | epio = hw_ep->regs; | |
2137 | if (!epio) | |
2138 | continue; | |
2139 | ||
ea737554 | 2140 | musb_writeb(musb_base, MUSB_INDEX, i); |
ae9b2ad2 | 2141 | musb_writew(epio, MUSB_TXMAXP, |
7421107b | 2142 | musb->context.index_regs[i].txmaxp); |
ae9b2ad2 | 2143 | musb_writew(epio, MUSB_TXCSR, |
7421107b | 2144 | musb->context.index_regs[i].txcsr); |
ae9b2ad2 | 2145 | musb_writew(epio, MUSB_RXMAXP, |
7421107b | 2146 | musb->context.index_regs[i].rxmaxp); |
ae9b2ad2 | 2147 | musb_writew(epio, MUSB_RXCSR, |
7421107b | 2148 | musb->context.index_regs[i].rxcsr); |
4f712e01 AKG |
2149 | |
2150 | if (musb->dyn_fifo) { | |
2151 | musb_write_txfifosz(musb_base, | |
7421107b | 2152 | musb->context.index_regs[i].txfifosz); |
4f712e01 | 2153 | musb_write_rxfifosz(musb_base, |
7421107b | 2154 | musb->context.index_regs[i].rxfifosz); |
4f712e01 | 2155 | musb_write_txfifoadd(musb_base, |
7421107b | 2156 | musb->context.index_regs[i].txfifoadd); |
4f712e01 | 2157 | musb_write_rxfifoadd(musb_base, |
7421107b | 2158 | musb->context.index_regs[i].rxfifoadd); |
4f712e01 AKG |
2159 | } |
2160 | ||
032ec49f | 2161 | musb_writeb(epio, MUSB_TXTYPE, |
7421107b | 2162 | musb->context.index_regs[i].txtype); |
032ec49f | 2163 | musb_writeb(epio, MUSB_TXINTERVAL, |
7421107b | 2164 | musb->context.index_regs[i].txinterval); |
032ec49f | 2165 | musb_writeb(epio, MUSB_RXTYPE, |
7421107b | 2166 | musb->context.index_regs[i].rxtype); |
032ec49f | 2167 | musb_writeb(epio, MUSB_RXINTERVAL, |
4f712e01 | 2168 | |
032ec49f FB |
2169 | musb->context.index_regs[i].rxinterval); |
2170 | musb_write_txfunaddr(musb_base, i, | |
7421107b | 2171 | musb->context.index_regs[i].txfunaddr); |
032ec49f | 2172 | musb_write_txhubaddr(musb_base, i, |
7421107b | 2173 | musb->context.index_regs[i].txhubaddr); |
032ec49f | 2174 | musb_write_txhubport(musb_base, i, |
7421107b | 2175 | musb->context.index_regs[i].txhubport); |
4f712e01 | 2176 | |
032ec49f FB |
2177 | ep_target_regs = |
2178 | musb_read_target_reg_base(i, musb_base); | |
4f712e01 | 2179 | |
032ec49f | 2180 | musb_write_rxfunaddr(ep_target_regs, |
7421107b | 2181 | musb->context.index_regs[i].rxfunaddr); |
032ec49f | 2182 | musb_write_rxhubaddr(ep_target_regs, |
7421107b | 2183 | musb->context.index_regs[i].rxhubaddr); |
032ec49f | 2184 | musb_write_rxhubport(ep_target_regs, |
7421107b | 2185 | musb->context.index_regs[i].rxhubport); |
4f712e01 | 2186 | } |
3c5fec75 | 2187 | musb_writeb(musb_base, MUSB_INDEX, musb->context.index); |
4f712e01 AKG |
2188 | } |
2189 | ||
48fea965 | 2190 | static int musb_suspend(struct device *dev) |
550a7375 | 2191 | { |
8220796d | 2192 | struct musb *musb = dev_to_musb(dev); |
550a7375 | 2193 | unsigned long flags; |
550a7375 | 2194 | |
550a7375 FB |
2195 | spin_lock_irqsave(&musb->lock, flags); |
2196 | ||
2197 | if (is_peripheral_active(musb)) { | |
2198 | /* FIXME force disconnect unless we know USB will wake | |
2199 | * the system up quickly enough to respond ... | |
2200 | */ | |
2201 | } else if (is_host_active(musb)) { | |
2202 | /* we know all the children are suspended; sometimes | |
2203 | * they will even be wakeup-enabled. | |
2204 | */ | |
2205 | } | |
2206 | ||
550a7375 FB |
2207 | spin_unlock_irqrestore(&musb->lock, flags); |
2208 | return 0; | |
2209 | } | |
2210 | ||
48fea965 | 2211 | static int musb_resume_noirq(struct device *dev) |
550a7375 | 2212 | { |
550a7375 | 2213 | /* for static cmos like DaVinci, register values were preserved |
0ec8fd70 KK |
2214 | * unless for some reason the whole soc powered down or the USB |
2215 | * module got reset through the PSC (vs just being disabled). | |
550a7375 | 2216 | */ |
550a7375 FB |
2217 | return 0; |
2218 | } | |
2219 | ||
7acc6197 HH |
2220 | static int musb_runtime_suspend(struct device *dev) |
2221 | { | |
2222 | struct musb *musb = dev_to_musb(dev); | |
2223 | ||
2224 | musb_save_context(musb); | |
2225 | ||
2226 | return 0; | |
2227 | } | |
2228 | ||
2229 | static int musb_runtime_resume(struct device *dev) | |
2230 | { | |
2231 | struct musb *musb = dev_to_musb(dev); | |
2232 | static int first = 1; | |
2233 | ||
2234 | /* | |
2235 | * When pm_runtime_get_sync called for the first time in driver | |
2236 | * init, some of the structure is still not initialized which is | |
2237 | * used in restore function. But clock needs to be | |
2238 | * enabled before any register access, so | |
2239 | * pm_runtime_get_sync has to be called. | |
2240 | * Also context restore without save does not make | |
2241 | * any sense | |
2242 | */ | |
2243 | if (!first) | |
2244 | musb_restore_context(musb); | |
2245 | first = 0; | |
2246 | ||
2247 | return 0; | |
2248 | } | |
2249 | ||
47145210 | 2250 | static const struct dev_pm_ops musb_dev_pm_ops = { |
48fea965 MD |
2251 | .suspend = musb_suspend, |
2252 | .resume_noirq = musb_resume_noirq, | |
7acc6197 HH |
2253 | .runtime_suspend = musb_runtime_suspend, |
2254 | .runtime_resume = musb_runtime_resume, | |
48fea965 MD |
2255 | }; |
2256 | ||
2257 | #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) | |
550a7375 | 2258 | #else |
48fea965 | 2259 | #define MUSB_DEV_PM_OPS NULL |
550a7375 FB |
2260 | #endif |
2261 | ||
2262 | static struct platform_driver musb_driver = { | |
2263 | .driver = { | |
2264 | .name = (char *)musb_driver_name, | |
2265 | .bus = &platform_bus_type, | |
2266 | .owner = THIS_MODULE, | |
48fea965 | 2267 | .pm = MUSB_DEV_PM_OPS, |
550a7375 | 2268 | }, |
e9e8c85e | 2269 | .probe = musb_probe, |
7690417d | 2270 | .remove = musb_remove, |
550a7375 | 2271 | .shutdown = musb_shutdown, |
550a7375 FB |
2272 | }; |
2273 | ||
2274 | /*-------------------------------------------------------------------------*/ | |
2275 | ||
2276 | static int __init musb_init(void) | |
2277 | { | |
550a7375 FB |
2278 | if (usb_disabled()) |
2279 | return 0; | |
550a7375 | 2280 | |
e9e8c85e | 2281 | return platform_driver_register(&musb_driver); |
550a7375 | 2282 | } |
e9e8c85e | 2283 | module_init(musb_init); |
550a7375 FB |
2284 | |
2285 | static void __exit musb_cleanup(void) | |
2286 | { | |
2287 | platform_driver_unregister(&musb_driver); | |
2288 | } | |
2289 | module_exit(musb_cleanup); |