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usb: musb: core: disable irqs inside babble recovery
[deliverable/linux.git] / drivers / usb / musb / musb_core.c
CommitLineData
550a7375
FB		 1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
550a7375 85 * - platform_device for addressing, irq, and platform_data
5ae477b0 86 * - platform_data is mostly for board-specific information
c767c1c6 87 * (plus recentrly, SOC or family details)
550a7375
FB		 88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
550a7375
FB		 96#include <linux/list.h>
97#include <linux/kobject.h>
9303961f 98#include <linux/prefetch.h>
550a7375
FB		 99#include <linux/platform_device.h>
100#include <linux/io.h>
8d2421e6 101#include <linux/dma-mapping.h>
550a7375 102
550a7375
FB		 103#include "musb_core.h"
104
f7f9d63e 105#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
550a7375
FB		 106
107
550a7375
FB		 108#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110
e8164f64 111#define MUSB_VERSION "6.0"
550a7375
FB		 112
113#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114
05ac10dd 115#define MUSB_DRIVER_NAME "musb-hdrc"
550a7375
FB		 116const char musb_driver_name[] = MUSB_DRIVER_NAME;
117
118MODULE_DESCRIPTION(DRIVER_INFO);
119MODULE_AUTHOR(DRIVER_AUTHOR);
120MODULE_LICENSE("GPL");
121MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122
123
124/*-------------------------------------------------------------------------*/
125
126static inline struct musb *dev_to_musb(struct device *dev)
127{
550a7375 128 return dev_get_drvdata(dev);
550a7375
FB		 129}
130
131/*-------------------------------------------------------------------------*/
132
ffb865b1 133#ifndef CONFIG_BLACKFIN
b96d3b08 134static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
ffb865b1 135{
b96d3b08 136 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 137 int i = 0;
138 u8 r;
139 u8 power;
bf070bc1
GI		 140 int ret;
141
142 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 143
144 /* Make sure the transceiver is not in low power mode */
145 power = musb_readb(addr, MUSB_POWER);
146 power &= ~MUSB_POWER_SUSPENDM;
147 musb_writeb(addr, MUSB_POWER, power);
148
149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
151 */
152
153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
156
157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158 & MUSB_ULPI_REG_CMPLT)) {
159 i++;
bf070bc1
GI		 160 if (i == 10000) {
161 ret = -ETIMEDOUT;
162 goto out;
163 }
ffb865b1
HK		 164
165 }
166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167 r &= ~MUSB_ULPI_REG_CMPLT;
168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
169
bf070bc1
GI		 170 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
171
172out:
173 pm_runtime_put(phy->io_dev);
174
175 return ret;
ffb865b1
HK		 176}
177
b96d3b08 178static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
ffb865b1 179{
b96d3b08 180 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 181 int i = 0;
182 u8 r = 0;
183 u8 power;
bf070bc1
GI		 184 int ret = 0;
185
186 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 187
188 /* Make sure the transceiver is not in low power mode */
189 power = musb_readb(addr, MUSB_POWER);
190 power &= ~MUSB_POWER_SUSPENDM;
191 musb_writeb(addr, MUSB_POWER, power);
192
193 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
194 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
195 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
196
197 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
198 & MUSB_ULPI_REG_CMPLT)) {
199 i++;
bf070bc1
GI		 200 if (i == 10000) {
201 ret = -ETIMEDOUT;
202 goto out;
203 }
ffb865b1
HK		 204 }
205
206 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
207 r &= ~MUSB_ULPI_REG_CMPLT;
208 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
209
bf070bc1
GI		 210out:
211 pm_runtime_put(phy->io_dev);
212
213 return ret;
ffb865b1
HK		 214}
215#else
f2263db7
MF		 216#define musb_ulpi_read NULL
217#define musb_ulpi_write NULL
ffb865b1
HK		 218#endif
219
b96d3b08 220static struct usb_phy_io_ops musb_ulpi_access = {
ffb865b1
HK		 221 .read = musb_ulpi_read,
222 .write = musb_ulpi_write,
223};
224
225/*-------------------------------------------------------------------------*/
226
1b40fc57
TL		 227static u32 musb_default_fifo_offset(u8 epnum)
228{
229 return 0x20 + (epnum * 4);
230}
231
d026e9c7
TL		 232/* "flat" mapping: each endpoint has its own i/o address */
233static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
234{
235}
236
237static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
238{
239 return 0x100 + (0x10 * epnum) + offset;
240}
241
242/* "indexed" mapping: INDEX register controls register bank select */
243static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
244{
245 musb_writeb(mbase, MUSB_INDEX, epnum);
246}
247
248static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
249{
250 return 0x10 + offset;
251}
252
1b40fc57
TL		 253static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
254{
255 return __raw_readb(addr + offset);
256}
257
258static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
259{
260 __raw_writeb(data, addr + offset);
261}
262
263static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
264{
265 return __raw_readw(addr + offset);
266}
267
268static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
269{
270 __raw_writew(data, addr + offset);
271}
272
273static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
274{
275 return __raw_readl(addr + offset);
276}
277
278static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
279{
280 __raw_writel(data, addr + offset);
281}
c6cf8b00 282
550a7375
FB		 283/*
284 * Load an endpoint's FIFO
285 */
1b40fc57
TL		 286static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
287 const u8 *src)
550a7375 288{
5c8a86e1 289 struct musb *musb = hw_ep->musb;
550a7375
FB		 290 void __iomem *fifo = hw_ep->fifo;
291
603fe2b2
AKG		 292 if (unlikely(len == 0))
293 return;
294
550a7375
FB		 295 prefetch((u8 *)src);
296
5c8a86e1 297 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 298 'T', hw_ep->epnum, fifo, len, src);
299
300 /* we can't assume unaligned reads work */
301 if (likely((0x01 & (unsigned long) src) == 0)) {
302 u16 index = 0;
303
304 /* best case is 32bit-aligned source address */
305 if ((0x02 & (unsigned long) src) == 0) {
306 if (len >= 4) {
2bf0a8f6 307 iowrite32_rep(fifo, src + index, len >> 2);
550a7375
FB		 308 index += len & ~0x03;
309 }
310 if (len & 0x02) {
311 musb_writew(fifo, 0, *(u16 *)&src[index]);
312 index += 2;
313 }
314 } else {
315 if (len >= 2) {
2bf0a8f6 316 iowrite16_rep(fifo, src + index, len >> 1);
550a7375
FB		 317 index += len & ~0x01;
318 }
319 }
320 if (len & 0x01)
321 musb_writeb(fifo, 0, src[index]);
322 } else {
323 /* byte aligned */
2bf0a8f6 324 iowrite8_rep(fifo, src, len);
550a7375
FB		 325 }
326}
327
328/*
329 * Unload an endpoint's FIFO
330 */
1b40fc57 331static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
550a7375 332{
5c8a86e1 333 struct musb *musb = hw_ep->musb;
550a7375
FB		 334 void __iomem *fifo = hw_ep->fifo;
335
603fe2b2
AKG		 336 if (unlikely(len == 0))
337 return;
338
5c8a86e1 339 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 340 'R', hw_ep->epnum, fifo, len, dst);
341
342 /* we can't assume unaligned writes work */
343 if (likely((0x01 & (unsigned long) dst) == 0)) {
344 u16 index = 0;
345
346 /* best case is 32bit-aligned destination address */
347 if ((0x02 & (unsigned long) dst) == 0) {
348 if (len >= 4) {
2bf0a8f6 349 ioread32_rep(fifo, dst, len >> 2);
550a7375
FB		 350 index = len & ~0x03;
351 }
352 if (len & 0x02) {
353 *(u16 *)&dst[index] = musb_readw(fifo, 0);
354 index += 2;
355 }
356 } else {
357 if (len >= 2) {
2bf0a8f6 358 ioread16_rep(fifo, dst, len >> 1);
550a7375
FB		 359 index = len & ~0x01;
360 }
361 }
362 if (len & 0x01)
363 dst[index] = musb_readb(fifo, 0);
364 } else {
365 /* byte aligned */
2bf0a8f6 366 ioread8_rep(fifo, dst, len);
550a7375
FB		 367 }
368}
369
1b40fc57
TL		 370/*
371 * Old style IO functions
372 */
373u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
374EXPORT_SYMBOL_GPL(musb_readb);
375
376void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
377EXPORT_SYMBOL_GPL(musb_writeb);
550a7375 378
1b40fc57
TL		 379u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
380EXPORT_SYMBOL_GPL(musb_readw);
381
382void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
383EXPORT_SYMBOL_GPL(musb_writew);
384
385u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
386EXPORT_SYMBOL_GPL(musb_readl);
387
388void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
389EXPORT_SYMBOL_GPL(musb_writel);
390
391/*
392 * New style IO functions
393 */
394void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
395{
396 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
397}
398
399void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
400{
401 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
402}
550a7375
FB		 403
404/*-------------------------------------------------------------------------*/
405
406/* for high speed test mode; see USB 2.0 spec 7.1.20 */
407static const u8 musb_test_packet[53] = {
408 /* implicit SYNC then DATA0 to start */
409
410 /* JKJKJKJK x9 */
411 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
412 /* JJKKJJKK x8 */
413 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
414 /* JJJJKKKK x8 */
415 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
416 /* JJJJJJJKKKKKKK x8 */
417 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
418 /* JJJJJJJK x8 */
419 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
420 /* JKKKKKKK x10, JK */
421 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
422
423 /* implicit CRC16 then EOP to end */
424};
425
426void musb_load_testpacket(struct musb *musb)
427{
428 void __iomem *regs = musb->endpoints[0].regs;
429
430 musb_ep_select(musb->mregs, 0);
431 musb_write_fifo(musb->control_ep,
432 sizeof(musb_test_packet), musb_test_packet);
433 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
434}
435
436/*-------------------------------------------------------------------------*/
437
550a7375
FB		 438/*
439 * Handles OTG hnp timeouts, such as b_ase0_brst
440 */
a156544b 441static void musb_otg_timer_func(unsigned long data)
550a7375
FB		 442{
443 struct musb *musb = (struct musb *)data;
444 unsigned long flags;
445
446 spin_lock_irqsave(&musb->lock, flags);
e47d9254 447 switch (musb->xceiv->otg->state) {
550a7375 448 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 449 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
550a7375 450 musb_g_disconnect(musb);
e47d9254 451 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 452 musb->is_active = 0;
453 break;
ab983f2a 454 case OTG_STATE_A_SUSPEND:
550a7375 455 case OTG_STATE_A_WAIT_BCON:
5c8a86e1 456 dev_dbg(musb->controller, "HNP: %s timeout\n",
e47d9254 457 usb_otg_state_string(musb->xceiv->otg->state));
743411b3 458 musb_platform_set_vbus(musb, 0);
e47d9254 459 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
550a7375
FB		 460 break;
461 default:
5c8a86e1 462 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
e47d9254 463 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 464 }
550a7375
FB		 465 spin_unlock_irqrestore(&musb->lock, flags);
466}
467
550a7375 468/*
f7f9d63e 469 * Stops the HNP transition. Caller must take care of locking.
550a7375
FB		 470 */
471void musb_hnp_stop(struct musb *musb)
472{
8b125df5 473 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 474 void __iomem *mbase = musb->mregs;
475 u8 reg;
476
42c0bf1c 477 dev_dbg(musb->controller, "HNP: stop from %s\n",
e47d9254 478 usb_otg_state_string(musb->xceiv->otg->state));
ab983f2a 479
e47d9254 480 switch (musb->xceiv->otg->state) {
550a7375 481 case OTG_STATE_A_PERIPHERAL:
550a7375 482 musb_g_disconnect(musb);
5c8a86e1 483 dev_dbg(musb->controller, "HNP: back to %s\n",
e47d9254 484 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 485 break;
486 case OTG_STATE_B_HOST:
5c8a86e1 487 dev_dbg(musb->controller, "HNP: Disabling HR\n");
74c2e936
DM		 488 if (hcd)
489 hcd->self.is_b_host = 0;
e47d9254 490 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 491 MUSB_DEV_MODE(musb);
492 reg = musb_readb(mbase, MUSB_POWER);
493 reg |= MUSB_POWER_SUSPENDM;
494 musb_writeb(mbase, MUSB_POWER, reg);
495 /* REVISIT: Start SESSION_REQUEST here? */
496 break;
497 default:
5c8a86e1 498 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
e47d9254 499 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 500 }
501
502 /*
503 * When returning to A state after HNP, avoid hub_port_rebounce(),
504 * which cause occasional OPT A "Did not receive reset after connect"
505 * errors.
506 */
749da5f8 507 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
550a7375
FB		 508}
509
83b8f5b8 510static void musb_recover_from_babble(struct musb *musb);
e1eb3eb8 511
550a7375
FB		 512/*
513 * Interrupt Service Routine to record USB "global" interrupts.
514 * Since these do not happen often and signify things of
515 * paramount importance, it seems OK to check them individually;
516 * the order of the tests is specified in the manual
517 *
518 * @param musb instance pointer
519 * @param int_usb register contents
520 * @param devctl
521 * @param power
522 */
523
550a7375 524static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
b11e94d0 525 u8 devctl)
550a7375
FB		 526{
527 irqreturn_t handled = IRQ_NONE;
550a7375 528
b11e94d0 529 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
550a7375
FB		 530 int_usb);
531
532 /* in host mode, the peripheral may issue remote wakeup.
533 * in peripheral mode, the host may resume the link.
534 * spurious RESUME irqs happen too, paired with SUSPEND.
535 */
536 if (int_usb & MUSB_INTR_RESUME) {
537 handled = IRQ_HANDLED;
0acff6b8
FB		 538 dev_dbg(musb->controller, "RESUME (%s)\n",
539 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 540
541 if (devctl & MUSB_DEVCTL_HM) {
e47d9254 542 switch (musb->xceiv->otg->state) {
550a7375
FB		 543 case OTG_STATE_A_SUSPEND:
544 /* remote wakeup? later, GetPortStatus
545 * will stop RESUME signaling
546 */
547
550a7375
FB		 548 musb->port1_status |=
549 (USB_PORT_STAT_C_SUSPEND << 16)
550 | MUSB_PORT_STAT_RESUME;
30d361bf
DM		 551 musb->rh_timer = jiffies
552 + msecs_to_jiffies(20);
baadd52f 553 musb->need_finish_resume = 1;
550a7375 554
e47d9254 555 musb->xceiv->otg->state = OTG_STATE_A_HOST;
550a7375 556 musb->is_active = 1;
9298b4aa 557 musb_host_resume_root_hub(musb);
550a7375
FB		 558 break;
559 case OTG_STATE_B_WAIT_ACON:
e47d9254 560 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 561 musb->is_active = 1;
562 MUSB_DEV_MODE(musb);
563 break;
564 default:
565 WARNING("bogus %s RESUME (%s)\n",
566 "host",
e47d9254 567 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 568 }
550a7375 569 } else {
e47d9254 570 switch (musb->xceiv->otg->state) {
550a7375
FB		 571 case OTG_STATE_A_SUSPEND:
572 /* possibly DISCONNECT is upcoming */
e47d9254 573 musb->xceiv->otg->state = OTG_STATE_A_HOST;
0b3eba44 574 musb_host_resume_root_hub(musb);
550a7375 575 break;
550a7375
FB		 576 case OTG_STATE_B_WAIT_ACON:
577 case OTG_STATE_B_PERIPHERAL:
578 /* disconnect while suspended? we may
579 * not get a disconnect irq...
580 */
581 if ((devctl & MUSB_DEVCTL_VBUS)
582 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
583 ) {
584 musb->int_usb |= MUSB_INTR_DISCONNECT;
585 musb->int_usb &= ~MUSB_INTR_SUSPEND;
586 break;
587 }
588 musb_g_resume(musb);
589 break;
590 case OTG_STATE_B_IDLE:
591 musb->int_usb &= ~MUSB_INTR_SUSPEND;
592 break;
550a7375
FB		 593 default:
594 WARNING("bogus %s RESUME (%s)\n",
595 "peripheral",
e47d9254 596 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 597 }
598 }
599 }
600
550a7375
FB		 601 /* see manual for the order of the tests */
602 if (int_usb & MUSB_INTR_SESSREQ) {
aa471456
FB		 603 void __iomem *mbase = musb->mregs;
604
19aab56c
HK		 605 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
606 && (devctl & MUSB_DEVCTL_BDEVICE)) {
5c8a86e1 607 dev_dbg(musb->controller, "SessReq while on B state\n");
a6038ee7
HK		 608 return IRQ_HANDLED;
609 }
610
5c8a86e1 611 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
e47d9254 612 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 613
614 /* IRQ arrives from ID pin sense or (later, if VBUS power
615 * is removed) SRP. responses are time critical:
616 * - turn on VBUS (with silicon-specific mechanism)
617 * - go through A_WAIT_VRISE
618 * - ... to A_WAIT_BCON.
619 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
620 */
621 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
622 musb->ep0_stage = MUSB_EP0_START;
e47d9254 623 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
550a7375 624 MUSB_HST_MODE(musb);
743411b3 625 musb_platform_set_vbus(musb, 1);
550a7375
FB		 626
627 handled = IRQ_HANDLED;
628 }
629
630 if (int_usb & MUSB_INTR_VBUSERROR) {
631 int ignore = 0;
632
633 /* During connection as an A-Device, we may see a short
634 * current spikes causing voltage drop, because of cable
635 * and peripheral capacitance combined with vbus draw.
636 * (So: less common with truly self-powered devices, where
637 * vbus doesn't act like a power supply.)
638 *
639 * Such spikes are short; usually less than ~500 usec, max
640 * of ~2 msec. That is, they're not sustained overcurrent
641 * errors, though they're reported using VBUSERROR irqs.
642 *
643 * Workarounds: (a) hardware: use self powered devices.
644 * (b) software: ignore non-repeated VBUS errors.
645 *
646 * REVISIT: do delays from lots of DEBUG_KERNEL checks
647 * make trouble here, keeping VBUS < 4.4V ?
648 */
e47d9254 649 switch (musb->xceiv->otg->state) {
550a7375
FB		 650 case OTG_STATE_A_HOST:
651 /* recovery is dicey once we've gotten past the
652 * initial stages of enumeration, but if VBUS
653 * stayed ok at the other end of the link, and
654 * another reset is due (at least for high speed,
655 * to redo the chirp etc), it might work OK...
656 */
657 case OTG_STATE_A_WAIT_BCON:
658 case OTG_STATE_A_WAIT_VRISE:
659 if (musb->vbuserr_retry) {
aa471456
FB		 660 void __iomem *mbase = musb->mregs;
661
550a7375
FB		 662 musb->vbuserr_retry--;
663 ignore = 1;
664 devctl |= MUSB_DEVCTL_SESSION;
665 musb_writeb(mbase, MUSB_DEVCTL, devctl);
666 } else {
667 musb->port1_status |=
749da5f8
AS		 668 USB_PORT_STAT_OVERCURRENT
669 | (USB_PORT_STAT_C_OVERCURRENT << 16);
550a7375
FB		 670 }
671 break;
672 default:
673 break;
674 }
675
54485116
GI		 676 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
677 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
e47d9254 678 usb_otg_state_string(musb->xceiv->otg->state),
550a7375
FB		 679 devctl,
680 ({ char *s;
681 switch (devctl & MUSB_DEVCTL_VBUS) {
682 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
683 s = "<SessEnd"; break;
684 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
685 s = "<AValid"; break;
686 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
687 s = "<VBusValid"; break;
688 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
689 default:
690 s = "VALID"; break;
2b84f92b 691 } s; }),
550a7375
FB		 692 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
693 musb->port1_status);
694
695 /* go through A_WAIT_VFALL then start a new session */
696 if (!ignore)
743411b3 697 musb_platform_set_vbus(musb, 0);
550a7375
FB		 698 handled = IRQ_HANDLED;
699 }
700
1c25fda4 701 if (int_usb & MUSB_INTR_SUSPEND) {
b11e94d0 702 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
e47d9254 703 usb_otg_state_string(musb->xceiv->otg->state), devctl);
1c25fda4
AM		 704 handled = IRQ_HANDLED;
705
e47d9254 706 switch (musb->xceiv->otg->state) {
1c25fda4
AM		 707 case OTG_STATE_A_PERIPHERAL:
708 /* We also come here if the cable is removed, since
709 * this silicon doesn't report ID-no-longer-grounded.
710 *
711 * We depend on T(a_wait_bcon) to shut us down, and
712 * hope users don't do anything dicey during this
713 * undesired detour through A_WAIT_BCON.
714 */
715 musb_hnp_stop(musb);
0b3eba44 716 musb_host_resume_root_hub(musb);
1c25fda4
AM		 717 musb_root_disconnect(musb);
718 musb_platform_try_idle(musb, jiffies
719 + msecs_to_jiffies(musb->a_wait_bcon
720 ? : OTG_TIME_A_WAIT_BCON));
721
722 break;
1c25fda4
AM		 723 case OTG_STATE_B_IDLE:
724 if (!musb->is_active)
725 break;
726 case OTG_STATE_B_PERIPHERAL:
727 musb_g_suspend(musb);
eee3f15d 728 musb->is_active = musb->g.b_hnp_enable;
1c25fda4 729 if (musb->is_active) {
e47d9254 730 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
5c8a86e1 731 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
1c25fda4
AM		 732 mod_timer(&musb->otg_timer, jiffies
733 + msecs_to_jiffies(
734 OTG_TIME_B_ASE0_BRST));
1c25fda4
AM		 735 }
736 break;
737 case OTG_STATE_A_WAIT_BCON:
738 if (musb->a_wait_bcon != 0)
739 musb_platform_try_idle(musb, jiffies
740 + msecs_to_jiffies(musb->a_wait_bcon));
741 break;
742 case OTG_STATE_A_HOST:
e47d9254 743 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
eee3f15d 744 musb->is_active = musb->hcd->self.b_hnp_enable;
1c25fda4
AM		 745 break;
746 case OTG_STATE_B_HOST:
747 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
5c8a86e1 748 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
1c25fda4
AM		 749 break;
750 default:
751 /* "should not happen" */
752 musb->is_active = 0;
753 break;
754 }
755 }
756
550a7375 757 if (int_usb & MUSB_INTR_CONNECT) {
8b125df5 758 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 759
760 handled = IRQ_HANDLED;
761 musb->is_active = 1;
550a7375
FB		 762
763 musb->ep0_stage = MUSB_EP0_START;
764
b18d26f6
SAS		 765 musb->intrtxe = musb->epmask;
766 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
af5ec14d
SAS		 767 musb->intrrxe = musb->epmask & 0xfffe;
768 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
d709d22e 769 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 770 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
771 |USB_PORT_STAT_HIGH_SPEED
772 |USB_PORT_STAT_ENABLE
773 );
774 musb->port1_status |= USB_PORT_STAT_CONNECTION
775 |(USB_PORT_STAT_C_CONNECTION << 16);
776
777 /* high vs full speed is just a guess until after reset */
778 if (devctl & MUSB_DEVCTL_LSDEV)
779 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
780
550a7375 781 /* indicate new connection to OTG machine */
e47d9254 782 switch (musb->xceiv->otg->state) {
550a7375
FB		 783 case OTG_STATE_B_PERIPHERAL:
784 if (int_usb & MUSB_INTR_SUSPEND) {
5c8a86e1 785 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
550a7375 786 int_usb &= ~MUSB_INTR_SUSPEND;
1de00dae 787 goto b_host;
550a7375 788 } else
5c8a86e1 789 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
550a7375
FB		 790 break;
791 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 792 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
1de00dae 793b_host:
e47d9254 794 musb->xceiv->otg->state = OTG_STATE_B_HOST;
74c2e936
DM		 795 if (musb->hcd)
796 musb->hcd->self.is_b_host = 1;
1de00dae 797 del_timer(&musb->otg_timer);
550a7375
FB		 798 break;
799 default:
800 if ((devctl & MUSB_DEVCTL_VBUS)
801 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
e47d9254 802 musb->xceiv->otg->state = OTG_STATE_A_HOST;
0b3eba44
DM		 803 if (hcd)
804 hcd->self.is_b_host = 0;
550a7375
FB		 805 }
806 break;
807 }
1de00dae 808
0b3eba44 809 musb_host_poke_root_hub(musb);
1de00dae 810
5c8a86e1 811 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
e47d9254 812 usb_otg_state_string(musb->xceiv->otg->state), devctl);
550a7375 813 }
550a7375 814
6d349671 815 if (int_usb & MUSB_INTR_DISCONNECT) {
5c8a86e1 816 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
e47d9254 817 usb_otg_state_string(musb->xceiv->otg->state),
1c25fda4
AM		 818 MUSB_MODE(musb), devctl);
819 handled = IRQ_HANDLED;
820
e47d9254 821 switch (musb->xceiv->otg->state) {
1c25fda4
AM		 822 case OTG_STATE_A_HOST:
823 case OTG_STATE_A_SUSPEND:
0b3eba44 824 musb_host_resume_root_hub(musb);
1c25fda4 825 musb_root_disconnect(musb);
032ec49f 826 if (musb->a_wait_bcon != 0)
1c25fda4
AM		 827 musb_platform_try_idle(musb, jiffies
828 + msecs_to_jiffies(musb->a_wait_bcon));
829 break;
1c25fda4
AM		 830 case OTG_STATE_B_HOST:
831 /* REVISIT this behaves for "real disconnect"
832 * cases; make sure the other transitions from
833 * from B_HOST act right too. The B_HOST code
834 * in hnp_stop() is currently not used...
835 */
836 musb_root_disconnect(musb);
74c2e936
DM		 837 if (musb->hcd)
838 musb->hcd->self.is_b_host = 0;
e47d9254 839 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
1c25fda4
AM		 840 MUSB_DEV_MODE(musb);
841 musb_g_disconnect(musb);
842 break;
843 case OTG_STATE_A_PERIPHERAL:
844 musb_hnp_stop(musb);
845 musb_root_disconnect(musb);
846 /* FALLTHROUGH */
847 case OTG_STATE_B_WAIT_ACON:
848 /* FALLTHROUGH */
1c25fda4
AM		 849 case OTG_STATE_B_PERIPHERAL:
850 case OTG_STATE_B_IDLE:
851 musb_g_disconnect(musb);
852 break;
1c25fda4
AM		 853 default:
854 WARNING("unhandled DISCONNECT transition (%s)\n",
e47d9254 855 usb_otg_state_string(musb->xceiv->otg->state));
1c25fda4
AM		 856 break;
857 }
858 }
859
550a7375
FB		 860 /* mentor saves a bit: bus reset and babble share the same irq.
861 * only host sees babble; only peripheral sees bus reset.
862 */
863 if (int_usb & MUSB_INTR_RESET) {
1c25fda4 864 handled = IRQ_HANDLED;
896f7ea3 865 if (devctl & MUSB_DEVCTL_HM) {
28378d5e
FB		 866 u8 power = musb_readl(musb->mregs, MUSB_POWER);
867
550a7375
FB		 868 /*
869 * Looks like non-HS BABBLE can be ignored, but
28378d5e
FB		 870 * HS BABBLE is an error condition.
871 *
872 * For HS the solution is to avoid babble in the first
873 * place and fix what caused BABBLE.
874 *
875 * When HS BABBLE happens what we can depends on which
876 * platform MUSB is running, because some platforms
877 * implemented proprietary means for 'recovering' from
878 * Babble conditions. One such platform is AM335x. In
879 * most cases, however, the only thing we can do is drop
880 * the session.
550a7375 881 */
28378d5e 882 if (power & MUSB_POWER_HSMODE) {
52b9e6eb 883 dev_err(musb->controller, "Babble\n");
d0fc0a20 884
0244336f 885 if (is_host_active(musb))
83b8f5b8 886 musb_recover_from_babble(musb);
550a7375 887 }
a04d46d0 888 } else {
5c8a86e1 889 dev_dbg(musb->controller, "BUS RESET as %s\n",
e47d9254
AT		 890 usb_otg_state_string(musb->xceiv->otg->state));
891 switch (musb->xceiv->otg->state) {
550a7375 892 case OTG_STATE_A_SUSPEND:
550a7375
FB		 893 musb_g_reset(musb);
894 /* FALLTHROUGH */
895 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
f7f9d63e 896 /* never use invalid T(a_wait_bcon) */
5c8a86e1 897 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
e47d9254 898 usb_otg_state_string(musb->xceiv->otg->state),
3df00453 899 TA_WAIT_BCON(musb));
f7f9d63e
DB		 900 mod_timer(&musb->otg_timer, jiffies
901 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
550a7375
FB		 902 break;
903 case OTG_STATE_A_PERIPHERAL:
1de00dae
DB		 904 del_timer(&musb->otg_timer);
905 musb_g_reset(musb);
550a7375
FB		 906 break;
907 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 908 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
e47d9254
AT		 909 usb_otg_state_string(musb->xceiv->otg->state));
910 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 911 musb_g_reset(musb);
912 break;
550a7375 913 case OTG_STATE_B_IDLE:
e47d9254 914 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 915 /* FALLTHROUGH */
916 case OTG_STATE_B_PERIPHERAL:
917 musb_g_reset(musb);
918 break;
919 default:
5c8a86e1 920 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
e47d9254 921 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 922 }
923 }
550a7375 924 }
550a7375
FB		 925
926#if 0
927/* REVISIT ... this would be for multiplexing periodic endpoints, or
928 * supporting transfer phasing to prevent exceeding ISO bandwidth
929 * limits of a given frame or microframe.
930 *
931 * It's not needed for peripheral side, which dedicates endpoints;
932 * though it _might_ use SOF irqs for other purposes.
933 *
934 * And it's not currently needed for host side, which also dedicates
935 * endpoints, relies on TX/RX interval registers, and isn't claimed
936 * to support ISO transfers yet.
937 */
938 if (int_usb & MUSB_INTR_SOF) {
939 void __iomem *mbase = musb->mregs;
940 struct musb_hw_ep *ep;
941 u8 epnum;
942 u16 frame;
943
5c8a86e1 944 dev_dbg(musb->controller, "START_OF_FRAME\n");
550a7375
FB		 945 handled = IRQ_HANDLED;
946
947 /* start any periodic Tx transfers waiting for current frame */
948 frame = musb_readw(mbase, MUSB_FRAME);
949 ep = musb->endpoints;
950 for (epnum = 1; (epnum < musb->nr_endpoints)
951 && (musb->epmask >= (1 << epnum));
952 epnum++, ep++) {
953 /*
954 * FIXME handle framecounter wraps (12 bits)
955 * eliminate duplicated StartUrb logic
956 */
957 if (ep->dwWaitFrame >= frame) {
958 ep->dwWaitFrame = 0;
959 pr_debug("SOF --> periodic TX%s on %d\n",
960 ep->tx_channel ? " DMA" : "",
961 epnum);
962 if (!ep->tx_channel)
963 musb_h_tx_start(musb, epnum);
964 else
965 cppi_hostdma_start(musb, epnum);
966 }
967 } /* end of for loop */
968 }
969#endif
970
1c25fda4 971 schedule_work(&musb->irq_work);
550a7375
FB		 972
973 return handled;
974}
975
976/*-------------------------------------------------------------------------*/
977
e1eb3eb8 978static void musb_disable_interrupts(struct musb *musb)
550a7375
FB		 979{
980 void __iomem *mbase = musb->mregs;
981 u16 temp;
982
983 /* disable interrupts */
984 musb_writeb(mbase, MUSB_INTRUSBE, 0);
b18d26f6 985 musb->intrtxe = 0;
550a7375 986 musb_writew(mbase, MUSB_INTRTXE, 0);
af5ec14d 987 musb->intrrxe = 0;
550a7375
FB		 988 musb_writew(mbase, MUSB_INTRRXE, 0);
989
550a7375
FB		 990 /* flush pending interrupts */
991 temp = musb_readb(mbase, MUSB_INTRUSB);
992 temp = musb_readw(mbase, MUSB_INTRTX);
993 temp = musb_readw(mbase, MUSB_INTRRX);
e1eb3eb8
FB		 994}
995
996static void musb_enable_interrupts(struct musb *musb)
997{
998 void __iomem *regs = musb->mregs;
999
1000 /* Set INT enable registers, enable interrupts */
1001 musb->intrtxe = musb->epmask;
1002 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1003 musb->intrrxe = musb->epmask & 0xfffe;
1004 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1005 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 1006
1007}
1008
e1eb3eb8
FB		 1009static void musb_generic_disable(struct musb *musb)
1010{
1011 void __iomem *mbase = musb->mregs;
1012
1013 musb_disable_interrupts(musb);
1014
1015 /* off */
1016 musb_writeb(mbase, MUSB_DEVCTL, 0);
1017}
1018
001dd84a
SAS		 1019/*
1020 * Program the HDRC to start (enable interrupts, dma, etc.).
1021 */
1022void musb_start(struct musb *musb)
1023{
1024 void __iomem *regs = musb->mregs;
1025 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1026
1027 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1028
e1eb3eb8 1029 musb_enable_interrupts(musb);
001dd84a
SAS		 1030 musb_writeb(regs, MUSB_TESTMODE, 0);
1031
1032 /* put into basic highspeed mode and start session */
1033 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
1034 | MUSB_POWER_HSENAB
1035 /* ENSUSPEND wedges tusb */
1036 /* | MUSB_POWER_ENSUSPEND */
1037 );
1038
1039 musb->is_active = 0;
1040 devctl = musb_readb(regs, MUSB_DEVCTL);
1041 devctl &= ~MUSB_DEVCTL_SESSION;
1042
1043 /* session started after:
1044 * (a) ID-grounded irq, host mode;
1045 * (b) vbus present/connect IRQ, peripheral mode;
1046 * (c) peripheral initiates, using SRP
1047 */
1048 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1049 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1050 musb->is_active = 1;
1051 } else {
1052 devctl |= MUSB_DEVCTL_SESSION;
1053 }
1054
1055 musb_platform_enable(musb);
1056 musb_writeb(regs, MUSB_DEVCTL, devctl);
1057}
1058
550a7375
FB		 1059/*
1060 * Make the HDRC stop (disable interrupts, etc.);
1061 * reversible by musb_start
1062 * called on gadget driver unregister
1063 * with controller locked, irqs blocked
1064 * acts as a NOP unless some role activated the hardware
1065 */
1066void musb_stop(struct musb *musb)
1067{
1068 /* stop IRQs, timers, ... */
1069 musb_platform_disable(musb);
1070 musb_generic_disable(musb);
5c8a86e1 1071 dev_dbg(musb->controller, "HDRC disabled\n");
550a7375
FB		 1072
1073 /* FIXME
1074 * - mark host and/or peripheral drivers unusable/inactive
1075 * - disable DMA (and enable it in HdrcStart)
1076 * - make sure we can musb_start() after musb_stop(); with
1077 * OTG mode, gadget driver module rmmod/modprobe cycles that
1078 * - ...
1079 */
1080 musb_platform_try_idle(musb, 0);
1081}
1082
1083static void musb_shutdown(struct platform_device *pdev)
1084{
1085 struct musb *musb = dev_to_musb(&pdev->dev);
1086 unsigned long flags;
1087
4f9edd2d 1088 pm_runtime_get_sync(musb->controller);
24307cae 1089
2cc65fea 1090 musb_host_cleanup(musb);
24307cae
GI		 1091 musb_gadget_cleanup(musb);
1092
550a7375
FB		 1093 spin_lock_irqsave(&musb->lock, flags);
1094 musb_platform_disable(musb);
1095 musb_generic_disable(musb);
550a7375
FB		 1096 spin_unlock_irqrestore(&musb->lock, flags);
1097
120d074c
GI		 1098 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1099 musb_platform_exit(musb);
120d074c 1100
4f9edd2d 1101 pm_runtime_put(musb->controller);
550a7375
FB		 1102 /* FIXME power down */
1103}
1104
1105
1106/*-------------------------------------------------------------------------*/
1107
1108/*
1109 * The silicon either has hard-wired endpoint configurations, or else
1110 * "dynamic fifo" sizing. The driver has support for both, though at this
c767c1c6
DB		 1111 * writing only the dynamic sizing is very well tested. Since we switched
1112 * away from compile-time hardware parameters, we can no longer rely on
1113 * dead code elimination to leave only the relevant one in the object file.
550a7375
FB		 1114 *
1115 * We don't currently use dynamic fifo setup capability to do anything
1116 * more than selecting one of a bunch of predefined configurations.
1117 */
8a77f05a 1118static ushort fifo_mode;
550a7375
FB		 1119
1120/* "modprobe ... fifo_mode=1" etc */
1121module_param(fifo_mode, ushort, 0);
1122MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1123
550a7375
FB		 1124/*
1125 * tables defining fifo_mode values. define more if you like.
1126 * for host side, make sure both halves of ep1 are set up.
1127 */
1128
1129/* mode 0 - fits in 2KB */
d3608b6d 1130static struct musb_fifo_cfg mode_0_cfg[] = {
550a7375
FB		 1131{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1132{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1133{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1134{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1135{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1136};
1137
1138/* mode 1 - fits in 4KB */
d3608b6d 1139static struct musb_fifo_cfg mode_1_cfg[] = {
550a7375
FB		 1140{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1141{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1142{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1143{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1144{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1145};
1146
1147/* mode 2 - fits in 4KB */
d3608b6d 1148static struct musb_fifo_cfg mode_2_cfg[] = {
550a7375
FB		 1149{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1150{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1151{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1152{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1153{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1154{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1155};
1156
1157/* mode 3 - fits in 4KB */
d3608b6d 1158static struct musb_fifo_cfg mode_3_cfg[] = {
550a7375
FB		 1159{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1160{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1161{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1162{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1163{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1164{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1165};
1166
1167/* mode 4 - fits in 16KB */
d3608b6d 1168static struct musb_fifo_cfg mode_4_cfg[] = {
550a7375
FB		 1169{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1170{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1171{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1172{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1173{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1174{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1175{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1176{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1177{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1178{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1179{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1180{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1181{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1182{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1183{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1184{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1185{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1186{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
a483d706
AKG		 1187{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1188{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1189{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1190{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1191{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1192{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1193{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
550a7375
FB		 1194{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1195{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1196};
1197
3b151526 1198/* mode 5 - fits in 8KB */
d3608b6d 1199static struct musb_fifo_cfg mode_5_cfg[] = {
3b151526
AKG		 1200{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1201{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1202{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1203{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1204{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1205{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1206{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1207{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1208{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1209{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1210{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1211{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1212{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1213{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1214{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1215{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1216{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1217{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1218{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1219{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1220{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1221{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1222{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1223{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1224{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1225{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1226{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1227};
550a7375
FB		 1228
1229/*
1230 * configure a fifo; for non-shared endpoints, this may be called
1231 * once for a tx fifo and once for an rx fifo.
1232 *
1233 * returns negative errno or offset for next fifo.
1234 */
41ac7b3a 1235static int
550a7375 1236fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
e6c213b2 1237 const struct musb_fifo_cfg *cfg, u16 offset)
550a7375
FB		 1238{
1239 void __iomem *mbase = musb->mregs;
1240 int size = 0;
1241 u16 maxpacket = cfg->maxpacket;
1242 u16 c_off = offset >> 3;
1243 u8 c_size;
1244
1245 /* expect hw_ep has already been zero-initialized */
1246
1247 size = ffs(max(maxpacket, (u16) 8)) - 1;
1248 maxpacket = 1 << size;
1249
1250 c_size = size - 3;
1251 if (cfg->mode == BUF_DOUBLE) {
ca6d1b13
FB		 1252 if ((offset + (maxpacket << 1)) >
1253 (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1254 return -EMSGSIZE;
1255 c_size |= MUSB_FIFOSZ_DPB;
1256 } else {
ca6d1b13 1257 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1258 return -EMSGSIZE;
1259 }
1260
1261 /* configure the FIFO */
1262 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1263
550a7375 1264 /* EP0 reserved endpoint for control, bidirectional;
5ae477b0 1265 * EP1 reserved for bulk, two unidirectional halves.
550a7375
FB		 1266 */
1267 if (hw_ep->epnum == 1)
1268 musb->bulk_ep = hw_ep;
1269 /* REVISIT error check: be sure ep0 can both rx and tx ... */
550a7375
FB		 1270 switch (cfg->style) {
1271 case FIFO_TX:
c6cf8b00
BW		 1272 musb_write_txfifosz(mbase, c_size);
1273 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1274 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1275 hw_ep->max_packet_sz_tx = maxpacket;
1276 break;
1277 case FIFO_RX:
c6cf8b00
BW		 1278 musb_write_rxfifosz(mbase, c_size);
1279 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1280 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1281 hw_ep->max_packet_sz_rx = maxpacket;
1282 break;
1283 case FIFO_RXTX:
c6cf8b00
BW		 1284 musb_write_txfifosz(mbase, c_size);
1285 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1286 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1287 hw_ep->max_packet_sz_rx = maxpacket;
1288
c6cf8b00
BW		 1289 musb_write_rxfifosz(mbase, c_size);
1290 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1291 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1292 hw_ep->max_packet_sz_tx = maxpacket;
1293
1294 hw_ep->is_shared_fifo = true;
1295 break;
1296 }
1297
1298 /* NOTE rx and tx endpoint irqs aren't managed separately,
1299 * which happens to be ok
1300 */
1301 musb->epmask |= (1 << hw_ep->epnum);
1302
1303 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1304}
1305
d3608b6d 1306static struct musb_fifo_cfg ep0_cfg = {
550a7375
FB		 1307 .style = FIFO_RXTX, .maxpacket = 64,
1308};
1309
41ac7b3a 1310static int ep_config_from_table(struct musb *musb)
550a7375 1311{
e6c213b2 1312 const struct musb_fifo_cfg *cfg;
550a7375
FB		 1313 unsigned i, n;
1314 int offset;
1315 struct musb_hw_ep *hw_ep = musb->endpoints;
1316
e6c213b2
FB		 1317 if (musb->config->fifo_cfg) {
1318 cfg = musb->config->fifo_cfg;
1319 n = musb->config->fifo_cfg_size;
1320 goto done;
1321 }
1322
550a7375
FB		 1323 switch (fifo_mode) {
1324 default:
1325 fifo_mode = 0;
1326 /* FALLTHROUGH */
1327 case 0:
1328 cfg = mode_0_cfg;
1329 n = ARRAY_SIZE(mode_0_cfg);
1330 break;
1331 case 1:
1332 cfg = mode_1_cfg;
1333 n = ARRAY_SIZE(mode_1_cfg);
1334 break;
1335 case 2:
1336 cfg = mode_2_cfg;
1337 n = ARRAY_SIZE(mode_2_cfg);
1338 break;
1339 case 3:
1340 cfg = mode_3_cfg;
1341 n = ARRAY_SIZE(mode_3_cfg);
1342 break;
1343 case 4:
1344 cfg = mode_4_cfg;
1345 n = ARRAY_SIZE(mode_4_cfg);
1346 break;
3b151526
AKG		 1347 case 5:
1348 cfg = mode_5_cfg;
1349 n = ARRAY_SIZE(mode_5_cfg);
1350 break;
550a7375
FB		 1351 }
1352
1353 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1354 musb_driver_name, fifo_mode);
1355
1356
e6c213b2 1357done:
550a7375
FB		 1358 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1359 /* assert(offset > 0) */
1360
1361 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
ca6d1b13 1362 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
550a7375
FB		 1363 */
1364
1365 for (i = 0; i < n; i++) {
1366 u8 epn = cfg->hw_ep_num;
1367
ca6d1b13 1368 if (epn >= musb->config->num_eps) {
550a7375
FB		 1369 pr_debug("%s: invalid ep %d\n",
1370 musb_driver_name, epn);
bb1c9ef1 1371 return -EINVAL;
550a7375
FB		 1372 }
1373 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1374 if (offset < 0) {
1375 pr_debug("%s: mem overrun, ep %d\n",
1376 musb_driver_name, epn);
f69dfa1f 1377 return offset;
550a7375
FB		 1378 }
1379 epn++;
1380 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1381 }
1382
1383 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1384 musb_driver_name,
ca6d1b13
FB		 1385 n + 1, musb->config->num_eps * 2 - 1,
1386 offset, (1 << (musb->config->ram_bits + 2)));
550a7375 1387
550a7375
FB		 1388 if (!musb->bulk_ep) {
1389 pr_debug("%s: missing bulk\n", musb_driver_name);
1390 return -EINVAL;
1391 }
550a7375
FB		 1392
1393 return 0;
1394}
1395
1396
1397/*
1398 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1399 * @param musb the controller
1400 */
41ac7b3a 1401static int ep_config_from_hw(struct musb *musb)
550a7375 1402{
c6cf8b00 1403 u8 epnum = 0;
550a7375 1404 struct musb_hw_ep *hw_ep;
a156544b 1405 void __iomem *mbase = musb->mregs;
c6cf8b00 1406 int ret = 0;
550a7375 1407
5c8a86e1 1408 dev_dbg(musb->controller, "<== static silicon ep config\n");
550a7375
FB		 1409
1410 /* FIXME pick up ep0 maxpacket size */
1411
ca6d1b13 1412 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
550a7375
FB		 1413 musb_ep_select(mbase, epnum);
1414 hw_ep = musb->endpoints + epnum;
1415
c6cf8b00
BW		 1416 ret = musb_read_fifosize(musb, hw_ep, epnum);
1417 if (ret < 0)
550a7375 1418 break;
550a7375
FB		 1419
1420 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1421
550a7375
FB		 1422 /* pick an RX/TX endpoint for bulk */
1423 if (hw_ep->max_packet_sz_tx < 512
1424 || hw_ep->max_packet_sz_rx < 512)
1425 continue;
1426
1427 /* REVISIT: this algorithm is lazy, we should at least
1428 * try to pick a double buffered endpoint.
1429 */
1430 if (musb->bulk_ep)
1431 continue;
1432 musb->bulk_ep = hw_ep;
550a7375
FB		 1433 }
1434
550a7375
FB		 1435 if (!musb->bulk_ep) {
1436 pr_debug("%s: missing bulk\n", musb_driver_name);
1437 return -EINVAL;
1438 }
550a7375
FB		 1439
1440 return 0;
1441}
1442
1443enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1444
1445/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1446 * configure endpoints, or take their config from silicon
1447 */
41ac7b3a 1448static int musb_core_init(u16 musb_type, struct musb *musb)
550a7375 1449{
550a7375
FB		 1450 u8 reg;
1451 char *type;
0ea52ff4 1452 char aInfo[90], aRevision[32], aDate[12];
550a7375
FB		 1453 void __iomem *mbase = musb->mregs;
1454 int status = 0;
1455 int i;
1456
1457 /* log core options (read using indexed model) */
c6cf8b00 1458 reg = musb_read_configdata(mbase);
550a7375
FB		 1459
1460 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
51bf0d0e 1461 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
550a7375 1462 strcat(aInfo, ", dyn FIFOs");
51bf0d0e
AKG		 1463 musb->dyn_fifo = true;
1464 }
550a7375
FB		 1465 if (reg & MUSB_CONFIGDATA_MPRXE) {
1466 strcat(aInfo, ", bulk combine");
550a7375 1467 musb->bulk_combine = true;
550a7375
FB		 1468 }
1469 if (reg & MUSB_CONFIGDATA_MPTXE) {
1470 strcat(aInfo, ", bulk split");
550a7375 1471 musb->bulk_split = true;
550a7375
FB		 1472 }
1473 if (reg & MUSB_CONFIGDATA_HBRXE) {
1474 strcat(aInfo, ", HB-ISO Rx");
a483d706 1475 musb->hb_iso_rx = true;
550a7375
FB		 1476 }
1477 if (reg & MUSB_CONFIGDATA_HBTXE) {
1478 strcat(aInfo, ", HB-ISO Tx");
a483d706 1479 musb->hb_iso_tx = true;
550a7375
FB		 1480 }
1481 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1482 strcat(aInfo, ", SoftConn");
1483
1484 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1485 musb_driver_name, reg, aInfo);
1486
550a7375 1487 aDate[0] = 0;
550a7375
FB		 1488 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1489 musb->is_multipoint = 1;
1490 type = "M";
1491 } else {
1492 musb->is_multipoint = 0;
1493 type = "";
550a7375
FB		 1494#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1495 printk(KERN_ERR
1496 "%s: kernel must blacklist external hubs\n",
1497 musb_driver_name);
550a7375
FB		 1498#endif
1499 }
1500
1501 /* log release info */
32c3b94e
AG		 1502 musb->hwvers = musb_read_hwvers(mbase);
1503 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1504 MUSB_HWVERS_MINOR(musb->hwvers),
1505 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
550a7375
FB		 1506 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1507 musb_driver_name, type, aRevision, aDate);
1508
1509 /* configure ep0 */
c6cf8b00 1510 musb_configure_ep0(musb);
550a7375
FB		 1511
1512 /* discover endpoint configuration */
1513 musb->nr_endpoints = 1;
1514 musb->epmask = 1;
1515
ad517e9e
FB		 1516 if (musb->dyn_fifo)
1517 status = ep_config_from_table(musb);
1518 else
1519 status = ep_config_from_hw(musb);
550a7375
FB		 1520
1521 if (status < 0)
1522 return status;
1523
1524 /* finish init, and print endpoint config */
1525 for (i = 0; i < musb->nr_endpoints; i++) {
1526 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1527
1b40fc57 1528 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
ebf39920 1529#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1b40fc57
TL		 1530 if (musb->io.quirks & MUSB_IN_TUSB) {
1531 hw_ep->fifo_async = musb->async + 0x400 +
1532 musb->io.fifo_offset(i);
1533 hw_ep->fifo_sync = musb->sync + 0x400 +
1534 musb->io.fifo_offset(i);
1535 hw_ep->fifo_sync_va =
1536 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1537
1538 if (i == 0)
1539 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1540 else
1541 hw_ep->conf = mbase + 0x400 +
1542 (((i - 1) & 0xf) << 2);
1543 }
550a7375
FB		 1544#endif
1545
d026e9c7 1546 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
c6cf8b00 1547 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
550a7375
FB		 1548 hw_ep->rx_reinit = 1;
1549 hw_ep->tx_reinit = 1;
550a7375
FB		 1550
1551 if (hw_ep->max_packet_sz_tx) {
5c8a86e1 1552 dev_dbg(musb->controller,
550a7375
FB		 1553 "%s: hw_ep %d%s, %smax %d\n",
1554 musb_driver_name, i,
1555 hw_ep->is_shared_fifo ? "shared" : "tx",
1556 hw_ep->tx_double_buffered
1557 ? "doublebuffer, " : "",
1558 hw_ep->max_packet_sz_tx);
1559 }
1560 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
5c8a86e1 1561 dev_dbg(musb->controller,
550a7375
FB		 1562 "%s: hw_ep %d%s, %smax %d\n",
1563 musb_driver_name, i,
1564 "rx",
1565 hw_ep->rx_double_buffered
1566 ? "doublebuffer, " : "",
1567 hw_ep->max_packet_sz_rx);
1568 }
1569 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
5c8a86e1 1570 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
550a7375
FB		 1571 }
1572
1573 return 0;
1574}
1575
1576/*-------------------------------------------------------------------------*/
1577
550a7375
FB		 1578/*
1579 * handle all the irqs defined by the HDRC core. for now we expect: other
1580 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1581 * will be assigned, and the irq will already have been acked.
1582 *
1583 * called in irq context with spinlock held, irqs blocked
1584 */
1585irqreturn_t musb_interrupt(struct musb *musb)
1586{
1587 irqreturn_t retval = IRQ_NONE;
31a0ede0
FB		 1588 unsigned long status;
1589 unsigned long epnum;
b11e94d0 1590 u8 devctl;
31a0ede0
FB		 1591
1592 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1593 return IRQ_NONE;
550a7375
FB		 1594
1595 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
550a7375 1596
5c8a86e1 1597 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
c03da38d 1598 is_host_active(musb) ? "host" : "peripheral",
550a7375
FB		 1599 musb->int_usb, musb->int_tx, musb->int_rx);
1600
e3c93e1a
FB		 1601 /**
1602 * According to Mentor Graphics' documentation, flowchart on page 98,
1603 * IRQ should be handled as follows:
1604 *
1605 * . Resume IRQ
1606 * . Session Request IRQ
1607 * . VBUS Error IRQ
1608 * . Suspend IRQ
1609 * . Connect IRQ
1610 * . Disconnect IRQ
1611 * . Reset/Babble IRQ
1612 * . SOF IRQ (we're not using this one)
1613 * . Endpoint 0 IRQ
1614 * . TX Endpoints
1615 * . RX Endpoints
1616 *
1617 * We will be following that flowchart in order to avoid any problems
1618 * that might arise with internal Finite State Machine.
550a7375 1619 */
e3c93e1a 1620
7d9645fd 1621 if (musb->int_usb)
31a0ede0 1622 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
550a7375 1623
550a7375 1624 if (musb->int_tx & 1) {
c03da38d 1625 if (is_host_active(musb))
550a7375
FB		 1626 retval |= musb_h_ep0_irq(musb);
1627 else
1628 retval |= musb_g_ep0_irq(musb);
31a0ede0
FB		 1629
1630 /* we have just handled endpoint 0 IRQ, clear it */
1631 musb->int_tx &= ~BIT(0);
550a7375
FB		 1632 }
1633
31a0ede0
FB		 1634 status = musb->int_tx;
1635
1636 for_each_set_bit(epnum, &status, 16) {
1637 retval = IRQ_HANDLED;
1638 if (is_host_active(musb))
1639 musb_host_tx(musb, epnum);
1640 else
1641 musb_g_tx(musb, epnum);
550a7375
FB		 1642 }
1643
31a0ede0 1644 status = musb->int_rx;
e3c93e1a 1645
31a0ede0
FB		 1646 for_each_set_bit(epnum, &status, 16) {
1647 retval = IRQ_HANDLED;
1648 if (is_host_active(musb))
1649 musb_host_rx(musb, epnum);
1650 else
1651 musb_g_rx(musb, epnum);
550a7375
FB		 1652 }
1653
550a7375
FB		 1654 return retval;
1655}
981430a1 1656EXPORT_SYMBOL_GPL(musb_interrupt);
550a7375
FB		 1657
1658#ifndef CONFIG_MUSB_PIO_ONLY
d3608b6d 1659static bool use_dma = 1;
550a7375
FB		 1660
1661/* "modprobe ... use_dma=0" etc */
1662module_param(use_dma, bool, 0);
1663MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1664
1665void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1666{
550a7375
FB		 1667 /* called with controller lock already held */
1668
1669 if (!epnum) {
1670#ifndef CONFIG_USB_TUSB_OMAP_DMA
1671 if (!is_cppi_enabled()) {
1672 /* endpoint 0 */
c03da38d 1673 if (is_host_active(musb))
550a7375
FB		 1674 musb_h_ep0_irq(musb);
1675 else
1676 musb_g_ep0_irq(musb);
1677 }
1678#endif
1679 } else {
1680 /* endpoints 1..15 */
1681 if (transmit) {
c03da38d 1682 if (is_host_active(musb))
a04d46d0
FB		 1683 musb_host_tx(musb, epnum);
1684 else
1685 musb_g_tx(musb, epnum);
550a7375
FB		 1686 } else {
1687 /* receive */
c03da38d 1688 if (is_host_active(musb))
a04d46d0
FB		 1689 musb_host_rx(musb, epnum);
1690 else
1691 musb_g_rx(musb, epnum);
550a7375
FB		 1692 }
1693 }
1694}
9a35f876 1695EXPORT_SYMBOL_GPL(musb_dma_completion);
550a7375
FB		 1696
1697#else
1698#define use_dma 0
1699#endif
1700
1701/*-------------------------------------------------------------------------*/
1702
550a7375
FB		 1703static ssize_t
1704musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1705{
1706 struct musb *musb = dev_to_musb(dev);
1707 unsigned long flags;
1708 int ret = -EINVAL;
1709
1710 spin_lock_irqsave(&musb->lock, flags);
e47d9254 1711 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 1712 spin_unlock_irqrestore(&musb->lock, flags);
1713
1714 return ret;
1715}
1716
1717static ssize_t
1718musb_mode_store(struct device *dev, struct device_attribute *attr,
1719 const char *buf, size_t n)
1720{
1721 struct musb *musb = dev_to_musb(dev);
1722 unsigned long flags;
96a274d1 1723 int status;
550a7375
FB		 1724
1725 spin_lock_irqsave(&musb->lock, flags);
96a274d1
DB		 1726 if (sysfs_streq(buf, "host"))
1727 status = musb_platform_set_mode(musb, MUSB_HOST);
1728 else if (sysfs_streq(buf, "peripheral"))
1729 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1730 else if (sysfs_streq(buf, "otg"))
1731 status = musb_platform_set_mode(musb, MUSB_OTG);
1732 else
1733 status = -EINVAL;
550a7375
FB		 1734 spin_unlock_irqrestore(&musb->lock, flags);
1735
96a274d1 1736 return (status == 0) ? n : status;
550a7375
FB		 1737}
1738static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1739
1740static ssize_t
1741musb_vbus_store(struct device *dev, struct device_attribute *attr,
1742 const char *buf, size_t n)
1743{
1744 struct musb *musb = dev_to_musb(dev);
1745 unsigned long flags;
1746 unsigned long val;
1747
1748 if (sscanf(buf, "%lu", &val) < 1) {
b3b1cc3b 1749 dev_err(dev, "Invalid VBUS timeout ms value\n");
550a7375
FB		 1750 return -EINVAL;
1751 }
1752
1753 spin_lock_irqsave(&musb->lock, flags);
f7f9d63e
DB		 1754 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1755 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
e47d9254 1756 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
550a7375
FB		 1757 musb->is_active = 0;
1758 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1759 spin_unlock_irqrestore(&musb->lock, flags);
1760
1761 return n;
1762}
1763
1764static ssize_t
1765musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1766{
1767 struct musb *musb = dev_to_musb(dev);
1768 unsigned long flags;
1769 unsigned long val;
1770 int vbus;
1771
1772 spin_lock_irqsave(&musb->lock, flags);
1773 val = musb->a_wait_bcon;
f7f9d63e
DB		 1774 /* FIXME get_vbus_status() is normally #defined as false...
1775 * and is effectively TUSB-specific.
1776 */
550a7375
FB		 1777 vbus = musb_platform_get_vbus_status(musb);
1778 spin_unlock_irqrestore(&musb->lock, flags);
1779
f7f9d63e 1780 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
550a7375
FB		 1781 vbus ? "on" : "off", val);
1782}
1783static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1784
550a7375
FB		 1785/* Gadget drivers can't know that a host is connected so they might want
1786 * to start SRP, but users can. This allows userspace to trigger SRP.
1787 */
1788static ssize_t
1789musb_srp_store(struct device *dev, struct device_attribute *attr,
1790 const char *buf, size_t n)
1791{
1792 struct musb *musb = dev_to_musb(dev);
1793 unsigned short srp;
1794
1795 if (sscanf(buf, "%hu", &srp) != 1
1796 || (srp != 1)) {
b3b1cc3b 1797 dev_err(dev, "SRP: Value must be 1\n");
550a7375
FB		 1798 return -EINVAL;
1799 }
1800
1801 if (srp == 1)
1802 musb_g_wakeup(musb);
1803
1804 return n;
1805}
1806static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1807
94375751
FB		 1808static struct attribute *musb_attributes[] = {
1809 &dev_attr_mode.attr,
1810 &dev_attr_vbus.attr,
94375751 1811 &dev_attr_srp.attr,
94375751
FB		 1812 NULL
1813};
1814
1815static const struct attribute_group musb_attr_group = {
1816 .attrs = musb_attributes,
1817};
1818
550a7375
FB		 1819/* Only used to provide driver mode change events */
1820static void musb_irq_work(struct work_struct *data)
1821{
1822 struct musb *musb = container_of(data, struct musb, irq_work);
550a7375 1823
e47d9254
AT		 1824 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1825 musb->xceiv_old_state = musb->xceiv->otg->state;
550a7375
FB		 1826 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1827 }
1828}
1829
83b8f5b8 1830static void musb_recover_from_babble(struct musb *musb)
ca88fc2e 1831{
b4dc38fd
FB		 1832 int ret;
1833 u8 devctl;
ca88fc2e 1834
0244336f
FB		 1835 musb_disable_interrupts(musb);
1836
83b8f5b8
FB		 1837 /*
1838 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1839 * it some slack and wait for 10us.
1840 */
1841 udelay(10);
1842
b28a6432 1843 ret = musb_platform_recover(musb);
ba7ee8bb
FB		 1844 if (ret) {
1845 musb_enable_interrupts(musb);
d871c622 1846 return;
ba7ee8bb 1847 }
ca88fc2e 1848
b4dc38fd
FB		 1849 /* drop session bit */
1850 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1851 devctl &= ~MUSB_DEVCTL_SESSION;
1852 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
ca88fc2e 1853
b4dc38fd
FB		 1854 /* tell usbcore about it */
1855 musb_root_disconnect(musb);
ca88fc2e
DM		 1856
1857 /*
d871c622
GC		 1858 * When a babble condition occurs, the musb controller
1859 * removes the session bit and the endpoint config is lost.
ca88fc2e
DM		 1860 */
1861 if (musb->dyn_fifo)
b4dc38fd 1862 ret = ep_config_from_table(musb);
ca88fc2e 1863 else
b4dc38fd 1864 ret = ep_config_from_hw(musb);
ca88fc2e 1865
b4dc38fd
FB		 1866 /* restart session */
1867 if (ret == 0)
ca88fc2e
DM		 1868 musb_start(musb);
1869}
1870
550a7375
FB		 1871/* --------------------------------------------------------------------------
1872 * Init support
1873 */
1874
41ac7b3a 1875static struct musb *allocate_instance(struct device *dev,
ca6d1b13 1876 struct musb_hdrc_config *config, void __iomem *mbase)
550a7375
FB		 1877{
1878 struct musb *musb;
1879 struct musb_hw_ep *ep;
1880 int epnum;
74c2e936 1881 int ret;
550a7375 1882
74c2e936
DM		 1883 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1884 if (!musb)
550a7375 1885 return NULL;
550a7375 1886
550a7375
FB		 1887 INIT_LIST_HEAD(&musb->control);
1888 INIT_LIST_HEAD(&musb->in_bulk);
1889 INIT_LIST_HEAD(&musb->out_bulk);
1890
550a7375 1891 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
f7f9d63e 1892 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
550a7375
FB		 1893 musb->mregs = mbase;
1894 musb->ctrl_base = mbase;
1895 musb->nIrq = -ENODEV;
ca6d1b13 1896 musb->config = config;
02582b92 1897 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
550a7375 1898 for (epnum = 0, ep = musb->endpoints;
ca6d1b13 1899 epnum < musb->config->num_eps;
550a7375 1900 epnum++, ep++) {
550a7375
FB		 1901 ep->musb = musb;
1902 ep->epnum = epnum;
1903 }
1904
1905 musb->controller = dev;
743411b3 1906
74c2e936
DM		 1907 ret = musb_host_alloc(musb);
1908 if (ret < 0)
1909 goto err_free;
1910
1911 dev_set_drvdata(dev, musb);
1912
550a7375 1913 return musb;
74c2e936
DM		 1914
1915err_free:
1916 return NULL;
550a7375
FB		 1917}
1918
1919static void musb_free(struct musb *musb)
1920{
1921 /* this has multiple entry modes. it handles fault cleanup after
1922 * probe(), where things may be partially set up, as well as rmmod
1923 * cleanup after everything's been de-activated.
1924 */
1925
1926#ifdef CONFIG_SYSFS
94375751 1927 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
550a7375
FB		 1928#endif
1929
97a39896
AKG		 1930 if (musb->nIrq >= 0) {
1931 if (musb->irq_wake)
1932 disable_irq_wake(musb->nIrq);
550a7375
FB		 1933 free_irq(musb->nIrq, musb);
1934 }
550a7375 1935
74c2e936 1936 musb_host_free(musb);
550a7375
FB		 1937}
1938
8ed1fb79
DM		 1939static void musb_deassert_reset(struct work_struct *work)
1940{
1941 struct musb *musb;
1942 unsigned long flags;
1943
1944 musb = container_of(work, struct musb, deassert_reset_work.work);
1945
1946 spin_lock_irqsave(&musb->lock, flags);
1947
1948 if (musb->port1_status & USB_PORT_STAT_RESET)
1949 musb_port_reset(musb, false);
1950
1951 spin_unlock_irqrestore(&musb->lock, flags);
1952}
1953
550a7375
FB		 1954/*
1955 * Perform generic per-controller initialization.
1956 *
28dd924a
SS		 1957 * @dev: the controller (already clocked, etc)
1958 * @nIrq: IRQ number
1959 * @ctrl: virtual address of controller registers,
550a7375
FB		 1960 * not yet corrected for platform-specific offsets
1961 */
41ac7b3a 1962static int
550a7375
FB		 1963musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1964{
1965 int status;
1966 struct musb *musb;
c1a7d67c 1967 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
550a7375
FB		 1968
1969 /* The driver might handle more features than the board; OK.
1970 * Fail when the board needs a feature that's not enabled.
1971 */
1972 if (!plat) {
1973 dev_dbg(dev, "no platform_data?\n");
34e2beb2
SS		 1974 status = -ENODEV;
1975 goto fail0;
550a7375 1976 }
34e2beb2 1977
550a7375 1978 /* allocate */
ca6d1b13 1979 musb = allocate_instance(dev, plat->config, ctrl);
34e2beb2
SS		 1980 if (!musb) {
1981 status = -ENOMEM;
1982 goto fail0;
1983 }
550a7375
FB		 1984
1985 spin_lock_init(&musb->lock);
550a7375 1986 musb->board_set_power = plat->set_power;
550a7375 1987 musb->min_power = plat->min_power;
f7ec9437 1988 musb->ops = plat->platform_ops;
9ad96e69 1989 musb->port_mode = plat->mode;
550a7375 1990
1b40fc57
TL		 1991 /*
1992 * Initialize the default IO functions. At least omap2430 needs
1993 * these early. We initialize the platform specific IO functions
1994 * later on.
1995 */
1996 musb_readb = musb_default_readb;
1997 musb_writeb = musb_default_writeb;
1998 musb_readw = musb_default_readw;
1999 musb_writew = musb_default_writew;
2000 musb_readl = musb_default_readl;
2001 musb_writel = musb_default_writel;
2002
3e43a072
FB		 2003 /* We need musb_read/write functions initialized for PM */
2004 pm_runtime_use_autosuspend(musb->controller);
2005 pm_runtime_set_autosuspend_delay(musb->controller, 200);
2006 pm_runtime_irq_safe(musb->controller);
2007 pm_runtime_enable(musb->controller);
2008
84e250ff 2009 /* The musb_platform_init() call:
baef653a
PDS		 2010 * - adjusts musb->mregs
2011 * - sets the musb->isr
5ae477b0 2012 * - may initialize an integrated transceiver
721002ec 2013 * - initializes musb->xceiv, usually by otg_get_phy()
84e250ff 2014 * - stops powering VBUS
84e250ff 2015 *
7c9d440e 2016 * There are various transceiver configurations. Blackfin,
84e250ff
DB		 2017 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2018 * external/discrete ones in various flavors (twl4030 family,
2019 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
550a7375 2020 */
ea65df57 2021 status = musb_platform_init(musb);
550a7375 2022 if (status < 0)
03491761 2023 goto fail1;
34e2beb2 2024
550a7375
FB		 2025 if (!musb->isr) {
2026 status = -ENODEV;
c04352a5 2027 goto fail2;
550a7375
FB		 2028 }
2029
1b40fc57
TL		 2030 if (musb->ops->quirks)
2031 musb->io.quirks = musb->ops->quirks;
2032
d026e9c7
TL		 2033 /* At least tusb6010 has it's own offsets.. */
2034 if (musb->ops->ep_offset)
2035 musb->io.ep_offset = musb->ops->ep_offset;
2036 if (musb->ops->ep_select)
2037 musb->io.ep_select = musb->ops->ep_select;
2038
2039 /* ..and some devices use indexed offset or flat offset */
2040 if (musb->io.quirks & MUSB_INDEXED_EP) {
2041 musb->io.ep_offset = musb_indexed_ep_offset;
2042 musb->io.ep_select = musb_indexed_ep_select;
2043 } else {
2044 musb->io.ep_offset = musb_flat_ep_offset;
2045 musb->io.ep_select = musb_flat_ep_select;
2046 }
2047
8a77f05a
TL		 2048 if (musb->ops->fifo_mode)
2049 fifo_mode = musb->ops->fifo_mode;
2050 else
2051 fifo_mode = 4;
2052
1b40fc57
TL		 2053 if (musb->ops->fifo_offset)
2054 musb->io.fifo_offset = musb->ops->fifo_offset;
2055 else
2056 musb->io.fifo_offset = musb_default_fifo_offset;
2057
2058 if (musb->ops->readb)
2059 musb_readb = musb->ops->readb;
2060 if (musb->ops->writeb)
2061 musb_writeb = musb->ops->writeb;
2062 if (musb->ops->readw)
2063 musb_readw = musb->ops->readw;
2064 if (musb->ops->writew)
2065 musb_writew = musb->ops->writew;
2066 if (musb->ops->readl)
2067 musb_readl = musb->ops->readl;
2068 if (musb->ops->writel)
2069 musb_writel = musb->ops->writel;
2070
2071 if (musb->ops->read_fifo)
2072 musb->io.read_fifo = musb->ops->read_fifo;
2073 else
2074 musb->io.read_fifo = musb_default_read_fifo;
2075
2076 if (musb->ops->write_fifo)
2077 musb->io.write_fifo = musb->ops->write_fifo;
2078 else
2079 musb->io.write_fifo = musb_default_write_fifo;
2080
ffb865b1 2081 if (!musb->xceiv->io_ops) {
bf070bc1 2082 musb->xceiv->io_dev = musb->controller;
ffb865b1
HK		 2083 musb->xceiv->io_priv = musb->mregs;
2084 musb->xceiv->io_ops = &musb_ulpi_access;
2085 }
2086
c04352a5
GI		 2087 pm_runtime_get_sync(musb->controller);
2088
48054147 2089 if (use_dma && dev->dma_mask) {
66c01883 2090 musb->dma_controller = dma_controller_create(musb, musb->mregs);
48054147
SAS		 2091 if (IS_ERR(musb->dma_controller)) {
2092 status = PTR_ERR(musb->dma_controller);
2093 goto fail2_5;
2094 }
2095 }
550a7375
FB		 2096
2097 /* be sure interrupts are disabled before connecting ISR */
2098 musb_platform_disable(musb);
2099 musb_generic_disable(musb);
2100
66fadea5
SAS		 2101 /* Init IRQ workqueue before request_irq */
2102 INIT_WORK(&musb->irq_work, musb_irq_work);
8ed1fb79
DM		 2103 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2104 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
66fadea5 2105
550a7375 2106 /* setup musb parts of the core (especially endpoints) */
ca6d1b13 2107 status = musb_core_init(plat->config->multipoint
550a7375
FB		 2108 ? MUSB_CONTROLLER_MHDRC
2109 : MUSB_CONTROLLER_HDRC, musb);
2110 if (status < 0)
34e2beb2 2111 goto fail3;
550a7375 2112
f7f9d63e 2113 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
f7f9d63e 2114
550a7375 2115 /* attach to the IRQ */
427c4f33 2116 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
550a7375
FB		 2117 dev_err(dev, "request_irq %d failed!\n", nIrq);
2118 status = -ENODEV;
34e2beb2 2119 goto fail3;
550a7375
FB		 2120 }
2121 musb->nIrq = nIrq;
032ec49f 2122 /* FIXME this handles wakeup irqs wrong */
c48a5155
FB		 2123 if (enable_irq_wake(nIrq) == 0) {
2124 musb->irq_wake = 1;
550a7375 2125 device_init_wakeup(dev, 1);
c48a5155
FB		 2126 } else {
2127 musb->irq_wake = 0;
2128 }
550a7375 2129
032ec49f
FB		 2130 /* program PHY to use external vBus if required */
2131 if (plat->extvbus) {
2132 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2133 busctl |= MUSB_ULPI_USE_EXTVBUS;
2134 musb_write_ulpi_buscontrol(musb->mregs, busctl);
550a7375 2135 }
550a7375 2136
e5615112
GI		 2137 if (musb->xceiv->otg->default_a) {
2138 MUSB_HST_MODE(musb);
e47d9254 2139 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
e5615112
GI		 2140 } else {
2141 MUSB_DEV_MODE(musb);
e47d9254 2142 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
e5615112 2143 }
550a7375 2144
6c5f6a6f
DM		 2145 switch (musb->port_mode) {
2146 case MUSB_PORT_MODE_HOST:
2147 status = musb_host_setup(musb, plat->power);
2df6761e
FB		 2148 if (status < 0)
2149 goto fail3;
2150 status = musb_platform_set_mode(musb, MUSB_HOST);
6c5f6a6f
DM		 2151 break;
2152 case MUSB_PORT_MODE_GADGET:
2153 status = musb_gadget_setup(musb);
2df6761e
FB		 2154 if (status < 0)
2155 goto fail3;
2156 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
6c5f6a6f
DM		 2157 break;
2158 case MUSB_PORT_MODE_DUAL_ROLE:
2159 status = musb_host_setup(musb, plat->power);
2160 if (status < 0)
2161 goto fail3;
2162 status = musb_gadget_setup(musb);
2df6761e 2163 if (status) {
0d2dd7ea 2164 musb_host_cleanup(musb);
2df6761e
FB		 2165 goto fail3;
2166 }
2167 status = musb_platform_set_mode(musb, MUSB_OTG);
6c5f6a6f
DM		 2168 break;
2169 default:
2170 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2171 break;
2172 }
550a7375 2173
461972d8 2174 if (status < 0)
34e2beb2 2175 goto fail3;
550a7375 2176
7f7f9e2a
FB		 2177 status = musb_init_debugfs(musb);
2178 if (status < 0)
b0f9da7e 2179 goto fail4;
7f7f9e2a 2180
94375751 2181 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
28c2c51c 2182 if (status)
b0f9da7e 2183 goto fail5;
550a7375 2184
c04352a5
GI		 2185 pm_runtime_put(musb->controller);
2186
28c2c51c 2187 return 0;
550a7375 2188
b0f9da7e
FB		 2189fail5:
2190 musb_exit_debugfs(musb);
2191
34e2beb2 2192fail4:
032ec49f 2193 musb_gadget_cleanup(musb);
0d2dd7ea 2194 musb_host_cleanup(musb);
34e2beb2
SS		 2195
2196fail3:
66fadea5 2197 cancel_work_sync(&musb->irq_work);
8ed1fb79
DM		 2198 cancel_delayed_work_sync(&musb->finish_resume_work);
2199 cancel_delayed_work_sync(&musb->deassert_reset_work);
f3ce4d5b
SAS		 2200 if (musb->dma_controller)
2201 dma_controller_destroy(musb->dma_controller);
48054147 2202fail2_5:
c04352a5
GI		 2203 pm_runtime_put_sync(musb->controller);
2204
2205fail2:
34e2beb2
SS		 2206 if (musb->irq_wake)
2207 device_init_wakeup(dev, 0);
550a7375 2208 musb_platform_exit(musb);
28c2c51c 2209
34e2beb2 2210fail1:
681d1e87 2211 pm_runtime_disable(musb->controller);
34e2beb2
SS		 2212 dev_err(musb->controller,
2213 "musb_init_controller failed with status %d\n", status);
2214
28c2c51c
FB		 2215 musb_free(musb);
2216
34e2beb2
SS		 2217fail0:
2218
28c2c51c
FB		 2219 return status;
2220
550a7375
FB		 2221}
2222
2223/*-------------------------------------------------------------------------*/
2224
2225/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2226 * bridge to a platform device; this driver then suffices.
2227 */
41ac7b3a 2228static int musb_probe(struct platform_device *pdev)
550a7375
FB		 2229{
2230 struct device *dev = &pdev->dev;
fcf173e4 2231 int irq = platform_get_irq_byname(pdev, "mc");
550a7375
FB		 2232 struct resource *iomem;
2233 void __iomem *base;
2234
1f79b26c 2235 if (irq <= 0)
550a7375
FB		 2236 return -ENODEV;
2237
1f79b26c 2238 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b42f7f30
FB		 2239 base = devm_ioremap_resource(dev, iomem);
2240 if (IS_ERR(base))
2241 return PTR_ERR(base);
550a7375 2242
b42f7f30 2243 return musb_init_controller(dev, irq, base);
550a7375
FB		 2244}
2245
fb4e98ab 2246static int musb_remove(struct platform_device *pdev)
550a7375 2247{
8d2421e6
AKG		 2248 struct device *dev = &pdev->dev;
2249 struct musb *musb = dev_to_musb(dev);
550a7375
FB		 2250
2251 /* this gets called on rmmod.
2252 * - Host mode: host may still be active
2253 * - Peripheral mode: peripheral is deactivated (or never-activated)
2254 * - OTG mode: both roles are deactivated (or never-activated)
2255 */
7f7f9e2a 2256 musb_exit_debugfs(musb);
550a7375 2257 musb_shutdown(pdev);
461972d8 2258
8d1aad74
SAS		 2259 if (musb->dma_controller)
2260 dma_controller_destroy(musb->dma_controller);
2261
66fadea5 2262 cancel_work_sync(&musb->irq_work);
8ed1fb79
DM		 2263 cancel_delayed_work_sync(&musb->finish_resume_work);
2264 cancel_delayed_work_sync(&musb->deassert_reset_work);
550a7375 2265 musb_free(musb);
8d2421e6 2266 device_init_wakeup(dev, 0);
550a7375
FB		 2267 return 0;
2268}
2269
2270#ifdef CONFIG_PM
2271
3c8a5fcc 2272static void musb_save_context(struct musb *musb)
4f712e01
AKG		 2273{
2274 int i;
2275 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2276 void __iomem *epio;
4f712e01 2277
032ec49f
FB		 2278 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2279 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2280 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
7421107b 2281 musb->context.power = musb_readb(musb_base, MUSB_POWER);
7421107b
FB		 2282 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2283 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2284 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
4f712e01 2285
ae9b2ad2 2286 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2287 struct musb_hw_ep *hw_ep;
2288
2289 hw_ep = &musb->endpoints[i];
2290 if (!hw_ep)
2291 continue;
2292
2293 epio = hw_ep->regs;
2294 if (!epio)
2295 continue;
2296
ea737554 2297 musb_writeb(musb_base, MUSB_INDEX, i);
7421107b 2298 musb->context.index_regs[i].txmaxp =
ae9b2ad2 2299 musb_readw(epio, MUSB_TXMAXP);
7421107b 2300 musb->context.index_regs[i].txcsr =
ae9b2ad2 2301 musb_readw(epio, MUSB_TXCSR);
7421107b 2302 musb->context.index_regs[i].rxmaxp =
ae9b2ad2 2303 musb_readw(epio, MUSB_RXMAXP);
7421107b 2304 musb->context.index_regs[i].rxcsr =
ae9b2ad2 2305 musb_readw(epio, MUSB_RXCSR);
4f712e01
AKG		 2306
2307 if (musb->dyn_fifo) {
7421107b 2308 musb->context.index_regs[i].txfifoadd =
4f712e01 2309 musb_read_txfifoadd(musb_base);
7421107b 2310 musb->context.index_regs[i].rxfifoadd =
4f712e01 2311 musb_read_rxfifoadd(musb_base);
7421107b 2312 musb->context.index_regs[i].txfifosz =
4f712e01 2313 musb_read_txfifosz(musb_base);
7421107b 2314 musb->context.index_regs[i].rxfifosz =
4f712e01
AKG		 2315 musb_read_rxfifosz(musb_base);
2316 }
032ec49f
FB		 2317
2318 musb->context.index_regs[i].txtype =
2319 musb_readb(epio, MUSB_TXTYPE);
2320 musb->context.index_regs[i].txinterval =
2321 musb_readb(epio, MUSB_TXINTERVAL);
2322 musb->context.index_regs[i].rxtype =
2323 musb_readb(epio, MUSB_RXTYPE);
2324 musb->context.index_regs[i].rxinterval =
2325 musb_readb(epio, MUSB_RXINTERVAL);
2326
2327 musb->context.index_regs[i].txfunaddr =
2328 musb_read_txfunaddr(musb_base, i);
2329 musb->context.index_regs[i].txhubaddr =
2330 musb_read_txhubaddr(musb_base, i);
2331 musb->context.index_regs[i].txhubport =
2332 musb_read_txhubport(musb_base, i);
2333
2334 musb->context.index_regs[i].rxfunaddr =
2335 musb_read_rxfunaddr(musb_base, i);
2336 musb->context.index_regs[i].rxhubaddr =
2337 musb_read_rxhubaddr(musb_base, i);
2338 musb->context.index_regs[i].rxhubport =
2339 musb_read_rxhubport(musb_base, i);
4f712e01 2340 }
4f712e01
AKG		 2341}
2342
3c8a5fcc 2343static void musb_restore_context(struct musb *musb)
4f712e01
AKG		 2344{
2345 int i;
2346 void __iomem *musb_base = musb->mregs;
2347 void __iomem *ep_target_regs;
ae9b2ad2 2348 void __iomem *epio;
33f8d75f 2349 u8 power;
4f712e01 2350
032ec49f
FB		 2351 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2352 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2353 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
33f8d75f
RQ		 2354
2355 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2356 power = musb_readb(musb_base, MUSB_POWER);
2357 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2358 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2359 power |= musb->context.power;
2360 musb_writeb(musb_base, MUSB_POWER, power);
2361
b18d26f6 2362 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
af5ec14d 2363 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
7421107b
FB		 2364 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2365 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
4f712e01 2366
ae9b2ad2 2367 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2368 struct musb_hw_ep *hw_ep;
2369
2370 hw_ep = &musb->endpoints[i];
2371 if (!hw_ep)
2372 continue;
2373
2374 epio = hw_ep->regs;
2375 if (!epio)
2376 continue;
2377
ea737554 2378 musb_writeb(musb_base, MUSB_INDEX, i);
ae9b2ad2 2379 musb_writew(epio, MUSB_TXMAXP,
7421107b 2380 musb->context.index_regs[i].txmaxp);
ae9b2ad2 2381 musb_writew(epio, MUSB_TXCSR,
7421107b 2382 musb->context.index_regs[i].txcsr);
ae9b2ad2 2383 musb_writew(epio, MUSB_RXMAXP,
7421107b 2384 musb->context.index_regs[i].rxmaxp);
ae9b2ad2 2385 musb_writew(epio, MUSB_RXCSR,
7421107b 2386 musb->context.index_regs[i].rxcsr);
4f712e01
AKG		 2387
2388 if (musb->dyn_fifo) {
2389 musb_write_txfifosz(musb_base,
7421107b 2390 musb->context.index_regs[i].txfifosz);
4f712e01 2391 musb_write_rxfifosz(musb_base,
7421107b 2392 musb->context.index_regs[i].rxfifosz);
4f712e01 2393 musb_write_txfifoadd(musb_base,
7421107b 2394 musb->context.index_regs[i].txfifoadd);
4f712e01 2395 musb_write_rxfifoadd(musb_base,
7421107b 2396 musb->context.index_regs[i].rxfifoadd);
4f712e01
AKG		 2397 }
2398
032ec49f 2399 musb_writeb(epio, MUSB_TXTYPE,
7421107b 2400 musb->context.index_regs[i].txtype);
032ec49f 2401 musb_writeb(epio, MUSB_TXINTERVAL,
7421107b 2402 musb->context.index_regs[i].txinterval);
032ec49f 2403 musb_writeb(epio, MUSB_RXTYPE,
7421107b 2404 musb->context.index_regs[i].rxtype);
032ec49f 2405 musb_writeb(epio, MUSB_RXINTERVAL,
4f712e01 2406
032ec49f
FB		 2407 musb->context.index_regs[i].rxinterval);
2408 musb_write_txfunaddr(musb_base, i,
7421107b 2409 musb->context.index_regs[i].txfunaddr);
032ec49f 2410 musb_write_txhubaddr(musb_base, i,
7421107b 2411 musb->context.index_regs[i].txhubaddr);
032ec49f 2412 musb_write_txhubport(musb_base, i,
7421107b 2413 musb->context.index_regs[i].txhubport);
4f712e01 2414
032ec49f
FB		 2415 ep_target_regs =
2416 musb_read_target_reg_base(i, musb_base);
4f712e01 2417
032ec49f 2418 musb_write_rxfunaddr(ep_target_regs,
7421107b 2419 musb->context.index_regs[i].rxfunaddr);
032ec49f 2420 musb_write_rxhubaddr(ep_target_regs,
7421107b 2421 musb->context.index_regs[i].rxhubaddr);
032ec49f 2422 musb_write_rxhubport(ep_target_regs,
7421107b 2423 musb->context.index_regs[i].rxhubport);
4f712e01 2424 }
3c5fec75 2425 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
4f712e01
AKG		 2426}
2427
48fea965 2428static int musb_suspend(struct device *dev)
550a7375 2429{
8220796d 2430 struct musb *musb = dev_to_musb(dev);
550a7375 2431 unsigned long flags;
550a7375 2432
550a7375
FB		 2433 spin_lock_irqsave(&musb->lock, flags);
2434
2435 if (is_peripheral_active(musb)) {
2436 /* FIXME force disconnect unless we know USB will wake
2437 * the system up quickly enough to respond ...
2438 */
2439 } else if (is_host_active(musb)) {
2440 /* we know all the children are suspended; sometimes
2441 * they will even be wakeup-enabled.
2442 */
2443 }
2444
c338412b
DM		 2445 musb_save_context(musb);
2446
550a7375
FB		 2447 spin_unlock_irqrestore(&musb->lock, flags);
2448 return 0;
2449}
2450
3e87d9a3 2451static int musb_resume(struct device *dev)
550a7375 2452{
c338412b 2453 struct musb *musb = dev_to_musb(dev);
b87fd2f7
SAS		 2454 u8 devctl;
2455 u8 mask;
c338412b
DM		 2456
2457 /*
2458 * For static cmos like DaVinci, register values were preserved
0ec8fd70
KK		 2459 * unless for some reason the whole soc powered down or the USB
2460 * module got reset through the PSC (vs just being disabled).
c338412b
DM		 2461 *
2462 * For the DSPS glue layer though, a full register restore has to
2463 * be done. As it shouldn't harm other platforms, we do it
2464 * unconditionally.
550a7375 2465 */
c338412b
DM		 2466
2467 musb_restore_context(musb);
2468
b87fd2f7
SAS		 2469 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2470 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2471 if ((devctl & mask) != (musb->context.devctl & mask))
2472 musb->port1_status = 0;
baadd52f
SAS		 2473 if (musb->need_finish_resume) {
2474 musb->need_finish_resume = 0;
2475 schedule_delayed_work(&musb->finish_resume_work,
2476 msecs_to_jiffies(20));
2477 }
a1fc1920
SAS		 2478
2479 /*
2480 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2481 * out of suspend
2482 */
2483 pm_runtime_disable(dev);
2484 pm_runtime_set_active(dev);
2485 pm_runtime_enable(dev);
550a7375
FB		 2486 return 0;
2487}
2488
7acc6197
HH		 2489static int musb_runtime_suspend(struct device *dev)
2490{
2491 struct musb *musb = dev_to_musb(dev);
2492
2493 musb_save_context(musb);
2494
2495 return 0;
2496}
2497
2498static int musb_runtime_resume(struct device *dev)
2499{
2500 struct musb *musb = dev_to_musb(dev);
2501 static int first = 1;
2502
2503 /*
2504 * When pm_runtime_get_sync called for the first time in driver
2505 * init, some of the structure is still not initialized which is
2506 * used in restore function. But clock needs to be
2507 * enabled before any register access, so
2508 * pm_runtime_get_sync has to be called.
2509 * Also context restore without save does not make
2510 * any sense
2511 */
2512 if (!first)
2513 musb_restore_context(musb);
2514 first = 0;
2515
9298b4aa
BL		 2516 if (musb->need_finish_resume) {
2517 musb->need_finish_resume = 0;
2518 schedule_delayed_work(&musb->finish_resume_work,
2519 msecs_to_jiffies(20));
2520 }
2521
7acc6197
HH		 2522 return 0;
2523}
2524
47145210 2525static const struct dev_pm_ops musb_dev_pm_ops = {
48fea965 2526 .suspend = musb_suspend,
3e87d9a3 2527 .resume = musb_resume,
7acc6197
HH		 2528 .runtime_suspend = musb_runtime_suspend,
2529 .runtime_resume = musb_runtime_resume,
48fea965
MD		 2530};
2531
2532#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
550a7375 2533#else
48fea965 2534#define MUSB_DEV_PM_OPS NULL
550a7375
FB		 2535#endif
2536
2537static struct platform_driver musb_driver = {
2538 .driver = {
2539 .name = (char *)musb_driver_name,
2540 .bus = &platform_bus_type,
48fea965 2541 .pm = MUSB_DEV_PM_OPS,
550a7375 2542 },
e9e8c85e 2543 .probe = musb_probe,
7690417d 2544 .remove = musb_remove,
550a7375 2545 .shutdown = musb_shutdown,
550a7375
FB		 2546};
2547
89f836a8 2548module_platform_driver(musb_driver);
Linux kernel - Deliverables
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