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usb: musb: Change to use new IO access
[deliverable/linux.git] / drivers / usb / musb / musb_core.c
CommitLineData
550a7375
FB		 1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
550a7375 85 * - platform_device for addressing, irq, and platform_data
5ae477b0 86 * - platform_data is mostly for board-specific information
c767c1c6 87 * (plus recentrly, SOC or family details)
550a7375
FB		 88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
550a7375
FB		 96#include <linux/list.h>
97#include <linux/kobject.h>
9303961f 98#include <linux/prefetch.h>
550a7375
FB		 99#include <linux/platform_device.h>
100#include <linux/io.h>
8d2421e6 101#include <linux/dma-mapping.h>
550a7375 102
550a7375
FB		 103#include "musb_core.h"
104
f7f9d63e 105#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
550a7375
FB		 106
107
550a7375
FB		 108#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110
e8164f64 111#define MUSB_VERSION "6.0"
550a7375
FB		 112
113#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114
05ac10dd 115#define MUSB_DRIVER_NAME "musb-hdrc"
550a7375
FB		 116const char musb_driver_name[] = MUSB_DRIVER_NAME;
117
118MODULE_DESCRIPTION(DRIVER_INFO);
119MODULE_AUTHOR(DRIVER_AUTHOR);
120MODULE_LICENSE("GPL");
121MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122
123
124/*-------------------------------------------------------------------------*/
125
126static inline struct musb *dev_to_musb(struct device *dev)
127{
550a7375 128 return dev_get_drvdata(dev);
550a7375
FB		 129}
130
131/*-------------------------------------------------------------------------*/
132
ffb865b1 133#ifndef CONFIG_BLACKFIN
b96d3b08 134static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
ffb865b1 135{
b96d3b08 136 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 137 int i = 0;
138 u8 r;
139 u8 power;
bf070bc1
GI		 140 int ret;
141
142 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 143
144 /* Make sure the transceiver is not in low power mode */
145 power = musb_readb(addr, MUSB_POWER);
146 power &= ~MUSB_POWER_SUSPENDM;
147 musb_writeb(addr, MUSB_POWER, power);
148
149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
151 */
152
153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
156
157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158 & MUSB_ULPI_REG_CMPLT)) {
159 i++;
bf070bc1
GI		 160 if (i == 10000) {
161 ret = -ETIMEDOUT;
162 goto out;
163 }
ffb865b1
HK		 164
165 }
166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167 r &= ~MUSB_ULPI_REG_CMPLT;
168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
169
bf070bc1
GI		 170 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
171
172out:
173 pm_runtime_put(phy->io_dev);
174
175 return ret;
ffb865b1
HK		 176}
177
b96d3b08 178static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
ffb865b1 179{
b96d3b08 180 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 181 int i = 0;
182 u8 r = 0;
183 u8 power;
bf070bc1
GI		 184 int ret = 0;
185
186 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 187
188 /* Make sure the transceiver is not in low power mode */
189 power = musb_readb(addr, MUSB_POWER);
190 power &= ~MUSB_POWER_SUSPENDM;
191 musb_writeb(addr, MUSB_POWER, power);
192
193 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
194 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
195 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
196
197 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
198 & MUSB_ULPI_REG_CMPLT)) {
199 i++;
bf070bc1
GI		 200 if (i == 10000) {
201 ret = -ETIMEDOUT;
202 goto out;
203 }
ffb865b1
HK		 204 }
205
206 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
207 r &= ~MUSB_ULPI_REG_CMPLT;
208 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
209
bf070bc1
GI		 210out:
211 pm_runtime_put(phy->io_dev);
212
213 return ret;
ffb865b1
HK		 214}
215#else
f2263db7
MF		 216#define musb_ulpi_read NULL
217#define musb_ulpi_write NULL
ffb865b1
HK		 218#endif
219
b96d3b08 220static struct usb_phy_io_ops musb_ulpi_access = {
ffb865b1
HK		 221 .read = musb_ulpi_read,
222 .write = musb_ulpi_write,
223};
224
225/*-------------------------------------------------------------------------*/
226
1b40fc57
TL		 227static u32 musb_default_fifo_offset(u8 epnum)
228{
229 return 0x20 + (epnum * 4);
230}
231
232static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
233{
234 return __raw_readb(addr + offset);
235}
236
237static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
238{
239 __raw_writeb(data, addr + offset);
240}
241
242static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
243{
244 return __raw_readw(addr + offset);
245}
246
247static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
248{
249 __raw_writew(data, addr + offset);
250}
251
252static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
253{
254 return __raw_readl(addr + offset);
255}
256
257static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
258{
259 __raw_writel(data, addr + offset);
260}
c6cf8b00 261
550a7375
FB		 262/*
263 * Load an endpoint's FIFO
264 */
1b40fc57
TL		 265static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
266 const u8 *src)
550a7375 267{
5c8a86e1 268 struct musb *musb = hw_ep->musb;
550a7375
FB		 269 void __iomem *fifo = hw_ep->fifo;
270
603fe2b2
AKG		 271 if (unlikely(len == 0))
272 return;
273
550a7375
FB		 274 prefetch((u8 *)src);
275
5c8a86e1 276 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 277 'T', hw_ep->epnum, fifo, len, src);
278
279 /* we can't assume unaligned reads work */
280 if (likely((0x01 & (unsigned long) src) == 0)) {
281 u16 index = 0;
282
283 /* best case is 32bit-aligned source address */
284 if ((0x02 & (unsigned long) src) == 0) {
285 if (len >= 4) {
2bf0a8f6 286 iowrite32_rep(fifo, src + index, len >> 2);
550a7375
FB		 287 index += len & ~0x03;
288 }
289 if (len & 0x02) {
290 musb_writew(fifo, 0, *(u16 *)&src[index]);
291 index += 2;
292 }
293 } else {
294 if (len >= 2) {
2bf0a8f6 295 iowrite16_rep(fifo, src + index, len >> 1);
550a7375
FB		 296 index += len & ~0x01;
297 }
298 }
299 if (len & 0x01)
300 musb_writeb(fifo, 0, src[index]);
301 } else {
302 /* byte aligned */
2bf0a8f6 303 iowrite8_rep(fifo, src, len);
550a7375
FB		 304 }
305}
306
307/*
308 * Unload an endpoint's FIFO
309 */
1b40fc57 310static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
550a7375 311{
5c8a86e1 312 struct musb *musb = hw_ep->musb;
550a7375
FB		 313 void __iomem *fifo = hw_ep->fifo;
314
603fe2b2
AKG		 315 if (unlikely(len == 0))
316 return;
317
5c8a86e1 318 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 319 'R', hw_ep->epnum, fifo, len, dst);
320
321 /* we can't assume unaligned writes work */
322 if (likely((0x01 & (unsigned long) dst) == 0)) {
323 u16 index = 0;
324
325 /* best case is 32bit-aligned destination address */
326 if ((0x02 & (unsigned long) dst) == 0) {
327 if (len >= 4) {
2bf0a8f6 328 ioread32_rep(fifo, dst, len >> 2);
550a7375
FB		 329 index = len & ~0x03;
330 }
331 if (len & 0x02) {
332 *(u16 *)&dst[index] = musb_readw(fifo, 0);
333 index += 2;
334 }
335 } else {
336 if (len >= 2) {
2bf0a8f6 337 ioread16_rep(fifo, dst, len >> 1);
550a7375
FB		 338 index = len & ~0x01;
339 }
340 }
341 if (len & 0x01)
342 dst[index] = musb_readb(fifo, 0);
343 } else {
344 /* byte aligned */
2bf0a8f6 345 ioread8_rep(fifo, dst, len);
550a7375
FB		 346 }
347}
348
1b40fc57
TL		 349/*
350 * Old style IO functions
351 */
352u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
353EXPORT_SYMBOL_GPL(musb_readb);
354
355void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
356EXPORT_SYMBOL_GPL(musb_writeb);
550a7375 357
1b40fc57
TL		 358u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
359EXPORT_SYMBOL_GPL(musb_readw);
360
361void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
362EXPORT_SYMBOL_GPL(musb_writew);
363
364u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
365EXPORT_SYMBOL_GPL(musb_readl);
366
367void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
368EXPORT_SYMBOL_GPL(musb_writel);
369
370/*
371 * New style IO functions
372 */
373void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
374{
375 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
376}
377
378void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
379{
380 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
381}
550a7375
FB		 382
383/*-------------------------------------------------------------------------*/
384
385/* for high speed test mode; see USB 2.0 spec 7.1.20 */
386static const u8 musb_test_packet[53] = {
387 /* implicit SYNC then DATA0 to start */
388
389 /* JKJKJKJK x9 */
390 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
391 /* JJKKJJKK x8 */
392 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
393 /* JJJJKKKK x8 */
394 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
395 /* JJJJJJJKKKKKKK x8 */
396 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
397 /* JJJJJJJK x8 */
398 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
399 /* JKKKKKKK x10, JK */
400 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
401
402 /* implicit CRC16 then EOP to end */
403};
404
405void musb_load_testpacket(struct musb *musb)
406{
407 void __iomem *regs = musb->endpoints[0].regs;
408
409 musb_ep_select(musb->mregs, 0);
410 musb_write_fifo(musb->control_ep,
411 sizeof(musb_test_packet), musb_test_packet);
412 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
413}
414
415/*-------------------------------------------------------------------------*/
416
550a7375
FB		 417/*
418 * Handles OTG hnp timeouts, such as b_ase0_brst
419 */
a156544b 420static void musb_otg_timer_func(unsigned long data)
550a7375
FB		 421{
422 struct musb *musb = (struct musb *)data;
423 unsigned long flags;
424
425 spin_lock_irqsave(&musb->lock, flags);
e47d9254 426 switch (musb->xceiv->otg->state) {
550a7375 427 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 428 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
550a7375 429 musb_g_disconnect(musb);
e47d9254 430 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 431 musb->is_active = 0;
432 break;
ab983f2a 433 case OTG_STATE_A_SUSPEND:
550a7375 434 case OTG_STATE_A_WAIT_BCON:
5c8a86e1 435 dev_dbg(musb->controller, "HNP: %s timeout\n",
e47d9254 436 usb_otg_state_string(musb->xceiv->otg->state));
743411b3 437 musb_platform_set_vbus(musb, 0);
e47d9254 438 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
550a7375
FB		 439 break;
440 default:
5c8a86e1 441 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
e47d9254 442 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 443 }
550a7375
FB		 444 spin_unlock_irqrestore(&musb->lock, flags);
445}
446
550a7375 447/*
f7f9d63e 448 * Stops the HNP transition. Caller must take care of locking.
550a7375
FB		 449 */
450void musb_hnp_stop(struct musb *musb)
451{
8b125df5 452 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 453 void __iomem *mbase = musb->mregs;
454 u8 reg;
455
42c0bf1c 456 dev_dbg(musb->controller, "HNP: stop from %s\n",
e47d9254 457 usb_otg_state_string(musb->xceiv->otg->state));
ab983f2a 458
e47d9254 459 switch (musb->xceiv->otg->state) {
550a7375 460 case OTG_STATE_A_PERIPHERAL:
550a7375 461 musb_g_disconnect(musb);
5c8a86e1 462 dev_dbg(musb->controller, "HNP: back to %s\n",
e47d9254 463 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 464 break;
465 case OTG_STATE_B_HOST:
5c8a86e1 466 dev_dbg(musb->controller, "HNP: Disabling HR\n");
74c2e936
DM		 467 if (hcd)
468 hcd->self.is_b_host = 0;
e47d9254 469 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 470 MUSB_DEV_MODE(musb);
471 reg = musb_readb(mbase, MUSB_POWER);
472 reg |= MUSB_POWER_SUSPENDM;
473 musb_writeb(mbase, MUSB_POWER, reg);
474 /* REVISIT: Start SESSION_REQUEST here? */
475 break;
476 default:
5c8a86e1 477 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
e47d9254 478 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 479 }
480
481 /*
482 * When returning to A state after HNP, avoid hub_port_rebounce(),
483 * which cause occasional OPT A "Did not receive reset after connect"
484 * errors.
485 */
749da5f8 486 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
550a7375
FB		 487}
488
f905bc68 489static void musb_generic_disable(struct musb *musb);
550a7375
FB		 490/*
491 * Interrupt Service Routine to record USB "global" interrupts.
492 * Since these do not happen often and signify things of
493 * paramount importance, it seems OK to check them individually;
494 * the order of the tests is specified in the manual
495 *
496 * @param musb instance pointer
497 * @param int_usb register contents
498 * @param devctl
499 * @param power
500 */
501
550a7375 502static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
b11e94d0 503 u8 devctl)
550a7375
FB		 504{
505 irqreturn_t handled = IRQ_NONE;
550a7375 506
b11e94d0 507 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
550a7375
FB		 508 int_usb);
509
510 /* in host mode, the peripheral may issue remote wakeup.
511 * in peripheral mode, the host may resume the link.
512 * spurious RESUME irqs happen too, paired with SUSPEND.
513 */
514 if (int_usb & MUSB_INTR_RESUME) {
515 handled = IRQ_HANDLED;
e47d9254 516 dev_dbg(musb->controller, "RESUME (%s)\n", usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 517
518 if (devctl & MUSB_DEVCTL_HM) {
aa471456 519 void __iomem *mbase = musb->mregs;
b11e94d0 520 u8 power;
aa471456 521
e47d9254 522 switch (musb->xceiv->otg->state) {
550a7375
FB		 523 case OTG_STATE_A_SUSPEND:
524 /* remote wakeup? later, GetPortStatus
525 * will stop RESUME signaling
526 */
527
b11e94d0 528 power = musb_readb(musb->mregs, MUSB_POWER);
550a7375
FB		 529 if (power & MUSB_POWER_SUSPENDM) {
530 /* spurious */
531 musb->int_usb &= ~MUSB_INTR_SUSPEND;
5c8a86e1 532 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
550a7375
FB		 533 break;
534 }
535
536 power &= ~MUSB_POWER_SUSPENDM;
537 musb_writeb(mbase, MUSB_POWER,
538 power | MUSB_POWER_RESUME);
539
540 musb->port1_status |=
541 (USB_PORT_STAT_C_SUSPEND << 16)
542 | MUSB_PORT_STAT_RESUME;
30d361bf
DM		 543 musb->rh_timer = jiffies
544 + msecs_to_jiffies(20);
baadd52f 545 musb->need_finish_resume = 1;
550a7375 546
e47d9254 547 musb->xceiv->otg->state = OTG_STATE_A_HOST;
550a7375 548 musb->is_active = 1;
550a7375
FB		 549 break;
550 case OTG_STATE_B_WAIT_ACON:
e47d9254 551 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 552 musb->is_active = 1;
553 MUSB_DEV_MODE(musb);
554 break;
555 default:
556 WARNING("bogus %s RESUME (%s)\n",
557 "host",
e47d9254 558 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 559 }
550a7375 560 } else {
e47d9254 561 switch (musb->xceiv->otg->state) {
550a7375
FB		 562 case OTG_STATE_A_SUSPEND:
563 /* possibly DISCONNECT is upcoming */
e47d9254 564 musb->xceiv->otg->state = OTG_STATE_A_HOST;
0b3eba44 565 musb_host_resume_root_hub(musb);
550a7375 566 break;
550a7375
FB		 567 case OTG_STATE_B_WAIT_ACON:
568 case OTG_STATE_B_PERIPHERAL:
569 /* disconnect while suspended? we may
570 * not get a disconnect irq...
571 */
572 if ((devctl & MUSB_DEVCTL_VBUS)
573 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
574 ) {
575 musb->int_usb |= MUSB_INTR_DISCONNECT;
576 musb->int_usb &= ~MUSB_INTR_SUSPEND;
577 break;
578 }
579 musb_g_resume(musb);
580 break;
581 case OTG_STATE_B_IDLE:
582 musb->int_usb &= ~MUSB_INTR_SUSPEND;
583 break;
550a7375
FB		 584 default:
585 WARNING("bogus %s RESUME (%s)\n",
586 "peripheral",
e47d9254 587 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 588 }
589 }
590 }
591
550a7375
FB		 592 /* see manual for the order of the tests */
593 if (int_usb & MUSB_INTR_SESSREQ) {
aa471456
FB		 594 void __iomem *mbase = musb->mregs;
595
19aab56c
HK		 596 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
597 && (devctl & MUSB_DEVCTL_BDEVICE)) {
5c8a86e1 598 dev_dbg(musb->controller, "SessReq while on B state\n");
a6038ee7
HK		 599 return IRQ_HANDLED;
600 }
601
5c8a86e1 602 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
e47d9254 603 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 604
605 /* IRQ arrives from ID pin sense or (later, if VBUS power
606 * is removed) SRP. responses are time critical:
607 * - turn on VBUS (with silicon-specific mechanism)
608 * - go through A_WAIT_VRISE
609 * - ... to A_WAIT_BCON.
610 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
611 */
612 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
613 musb->ep0_stage = MUSB_EP0_START;
e47d9254 614 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
550a7375 615 MUSB_HST_MODE(musb);
743411b3 616 musb_platform_set_vbus(musb, 1);
550a7375
FB		 617
618 handled = IRQ_HANDLED;
619 }
620
621 if (int_usb & MUSB_INTR_VBUSERROR) {
622 int ignore = 0;
623
624 /* During connection as an A-Device, we may see a short
625 * current spikes causing voltage drop, because of cable
626 * and peripheral capacitance combined with vbus draw.
627 * (So: less common with truly self-powered devices, where
628 * vbus doesn't act like a power supply.)
629 *
630 * Such spikes are short; usually less than ~500 usec, max
631 * of ~2 msec. That is, they're not sustained overcurrent
632 * errors, though they're reported using VBUSERROR irqs.
633 *
634 * Workarounds: (a) hardware: use self powered devices.
635 * (b) software: ignore non-repeated VBUS errors.
636 *
637 * REVISIT: do delays from lots of DEBUG_KERNEL checks
638 * make trouble here, keeping VBUS < 4.4V ?
639 */
e47d9254 640 switch (musb->xceiv->otg->state) {
550a7375
FB		 641 case OTG_STATE_A_HOST:
642 /* recovery is dicey once we've gotten past the
643 * initial stages of enumeration, but if VBUS
644 * stayed ok at the other end of the link, and
645 * another reset is due (at least for high speed,
646 * to redo the chirp etc), it might work OK...
647 */
648 case OTG_STATE_A_WAIT_BCON:
649 case OTG_STATE_A_WAIT_VRISE:
650 if (musb->vbuserr_retry) {
aa471456
FB		 651 void __iomem *mbase = musb->mregs;
652
550a7375
FB		 653 musb->vbuserr_retry--;
654 ignore = 1;
655 devctl |= MUSB_DEVCTL_SESSION;
656 musb_writeb(mbase, MUSB_DEVCTL, devctl);
657 } else {
658 musb->port1_status |=
749da5f8
AS		 659 USB_PORT_STAT_OVERCURRENT
660 | (USB_PORT_STAT_C_OVERCURRENT << 16);
550a7375
FB		 661 }
662 break;
663 default:
664 break;
665 }
666
54485116
GI		 667 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
668 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
e47d9254 669 usb_otg_state_string(musb->xceiv->otg->state),
550a7375
FB		 670 devctl,
671 ({ char *s;
672 switch (devctl & MUSB_DEVCTL_VBUS) {
673 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
674 s = "<SessEnd"; break;
675 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
676 s = "<AValid"; break;
677 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
678 s = "<VBusValid"; break;
679 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
680 default:
681 s = "VALID"; break;
2b84f92b 682 } s; }),
550a7375
FB		 683 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
684 musb->port1_status);
685
686 /* go through A_WAIT_VFALL then start a new session */
687 if (!ignore)
743411b3 688 musb_platform_set_vbus(musb, 0);
550a7375
FB		 689 handled = IRQ_HANDLED;
690 }
691
1c25fda4 692 if (int_usb & MUSB_INTR_SUSPEND) {
b11e94d0 693 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
e47d9254 694 usb_otg_state_string(musb->xceiv->otg->state), devctl);
1c25fda4
AM		 695 handled = IRQ_HANDLED;
696
e47d9254 697 switch (musb->xceiv->otg->state) {
1c25fda4
AM		 698 case OTG_STATE_A_PERIPHERAL:
699 /* We also come here if the cable is removed, since
700 * this silicon doesn't report ID-no-longer-grounded.
701 *
702 * We depend on T(a_wait_bcon) to shut us down, and
703 * hope users don't do anything dicey during this
704 * undesired detour through A_WAIT_BCON.
705 */
706 musb_hnp_stop(musb);
0b3eba44 707 musb_host_resume_root_hub(musb);
1c25fda4
AM		 708 musb_root_disconnect(musb);
709 musb_platform_try_idle(musb, jiffies
710 + msecs_to_jiffies(musb->a_wait_bcon
711 ? : OTG_TIME_A_WAIT_BCON));
712
713 break;
1c25fda4
AM		 714 case OTG_STATE_B_IDLE:
715 if (!musb->is_active)
716 break;
717 case OTG_STATE_B_PERIPHERAL:
718 musb_g_suspend(musb);
eee3f15d 719 musb->is_active = musb->g.b_hnp_enable;
1c25fda4 720 if (musb->is_active) {
e47d9254 721 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
5c8a86e1 722 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
1c25fda4
AM		 723 mod_timer(&musb->otg_timer, jiffies
724 + msecs_to_jiffies(
725 OTG_TIME_B_ASE0_BRST));
1c25fda4
AM		 726 }
727 break;
728 case OTG_STATE_A_WAIT_BCON:
729 if (musb->a_wait_bcon != 0)
730 musb_platform_try_idle(musb, jiffies
731 + msecs_to_jiffies(musb->a_wait_bcon));
732 break;
733 case OTG_STATE_A_HOST:
e47d9254 734 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
eee3f15d 735 musb->is_active = musb->hcd->self.b_hnp_enable;
1c25fda4
AM		 736 break;
737 case OTG_STATE_B_HOST:
738 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
5c8a86e1 739 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
1c25fda4
AM		 740 break;
741 default:
742 /* "should not happen" */
743 musb->is_active = 0;
744 break;
745 }
746 }
747
550a7375 748 if (int_usb & MUSB_INTR_CONNECT) {
8b125df5 749 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 750
751 handled = IRQ_HANDLED;
752 musb->is_active = 1;
550a7375
FB		 753
754 musb->ep0_stage = MUSB_EP0_START;
755
550a7375
FB		 756 /* flush endpoints when transitioning from Device Mode */
757 if (is_peripheral_active(musb)) {
758 /* REVISIT HNP; just force disconnect */
759 }
b18d26f6
SAS		 760 musb->intrtxe = musb->epmask;
761 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
af5ec14d
SAS		 762 musb->intrrxe = musb->epmask & 0xfffe;
763 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
d709d22e 764 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 765 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
766 |USB_PORT_STAT_HIGH_SPEED
767 |USB_PORT_STAT_ENABLE
768 );
769 musb->port1_status |= USB_PORT_STAT_CONNECTION
770 |(USB_PORT_STAT_C_CONNECTION << 16);
771
772 /* high vs full speed is just a guess until after reset */
773 if (devctl & MUSB_DEVCTL_LSDEV)
774 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
775
550a7375 776 /* indicate new connection to OTG machine */
e47d9254 777 switch (musb->xceiv->otg->state) {
550a7375
FB		 778 case OTG_STATE_B_PERIPHERAL:
779 if (int_usb & MUSB_INTR_SUSPEND) {
5c8a86e1 780 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
550a7375 781 int_usb &= ~MUSB_INTR_SUSPEND;
1de00dae 782 goto b_host;
550a7375 783 } else
5c8a86e1 784 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
550a7375
FB		 785 break;
786 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 787 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
1de00dae 788b_host:
e47d9254 789 musb->xceiv->otg->state = OTG_STATE_B_HOST;
74c2e936
DM		 790 if (musb->hcd)
791 musb->hcd->self.is_b_host = 1;
1de00dae 792 del_timer(&musb->otg_timer);
550a7375
FB		 793 break;
794 default:
795 if ((devctl & MUSB_DEVCTL_VBUS)
796 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
e47d9254 797 musb->xceiv->otg->state = OTG_STATE_A_HOST;
0b3eba44
DM		 798 if (hcd)
799 hcd->self.is_b_host = 0;
550a7375
FB		 800 }
801 break;
802 }
1de00dae 803
0b3eba44 804 musb_host_poke_root_hub(musb);
1de00dae 805
5c8a86e1 806 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
e47d9254 807 usb_otg_state_string(musb->xceiv->otg->state), devctl);
550a7375 808 }
550a7375 809
6d349671 810 if (int_usb & MUSB_INTR_DISCONNECT) {
5c8a86e1 811 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
e47d9254 812 usb_otg_state_string(musb->xceiv->otg->state),
1c25fda4
AM		 813 MUSB_MODE(musb), devctl);
814 handled = IRQ_HANDLED;
815
e47d9254 816 switch (musb->xceiv->otg->state) {
1c25fda4
AM		 817 case OTG_STATE_A_HOST:
818 case OTG_STATE_A_SUSPEND:
0b3eba44 819 musb_host_resume_root_hub(musb);
1c25fda4 820 musb_root_disconnect(musb);
032ec49f 821 if (musb->a_wait_bcon != 0)
1c25fda4
AM		 822 musb_platform_try_idle(musb, jiffies
823 + msecs_to_jiffies(musb->a_wait_bcon));
824 break;
1c25fda4
AM		 825 case OTG_STATE_B_HOST:
826 /* REVISIT this behaves for "real disconnect"
827 * cases; make sure the other transitions from
828 * from B_HOST act right too. The B_HOST code
829 * in hnp_stop() is currently not used...
830 */
831 musb_root_disconnect(musb);
74c2e936
DM		 832 if (musb->hcd)
833 musb->hcd->self.is_b_host = 0;
e47d9254 834 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
1c25fda4
AM		 835 MUSB_DEV_MODE(musb);
836 musb_g_disconnect(musb);
837 break;
838 case OTG_STATE_A_PERIPHERAL:
839 musb_hnp_stop(musb);
840 musb_root_disconnect(musb);
841 /* FALLTHROUGH */
842 case OTG_STATE_B_WAIT_ACON:
843 /* FALLTHROUGH */
1c25fda4
AM		 844 case OTG_STATE_B_PERIPHERAL:
845 case OTG_STATE_B_IDLE:
846 musb_g_disconnect(musb);
847 break;
1c25fda4
AM		 848 default:
849 WARNING("unhandled DISCONNECT transition (%s)\n",
e47d9254 850 usb_otg_state_string(musb->xceiv->otg->state));
1c25fda4
AM		 851 break;
852 }
853 }
854
550a7375
FB		 855 /* mentor saves a bit: bus reset and babble share the same irq.
856 * only host sees babble; only peripheral sees bus reset.
857 */
858 if (int_usb & MUSB_INTR_RESET) {
1c25fda4 859 handled = IRQ_HANDLED;
a04d46d0 860 if ((devctl & MUSB_DEVCTL_HM) != 0) {
550a7375
FB		 861 /*
862 * Looks like non-HS BABBLE can be ignored, but
863 * HS BABBLE is an error condition. For HS the solution
864 * is to avoid babble in the first place and fix what
865 * caused BABBLE. When HS BABBLE happens we can only
866 * stop the session.
867 */
868 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
5c8a86e1 869 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
550a7375
FB		 870 else {
871 ERR("Stopping host session -- babble\n");
1c25fda4 872 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
550a7375 873 }
a04d46d0 874 } else {
5c8a86e1 875 dev_dbg(musb->controller, "BUS RESET as %s\n",
e47d9254
AT		 876 usb_otg_state_string(musb->xceiv->otg->state));
877 switch (musb->xceiv->otg->state) {
550a7375 878 case OTG_STATE_A_SUSPEND:
550a7375
FB		 879 musb_g_reset(musb);
880 /* FALLTHROUGH */
881 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
f7f9d63e 882 /* never use invalid T(a_wait_bcon) */
5c8a86e1 883 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
e47d9254 884 usb_otg_state_string(musb->xceiv->otg->state),
3df00453 885 TA_WAIT_BCON(musb));
f7f9d63e
DB		 886 mod_timer(&musb->otg_timer, jiffies
887 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
550a7375
FB		 888 break;
889 case OTG_STATE_A_PERIPHERAL:
1de00dae
DB		 890 del_timer(&musb->otg_timer);
891 musb_g_reset(musb);
550a7375
FB		 892 break;
893 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 894 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
e47d9254
AT		 895 usb_otg_state_string(musb->xceiv->otg->state));
896 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 897 musb_g_reset(musb);
898 break;
550a7375 899 case OTG_STATE_B_IDLE:
e47d9254 900 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 901 /* FALLTHROUGH */
902 case OTG_STATE_B_PERIPHERAL:
903 musb_g_reset(musb);
904 break;
905 default:
5c8a86e1 906 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
e47d9254 907 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 908 }
909 }
550a7375 910 }
550a7375 911
ca88fc2e 912 /* handle babble condition */
f905bc68
GC		 913 if (int_usb & MUSB_INTR_BABBLE && is_host_active(musb)) {
914 musb_generic_disable(musb);
675ae763
GC		 915 schedule_delayed_work(&musb->recover_work,
916 msecs_to_jiffies(100));
f905bc68 917 }
ca88fc2e 918
550a7375
FB		 919#if 0
920/* REVISIT ... this would be for multiplexing periodic endpoints, or
921 * supporting transfer phasing to prevent exceeding ISO bandwidth
922 * limits of a given frame or microframe.
923 *
924 * It's not needed for peripheral side, which dedicates endpoints;
925 * though it _might_ use SOF irqs for other purposes.
926 *
927 * And it's not currently needed for host side, which also dedicates
928 * endpoints, relies on TX/RX interval registers, and isn't claimed
929 * to support ISO transfers yet.
930 */
931 if (int_usb & MUSB_INTR_SOF) {
932 void __iomem *mbase = musb->mregs;
933 struct musb_hw_ep *ep;
934 u8 epnum;
935 u16 frame;
936
5c8a86e1 937 dev_dbg(musb->controller, "START_OF_FRAME\n");
550a7375
FB		 938 handled = IRQ_HANDLED;
939
940 /* start any periodic Tx transfers waiting for current frame */
941 frame = musb_readw(mbase, MUSB_FRAME);
942 ep = musb->endpoints;
943 for (epnum = 1; (epnum < musb->nr_endpoints)
944 && (musb->epmask >= (1 << epnum));
945 epnum++, ep++) {
946 /*
947 * FIXME handle framecounter wraps (12 bits)
948 * eliminate duplicated StartUrb logic
949 */
950 if (ep->dwWaitFrame >= frame) {
951 ep->dwWaitFrame = 0;
952 pr_debug("SOF --> periodic TX%s on %d\n",
953 ep->tx_channel ? " DMA" : "",
954 epnum);
955 if (!ep->tx_channel)
956 musb_h_tx_start(musb, epnum);
957 else
958 cppi_hostdma_start(musb, epnum);
959 }
960 } /* end of for loop */
961 }
962#endif
963
1c25fda4 964 schedule_work(&musb->irq_work);
550a7375
FB		 965
966 return handled;
967}
968
969/*-------------------------------------------------------------------------*/
970
550a7375
FB		 971static void musb_generic_disable(struct musb *musb)
972{
973 void __iomem *mbase = musb->mregs;
974 u16 temp;
975
976 /* disable interrupts */
977 musb_writeb(mbase, MUSB_INTRUSBE, 0);
b18d26f6 978 musb->intrtxe = 0;
550a7375 979 musb_writew(mbase, MUSB_INTRTXE, 0);
af5ec14d 980 musb->intrrxe = 0;
550a7375
FB		 981 musb_writew(mbase, MUSB_INTRRXE, 0);
982
983 /* off */
984 musb_writeb(mbase, MUSB_DEVCTL, 0);
985
986 /* flush pending interrupts */
987 temp = musb_readb(mbase, MUSB_INTRUSB);
988 temp = musb_readw(mbase, MUSB_INTRTX);
989 temp = musb_readw(mbase, MUSB_INTRRX);
990
991}
992
001dd84a
SAS		 993/*
994 * Program the HDRC to start (enable interrupts, dma, etc.).
995 */
996void musb_start(struct musb *musb)
997{
998 void __iomem *regs = musb->mregs;
999 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1000
1001 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1002
1003 /* Set INT enable registers, enable interrupts */
1004 musb->intrtxe = musb->epmask;
1005 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1006 musb->intrrxe = musb->epmask & 0xfffe;
1007 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1008 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1009
1010 musb_writeb(regs, MUSB_TESTMODE, 0);
1011
1012 /* put into basic highspeed mode and start session */
1013 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
1014 | MUSB_POWER_HSENAB
1015 /* ENSUSPEND wedges tusb */
1016 /* | MUSB_POWER_ENSUSPEND */
1017 );
1018
1019 musb->is_active = 0;
1020 devctl = musb_readb(regs, MUSB_DEVCTL);
1021 devctl &= ~MUSB_DEVCTL_SESSION;
1022
1023 /* session started after:
1024 * (a) ID-grounded irq, host mode;
1025 * (b) vbus present/connect IRQ, peripheral mode;
1026 * (c) peripheral initiates, using SRP
1027 */
1028 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1029 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1030 musb->is_active = 1;
1031 } else {
1032 devctl |= MUSB_DEVCTL_SESSION;
1033 }
1034
1035 musb_platform_enable(musb);
1036 musb_writeb(regs, MUSB_DEVCTL, devctl);
1037}
1038
550a7375
FB		 1039/*
1040 * Make the HDRC stop (disable interrupts, etc.);
1041 * reversible by musb_start
1042 * called on gadget driver unregister
1043 * with controller locked, irqs blocked
1044 * acts as a NOP unless some role activated the hardware
1045 */
1046void musb_stop(struct musb *musb)
1047{
1048 /* stop IRQs, timers, ... */
1049 musb_platform_disable(musb);
1050 musb_generic_disable(musb);
5c8a86e1 1051 dev_dbg(musb->controller, "HDRC disabled\n");
550a7375
FB		 1052
1053 /* FIXME
1054 * - mark host and/or peripheral drivers unusable/inactive
1055 * - disable DMA (and enable it in HdrcStart)
1056 * - make sure we can musb_start() after musb_stop(); with
1057 * OTG mode, gadget driver module rmmod/modprobe cycles that
1058 * - ...
1059 */
1060 musb_platform_try_idle(musb, 0);
1061}
1062
1063static void musb_shutdown(struct platform_device *pdev)
1064{
1065 struct musb *musb = dev_to_musb(&pdev->dev);
1066 unsigned long flags;
1067
4f9edd2d 1068 pm_runtime_get_sync(musb->controller);
24307cae 1069
2cc65fea 1070 musb_host_cleanup(musb);
24307cae
GI		 1071 musb_gadget_cleanup(musb);
1072
550a7375
FB		 1073 spin_lock_irqsave(&musb->lock, flags);
1074 musb_platform_disable(musb);
1075 musb_generic_disable(musb);
550a7375
FB		 1076 spin_unlock_irqrestore(&musb->lock, flags);
1077
120d074c
GI		 1078 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1079 musb_platform_exit(musb);
120d074c 1080
4f9edd2d 1081 pm_runtime_put(musb->controller);
550a7375
FB		 1082 /* FIXME power down */
1083}
1084
1085
1086/*-------------------------------------------------------------------------*/
1087
1088/*
1089 * The silicon either has hard-wired endpoint configurations, or else
1090 * "dynamic fifo" sizing. The driver has support for both, though at this
c767c1c6
DB		 1091 * writing only the dynamic sizing is very well tested. Since we switched
1092 * away from compile-time hardware parameters, we can no longer rely on
1093 * dead code elimination to leave only the relevant one in the object file.
550a7375
FB		 1094 *
1095 * We don't currently use dynamic fifo setup capability to do anything
1096 * more than selecting one of a bunch of predefined configurations.
1097 */
ee34e51a
FB		 1098#if defined(CONFIG_USB_MUSB_TUSB6010) \
1099 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1100 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1101 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1102 || defined(CONFIG_USB_MUSB_AM35X) \
9ecb8875
AKG		 1103 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \
1104 || defined(CONFIG_USB_MUSB_DSPS) \
1105 || defined(CONFIG_USB_MUSB_DSPS_MODULE)
d3608b6d 1106static ushort fifo_mode = 4;
ee34e51a
FB		 1107#elif defined(CONFIG_USB_MUSB_UX500) \
1108 || defined(CONFIG_USB_MUSB_UX500_MODULE)
d3608b6d 1109static ushort fifo_mode = 5;
550a7375 1110#else
d3608b6d 1111static ushort fifo_mode = 2;
550a7375
FB		 1112#endif
1113
1114/* "modprobe ... fifo_mode=1" etc */
1115module_param(fifo_mode, ushort, 0);
1116MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1117
550a7375
FB		 1118/*
1119 * tables defining fifo_mode values. define more if you like.
1120 * for host side, make sure both halves of ep1 are set up.
1121 */
1122
1123/* mode 0 - fits in 2KB */
d3608b6d 1124static struct musb_fifo_cfg mode_0_cfg[] = {
550a7375
FB		 1125{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1126{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1127{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1128{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1129{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1130};
1131
1132/* mode 1 - fits in 4KB */
d3608b6d 1133static struct musb_fifo_cfg mode_1_cfg[] = {
550a7375
FB		 1134{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1135{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1136{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1137{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1138{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1139};
1140
1141/* mode 2 - fits in 4KB */
d3608b6d 1142static struct musb_fifo_cfg mode_2_cfg[] = {
550a7375
FB		 1143{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1144{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1145{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1146{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1147{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1148{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1149};
1150
1151/* mode 3 - fits in 4KB */
d3608b6d 1152static struct musb_fifo_cfg mode_3_cfg[] = {
550a7375
FB		 1153{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1154{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1155{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1156{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1157{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1158{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1159};
1160
1161/* mode 4 - fits in 16KB */
d3608b6d 1162static struct musb_fifo_cfg mode_4_cfg[] = {
550a7375
FB		 1163{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1164{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1165{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1166{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1167{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1168{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1169{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1170{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1171{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1172{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1173{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1174{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1175{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1176{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1177{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1178{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1179{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1180{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
a483d706
AKG		 1181{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1182{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1183{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1184{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1185{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1186{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1187{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
550a7375
FB		 1188{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1189{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1190};
1191
3b151526 1192/* mode 5 - fits in 8KB */
d3608b6d 1193static struct musb_fifo_cfg mode_5_cfg[] = {
3b151526
AKG		 1194{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1195{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1196{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1197{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1198{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1199{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1200{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1201{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1202{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1203{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1204{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1205{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1206{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1207{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1208{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1209{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1210{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1211{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1212{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1213{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1214{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1215{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1216{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1217{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1218{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1219{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1220{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1221};
550a7375
FB		 1222
1223/*
1224 * configure a fifo; for non-shared endpoints, this may be called
1225 * once for a tx fifo and once for an rx fifo.
1226 *
1227 * returns negative errno or offset for next fifo.
1228 */
41ac7b3a 1229static int
550a7375 1230fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
e6c213b2 1231 const struct musb_fifo_cfg *cfg, u16 offset)
550a7375
FB		 1232{
1233 void __iomem *mbase = musb->mregs;
1234 int size = 0;
1235 u16 maxpacket = cfg->maxpacket;
1236 u16 c_off = offset >> 3;
1237 u8 c_size;
1238
1239 /* expect hw_ep has already been zero-initialized */
1240
1241 size = ffs(max(maxpacket, (u16) 8)) - 1;
1242 maxpacket = 1 << size;
1243
1244 c_size = size - 3;
1245 if (cfg->mode == BUF_DOUBLE) {
ca6d1b13
FB		 1246 if ((offset + (maxpacket << 1)) >
1247 (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1248 return -EMSGSIZE;
1249 c_size |= MUSB_FIFOSZ_DPB;
1250 } else {
ca6d1b13 1251 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1252 return -EMSGSIZE;
1253 }
1254
1255 /* configure the FIFO */
1256 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1257
550a7375 1258 /* EP0 reserved endpoint for control, bidirectional;
5ae477b0 1259 * EP1 reserved for bulk, two unidirectional halves.
550a7375
FB		 1260 */
1261 if (hw_ep->epnum == 1)
1262 musb->bulk_ep = hw_ep;
1263 /* REVISIT error check: be sure ep0 can both rx and tx ... */
550a7375
FB		 1264 switch (cfg->style) {
1265 case FIFO_TX:
c6cf8b00
BW		 1266 musb_write_txfifosz(mbase, c_size);
1267 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1268 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1269 hw_ep->max_packet_sz_tx = maxpacket;
1270 break;
1271 case FIFO_RX:
c6cf8b00
BW		 1272 musb_write_rxfifosz(mbase, c_size);
1273 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1274 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1275 hw_ep->max_packet_sz_rx = maxpacket;
1276 break;
1277 case FIFO_RXTX:
c6cf8b00
BW		 1278 musb_write_txfifosz(mbase, c_size);
1279 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1280 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1281 hw_ep->max_packet_sz_rx = maxpacket;
1282
c6cf8b00
BW		 1283 musb_write_rxfifosz(mbase, c_size);
1284 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1285 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1286 hw_ep->max_packet_sz_tx = maxpacket;
1287
1288 hw_ep->is_shared_fifo = true;
1289 break;
1290 }
1291
1292 /* NOTE rx and tx endpoint irqs aren't managed separately,
1293 * which happens to be ok
1294 */
1295 musb->epmask |= (1 << hw_ep->epnum);
1296
1297 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1298}
1299
d3608b6d 1300static struct musb_fifo_cfg ep0_cfg = {
550a7375
FB		 1301 .style = FIFO_RXTX, .maxpacket = 64,
1302};
1303
41ac7b3a 1304static int ep_config_from_table(struct musb *musb)
550a7375 1305{
e6c213b2 1306 const struct musb_fifo_cfg *cfg;
550a7375
FB		 1307 unsigned i, n;
1308 int offset;
1309 struct musb_hw_ep *hw_ep = musb->endpoints;
1310
e6c213b2
FB		 1311 if (musb->config->fifo_cfg) {
1312 cfg = musb->config->fifo_cfg;
1313 n = musb->config->fifo_cfg_size;
1314 goto done;
1315 }
1316
550a7375
FB		 1317 switch (fifo_mode) {
1318 default:
1319 fifo_mode = 0;
1320 /* FALLTHROUGH */
1321 case 0:
1322 cfg = mode_0_cfg;
1323 n = ARRAY_SIZE(mode_0_cfg);
1324 break;
1325 case 1:
1326 cfg = mode_1_cfg;
1327 n = ARRAY_SIZE(mode_1_cfg);
1328 break;
1329 case 2:
1330 cfg = mode_2_cfg;
1331 n = ARRAY_SIZE(mode_2_cfg);
1332 break;
1333 case 3:
1334 cfg = mode_3_cfg;
1335 n = ARRAY_SIZE(mode_3_cfg);
1336 break;
1337 case 4:
1338 cfg = mode_4_cfg;
1339 n = ARRAY_SIZE(mode_4_cfg);
1340 break;
3b151526
AKG		 1341 case 5:
1342 cfg = mode_5_cfg;
1343 n = ARRAY_SIZE(mode_5_cfg);
1344 break;
550a7375
FB		 1345 }
1346
1347 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1348 musb_driver_name, fifo_mode);
1349
1350
e6c213b2 1351done:
550a7375
FB		 1352 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1353 /* assert(offset > 0) */
1354
1355 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
ca6d1b13 1356 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
550a7375
FB		 1357 */
1358
1359 for (i = 0; i < n; i++) {
1360 u8 epn = cfg->hw_ep_num;
1361
ca6d1b13 1362 if (epn >= musb->config->num_eps) {
550a7375
FB		 1363 pr_debug("%s: invalid ep %d\n",
1364 musb_driver_name, epn);
bb1c9ef1 1365 return -EINVAL;
550a7375
FB		 1366 }
1367 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1368 if (offset < 0) {
1369 pr_debug("%s: mem overrun, ep %d\n",
1370 musb_driver_name, epn);
f69dfa1f 1371 return offset;
550a7375
FB		 1372 }
1373 epn++;
1374 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1375 }
1376
1377 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1378 musb_driver_name,
ca6d1b13
FB		 1379 n + 1, musb->config->num_eps * 2 - 1,
1380 offset, (1 << (musb->config->ram_bits + 2)));
550a7375 1381
550a7375
FB		 1382 if (!musb->bulk_ep) {
1383 pr_debug("%s: missing bulk\n", musb_driver_name);
1384 return -EINVAL;
1385 }
550a7375
FB		 1386
1387 return 0;
1388}
1389
1390
1391/*
1392 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1393 * @param musb the controller
1394 */
41ac7b3a 1395static int ep_config_from_hw(struct musb *musb)
550a7375 1396{
c6cf8b00 1397 u8 epnum = 0;
550a7375 1398 struct musb_hw_ep *hw_ep;
a156544b 1399 void __iomem *mbase = musb->mregs;
c6cf8b00 1400 int ret = 0;
550a7375 1401
5c8a86e1 1402 dev_dbg(musb->controller, "<== static silicon ep config\n");
550a7375
FB		 1403
1404 /* FIXME pick up ep0 maxpacket size */
1405
ca6d1b13 1406 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
550a7375
FB		 1407 musb_ep_select(mbase, epnum);
1408 hw_ep = musb->endpoints + epnum;
1409
c6cf8b00
BW		 1410 ret = musb_read_fifosize(musb, hw_ep, epnum);
1411 if (ret < 0)
550a7375 1412 break;
550a7375
FB		 1413
1414 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1415
550a7375
FB		 1416 /* pick an RX/TX endpoint for bulk */
1417 if (hw_ep->max_packet_sz_tx < 512
1418 || hw_ep->max_packet_sz_rx < 512)
1419 continue;
1420
1421 /* REVISIT: this algorithm is lazy, we should at least
1422 * try to pick a double buffered endpoint.
1423 */
1424 if (musb->bulk_ep)
1425 continue;
1426 musb->bulk_ep = hw_ep;
550a7375
FB		 1427 }
1428
550a7375
FB		 1429 if (!musb->bulk_ep) {
1430 pr_debug("%s: missing bulk\n", musb_driver_name);
1431 return -EINVAL;
1432 }
550a7375
FB		 1433
1434 return 0;
1435}
1436
1437enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1438
1439/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1440 * configure endpoints, or take their config from silicon
1441 */
41ac7b3a 1442static int musb_core_init(u16 musb_type, struct musb *musb)
550a7375 1443{
550a7375
FB		 1444 u8 reg;
1445 char *type;
0ea52ff4 1446 char aInfo[90], aRevision[32], aDate[12];
550a7375
FB		 1447 void __iomem *mbase = musb->mregs;
1448 int status = 0;
1449 int i;
1450
1451 /* log core options (read using indexed model) */
c6cf8b00 1452 reg = musb_read_configdata(mbase);
550a7375
FB		 1453
1454 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
51bf0d0e 1455 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
550a7375 1456 strcat(aInfo, ", dyn FIFOs");
51bf0d0e
AKG		 1457 musb->dyn_fifo = true;
1458 }
550a7375
FB		 1459 if (reg & MUSB_CONFIGDATA_MPRXE) {
1460 strcat(aInfo, ", bulk combine");
550a7375 1461 musb->bulk_combine = true;
550a7375
FB		 1462 }
1463 if (reg & MUSB_CONFIGDATA_MPTXE) {
1464 strcat(aInfo, ", bulk split");
550a7375 1465 musb->bulk_split = true;
550a7375
FB		 1466 }
1467 if (reg & MUSB_CONFIGDATA_HBRXE) {
1468 strcat(aInfo, ", HB-ISO Rx");
a483d706 1469 musb->hb_iso_rx = true;
550a7375
FB		 1470 }
1471 if (reg & MUSB_CONFIGDATA_HBTXE) {
1472 strcat(aInfo, ", HB-ISO Tx");
a483d706 1473 musb->hb_iso_tx = true;
550a7375
FB		 1474 }
1475 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1476 strcat(aInfo, ", SoftConn");
1477
1478 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1479 musb_driver_name, reg, aInfo);
1480
550a7375 1481 aDate[0] = 0;
550a7375
FB		 1482 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1483 musb->is_multipoint = 1;
1484 type = "M";
1485 } else {
1486 musb->is_multipoint = 0;
1487 type = "";
550a7375
FB		 1488#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1489 printk(KERN_ERR
1490 "%s: kernel must blacklist external hubs\n",
1491 musb_driver_name);
550a7375
FB		 1492#endif
1493 }
1494
1495 /* log release info */
32c3b94e
AG		 1496 musb->hwvers = musb_read_hwvers(mbase);
1497 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1498 MUSB_HWVERS_MINOR(musb->hwvers),
1499 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
550a7375
FB		 1500 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1501 musb_driver_name, type, aRevision, aDate);
1502
1503 /* configure ep0 */
c6cf8b00 1504 musb_configure_ep0(musb);
550a7375
FB		 1505
1506 /* discover endpoint configuration */
1507 musb->nr_endpoints = 1;
1508 musb->epmask = 1;
1509
ad517e9e
FB		 1510 if (musb->dyn_fifo)
1511 status = ep_config_from_table(musb);
1512 else
1513 status = ep_config_from_hw(musb);
550a7375
FB		 1514
1515 if (status < 0)
1516 return status;
1517
1518 /* finish init, and print endpoint config */
1519 for (i = 0; i < musb->nr_endpoints; i++) {
1520 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1521
1b40fc57 1522 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
9a35f876 1523#if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
1b40fc57
TL		 1524 if (musb->io.quirks & MUSB_IN_TUSB) {
1525 hw_ep->fifo_async = musb->async + 0x400 +
1526 musb->io.fifo_offset(i);
1527 hw_ep->fifo_sync = musb->sync + 0x400 +
1528 musb->io.fifo_offset(i);
1529 hw_ep->fifo_sync_va =
1530 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1531
1532 if (i == 0)
1533 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1534 else
1535 hw_ep->conf = mbase + 0x400 +
1536 (((i - 1) & 0xf) << 2);
1537 }
550a7375
FB		 1538#endif
1539
1540 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
c6cf8b00 1541 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
550a7375
FB		 1542 hw_ep->rx_reinit = 1;
1543 hw_ep->tx_reinit = 1;
550a7375
FB		 1544
1545 if (hw_ep->max_packet_sz_tx) {
5c8a86e1 1546 dev_dbg(musb->controller,
550a7375
FB		 1547 "%s: hw_ep %d%s, %smax %d\n",
1548 musb_driver_name, i,
1549 hw_ep->is_shared_fifo ? "shared" : "tx",
1550 hw_ep->tx_double_buffered
1551 ? "doublebuffer, " : "",
1552 hw_ep->max_packet_sz_tx);
1553 }
1554 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
5c8a86e1 1555 dev_dbg(musb->controller,
550a7375
FB		 1556 "%s: hw_ep %d%s, %smax %d\n",
1557 musb_driver_name, i,
1558 "rx",
1559 hw_ep->rx_double_buffered
1560 ? "doublebuffer, " : "",
1561 hw_ep->max_packet_sz_rx);
1562 }
1563 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
5c8a86e1 1564 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
550a7375
FB		 1565 }
1566
1567 return 0;
1568}
1569
1570/*-------------------------------------------------------------------------*/
1571
550a7375
FB		 1572/*
1573 * handle all the irqs defined by the HDRC core. for now we expect: other
1574 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1575 * will be assigned, and the irq will already have been acked.
1576 *
1577 * called in irq context with spinlock held, irqs blocked
1578 */
1579irqreturn_t musb_interrupt(struct musb *musb)
1580{
1581 irqreturn_t retval = IRQ_NONE;
b11e94d0 1582 u8 devctl;
550a7375
FB		 1583 int ep_num;
1584 u32 reg;
1585
1586 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
550a7375 1587
5c8a86e1 1588 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
c03da38d 1589 is_host_active(musb) ? "host" : "peripheral",
550a7375
FB		 1590 musb->int_usb, musb->int_tx, musb->int_rx);
1591
1592 /* the core can interrupt us for multiple reasons; docs have
1593 * a generic interrupt flowchart to follow
1594 */
7d9645fd 1595 if (musb->int_usb)
550a7375 1596 retval |= musb_stage0_irq(musb, musb->int_usb,
b11e94d0 1597 devctl);
550a7375
FB		 1598
1599 /* "stage 1" is handling endpoint irqs */
1600
1601 /* handle endpoint 0 first */
1602 if (musb->int_tx & 1) {
c03da38d 1603 if (is_host_active(musb))
550a7375
FB		 1604 retval |= musb_h_ep0_irq(musb);
1605 else
1606 retval |= musb_g_ep0_irq(musb);
1607 }
1608
1609 /* RX on endpoints 1-15 */
1610 reg = musb->int_rx >> 1;
1611 ep_num = 1;
1612 while (reg) {
1613 if (reg & 1) {
1614 /* musb_ep_select(musb->mregs, ep_num); */
1615 /* REVISIT just retval = ep->rx_irq(...) */
1616 retval = IRQ_HANDLED;
c03da38d 1617 if (is_host_active(musb))
a04d46d0
FB		 1618 musb_host_rx(musb, ep_num);
1619 else
1620 musb_g_rx(musb, ep_num);
550a7375
FB		 1621 }
1622
1623 reg >>= 1;
1624 ep_num++;
1625 }
1626
1627 /* TX on endpoints 1-15 */
1628 reg = musb->int_tx >> 1;
1629 ep_num = 1;
1630 while (reg) {
1631 if (reg & 1) {
1632 /* musb_ep_select(musb->mregs, ep_num); */
1633 /* REVISIT just retval |= ep->tx_irq(...) */
1634 retval = IRQ_HANDLED;
c03da38d 1635 if (is_host_active(musb))
a04d46d0
FB		 1636 musb_host_tx(musb, ep_num);
1637 else
1638 musb_g_tx(musb, ep_num);
550a7375
FB		 1639 }
1640 reg >>= 1;
1641 ep_num++;
1642 }
1643
550a7375
FB		 1644 return retval;
1645}
981430a1 1646EXPORT_SYMBOL_GPL(musb_interrupt);
550a7375
FB		 1647
1648#ifndef CONFIG_MUSB_PIO_ONLY
d3608b6d 1649static bool use_dma = 1;
550a7375
FB		 1650
1651/* "modprobe ... use_dma=0" etc */
1652module_param(use_dma, bool, 0);
1653MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1654
1655void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1656{
550a7375
FB		 1657 /* called with controller lock already held */
1658
1659 if (!epnum) {
1660#ifndef CONFIG_USB_TUSB_OMAP_DMA
1661 if (!is_cppi_enabled()) {
1662 /* endpoint 0 */
c03da38d 1663 if (is_host_active(musb))
550a7375
FB		 1664 musb_h_ep0_irq(musb);
1665 else
1666 musb_g_ep0_irq(musb);
1667 }
1668#endif
1669 } else {
1670 /* endpoints 1..15 */
1671 if (transmit) {
c03da38d 1672 if (is_host_active(musb))
a04d46d0
FB		 1673 musb_host_tx(musb, epnum);
1674 else
1675 musb_g_tx(musb, epnum);
550a7375
FB		 1676 } else {
1677 /* receive */
c03da38d 1678 if (is_host_active(musb))
a04d46d0
FB		 1679 musb_host_rx(musb, epnum);
1680 else
1681 musb_g_rx(musb, epnum);
550a7375
FB		 1682 }
1683 }
1684}
9a35f876 1685EXPORT_SYMBOL_GPL(musb_dma_completion);
550a7375
FB		 1686
1687#else
1688#define use_dma 0
1689#endif
1690
1691/*-------------------------------------------------------------------------*/
1692
550a7375
FB		 1693static ssize_t
1694musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1695{
1696 struct musb *musb = dev_to_musb(dev);
1697 unsigned long flags;
1698 int ret = -EINVAL;
1699
1700 spin_lock_irqsave(&musb->lock, flags);
e47d9254 1701 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 1702 spin_unlock_irqrestore(&musb->lock, flags);
1703
1704 return ret;
1705}
1706
1707static ssize_t
1708musb_mode_store(struct device *dev, struct device_attribute *attr,
1709 const char *buf, size_t n)
1710{
1711 struct musb *musb = dev_to_musb(dev);
1712 unsigned long flags;
96a274d1 1713 int status;
550a7375
FB		 1714
1715 spin_lock_irqsave(&musb->lock, flags);
96a274d1
DB		 1716 if (sysfs_streq(buf, "host"))
1717 status = musb_platform_set_mode(musb, MUSB_HOST);
1718 else if (sysfs_streq(buf, "peripheral"))
1719 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1720 else if (sysfs_streq(buf, "otg"))
1721 status = musb_platform_set_mode(musb, MUSB_OTG);
1722 else
1723 status = -EINVAL;
550a7375
FB		 1724 spin_unlock_irqrestore(&musb->lock, flags);
1725
96a274d1 1726 return (status == 0) ? n : status;
550a7375
FB		 1727}
1728static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1729
1730static ssize_t
1731musb_vbus_store(struct device *dev, struct device_attribute *attr,
1732 const char *buf, size_t n)
1733{
1734 struct musb *musb = dev_to_musb(dev);
1735 unsigned long flags;
1736 unsigned long val;
1737
1738 if (sscanf(buf, "%lu", &val) < 1) {
b3b1cc3b 1739 dev_err(dev, "Invalid VBUS timeout ms value\n");
550a7375
FB		 1740 return -EINVAL;
1741 }
1742
1743 spin_lock_irqsave(&musb->lock, flags);
f7f9d63e
DB		 1744 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1745 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
e47d9254 1746 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
550a7375
FB		 1747 musb->is_active = 0;
1748 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1749 spin_unlock_irqrestore(&musb->lock, flags);
1750
1751 return n;
1752}
1753
1754static ssize_t
1755musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1756{
1757 struct musb *musb = dev_to_musb(dev);
1758 unsigned long flags;
1759 unsigned long val;
1760 int vbus;
1761
1762 spin_lock_irqsave(&musb->lock, flags);
1763 val = musb->a_wait_bcon;
f7f9d63e
DB		 1764 /* FIXME get_vbus_status() is normally #defined as false...
1765 * and is effectively TUSB-specific.
1766 */
550a7375
FB		 1767 vbus = musb_platform_get_vbus_status(musb);
1768 spin_unlock_irqrestore(&musb->lock, flags);
1769
f7f9d63e 1770 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
550a7375
FB		 1771 vbus ? "on" : "off", val);
1772}
1773static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1774
550a7375
FB		 1775/* Gadget drivers can't know that a host is connected so they might want
1776 * to start SRP, but users can. This allows userspace to trigger SRP.
1777 */
1778static ssize_t
1779musb_srp_store(struct device *dev, struct device_attribute *attr,
1780 const char *buf, size_t n)
1781{
1782 struct musb *musb = dev_to_musb(dev);
1783 unsigned short srp;
1784
1785 if (sscanf(buf, "%hu", &srp) != 1
1786 || (srp != 1)) {
b3b1cc3b 1787 dev_err(dev, "SRP: Value must be 1\n");
550a7375
FB		 1788 return -EINVAL;
1789 }
1790
1791 if (srp == 1)
1792 musb_g_wakeup(musb);
1793
1794 return n;
1795}
1796static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1797
94375751
FB		 1798static struct attribute *musb_attributes[] = {
1799 &dev_attr_mode.attr,
1800 &dev_attr_vbus.attr,
94375751 1801 &dev_attr_srp.attr,
94375751
FB		 1802 NULL
1803};
1804
1805static const struct attribute_group musb_attr_group = {
1806 .attrs = musb_attributes,
1807};
1808
550a7375
FB		 1809/* Only used to provide driver mode change events */
1810static void musb_irq_work(struct work_struct *data)
1811{
1812 struct musb *musb = container_of(data, struct musb, irq_work);
550a7375 1813
e47d9254
AT		 1814 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1815 musb->xceiv_old_state = musb->xceiv->otg->state;
550a7375
FB		 1816 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1817 }
1818}
1819
ca88fc2e
DM		 1820/* Recover from babble interrupt conditions */
1821static void musb_recover_work(struct work_struct *data)
1822{
675ae763 1823 struct musb *musb = container_of(data, struct musb, recover_work.work);
d871c622 1824 int status, ret;
ca88fc2e 1825
d871c622
GC		 1826 ret = musb_platform_reset(musb);
1827 if (ret)
1828 return;
ca88fc2e
DM		 1829
1830 usb_phy_vbus_off(musb->xceiv);
675ae763 1831 usleep_range(100, 200);
ca88fc2e
DM		 1832
1833 usb_phy_vbus_on(musb->xceiv);
675ae763 1834 usleep_range(100, 200);
ca88fc2e
DM		 1835
1836 /*
d871c622
GC		 1837 * When a babble condition occurs, the musb controller
1838 * removes the session bit and the endpoint config is lost.
ca88fc2e
DM		 1839 */
1840 if (musb->dyn_fifo)
1841 status = ep_config_from_table(musb);
1842 else
1843 status = ep_config_from_hw(musb);
1844
1845 /* start the session again */
1846 if (status == 0)
1847 musb_start(musb);
1848}
1849
550a7375
FB		 1850/* --------------------------------------------------------------------------
1851 * Init support
1852 */
1853
41ac7b3a 1854static struct musb *allocate_instance(struct device *dev,
ca6d1b13 1855 struct musb_hdrc_config *config, void __iomem *mbase)
550a7375
FB		 1856{
1857 struct musb *musb;
1858 struct musb_hw_ep *ep;
1859 int epnum;
74c2e936 1860 int ret;
550a7375 1861
74c2e936
DM		 1862 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1863 if (!musb)
550a7375 1864 return NULL;
550a7375 1865
550a7375
FB		 1866 INIT_LIST_HEAD(&musb->control);
1867 INIT_LIST_HEAD(&musb->in_bulk);
1868 INIT_LIST_HEAD(&musb->out_bulk);
1869
550a7375 1870 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
f7f9d63e 1871 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
550a7375
FB		 1872 musb->mregs = mbase;
1873 musb->ctrl_base = mbase;
1874 musb->nIrq = -ENODEV;
ca6d1b13 1875 musb->config = config;
02582b92 1876 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
550a7375 1877 for (epnum = 0, ep = musb->endpoints;
ca6d1b13 1878 epnum < musb->config->num_eps;
550a7375 1879 epnum++, ep++) {
550a7375
FB		 1880 ep->musb = musb;
1881 ep->epnum = epnum;
1882 }
1883
1884 musb->controller = dev;
743411b3 1885
74c2e936
DM		 1886 ret = musb_host_alloc(musb);
1887 if (ret < 0)
1888 goto err_free;
1889
1890 dev_set_drvdata(dev, musb);
1891
550a7375 1892 return musb;
74c2e936
DM		 1893
1894err_free:
1895 return NULL;
550a7375
FB		 1896}
1897
1898static void musb_free(struct musb *musb)
1899{
1900 /* this has multiple entry modes. it handles fault cleanup after
1901 * probe(), where things may be partially set up, as well as rmmod
1902 * cleanup after everything's been de-activated.
1903 */
1904
1905#ifdef CONFIG_SYSFS
94375751 1906 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
550a7375
FB		 1907#endif
1908
97a39896
AKG		 1909 if (musb->nIrq >= 0) {
1910 if (musb->irq_wake)
1911 disable_irq_wake(musb->nIrq);
550a7375
FB		 1912 free_irq(musb->nIrq, musb);
1913 }
550a7375 1914
74c2e936 1915 musb_host_free(musb);
550a7375
FB		 1916}
1917
8ed1fb79
DM		 1918static void musb_deassert_reset(struct work_struct *work)
1919{
1920 struct musb *musb;
1921 unsigned long flags;
1922
1923 musb = container_of(work, struct musb, deassert_reset_work.work);
1924
1925 spin_lock_irqsave(&musb->lock, flags);
1926
1927 if (musb->port1_status & USB_PORT_STAT_RESET)
1928 musb_port_reset(musb, false);
1929
1930 spin_unlock_irqrestore(&musb->lock, flags);
1931}
1932
550a7375
FB		 1933/*
1934 * Perform generic per-controller initialization.
1935 *
28dd924a
SS		 1936 * @dev: the controller (already clocked, etc)
1937 * @nIrq: IRQ number
1938 * @ctrl: virtual address of controller registers,
550a7375
FB		 1939 * not yet corrected for platform-specific offsets
1940 */
41ac7b3a 1941static int
550a7375
FB		 1942musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1943{
1944 int status;
1945 struct musb *musb;
c1a7d67c 1946 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
550a7375
FB		 1947
1948 /* The driver might handle more features than the board; OK.
1949 * Fail when the board needs a feature that's not enabled.
1950 */
1951 if (!plat) {
1952 dev_dbg(dev, "no platform_data?\n");
34e2beb2
SS		 1953 status = -ENODEV;
1954 goto fail0;
550a7375 1955 }
34e2beb2 1956
550a7375 1957 /* allocate */
ca6d1b13 1958 musb = allocate_instance(dev, plat->config, ctrl);
34e2beb2
SS		 1959 if (!musb) {
1960 status = -ENOMEM;
1961 goto fail0;
1962 }
550a7375 1963
7acc6197
HH		 1964 pm_runtime_use_autosuspend(musb->controller);
1965 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1966 pm_runtime_enable(musb->controller);
1967
550a7375 1968 spin_lock_init(&musb->lock);
550a7375 1969 musb->board_set_power = plat->set_power;
550a7375 1970 musb->min_power = plat->min_power;
f7ec9437 1971 musb->ops = plat->platform_ops;
9ad96e69 1972 musb->port_mode = plat->mode;
550a7375 1973
1b40fc57
TL		 1974 /*
1975 * Initialize the default IO functions. At least omap2430 needs
1976 * these early. We initialize the platform specific IO functions
1977 * later on.
1978 */
1979 musb_readb = musb_default_readb;
1980 musb_writeb = musb_default_writeb;
1981 musb_readw = musb_default_readw;
1982 musb_writew = musb_default_writew;
1983 musb_readl = musb_default_readl;
1984 musb_writel = musb_default_writel;
1985
84e250ff 1986 /* The musb_platform_init() call:
baef653a
PDS		 1987 * - adjusts musb->mregs
1988 * - sets the musb->isr
5ae477b0 1989 * - may initialize an integrated transceiver
721002ec 1990 * - initializes musb->xceiv, usually by otg_get_phy()
84e250ff 1991 * - stops powering VBUS
84e250ff 1992 *
7c9d440e 1993 * There are various transceiver configurations. Blackfin,
84e250ff
DB		 1994 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1995 * external/discrete ones in various flavors (twl4030 family,
1996 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
550a7375 1997 */
ea65df57 1998 status = musb_platform_init(musb);
550a7375 1999 if (status < 0)
03491761 2000 goto fail1;
34e2beb2 2001
550a7375
FB		 2002 if (!musb->isr) {
2003 status = -ENODEV;
c04352a5 2004 goto fail2;
550a7375
FB		 2005 }
2006
1b40fc57
TL		 2007 if (musb->ops->quirks)
2008 musb->io.quirks = musb->ops->quirks;
2009
2010 if (musb->ops->fifo_offset)
2011 musb->io.fifo_offset = musb->ops->fifo_offset;
2012 else
2013 musb->io.fifo_offset = musb_default_fifo_offset;
2014
2015 if (musb->ops->readb)
2016 musb_readb = musb->ops->readb;
2017 if (musb->ops->writeb)
2018 musb_writeb = musb->ops->writeb;
2019 if (musb->ops->readw)
2020 musb_readw = musb->ops->readw;
2021 if (musb->ops->writew)
2022 musb_writew = musb->ops->writew;
2023 if (musb->ops->readl)
2024 musb_readl = musb->ops->readl;
2025 if (musb->ops->writel)
2026 musb_writel = musb->ops->writel;
2027
2028 if (musb->ops->read_fifo)
2029 musb->io.read_fifo = musb->ops->read_fifo;
2030 else
2031 musb->io.read_fifo = musb_default_read_fifo;
2032
2033 if (musb->ops->write_fifo)
2034 musb->io.write_fifo = musb->ops->write_fifo;
2035 else
2036 musb->io.write_fifo = musb_default_write_fifo;
2037
ffb865b1 2038 if (!musb->xceiv->io_ops) {
bf070bc1 2039 musb->xceiv->io_dev = musb->controller;
ffb865b1
HK		 2040 musb->xceiv->io_priv = musb->mregs;
2041 musb->xceiv->io_ops = &musb_ulpi_access;
2042 }
2043
c04352a5
GI		 2044 pm_runtime_get_sync(musb->controller);
2045
48054147 2046 if (use_dma && dev->dma_mask) {
66c01883 2047 musb->dma_controller = dma_controller_create(musb, musb->mregs);
48054147
SAS		 2048 if (IS_ERR(musb->dma_controller)) {
2049 status = PTR_ERR(musb->dma_controller);
2050 goto fail2_5;
2051 }
2052 }
550a7375
FB		 2053
2054 /* be sure interrupts are disabled before connecting ISR */
2055 musb_platform_disable(musb);
2056 musb_generic_disable(musb);
2057
66fadea5
SAS		 2058 /* Init IRQ workqueue before request_irq */
2059 INIT_WORK(&musb->irq_work, musb_irq_work);
675ae763 2060 INIT_DELAYED_WORK(&musb->recover_work, musb_recover_work);
8ed1fb79
DM		 2061 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2062 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
66fadea5 2063
550a7375 2064 /* setup musb parts of the core (especially endpoints) */
ca6d1b13 2065 status = musb_core_init(plat->config->multipoint
550a7375
FB		 2066 ? MUSB_CONTROLLER_MHDRC
2067 : MUSB_CONTROLLER_HDRC, musb);
2068 if (status < 0)
34e2beb2 2069 goto fail3;
550a7375 2070
f7f9d63e 2071 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
f7f9d63e 2072
550a7375 2073 /* attach to the IRQ */
427c4f33 2074 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
550a7375
FB		 2075 dev_err(dev, "request_irq %d failed!\n", nIrq);
2076 status = -ENODEV;
34e2beb2 2077 goto fail3;
550a7375
FB		 2078 }
2079 musb->nIrq = nIrq;
032ec49f 2080 /* FIXME this handles wakeup irqs wrong */
c48a5155
FB		 2081 if (enable_irq_wake(nIrq) == 0) {
2082 musb->irq_wake = 1;
550a7375 2083 device_init_wakeup(dev, 1);
c48a5155
FB		 2084 } else {
2085 musb->irq_wake = 0;
2086 }
550a7375 2087
032ec49f
FB		 2088 /* program PHY to use external vBus if required */
2089 if (plat->extvbus) {
2090 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2091 busctl |= MUSB_ULPI_USE_EXTVBUS;
2092 musb_write_ulpi_buscontrol(musb->mregs, busctl);
550a7375 2093 }
550a7375 2094
e5615112
GI		 2095 if (musb->xceiv->otg->default_a) {
2096 MUSB_HST_MODE(musb);
e47d9254 2097 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
e5615112
GI		 2098 } else {
2099 MUSB_DEV_MODE(musb);
e47d9254 2100 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
e5615112 2101 }
550a7375 2102
6c5f6a6f
DM		 2103 switch (musb->port_mode) {
2104 case MUSB_PORT_MODE_HOST:
2105 status = musb_host_setup(musb, plat->power);
2df6761e
FB		 2106 if (status < 0)
2107 goto fail3;
2108 status = musb_platform_set_mode(musb, MUSB_HOST);
6c5f6a6f
DM		 2109 break;
2110 case MUSB_PORT_MODE_GADGET:
2111 status = musb_gadget_setup(musb);
2df6761e
FB		 2112 if (status < 0)
2113 goto fail3;
2114 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
6c5f6a6f
DM		 2115 break;
2116 case MUSB_PORT_MODE_DUAL_ROLE:
2117 status = musb_host_setup(musb, plat->power);
2118 if (status < 0)
2119 goto fail3;
2120 status = musb_gadget_setup(musb);
2df6761e 2121 if (status) {
0d2dd7ea 2122 musb_host_cleanup(musb);
2df6761e
FB		 2123 goto fail3;
2124 }
2125 status = musb_platform_set_mode(musb, MUSB_OTG);
6c5f6a6f
DM		 2126 break;
2127 default:
2128 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2129 break;
2130 }
550a7375 2131
461972d8 2132 if (status < 0)
34e2beb2 2133 goto fail3;
550a7375 2134
7f7f9e2a
FB		 2135 status = musb_init_debugfs(musb);
2136 if (status < 0)
b0f9da7e 2137 goto fail4;
7f7f9e2a 2138
94375751 2139 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
28c2c51c 2140 if (status)
b0f9da7e 2141 goto fail5;
550a7375 2142
c04352a5
GI		 2143 pm_runtime_put(musb->controller);
2144
28c2c51c 2145 return 0;
550a7375 2146
b0f9da7e
FB		 2147fail5:
2148 musb_exit_debugfs(musb);
2149
34e2beb2 2150fail4:
032ec49f 2151 musb_gadget_cleanup(musb);
0d2dd7ea 2152 musb_host_cleanup(musb);
34e2beb2
SS		 2153
2154fail3:
66fadea5 2155 cancel_work_sync(&musb->irq_work);
675ae763 2156 cancel_delayed_work_sync(&musb->recover_work);
8ed1fb79
DM		 2157 cancel_delayed_work_sync(&musb->finish_resume_work);
2158 cancel_delayed_work_sync(&musb->deassert_reset_work);
f3ce4d5b
SAS		 2159 if (musb->dma_controller)
2160 dma_controller_destroy(musb->dma_controller);
48054147 2161fail2_5:
c04352a5
GI		 2162 pm_runtime_put_sync(musb->controller);
2163
2164fail2:
34e2beb2
SS		 2165 if (musb->irq_wake)
2166 device_init_wakeup(dev, 0);
550a7375 2167 musb_platform_exit(musb);
28c2c51c 2168
34e2beb2 2169fail1:
681d1e87 2170 pm_runtime_disable(musb->controller);
34e2beb2
SS		 2171 dev_err(musb->controller,
2172 "musb_init_controller failed with status %d\n", status);
2173
28c2c51c
FB		 2174 musb_free(musb);
2175
34e2beb2
SS		 2176fail0:
2177
28c2c51c
FB		 2178 return status;
2179
550a7375
FB		 2180}
2181
2182/*-------------------------------------------------------------------------*/
2183
2184/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2185 * bridge to a platform device; this driver then suffices.
2186 */
41ac7b3a 2187static int musb_probe(struct platform_device *pdev)
550a7375
FB		 2188{
2189 struct device *dev = &pdev->dev;
fcf173e4 2190 int irq = platform_get_irq_byname(pdev, "mc");
550a7375
FB		 2191 struct resource *iomem;
2192 void __iomem *base;
2193
1f79b26c 2194 if (irq <= 0)
550a7375
FB		 2195 return -ENODEV;
2196
1f79b26c 2197 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b42f7f30
FB		 2198 base = devm_ioremap_resource(dev, iomem);
2199 if (IS_ERR(base))
2200 return PTR_ERR(base);
550a7375 2201
b42f7f30 2202 return musb_init_controller(dev, irq, base);
550a7375
FB		 2203}
2204
fb4e98ab 2205static int musb_remove(struct platform_device *pdev)
550a7375 2206{
8d2421e6
AKG		 2207 struct device *dev = &pdev->dev;
2208 struct musb *musb = dev_to_musb(dev);
550a7375
FB		 2209
2210 /* this gets called on rmmod.
2211 * - Host mode: host may still be active
2212 * - Peripheral mode: peripheral is deactivated (or never-activated)
2213 * - OTG mode: both roles are deactivated (or never-activated)
2214 */
7f7f9e2a 2215 musb_exit_debugfs(musb);
550a7375 2216 musb_shutdown(pdev);
461972d8 2217
8d1aad74
SAS		 2218 if (musb->dma_controller)
2219 dma_controller_destroy(musb->dma_controller);
2220
66fadea5 2221 cancel_work_sync(&musb->irq_work);
675ae763 2222 cancel_delayed_work_sync(&musb->recover_work);
8ed1fb79
DM		 2223 cancel_delayed_work_sync(&musb->finish_resume_work);
2224 cancel_delayed_work_sync(&musb->deassert_reset_work);
550a7375 2225 musb_free(musb);
8d2421e6 2226 device_init_wakeup(dev, 0);
550a7375
FB		 2227 return 0;
2228}
2229
2230#ifdef CONFIG_PM
2231
3c8a5fcc 2232static void musb_save_context(struct musb *musb)
4f712e01
AKG		 2233{
2234 int i;
2235 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2236 void __iomem *epio;
4f712e01 2237
032ec49f
FB		 2238 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2239 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2240 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
7421107b 2241 musb->context.power = musb_readb(musb_base, MUSB_POWER);
7421107b
FB		 2242 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2243 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2244 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
4f712e01 2245
ae9b2ad2 2246 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2247 struct musb_hw_ep *hw_ep;
2248
2249 hw_ep = &musb->endpoints[i];
2250 if (!hw_ep)
2251 continue;
2252
2253 epio = hw_ep->regs;
2254 if (!epio)
2255 continue;
2256
ea737554 2257 musb_writeb(musb_base, MUSB_INDEX, i);
7421107b 2258 musb->context.index_regs[i].txmaxp =
ae9b2ad2 2259 musb_readw(epio, MUSB_TXMAXP);
7421107b 2260 musb->context.index_regs[i].txcsr =
ae9b2ad2 2261 musb_readw(epio, MUSB_TXCSR);
7421107b 2262 musb->context.index_regs[i].rxmaxp =
ae9b2ad2 2263 musb_readw(epio, MUSB_RXMAXP);
7421107b 2264 musb->context.index_regs[i].rxcsr =
ae9b2ad2 2265 musb_readw(epio, MUSB_RXCSR);
4f712e01
AKG		 2266
2267 if (musb->dyn_fifo) {
7421107b 2268 musb->context.index_regs[i].txfifoadd =
4f712e01 2269 musb_read_txfifoadd(musb_base);
7421107b 2270 musb->context.index_regs[i].rxfifoadd =
4f712e01 2271 musb_read_rxfifoadd(musb_base);
7421107b 2272 musb->context.index_regs[i].txfifosz =
4f712e01 2273 musb_read_txfifosz(musb_base);
7421107b 2274 musb->context.index_regs[i].rxfifosz =
4f712e01
AKG		 2275 musb_read_rxfifosz(musb_base);
2276 }
032ec49f
FB		 2277
2278 musb->context.index_regs[i].txtype =
2279 musb_readb(epio, MUSB_TXTYPE);
2280 musb->context.index_regs[i].txinterval =
2281 musb_readb(epio, MUSB_TXINTERVAL);
2282 musb->context.index_regs[i].rxtype =
2283 musb_readb(epio, MUSB_RXTYPE);
2284 musb->context.index_regs[i].rxinterval =
2285 musb_readb(epio, MUSB_RXINTERVAL);
2286
2287 musb->context.index_regs[i].txfunaddr =
2288 musb_read_txfunaddr(musb_base, i);
2289 musb->context.index_regs[i].txhubaddr =
2290 musb_read_txhubaddr(musb_base, i);
2291 musb->context.index_regs[i].txhubport =
2292 musb_read_txhubport(musb_base, i);
2293
2294 musb->context.index_regs[i].rxfunaddr =
2295 musb_read_rxfunaddr(musb_base, i);
2296 musb->context.index_regs[i].rxhubaddr =
2297 musb_read_rxhubaddr(musb_base, i);
2298 musb->context.index_regs[i].rxhubport =
2299 musb_read_rxhubport(musb_base, i);
4f712e01 2300 }
4f712e01
AKG		 2301}
2302
3c8a5fcc 2303static void musb_restore_context(struct musb *musb)
4f712e01
AKG		 2304{
2305 int i;
2306 void __iomem *musb_base = musb->mregs;
2307 void __iomem *ep_target_regs;
ae9b2ad2 2308 void __iomem *epio;
33f8d75f 2309 u8 power;
4f712e01 2310
032ec49f
FB		 2311 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2312 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2313 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
33f8d75f
RQ		 2314
2315 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2316 power = musb_readb(musb_base, MUSB_POWER);
2317 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2318 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2319 power |= musb->context.power;
2320 musb_writeb(musb_base, MUSB_POWER, power);
2321
b18d26f6 2322 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
af5ec14d 2323 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
7421107b
FB		 2324 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2325 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
4f712e01 2326
ae9b2ad2 2327 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2328 struct musb_hw_ep *hw_ep;
2329
2330 hw_ep = &musb->endpoints[i];
2331 if (!hw_ep)
2332 continue;
2333
2334 epio = hw_ep->regs;
2335 if (!epio)
2336 continue;
2337
ea737554 2338 musb_writeb(musb_base, MUSB_INDEX, i);
ae9b2ad2 2339 musb_writew(epio, MUSB_TXMAXP,
7421107b 2340 musb->context.index_regs[i].txmaxp);
ae9b2ad2 2341 musb_writew(epio, MUSB_TXCSR,
7421107b 2342 musb->context.index_regs[i].txcsr);
ae9b2ad2 2343 musb_writew(epio, MUSB_RXMAXP,
7421107b 2344 musb->context.index_regs[i].rxmaxp);
ae9b2ad2 2345 musb_writew(epio, MUSB_RXCSR,
7421107b 2346 musb->context.index_regs[i].rxcsr);
4f712e01
AKG		 2347
2348 if (musb->dyn_fifo) {
2349 musb_write_txfifosz(musb_base,
7421107b 2350 musb->context.index_regs[i].txfifosz);
4f712e01 2351 musb_write_rxfifosz(musb_base,
7421107b 2352 musb->context.index_regs[i].rxfifosz);
4f712e01 2353 musb_write_txfifoadd(musb_base,
7421107b 2354 musb->context.index_regs[i].txfifoadd);
4f712e01 2355 musb_write_rxfifoadd(musb_base,
7421107b 2356 musb->context.index_regs[i].rxfifoadd);
4f712e01
AKG		 2357 }
2358
032ec49f 2359 musb_writeb(epio, MUSB_TXTYPE,
7421107b 2360 musb->context.index_regs[i].txtype);
032ec49f 2361 musb_writeb(epio, MUSB_TXINTERVAL,
7421107b 2362 musb->context.index_regs[i].txinterval);
032ec49f 2363 musb_writeb(epio, MUSB_RXTYPE,
7421107b 2364 musb->context.index_regs[i].rxtype);
032ec49f 2365 musb_writeb(epio, MUSB_RXINTERVAL,
4f712e01 2366
032ec49f
FB		 2367 musb->context.index_regs[i].rxinterval);
2368 musb_write_txfunaddr(musb_base, i,
7421107b 2369 musb->context.index_regs[i].txfunaddr);
032ec49f 2370 musb_write_txhubaddr(musb_base, i,
7421107b 2371 musb->context.index_regs[i].txhubaddr);
032ec49f 2372 musb_write_txhubport(musb_base, i,
7421107b 2373 musb->context.index_regs[i].txhubport);
4f712e01 2374
032ec49f
FB		 2375 ep_target_regs =
2376 musb_read_target_reg_base(i, musb_base);
4f712e01 2377
032ec49f 2378 musb_write_rxfunaddr(ep_target_regs,
7421107b 2379 musb->context.index_regs[i].rxfunaddr);
032ec49f 2380 musb_write_rxhubaddr(ep_target_regs,
7421107b 2381 musb->context.index_regs[i].rxhubaddr);
032ec49f 2382 musb_write_rxhubport(ep_target_regs,
7421107b 2383 musb->context.index_regs[i].rxhubport);
4f712e01 2384 }
3c5fec75 2385 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
4f712e01
AKG		 2386}
2387
48fea965 2388static int musb_suspend(struct device *dev)
550a7375 2389{
8220796d 2390 struct musb *musb = dev_to_musb(dev);
550a7375 2391 unsigned long flags;
550a7375 2392
550a7375
FB		 2393 spin_lock_irqsave(&musb->lock, flags);
2394
2395 if (is_peripheral_active(musb)) {
2396 /* FIXME force disconnect unless we know USB will wake
2397 * the system up quickly enough to respond ...
2398 */
2399 } else if (is_host_active(musb)) {
2400 /* we know all the children are suspended; sometimes
2401 * they will even be wakeup-enabled.
2402 */
2403 }
2404
c338412b
DM		 2405 musb_save_context(musb);
2406
550a7375
FB		 2407 spin_unlock_irqrestore(&musb->lock, flags);
2408 return 0;
2409}
2410
3e87d9a3 2411static int musb_resume(struct device *dev)
550a7375 2412{
c338412b 2413 struct musb *musb = dev_to_musb(dev);
b87fd2f7
SAS		 2414 u8 devctl;
2415 u8 mask;
c338412b
DM		 2416
2417 /*
2418 * For static cmos like DaVinci, register values were preserved
0ec8fd70
KK		 2419 * unless for some reason the whole soc powered down or the USB
2420 * module got reset through the PSC (vs just being disabled).
c338412b
DM		 2421 *
2422 * For the DSPS glue layer though, a full register restore has to
2423 * be done. As it shouldn't harm other platforms, we do it
2424 * unconditionally.
550a7375 2425 */
c338412b
DM		 2426
2427 musb_restore_context(musb);
2428
b87fd2f7
SAS		 2429 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2430 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2431 if ((devctl & mask) != (musb->context.devctl & mask))
2432 musb->port1_status = 0;
baadd52f
SAS		 2433 if (musb->need_finish_resume) {
2434 musb->need_finish_resume = 0;
2435 schedule_delayed_work(&musb->finish_resume_work,
2436 msecs_to_jiffies(20));
2437 }
a1fc1920
SAS		 2438
2439 /*
2440 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2441 * out of suspend
2442 */
2443 pm_runtime_disable(dev);
2444 pm_runtime_set_active(dev);
2445 pm_runtime_enable(dev);
550a7375
FB		 2446 return 0;
2447}
2448
7acc6197
HH		 2449static int musb_runtime_suspend(struct device *dev)
2450{
2451 struct musb *musb = dev_to_musb(dev);
2452
2453 musb_save_context(musb);
2454
2455 return 0;
2456}
2457
2458static int musb_runtime_resume(struct device *dev)
2459{
2460 struct musb *musb = dev_to_musb(dev);
2461 static int first = 1;
2462
2463 /*
2464 * When pm_runtime_get_sync called for the first time in driver
2465 * init, some of the structure is still not initialized which is
2466 * used in restore function. But clock needs to be
2467 * enabled before any register access, so
2468 * pm_runtime_get_sync has to be called.
2469 * Also context restore without save does not make
2470 * any sense
2471 */
2472 if (!first)
2473 musb_restore_context(musb);
2474 first = 0;
2475
2476 return 0;
2477}
2478
47145210 2479static const struct dev_pm_ops musb_dev_pm_ops = {
48fea965 2480 .suspend = musb_suspend,
3e87d9a3 2481 .resume = musb_resume,
7acc6197
HH		 2482 .runtime_suspend = musb_runtime_suspend,
2483 .runtime_resume = musb_runtime_resume,
48fea965
MD		 2484};
2485
2486#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
550a7375 2487#else
48fea965 2488#define MUSB_DEV_PM_OPS NULL
550a7375
FB		 2489#endif
2490
2491static struct platform_driver musb_driver = {
2492 .driver = {
2493 .name = (char *)musb_driver_name,
2494 .bus = &platform_bus_type,
2495 .owner = THIS_MODULE,
48fea965 2496 .pm = MUSB_DEV_PM_OPS,
550a7375 2497 },
e9e8c85e 2498 .probe = musb_probe,
7690417d 2499 .remove = musb_remove,
550a7375 2500 .shutdown = musb_shutdown,
550a7375
FB		 2501};
2502
89f836a8 2503module_platform_driver(musb_driver);
Linux kernel - Deliverables
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