Commit | Line | Data |
---|---|---|
550a7375 FB |
1 | /* |
2 | * MUSB OTG driver core code | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
23 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
25 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
26 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
27 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
28 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | */ | |
34 | ||
35 | /* | |
36 | * Inventra (Multipoint) Dual-Role Controller Driver for Linux. | |
37 | * | |
38 | * This consists of a Host Controller Driver (HCD) and a peripheral | |
39 | * controller driver implementing the "Gadget" API; OTG support is | |
40 | * in the works. These are normal Linux-USB controller drivers which | |
41 | * use IRQs and have no dedicated thread. | |
42 | * | |
43 | * This version of the driver has only been used with products from | |
44 | * Texas Instruments. Those products integrate the Inventra logic | |
45 | * with other DMA, IRQ, and bus modules, as well as other logic that | |
46 | * needs to be reflected in this driver. | |
47 | * | |
48 | * | |
49 | * NOTE: the original Mentor code here was pretty much a collection | |
50 | * of mechanisms that don't seem to have been fully integrated/working | |
51 | * for *any* Linux kernel version. This version aims at Linux 2.6.now, | |
52 | * Key open issues include: | |
53 | * | |
54 | * - Lack of host-side transaction scheduling, for all transfer types. | |
55 | * The hardware doesn't do it; instead, software must. | |
56 | * | |
57 | * This is not an issue for OTG devices that don't support external | |
58 | * hubs, but for more "normal" USB hosts it's a user issue that the | |
59 | * "multipoint" support doesn't scale in the expected ways. That | |
60 | * includes DaVinci EVM in a common non-OTG mode. | |
61 | * | |
62 | * * Control and bulk use dedicated endpoints, and there's as | |
63 | * yet no mechanism to either (a) reclaim the hardware when | |
64 | * peripherals are NAKing, which gets complicated with bulk | |
65 | * endpoints, or (b) use more than a single bulk endpoint in | |
66 | * each direction. | |
67 | * | |
68 | * RESULT: one device may be perceived as blocking another one. | |
69 | * | |
70 | * * Interrupt and isochronous will dynamically allocate endpoint | |
71 | * hardware, but (a) there's no record keeping for bandwidth; | |
72 | * (b) in the common case that few endpoints are available, there | |
73 | * is no mechanism to reuse endpoints to talk to multiple devices. | |
74 | * | |
75 | * RESULT: At one extreme, bandwidth can be overcommitted in | |
76 | * some hardware configurations, no faults will be reported. | |
77 | * At the other extreme, the bandwidth capabilities which do | |
78 | * exist tend to be severely undercommitted. You can't yet hook | |
79 | * up both a keyboard and a mouse to an external USB hub. | |
80 | */ | |
81 | ||
82 | /* | |
83 | * This gets many kinds of configuration information: | |
84 | * - Kconfig for everything user-configurable | |
550a7375 | 85 | * - platform_device for addressing, irq, and platform_data |
5ae477b0 | 86 | * - platform_data is mostly for board-specific information |
c767c1c6 | 87 | * (plus recentrly, SOC or family details) |
550a7375 FB |
88 | * |
89 | * Most of the conditional compilation will (someday) vanish. | |
90 | */ | |
91 | ||
92 | #include <linux/module.h> | |
93 | #include <linux/kernel.h> | |
94 | #include <linux/sched.h> | |
95 | #include <linux/slab.h> | |
550a7375 FB |
96 | #include <linux/list.h> |
97 | #include <linux/kobject.h> | |
9303961f | 98 | #include <linux/prefetch.h> |
550a7375 FB |
99 | #include <linux/platform_device.h> |
100 | #include <linux/io.h> | |
8d2421e6 | 101 | #include <linux/dma-mapping.h> |
309be239 | 102 | #include <linux/usb.h> |
550a7375 | 103 | |
550a7375 FB |
104 | #include "musb_core.h" |
105 | ||
f7f9d63e | 106 | #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) |
550a7375 FB |
107 | |
108 | ||
550a7375 FB |
109 | #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" |
110 | #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" | |
111 | ||
e8164f64 | 112 | #define MUSB_VERSION "6.0" |
550a7375 FB |
113 | |
114 | #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION | |
115 | ||
05ac10dd | 116 | #define MUSB_DRIVER_NAME "musb-hdrc" |
550a7375 FB |
117 | const char musb_driver_name[] = MUSB_DRIVER_NAME; |
118 | ||
119 | MODULE_DESCRIPTION(DRIVER_INFO); | |
120 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
121 | MODULE_LICENSE("GPL"); | |
122 | MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); | |
123 | ||
124 | ||
125 | /*-------------------------------------------------------------------------*/ | |
126 | ||
127 | static inline struct musb *dev_to_musb(struct device *dev) | |
128 | { | |
550a7375 | 129 | return dev_get_drvdata(dev); |
550a7375 FB |
130 | } |
131 | ||
132 | /*-------------------------------------------------------------------------*/ | |
133 | ||
ffb865b1 | 134 | #ifndef CONFIG_BLACKFIN |
b96d3b08 | 135 | static int musb_ulpi_read(struct usb_phy *phy, u32 offset) |
ffb865b1 | 136 | { |
b96d3b08 | 137 | void __iomem *addr = phy->io_priv; |
ffb865b1 HK |
138 | int i = 0; |
139 | u8 r; | |
140 | u8 power; | |
bf070bc1 GI |
141 | int ret; |
142 | ||
143 | pm_runtime_get_sync(phy->io_dev); | |
ffb865b1 HK |
144 | |
145 | /* Make sure the transceiver is not in low power mode */ | |
146 | power = musb_readb(addr, MUSB_POWER); | |
147 | power &= ~MUSB_POWER_SUSPENDM; | |
148 | musb_writeb(addr, MUSB_POWER, power); | |
149 | ||
150 | /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the | |
151 | * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. | |
152 | */ | |
153 | ||
154 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); | |
155 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, | |
156 | MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); | |
157 | ||
158 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) | |
159 | & MUSB_ULPI_REG_CMPLT)) { | |
160 | i++; | |
bf070bc1 GI |
161 | if (i == 10000) { |
162 | ret = -ETIMEDOUT; | |
163 | goto out; | |
164 | } | |
ffb865b1 HK |
165 | |
166 | } | |
167 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); | |
168 | r &= ~MUSB_ULPI_REG_CMPLT; | |
169 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); | |
170 | ||
bf070bc1 GI |
171 | ret = musb_readb(addr, MUSB_ULPI_REG_DATA); |
172 | ||
173 | out: | |
174 | pm_runtime_put(phy->io_dev); | |
175 | ||
176 | return ret; | |
ffb865b1 HK |
177 | } |
178 | ||
b96d3b08 | 179 | static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) |
ffb865b1 | 180 | { |
b96d3b08 | 181 | void __iomem *addr = phy->io_priv; |
ffb865b1 HK |
182 | int i = 0; |
183 | u8 r = 0; | |
184 | u8 power; | |
bf070bc1 GI |
185 | int ret = 0; |
186 | ||
187 | pm_runtime_get_sync(phy->io_dev); | |
ffb865b1 HK |
188 | |
189 | /* Make sure the transceiver is not in low power mode */ | |
190 | power = musb_readb(addr, MUSB_POWER); | |
191 | power &= ~MUSB_POWER_SUSPENDM; | |
192 | musb_writeb(addr, MUSB_POWER, power); | |
193 | ||
194 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); | |
195 | musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); | |
196 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); | |
197 | ||
198 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) | |
199 | & MUSB_ULPI_REG_CMPLT)) { | |
200 | i++; | |
bf070bc1 GI |
201 | if (i == 10000) { |
202 | ret = -ETIMEDOUT; | |
203 | goto out; | |
204 | } | |
ffb865b1 HK |
205 | } |
206 | ||
207 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); | |
208 | r &= ~MUSB_ULPI_REG_CMPLT; | |
209 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); | |
210 | ||
bf070bc1 GI |
211 | out: |
212 | pm_runtime_put(phy->io_dev); | |
213 | ||
214 | return ret; | |
ffb865b1 HK |
215 | } |
216 | #else | |
f2263db7 MF |
217 | #define musb_ulpi_read NULL |
218 | #define musb_ulpi_write NULL | |
ffb865b1 HK |
219 | #endif |
220 | ||
b96d3b08 | 221 | static struct usb_phy_io_ops musb_ulpi_access = { |
ffb865b1 HK |
222 | .read = musb_ulpi_read, |
223 | .write = musb_ulpi_write, | |
224 | }; | |
225 | ||
226 | /*-------------------------------------------------------------------------*/ | |
227 | ||
1b40fc57 TL |
228 | static u32 musb_default_fifo_offset(u8 epnum) |
229 | { | |
230 | return 0x20 + (epnum * 4); | |
231 | } | |
232 | ||
d026e9c7 TL |
233 | /* "flat" mapping: each endpoint has its own i/o address */ |
234 | static void musb_flat_ep_select(void __iomem *mbase, u8 epnum) | |
235 | { | |
236 | } | |
237 | ||
238 | static u32 musb_flat_ep_offset(u8 epnum, u16 offset) | |
239 | { | |
240 | return 0x100 + (0x10 * epnum) + offset; | |
241 | } | |
242 | ||
243 | /* "indexed" mapping: INDEX register controls register bank select */ | |
244 | static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum) | |
245 | { | |
246 | musb_writeb(mbase, MUSB_INDEX, epnum); | |
247 | } | |
248 | ||
249 | static u32 musb_indexed_ep_offset(u8 epnum, u16 offset) | |
250 | { | |
251 | return 0x10 + offset; | |
252 | } | |
253 | ||
6cc2af6d HG |
254 | static u32 musb_default_busctl_offset(u8 epnum, u16 offset) |
255 | { | |
256 | return 0x80 + (0x08 * epnum) + offset; | |
257 | } | |
258 | ||
1b40fc57 TL |
259 | static u8 musb_default_readb(const void __iomem *addr, unsigned offset) |
260 | { | |
261 | return __raw_readb(addr + offset); | |
262 | } | |
263 | ||
264 | static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data) | |
265 | { | |
266 | __raw_writeb(data, addr + offset); | |
267 | } | |
268 | ||
269 | static u16 musb_default_readw(const void __iomem *addr, unsigned offset) | |
270 | { | |
271 | return __raw_readw(addr + offset); | |
272 | } | |
273 | ||
274 | static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data) | |
275 | { | |
276 | __raw_writew(data, addr + offset); | |
277 | } | |
278 | ||
279 | static u32 musb_default_readl(const void __iomem *addr, unsigned offset) | |
280 | { | |
281 | return __raw_readl(addr + offset); | |
282 | } | |
283 | ||
284 | static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data) | |
285 | { | |
286 | __raw_writel(data, addr + offset); | |
287 | } | |
c6cf8b00 | 288 | |
550a7375 FB |
289 | /* |
290 | * Load an endpoint's FIFO | |
291 | */ | |
1b40fc57 TL |
292 | static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len, |
293 | const u8 *src) | |
550a7375 | 294 | { |
5c8a86e1 | 295 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
296 | void __iomem *fifo = hw_ep->fifo; |
297 | ||
603fe2b2 AKG |
298 | if (unlikely(len == 0)) |
299 | return; | |
300 | ||
550a7375 FB |
301 | prefetch((u8 *)src); |
302 | ||
5c8a86e1 | 303 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
304 | 'T', hw_ep->epnum, fifo, len, src); |
305 | ||
306 | /* we can't assume unaligned reads work */ | |
307 | if (likely((0x01 & (unsigned long) src) == 0)) { | |
308 | u16 index = 0; | |
309 | ||
310 | /* best case is 32bit-aligned source address */ | |
311 | if ((0x02 & (unsigned long) src) == 0) { | |
312 | if (len >= 4) { | |
2bf0a8f6 | 313 | iowrite32_rep(fifo, src + index, len >> 2); |
550a7375 FB |
314 | index += len & ~0x03; |
315 | } | |
316 | if (len & 0x02) { | |
be780381 | 317 | __raw_writew(*(u16 *)&src[index], fifo); |
550a7375 FB |
318 | index += 2; |
319 | } | |
320 | } else { | |
321 | if (len >= 2) { | |
2bf0a8f6 | 322 | iowrite16_rep(fifo, src + index, len >> 1); |
550a7375 FB |
323 | index += len & ~0x01; |
324 | } | |
325 | } | |
326 | if (len & 0x01) | |
be780381 | 327 | __raw_writeb(src[index], fifo); |
550a7375 FB |
328 | } else { |
329 | /* byte aligned */ | |
2bf0a8f6 | 330 | iowrite8_rep(fifo, src, len); |
550a7375 FB |
331 | } |
332 | } | |
333 | ||
334 | /* | |
335 | * Unload an endpoint's FIFO | |
336 | */ | |
1b40fc57 | 337 | static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) |
550a7375 | 338 | { |
5c8a86e1 | 339 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
340 | void __iomem *fifo = hw_ep->fifo; |
341 | ||
603fe2b2 AKG |
342 | if (unlikely(len == 0)) |
343 | return; | |
344 | ||
5c8a86e1 | 345 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
346 | 'R', hw_ep->epnum, fifo, len, dst); |
347 | ||
348 | /* we can't assume unaligned writes work */ | |
349 | if (likely((0x01 & (unsigned long) dst) == 0)) { | |
350 | u16 index = 0; | |
351 | ||
352 | /* best case is 32bit-aligned destination address */ | |
353 | if ((0x02 & (unsigned long) dst) == 0) { | |
354 | if (len >= 4) { | |
2bf0a8f6 | 355 | ioread32_rep(fifo, dst, len >> 2); |
550a7375 FB |
356 | index = len & ~0x03; |
357 | } | |
358 | if (len & 0x02) { | |
be780381 | 359 | *(u16 *)&dst[index] = __raw_readw(fifo); |
550a7375 FB |
360 | index += 2; |
361 | } | |
362 | } else { | |
363 | if (len >= 2) { | |
2bf0a8f6 | 364 | ioread16_rep(fifo, dst, len >> 1); |
550a7375 FB |
365 | index = len & ~0x01; |
366 | } | |
367 | } | |
368 | if (len & 0x01) | |
be780381 | 369 | dst[index] = __raw_readb(fifo); |
550a7375 FB |
370 | } else { |
371 | /* byte aligned */ | |
2bf0a8f6 | 372 | ioread8_rep(fifo, dst, len); |
550a7375 FB |
373 | } |
374 | } | |
375 | ||
1b40fc57 TL |
376 | /* |
377 | * Old style IO functions | |
378 | */ | |
379 | u8 (*musb_readb)(const void __iomem *addr, unsigned offset); | |
380 | EXPORT_SYMBOL_GPL(musb_readb); | |
381 | ||
382 | void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data); | |
383 | EXPORT_SYMBOL_GPL(musb_writeb); | |
550a7375 | 384 | |
1b40fc57 TL |
385 | u16 (*musb_readw)(const void __iomem *addr, unsigned offset); |
386 | EXPORT_SYMBOL_GPL(musb_readw); | |
387 | ||
388 | void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data); | |
389 | EXPORT_SYMBOL_GPL(musb_writew); | |
390 | ||
391 | u32 (*musb_readl)(const void __iomem *addr, unsigned offset); | |
392 | EXPORT_SYMBOL_GPL(musb_readl); | |
393 | ||
394 | void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data); | |
395 | EXPORT_SYMBOL_GPL(musb_writel); | |
396 | ||
7f6283ed TL |
397 | #ifndef CONFIG_MUSB_PIO_ONLY |
398 | struct dma_controller * | |
399 | (*musb_dma_controller_create)(struct musb *musb, void __iomem *base); | |
400 | EXPORT_SYMBOL(musb_dma_controller_create); | |
401 | ||
402 | void (*musb_dma_controller_destroy)(struct dma_controller *c); | |
403 | EXPORT_SYMBOL(musb_dma_controller_destroy); | |
404 | #endif | |
405 | ||
1b40fc57 TL |
406 | /* |
407 | * New style IO functions | |
408 | */ | |
409 | void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) | |
410 | { | |
411 | return hw_ep->musb->io.read_fifo(hw_ep, len, dst); | |
412 | } | |
413 | ||
414 | void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) | |
415 | { | |
416 | return hw_ep->musb->io.write_fifo(hw_ep, len, src); | |
417 | } | |
550a7375 FB |
418 | |
419 | /*-------------------------------------------------------------------------*/ | |
420 | ||
421 | /* for high speed test mode; see USB 2.0 spec 7.1.20 */ | |
422 | static const u8 musb_test_packet[53] = { | |
423 | /* implicit SYNC then DATA0 to start */ | |
424 | ||
425 | /* JKJKJKJK x9 */ | |
426 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
427 | /* JJKKJJKK x8 */ | |
428 | 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, | |
429 | /* JJJJKKKK x8 */ | |
430 | 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, | |
431 | /* JJJJJJJKKKKKKK x8 */ | |
432 | 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
433 | /* JJJJJJJK x8 */ | |
434 | 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, | |
435 | /* JKKKKKKK x10, JK */ | |
436 | 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e | |
437 | ||
438 | /* implicit CRC16 then EOP to end */ | |
439 | }; | |
440 | ||
441 | void musb_load_testpacket(struct musb *musb) | |
442 | { | |
443 | void __iomem *regs = musb->endpoints[0].regs; | |
444 | ||
445 | musb_ep_select(musb->mregs, 0); | |
446 | musb_write_fifo(musb->control_ep, | |
447 | sizeof(musb_test_packet), musb_test_packet); | |
448 | musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); | |
449 | } | |
450 | ||
451 | /*-------------------------------------------------------------------------*/ | |
452 | ||
550a7375 FB |
453 | /* |
454 | * Handles OTG hnp timeouts, such as b_ase0_brst | |
455 | */ | |
a156544b | 456 | static void musb_otg_timer_func(unsigned long data) |
550a7375 FB |
457 | { |
458 | struct musb *musb = (struct musb *)data; | |
459 | unsigned long flags; | |
460 | ||
461 | spin_lock_irqsave(&musb->lock, flags); | |
e47d9254 | 462 | switch (musb->xceiv->otg->state) { |
550a7375 | 463 | case OTG_STATE_B_WAIT_ACON: |
5c8a86e1 | 464 | dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); |
550a7375 | 465 | musb_g_disconnect(musb); |
e47d9254 | 466 | musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
467 | musb->is_active = 0; |
468 | break; | |
ab983f2a | 469 | case OTG_STATE_A_SUSPEND: |
550a7375 | 470 | case OTG_STATE_A_WAIT_BCON: |
5c8a86e1 | 471 | dev_dbg(musb->controller, "HNP: %s timeout\n", |
e47d9254 | 472 | usb_otg_state_string(musb->xceiv->otg->state)); |
743411b3 | 473 | musb_platform_set_vbus(musb, 0); |
e47d9254 | 474 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; |
550a7375 FB |
475 | break; |
476 | default: | |
5c8a86e1 | 477 | dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", |
e47d9254 | 478 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 | 479 | } |
550a7375 FB |
480 | spin_unlock_irqrestore(&musb->lock, flags); |
481 | } | |
482 | ||
550a7375 | 483 | /* |
f7f9d63e | 484 | * Stops the HNP transition. Caller must take care of locking. |
550a7375 FB |
485 | */ |
486 | void musb_hnp_stop(struct musb *musb) | |
487 | { | |
8b125df5 | 488 | struct usb_hcd *hcd = musb->hcd; |
550a7375 FB |
489 | void __iomem *mbase = musb->mregs; |
490 | u8 reg; | |
491 | ||
42c0bf1c | 492 | dev_dbg(musb->controller, "HNP: stop from %s\n", |
e47d9254 | 493 | usb_otg_state_string(musb->xceiv->otg->state)); |
ab983f2a | 494 | |
e47d9254 | 495 | switch (musb->xceiv->otg->state) { |
550a7375 | 496 | case OTG_STATE_A_PERIPHERAL: |
550a7375 | 497 | musb_g_disconnect(musb); |
5c8a86e1 | 498 | dev_dbg(musb->controller, "HNP: back to %s\n", |
e47d9254 | 499 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 FB |
500 | break; |
501 | case OTG_STATE_B_HOST: | |
5c8a86e1 | 502 | dev_dbg(musb->controller, "HNP: Disabling HR\n"); |
74c2e936 DM |
503 | if (hcd) |
504 | hcd->self.is_b_host = 0; | |
e47d9254 | 505 | musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
506 | MUSB_DEV_MODE(musb); |
507 | reg = musb_readb(mbase, MUSB_POWER); | |
508 | reg |= MUSB_POWER_SUSPENDM; | |
509 | musb_writeb(mbase, MUSB_POWER, reg); | |
510 | /* REVISIT: Start SESSION_REQUEST here? */ | |
511 | break; | |
512 | default: | |
5c8a86e1 | 513 | dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", |
e47d9254 | 514 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 FB |
515 | } |
516 | ||
517 | /* | |
518 | * When returning to A state after HNP, avoid hub_port_rebounce(), | |
519 | * which cause occasional OPT A "Did not receive reset after connect" | |
520 | * errors. | |
521 | */ | |
749da5f8 | 522 | musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); |
550a7375 FB |
523 | } |
524 | ||
83b8f5b8 | 525 | static void musb_recover_from_babble(struct musb *musb); |
e1eb3eb8 | 526 | |
550a7375 FB |
527 | /* |
528 | * Interrupt Service Routine to record USB "global" interrupts. | |
529 | * Since these do not happen often and signify things of | |
530 | * paramount importance, it seems OK to check them individually; | |
531 | * the order of the tests is specified in the manual | |
532 | * | |
533 | * @param musb instance pointer | |
534 | * @param int_usb register contents | |
535 | * @param devctl | |
536 | * @param power | |
537 | */ | |
538 | ||
550a7375 | 539 | static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, |
b11e94d0 | 540 | u8 devctl) |
550a7375 FB |
541 | { |
542 | irqreturn_t handled = IRQ_NONE; | |
550a7375 | 543 | |
b11e94d0 | 544 | dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl, |
550a7375 FB |
545 | int_usb); |
546 | ||
547 | /* in host mode, the peripheral may issue remote wakeup. | |
548 | * in peripheral mode, the host may resume the link. | |
549 | * spurious RESUME irqs happen too, paired with SUSPEND. | |
550 | */ | |
551 | if (int_usb & MUSB_INTR_RESUME) { | |
552 | handled = IRQ_HANDLED; | |
0acff6b8 FB |
553 | dev_dbg(musb->controller, "RESUME (%s)\n", |
554 | usb_otg_state_string(musb->xceiv->otg->state)); | |
550a7375 FB |
555 | |
556 | if (devctl & MUSB_DEVCTL_HM) { | |
e47d9254 | 557 | switch (musb->xceiv->otg->state) { |
550a7375 FB |
558 | case OTG_STATE_A_SUSPEND: |
559 | /* remote wakeup? later, GetPortStatus | |
560 | * will stop RESUME signaling | |
561 | */ | |
562 | ||
550a7375 FB |
563 | musb->port1_status |= |
564 | (USB_PORT_STAT_C_SUSPEND << 16) | |
565 | | MUSB_PORT_STAT_RESUME; | |
30d361bf | 566 | musb->rh_timer = jiffies |
309be239 | 567 | + msecs_to_jiffies(USB_RESUME_TIMEOUT); |
baadd52f | 568 | musb->need_finish_resume = 1; |
550a7375 | 569 | |
e47d9254 | 570 | musb->xceiv->otg->state = OTG_STATE_A_HOST; |
550a7375 | 571 | musb->is_active = 1; |
9298b4aa | 572 | musb_host_resume_root_hub(musb); |
550a7375 FB |
573 | break; |
574 | case OTG_STATE_B_WAIT_ACON: | |
e47d9254 | 575 | musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
576 | musb->is_active = 1; |
577 | MUSB_DEV_MODE(musb); | |
578 | break; | |
579 | default: | |
580 | WARNING("bogus %s RESUME (%s)\n", | |
581 | "host", | |
e47d9254 | 582 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 | 583 | } |
550a7375 | 584 | } else { |
e47d9254 | 585 | switch (musb->xceiv->otg->state) { |
550a7375 FB |
586 | case OTG_STATE_A_SUSPEND: |
587 | /* possibly DISCONNECT is upcoming */ | |
e47d9254 | 588 | musb->xceiv->otg->state = OTG_STATE_A_HOST; |
0b3eba44 | 589 | musb_host_resume_root_hub(musb); |
550a7375 | 590 | break; |
550a7375 FB |
591 | case OTG_STATE_B_WAIT_ACON: |
592 | case OTG_STATE_B_PERIPHERAL: | |
593 | /* disconnect while suspended? we may | |
594 | * not get a disconnect irq... | |
595 | */ | |
596 | if ((devctl & MUSB_DEVCTL_VBUS) | |
597 | != (3 << MUSB_DEVCTL_VBUS_SHIFT) | |
598 | ) { | |
599 | musb->int_usb |= MUSB_INTR_DISCONNECT; | |
600 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
601 | break; | |
602 | } | |
603 | musb_g_resume(musb); | |
604 | break; | |
605 | case OTG_STATE_B_IDLE: | |
606 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
607 | break; | |
550a7375 FB |
608 | default: |
609 | WARNING("bogus %s RESUME (%s)\n", | |
610 | "peripheral", | |
e47d9254 | 611 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 FB |
612 | } |
613 | } | |
614 | } | |
615 | ||
550a7375 FB |
616 | /* see manual for the order of the tests */ |
617 | if (int_usb & MUSB_INTR_SESSREQ) { | |
aa471456 FB |
618 | void __iomem *mbase = musb->mregs; |
619 | ||
19aab56c HK |
620 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS |
621 | && (devctl & MUSB_DEVCTL_BDEVICE)) { | |
5c8a86e1 | 622 | dev_dbg(musb->controller, "SessReq while on B state\n"); |
a6038ee7 HK |
623 | return IRQ_HANDLED; |
624 | } | |
625 | ||
5c8a86e1 | 626 | dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", |
e47d9254 | 627 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 FB |
628 | |
629 | /* IRQ arrives from ID pin sense or (later, if VBUS power | |
630 | * is removed) SRP. responses are time critical: | |
631 | * - turn on VBUS (with silicon-specific mechanism) | |
632 | * - go through A_WAIT_VRISE | |
633 | * - ... to A_WAIT_BCON. | |
634 | * a_wait_vrise_tmout triggers VBUS_ERROR transitions | |
635 | */ | |
636 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
637 | musb->ep0_stage = MUSB_EP0_START; | |
e47d9254 | 638 | musb->xceiv->otg->state = OTG_STATE_A_IDLE; |
550a7375 | 639 | MUSB_HST_MODE(musb); |
743411b3 | 640 | musb_platform_set_vbus(musb, 1); |
550a7375 FB |
641 | |
642 | handled = IRQ_HANDLED; | |
643 | } | |
644 | ||
645 | if (int_usb & MUSB_INTR_VBUSERROR) { | |
646 | int ignore = 0; | |
647 | ||
648 | /* During connection as an A-Device, we may see a short | |
649 | * current spikes causing voltage drop, because of cable | |
650 | * and peripheral capacitance combined with vbus draw. | |
651 | * (So: less common with truly self-powered devices, where | |
652 | * vbus doesn't act like a power supply.) | |
653 | * | |
654 | * Such spikes are short; usually less than ~500 usec, max | |
655 | * of ~2 msec. That is, they're not sustained overcurrent | |
656 | * errors, though they're reported using VBUSERROR irqs. | |
657 | * | |
658 | * Workarounds: (a) hardware: use self powered devices. | |
659 | * (b) software: ignore non-repeated VBUS errors. | |
660 | * | |
661 | * REVISIT: do delays from lots of DEBUG_KERNEL checks | |
662 | * make trouble here, keeping VBUS < 4.4V ? | |
663 | */ | |
e47d9254 | 664 | switch (musb->xceiv->otg->state) { |
550a7375 FB |
665 | case OTG_STATE_A_HOST: |
666 | /* recovery is dicey once we've gotten past the | |
667 | * initial stages of enumeration, but if VBUS | |
668 | * stayed ok at the other end of the link, and | |
669 | * another reset is due (at least for high speed, | |
670 | * to redo the chirp etc), it might work OK... | |
671 | */ | |
672 | case OTG_STATE_A_WAIT_BCON: | |
673 | case OTG_STATE_A_WAIT_VRISE: | |
674 | if (musb->vbuserr_retry) { | |
aa471456 FB |
675 | void __iomem *mbase = musb->mregs; |
676 | ||
550a7375 FB |
677 | musb->vbuserr_retry--; |
678 | ignore = 1; | |
679 | devctl |= MUSB_DEVCTL_SESSION; | |
680 | musb_writeb(mbase, MUSB_DEVCTL, devctl); | |
681 | } else { | |
682 | musb->port1_status |= | |
749da5f8 AS |
683 | USB_PORT_STAT_OVERCURRENT |
684 | | (USB_PORT_STAT_C_OVERCURRENT << 16); | |
550a7375 FB |
685 | } |
686 | break; | |
687 | default: | |
688 | break; | |
689 | } | |
690 | ||
54485116 GI |
691 | dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller, |
692 | "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", | |
e47d9254 | 693 | usb_otg_state_string(musb->xceiv->otg->state), |
550a7375 FB |
694 | devctl, |
695 | ({ char *s; | |
696 | switch (devctl & MUSB_DEVCTL_VBUS) { | |
697 | case 0 << MUSB_DEVCTL_VBUS_SHIFT: | |
698 | s = "<SessEnd"; break; | |
699 | case 1 << MUSB_DEVCTL_VBUS_SHIFT: | |
700 | s = "<AValid"; break; | |
701 | case 2 << MUSB_DEVCTL_VBUS_SHIFT: | |
702 | s = "<VBusValid"; break; | |
703 | /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ | |
704 | default: | |
705 | s = "VALID"; break; | |
2b84f92b | 706 | } s; }), |
550a7375 FB |
707 | VBUSERR_RETRY_COUNT - musb->vbuserr_retry, |
708 | musb->port1_status); | |
709 | ||
710 | /* go through A_WAIT_VFALL then start a new session */ | |
711 | if (!ignore) | |
743411b3 | 712 | musb_platform_set_vbus(musb, 0); |
550a7375 FB |
713 | handled = IRQ_HANDLED; |
714 | } | |
715 | ||
1c25fda4 | 716 | if (int_usb & MUSB_INTR_SUSPEND) { |
b11e94d0 | 717 | dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n", |
e47d9254 | 718 | usb_otg_state_string(musb->xceiv->otg->state), devctl); |
1c25fda4 AM |
719 | handled = IRQ_HANDLED; |
720 | ||
e47d9254 | 721 | switch (musb->xceiv->otg->state) { |
1c25fda4 AM |
722 | case OTG_STATE_A_PERIPHERAL: |
723 | /* We also come here if the cable is removed, since | |
724 | * this silicon doesn't report ID-no-longer-grounded. | |
725 | * | |
726 | * We depend on T(a_wait_bcon) to shut us down, and | |
727 | * hope users don't do anything dicey during this | |
728 | * undesired detour through A_WAIT_BCON. | |
729 | */ | |
730 | musb_hnp_stop(musb); | |
0b3eba44 | 731 | musb_host_resume_root_hub(musb); |
1c25fda4 AM |
732 | musb_root_disconnect(musb); |
733 | musb_platform_try_idle(musb, jiffies | |
734 | + msecs_to_jiffies(musb->a_wait_bcon | |
735 | ? : OTG_TIME_A_WAIT_BCON)); | |
736 | ||
737 | break; | |
1c25fda4 AM |
738 | case OTG_STATE_B_IDLE: |
739 | if (!musb->is_active) | |
740 | break; | |
741 | case OTG_STATE_B_PERIPHERAL: | |
742 | musb_g_suspend(musb); | |
eee3f15d | 743 | musb->is_active = musb->g.b_hnp_enable; |
1c25fda4 | 744 | if (musb->is_active) { |
e47d9254 | 745 | musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON; |
5c8a86e1 | 746 | dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); |
1c25fda4 AM |
747 | mod_timer(&musb->otg_timer, jiffies |
748 | + msecs_to_jiffies( | |
749 | OTG_TIME_B_ASE0_BRST)); | |
1c25fda4 AM |
750 | } |
751 | break; | |
752 | case OTG_STATE_A_WAIT_BCON: | |
753 | if (musb->a_wait_bcon != 0) | |
754 | musb_platform_try_idle(musb, jiffies | |
755 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
756 | break; | |
757 | case OTG_STATE_A_HOST: | |
e47d9254 | 758 | musb->xceiv->otg->state = OTG_STATE_A_SUSPEND; |
eee3f15d | 759 | musb->is_active = musb->hcd->self.b_hnp_enable; |
1c25fda4 AM |
760 | break; |
761 | case OTG_STATE_B_HOST: | |
762 | /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ | |
5c8a86e1 | 763 | dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); |
1c25fda4 AM |
764 | break; |
765 | default: | |
766 | /* "should not happen" */ | |
767 | musb->is_active = 0; | |
768 | break; | |
769 | } | |
770 | } | |
771 | ||
550a7375 | 772 | if (int_usb & MUSB_INTR_CONNECT) { |
8b125df5 | 773 | struct usb_hcd *hcd = musb->hcd; |
550a7375 FB |
774 | |
775 | handled = IRQ_HANDLED; | |
776 | musb->is_active = 1; | |
550a7375 FB |
777 | |
778 | musb->ep0_stage = MUSB_EP0_START; | |
779 | ||
b18d26f6 SAS |
780 | musb->intrtxe = musb->epmask; |
781 | musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe); | |
af5ec14d SAS |
782 | musb->intrrxe = musb->epmask & 0xfffe; |
783 | musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe); | |
d709d22e | 784 | musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); |
550a7375 FB |
785 | musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED |
786 | |USB_PORT_STAT_HIGH_SPEED | |
787 | |USB_PORT_STAT_ENABLE | |
788 | ); | |
789 | musb->port1_status |= USB_PORT_STAT_CONNECTION | |
790 | |(USB_PORT_STAT_C_CONNECTION << 16); | |
791 | ||
792 | /* high vs full speed is just a guess until after reset */ | |
793 | if (devctl & MUSB_DEVCTL_LSDEV) | |
794 | musb->port1_status |= USB_PORT_STAT_LOW_SPEED; | |
795 | ||
550a7375 | 796 | /* indicate new connection to OTG machine */ |
e47d9254 | 797 | switch (musb->xceiv->otg->state) { |
550a7375 FB |
798 | case OTG_STATE_B_PERIPHERAL: |
799 | if (int_usb & MUSB_INTR_SUSPEND) { | |
5c8a86e1 | 800 | dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); |
550a7375 | 801 | int_usb &= ~MUSB_INTR_SUSPEND; |
1de00dae | 802 | goto b_host; |
550a7375 | 803 | } else |
5c8a86e1 | 804 | dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); |
550a7375 FB |
805 | break; |
806 | case OTG_STATE_B_WAIT_ACON: | |
5c8a86e1 | 807 | dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); |
1de00dae | 808 | b_host: |
e47d9254 | 809 | musb->xceiv->otg->state = OTG_STATE_B_HOST; |
74c2e936 DM |
810 | if (musb->hcd) |
811 | musb->hcd->self.is_b_host = 1; | |
1de00dae | 812 | del_timer(&musb->otg_timer); |
550a7375 FB |
813 | break; |
814 | default: | |
815 | if ((devctl & MUSB_DEVCTL_VBUS) | |
816 | == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { | |
e47d9254 | 817 | musb->xceiv->otg->state = OTG_STATE_A_HOST; |
0b3eba44 DM |
818 | if (hcd) |
819 | hcd->self.is_b_host = 0; | |
550a7375 FB |
820 | } |
821 | break; | |
822 | } | |
1de00dae | 823 | |
0b3eba44 | 824 | musb_host_poke_root_hub(musb); |
1de00dae | 825 | |
5c8a86e1 | 826 | dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", |
e47d9254 | 827 | usb_otg_state_string(musb->xceiv->otg->state), devctl); |
550a7375 | 828 | } |
550a7375 | 829 | |
6d349671 | 830 | if (int_usb & MUSB_INTR_DISCONNECT) { |
5c8a86e1 | 831 | dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", |
e47d9254 | 832 | usb_otg_state_string(musb->xceiv->otg->state), |
1c25fda4 AM |
833 | MUSB_MODE(musb), devctl); |
834 | handled = IRQ_HANDLED; | |
835 | ||
e47d9254 | 836 | switch (musb->xceiv->otg->state) { |
1c25fda4 AM |
837 | case OTG_STATE_A_HOST: |
838 | case OTG_STATE_A_SUSPEND: | |
0b3eba44 | 839 | musb_host_resume_root_hub(musb); |
1c25fda4 | 840 | musb_root_disconnect(musb); |
032ec49f | 841 | if (musb->a_wait_bcon != 0) |
1c25fda4 AM |
842 | musb_platform_try_idle(musb, jiffies |
843 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
844 | break; | |
1c25fda4 AM |
845 | case OTG_STATE_B_HOST: |
846 | /* REVISIT this behaves for "real disconnect" | |
847 | * cases; make sure the other transitions from | |
848 | * from B_HOST act right too. The B_HOST code | |
849 | * in hnp_stop() is currently not used... | |
850 | */ | |
851 | musb_root_disconnect(musb); | |
74c2e936 DM |
852 | if (musb->hcd) |
853 | musb->hcd->self.is_b_host = 0; | |
e47d9254 | 854 | musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; |
1c25fda4 AM |
855 | MUSB_DEV_MODE(musb); |
856 | musb_g_disconnect(musb); | |
857 | break; | |
858 | case OTG_STATE_A_PERIPHERAL: | |
859 | musb_hnp_stop(musb); | |
860 | musb_root_disconnect(musb); | |
861 | /* FALLTHROUGH */ | |
862 | case OTG_STATE_B_WAIT_ACON: | |
863 | /* FALLTHROUGH */ | |
1c25fda4 AM |
864 | case OTG_STATE_B_PERIPHERAL: |
865 | case OTG_STATE_B_IDLE: | |
866 | musb_g_disconnect(musb); | |
867 | break; | |
1c25fda4 AM |
868 | default: |
869 | WARNING("unhandled DISCONNECT transition (%s)\n", | |
e47d9254 | 870 | usb_otg_state_string(musb->xceiv->otg->state)); |
1c25fda4 AM |
871 | break; |
872 | } | |
873 | } | |
874 | ||
550a7375 FB |
875 | /* mentor saves a bit: bus reset and babble share the same irq. |
876 | * only host sees babble; only peripheral sees bus reset. | |
877 | */ | |
878 | if (int_usb & MUSB_INTR_RESET) { | |
1c25fda4 | 879 | handled = IRQ_HANDLED; |
896f7ea3 | 880 | if (devctl & MUSB_DEVCTL_HM) { |
550a7375 | 881 | /* |
34754dec | 882 | * When BABBLE happens what we can depends on which |
28378d5e FB |
883 | * platform MUSB is running, because some platforms |
884 | * implemented proprietary means for 'recovering' from | |
885 | * Babble conditions. One such platform is AM335x. In | |
34754dec FB |
886 | * most cases, however, the only thing we can do is |
887 | * drop the session. | |
550a7375 | 888 | */ |
34754dec | 889 | dev_err(musb->controller, "Babble\n"); |
d0fc0a20 | 890 | |
34754dec FB |
891 | if (is_host_active(musb)) |
892 | musb_recover_from_babble(musb); | |
a04d46d0 | 893 | } else { |
5c8a86e1 | 894 | dev_dbg(musb->controller, "BUS RESET as %s\n", |
e47d9254 AT |
895 | usb_otg_state_string(musb->xceiv->otg->state)); |
896 | switch (musb->xceiv->otg->state) { | |
550a7375 | 897 | case OTG_STATE_A_SUSPEND: |
550a7375 FB |
898 | musb_g_reset(musb); |
899 | /* FALLTHROUGH */ | |
900 | case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ | |
f7f9d63e | 901 | /* never use invalid T(a_wait_bcon) */ |
5c8a86e1 | 902 | dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", |
e47d9254 | 903 | usb_otg_state_string(musb->xceiv->otg->state), |
3df00453 | 904 | TA_WAIT_BCON(musb)); |
f7f9d63e DB |
905 | mod_timer(&musb->otg_timer, jiffies |
906 | + msecs_to_jiffies(TA_WAIT_BCON(musb))); | |
550a7375 FB |
907 | break; |
908 | case OTG_STATE_A_PERIPHERAL: | |
1de00dae DB |
909 | del_timer(&musb->otg_timer); |
910 | musb_g_reset(musb); | |
550a7375 FB |
911 | break; |
912 | case OTG_STATE_B_WAIT_ACON: | |
5c8a86e1 | 913 | dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", |
e47d9254 AT |
914 | usb_otg_state_string(musb->xceiv->otg->state)); |
915 | musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; | |
550a7375 FB |
916 | musb_g_reset(musb); |
917 | break; | |
550a7375 | 918 | case OTG_STATE_B_IDLE: |
e47d9254 | 919 | musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
920 | /* FALLTHROUGH */ |
921 | case OTG_STATE_B_PERIPHERAL: | |
922 | musb_g_reset(musb); | |
923 | break; | |
924 | default: | |
5c8a86e1 | 925 | dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", |
e47d9254 | 926 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 FB |
927 | } |
928 | } | |
550a7375 | 929 | } |
550a7375 FB |
930 | |
931 | #if 0 | |
932 | /* REVISIT ... this would be for multiplexing periodic endpoints, or | |
933 | * supporting transfer phasing to prevent exceeding ISO bandwidth | |
934 | * limits of a given frame or microframe. | |
935 | * | |
936 | * It's not needed for peripheral side, which dedicates endpoints; | |
937 | * though it _might_ use SOF irqs for other purposes. | |
938 | * | |
939 | * And it's not currently needed for host side, which also dedicates | |
940 | * endpoints, relies on TX/RX interval registers, and isn't claimed | |
941 | * to support ISO transfers yet. | |
942 | */ | |
943 | if (int_usb & MUSB_INTR_SOF) { | |
944 | void __iomem *mbase = musb->mregs; | |
945 | struct musb_hw_ep *ep; | |
946 | u8 epnum; | |
947 | u16 frame; | |
948 | ||
5c8a86e1 | 949 | dev_dbg(musb->controller, "START_OF_FRAME\n"); |
550a7375 FB |
950 | handled = IRQ_HANDLED; |
951 | ||
952 | /* start any periodic Tx transfers waiting for current frame */ | |
953 | frame = musb_readw(mbase, MUSB_FRAME); | |
954 | ep = musb->endpoints; | |
955 | for (epnum = 1; (epnum < musb->nr_endpoints) | |
956 | && (musb->epmask >= (1 << epnum)); | |
957 | epnum++, ep++) { | |
958 | /* | |
959 | * FIXME handle framecounter wraps (12 bits) | |
960 | * eliminate duplicated StartUrb logic | |
961 | */ | |
962 | if (ep->dwWaitFrame >= frame) { | |
963 | ep->dwWaitFrame = 0; | |
964 | pr_debug("SOF --> periodic TX%s on %d\n", | |
965 | ep->tx_channel ? " DMA" : "", | |
966 | epnum); | |
967 | if (!ep->tx_channel) | |
968 | musb_h_tx_start(musb, epnum); | |
969 | else | |
970 | cppi_hostdma_start(musb, epnum); | |
971 | } | |
972 | } /* end of for loop */ | |
973 | } | |
974 | #endif | |
975 | ||
1c25fda4 | 976 | schedule_work(&musb->irq_work); |
550a7375 FB |
977 | |
978 | return handled; | |
979 | } | |
980 | ||
981 | /*-------------------------------------------------------------------------*/ | |
982 | ||
e1eb3eb8 | 983 | static void musb_disable_interrupts(struct musb *musb) |
550a7375 FB |
984 | { |
985 | void __iomem *mbase = musb->mregs; | |
986 | u16 temp; | |
987 | ||
988 | /* disable interrupts */ | |
989 | musb_writeb(mbase, MUSB_INTRUSBE, 0); | |
b18d26f6 | 990 | musb->intrtxe = 0; |
550a7375 | 991 | musb_writew(mbase, MUSB_INTRTXE, 0); |
af5ec14d | 992 | musb->intrrxe = 0; |
550a7375 FB |
993 | musb_writew(mbase, MUSB_INTRRXE, 0); |
994 | ||
550a7375 FB |
995 | /* flush pending interrupts */ |
996 | temp = musb_readb(mbase, MUSB_INTRUSB); | |
997 | temp = musb_readw(mbase, MUSB_INTRTX); | |
998 | temp = musb_readw(mbase, MUSB_INTRRX); | |
e1eb3eb8 FB |
999 | } |
1000 | ||
1001 | static void musb_enable_interrupts(struct musb *musb) | |
1002 | { | |
1003 | void __iomem *regs = musb->mregs; | |
1004 | ||
1005 | /* Set INT enable registers, enable interrupts */ | |
1006 | musb->intrtxe = musb->epmask; | |
1007 | musb_writew(regs, MUSB_INTRTXE, musb->intrtxe); | |
1008 | musb->intrrxe = musb->epmask & 0xfffe; | |
1009 | musb_writew(regs, MUSB_INTRRXE, musb->intrrxe); | |
1010 | musb_writeb(regs, MUSB_INTRUSBE, 0xf7); | |
550a7375 FB |
1011 | |
1012 | } | |
1013 | ||
e1eb3eb8 FB |
1014 | static void musb_generic_disable(struct musb *musb) |
1015 | { | |
1016 | void __iomem *mbase = musb->mregs; | |
1017 | ||
1018 | musb_disable_interrupts(musb); | |
1019 | ||
1020 | /* off */ | |
1021 | musb_writeb(mbase, MUSB_DEVCTL, 0); | |
1022 | } | |
1023 | ||
001dd84a SAS |
1024 | /* |
1025 | * Program the HDRC to start (enable interrupts, dma, etc.). | |
1026 | */ | |
1027 | void musb_start(struct musb *musb) | |
1028 | { | |
1029 | void __iomem *regs = musb->mregs; | |
1030 | u8 devctl = musb_readb(regs, MUSB_DEVCTL); | |
1031 | ||
1032 | dev_dbg(musb->controller, "<== devctl %02x\n", devctl); | |
1033 | ||
e1eb3eb8 | 1034 | musb_enable_interrupts(musb); |
001dd84a SAS |
1035 | musb_writeb(regs, MUSB_TESTMODE, 0); |
1036 | ||
1037 | /* put into basic highspeed mode and start session */ | |
1038 | musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE | |
1039 | | MUSB_POWER_HSENAB | |
1040 | /* ENSUSPEND wedges tusb */ | |
1041 | /* | MUSB_POWER_ENSUSPEND */ | |
1042 | ); | |
1043 | ||
1044 | musb->is_active = 0; | |
1045 | devctl = musb_readb(regs, MUSB_DEVCTL); | |
1046 | devctl &= ~MUSB_DEVCTL_SESSION; | |
1047 | ||
1048 | /* session started after: | |
1049 | * (a) ID-grounded irq, host mode; | |
1050 | * (b) vbus present/connect IRQ, peripheral mode; | |
1051 | * (c) peripheral initiates, using SRP | |
1052 | */ | |
1053 | if (musb->port_mode != MUSB_PORT_MODE_HOST && | |
40af177e | 1054 | musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON && |
001dd84a SAS |
1055 | (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) { |
1056 | musb->is_active = 1; | |
1057 | } else { | |
1058 | devctl |= MUSB_DEVCTL_SESSION; | |
1059 | } | |
1060 | ||
1061 | musb_platform_enable(musb); | |
1062 | musb_writeb(regs, MUSB_DEVCTL, devctl); | |
1063 | } | |
1064 | ||
550a7375 FB |
1065 | /* |
1066 | * Make the HDRC stop (disable interrupts, etc.); | |
1067 | * reversible by musb_start | |
1068 | * called on gadget driver unregister | |
1069 | * with controller locked, irqs blocked | |
1070 | * acts as a NOP unless some role activated the hardware | |
1071 | */ | |
1072 | void musb_stop(struct musb *musb) | |
1073 | { | |
1074 | /* stop IRQs, timers, ... */ | |
1075 | musb_platform_disable(musb); | |
1076 | musb_generic_disable(musb); | |
5c8a86e1 | 1077 | dev_dbg(musb->controller, "HDRC disabled\n"); |
550a7375 FB |
1078 | |
1079 | /* FIXME | |
1080 | * - mark host and/or peripheral drivers unusable/inactive | |
1081 | * - disable DMA (and enable it in HdrcStart) | |
1082 | * - make sure we can musb_start() after musb_stop(); with | |
1083 | * OTG mode, gadget driver module rmmod/modprobe cycles that | |
1084 | * - ... | |
1085 | */ | |
1086 | musb_platform_try_idle(musb, 0); | |
1087 | } | |
1088 | ||
1089 | static void musb_shutdown(struct platform_device *pdev) | |
1090 | { | |
1091 | struct musb *musb = dev_to_musb(&pdev->dev); | |
1092 | unsigned long flags; | |
1093 | ||
4f9edd2d | 1094 | pm_runtime_get_sync(musb->controller); |
24307cae | 1095 | |
2cc65fea | 1096 | musb_host_cleanup(musb); |
24307cae GI |
1097 | musb_gadget_cleanup(musb); |
1098 | ||
550a7375 FB |
1099 | spin_lock_irqsave(&musb->lock, flags); |
1100 | musb_platform_disable(musb); | |
1101 | musb_generic_disable(musb); | |
550a7375 FB |
1102 | spin_unlock_irqrestore(&musb->lock, flags); |
1103 | ||
120d074c GI |
1104 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); |
1105 | musb_platform_exit(musb); | |
120d074c | 1106 | |
4f9edd2d | 1107 | pm_runtime_put(musb->controller); |
550a7375 FB |
1108 | /* FIXME power down */ |
1109 | } | |
1110 | ||
1111 | ||
1112 | /*-------------------------------------------------------------------------*/ | |
1113 | ||
1114 | /* | |
1115 | * The silicon either has hard-wired endpoint configurations, or else | |
1116 | * "dynamic fifo" sizing. The driver has support for both, though at this | |
c767c1c6 DB |
1117 | * writing only the dynamic sizing is very well tested. Since we switched |
1118 | * away from compile-time hardware parameters, we can no longer rely on | |
1119 | * dead code elimination to leave only the relevant one in the object file. | |
550a7375 FB |
1120 | * |
1121 | * We don't currently use dynamic fifo setup capability to do anything | |
1122 | * more than selecting one of a bunch of predefined configurations. | |
1123 | */ | |
8a77f05a | 1124 | static ushort fifo_mode; |
550a7375 FB |
1125 | |
1126 | /* "modprobe ... fifo_mode=1" etc */ | |
1127 | module_param(fifo_mode, ushort, 0); | |
1128 | MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); | |
1129 | ||
550a7375 FB |
1130 | /* |
1131 | * tables defining fifo_mode values. define more if you like. | |
1132 | * for host side, make sure both halves of ep1 are set up. | |
1133 | */ | |
1134 | ||
1135 | /* mode 0 - fits in 2KB */ | |
d3608b6d | 1136 | static struct musb_fifo_cfg mode_0_cfg[] = { |
550a7375 FB |
1137 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1138 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1139 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1140 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1141 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1142 | }; | |
1143 | ||
1144 | /* mode 1 - fits in 4KB */ | |
d3608b6d | 1145 | static struct musb_fifo_cfg mode_1_cfg[] = { |
550a7375 FB |
1146 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
1147 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1148 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1149 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1150 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1151 | }; | |
1152 | ||
1153 | /* mode 2 - fits in 4KB */ | |
d3608b6d | 1154 | static struct musb_fifo_cfg mode_2_cfg[] = { |
550a7375 FB |
1155 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1156 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1157 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1158 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1159 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1160 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1161 | }; | |
1162 | ||
1163 | /* mode 3 - fits in 4KB */ | |
d3608b6d | 1164 | static struct musb_fifo_cfg mode_3_cfg[] = { |
550a7375 FB |
1165 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
1166 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1167 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1168 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1169 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1170 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1171 | }; | |
1172 | ||
1173 | /* mode 4 - fits in 16KB */ | |
d3608b6d | 1174 | static struct musb_fifo_cfg mode_4_cfg[] = { |
550a7375 FB |
1175 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1176 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1177 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1178 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1179 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1180 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1181 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1182 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1183 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1184 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1185 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, | |
1186 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, | |
1187 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, | |
1188 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, | |
1189 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, | |
1190 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, | |
1191 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, | |
1192 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, | |
a483d706 AKG |
1193 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, |
1194 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, | |
1195 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, | |
1196 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, | |
1197 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, | |
1198 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, | |
1199 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, | |
550a7375 FB |
1200 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, |
1201 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1202 | }; | |
1203 | ||
3b151526 | 1204 | /* mode 5 - fits in 8KB */ |
d3608b6d | 1205 | static struct musb_fifo_cfg mode_5_cfg[] = { |
3b151526 AKG |
1206 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1207 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1208 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1209 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1210 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1211 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1212 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1213 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1214 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1215 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1216 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, | |
1217 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, | |
1218 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, | |
1219 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, | |
1220 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, | |
1221 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, | |
1222 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, | |
1223 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, | |
1224 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, | |
1225 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, | |
1226 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, | |
1227 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, | |
1228 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, | |
1229 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, | |
1230 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1231 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1232 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1233 | }; | |
550a7375 FB |
1234 | |
1235 | /* | |
1236 | * configure a fifo; for non-shared endpoints, this may be called | |
1237 | * once for a tx fifo and once for an rx fifo. | |
1238 | * | |
1239 | * returns negative errno or offset for next fifo. | |
1240 | */ | |
41ac7b3a | 1241 | static int |
550a7375 | 1242 | fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, |
e6c213b2 | 1243 | const struct musb_fifo_cfg *cfg, u16 offset) |
550a7375 FB |
1244 | { |
1245 | void __iomem *mbase = musb->mregs; | |
1246 | int size = 0; | |
1247 | u16 maxpacket = cfg->maxpacket; | |
1248 | u16 c_off = offset >> 3; | |
1249 | u8 c_size; | |
1250 | ||
1251 | /* expect hw_ep has already been zero-initialized */ | |
1252 | ||
1253 | size = ffs(max(maxpacket, (u16) 8)) - 1; | |
1254 | maxpacket = 1 << size; | |
1255 | ||
1256 | c_size = size - 3; | |
1257 | if (cfg->mode == BUF_DOUBLE) { | |
ca6d1b13 FB |
1258 | if ((offset + (maxpacket << 1)) > |
1259 | (1 << (musb->config->ram_bits + 2))) | |
550a7375 FB |
1260 | return -EMSGSIZE; |
1261 | c_size |= MUSB_FIFOSZ_DPB; | |
1262 | } else { | |
ca6d1b13 | 1263 | if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) |
550a7375 FB |
1264 | return -EMSGSIZE; |
1265 | } | |
1266 | ||
1267 | /* configure the FIFO */ | |
1268 | musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); | |
1269 | ||
550a7375 | 1270 | /* EP0 reserved endpoint for control, bidirectional; |
5ae477b0 | 1271 | * EP1 reserved for bulk, two unidirectional halves. |
550a7375 FB |
1272 | */ |
1273 | if (hw_ep->epnum == 1) | |
1274 | musb->bulk_ep = hw_ep; | |
1275 | /* REVISIT error check: be sure ep0 can both rx and tx ... */ | |
550a7375 FB |
1276 | switch (cfg->style) { |
1277 | case FIFO_TX: | |
c6cf8b00 BW |
1278 | musb_write_txfifosz(mbase, c_size); |
1279 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1280 | hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1281 | hw_ep->max_packet_sz_tx = maxpacket; | |
1282 | break; | |
1283 | case FIFO_RX: | |
c6cf8b00 BW |
1284 | musb_write_rxfifosz(mbase, c_size); |
1285 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1286 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1287 | hw_ep->max_packet_sz_rx = maxpacket; | |
1288 | break; | |
1289 | case FIFO_RXTX: | |
c6cf8b00 BW |
1290 | musb_write_txfifosz(mbase, c_size); |
1291 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1292 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1293 | hw_ep->max_packet_sz_rx = maxpacket; | |
1294 | ||
c6cf8b00 BW |
1295 | musb_write_rxfifosz(mbase, c_size); |
1296 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1297 | hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; |
1298 | hw_ep->max_packet_sz_tx = maxpacket; | |
1299 | ||
1300 | hw_ep->is_shared_fifo = true; | |
1301 | break; | |
1302 | } | |
1303 | ||
1304 | /* NOTE rx and tx endpoint irqs aren't managed separately, | |
1305 | * which happens to be ok | |
1306 | */ | |
1307 | musb->epmask |= (1 << hw_ep->epnum); | |
1308 | ||
1309 | return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); | |
1310 | } | |
1311 | ||
d3608b6d | 1312 | static struct musb_fifo_cfg ep0_cfg = { |
550a7375 FB |
1313 | .style = FIFO_RXTX, .maxpacket = 64, |
1314 | }; | |
1315 | ||
41ac7b3a | 1316 | static int ep_config_from_table(struct musb *musb) |
550a7375 | 1317 | { |
e6c213b2 | 1318 | const struct musb_fifo_cfg *cfg; |
550a7375 FB |
1319 | unsigned i, n; |
1320 | int offset; | |
1321 | struct musb_hw_ep *hw_ep = musb->endpoints; | |
1322 | ||
e6c213b2 FB |
1323 | if (musb->config->fifo_cfg) { |
1324 | cfg = musb->config->fifo_cfg; | |
1325 | n = musb->config->fifo_cfg_size; | |
1326 | goto done; | |
1327 | } | |
1328 | ||
550a7375 FB |
1329 | switch (fifo_mode) { |
1330 | default: | |
1331 | fifo_mode = 0; | |
1332 | /* FALLTHROUGH */ | |
1333 | case 0: | |
1334 | cfg = mode_0_cfg; | |
1335 | n = ARRAY_SIZE(mode_0_cfg); | |
1336 | break; | |
1337 | case 1: | |
1338 | cfg = mode_1_cfg; | |
1339 | n = ARRAY_SIZE(mode_1_cfg); | |
1340 | break; | |
1341 | case 2: | |
1342 | cfg = mode_2_cfg; | |
1343 | n = ARRAY_SIZE(mode_2_cfg); | |
1344 | break; | |
1345 | case 3: | |
1346 | cfg = mode_3_cfg; | |
1347 | n = ARRAY_SIZE(mode_3_cfg); | |
1348 | break; | |
1349 | case 4: | |
1350 | cfg = mode_4_cfg; | |
1351 | n = ARRAY_SIZE(mode_4_cfg); | |
1352 | break; | |
3b151526 AKG |
1353 | case 5: |
1354 | cfg = mode_5_cfg; | |
1355 | n = ARRAY_SIZE(mode_5_cfg); | |
1356 | break; | |
550a7375 FB |
1357 | } |
1358 | ||
1359 | printk(KERN_DEBUG "%s: setup fifo_mode %d\n", | |
1360 | musb_driver_name, fifo_mode); | |
1361 | ||
1362 | ||
e6c213b2 | 1363 | done: |
550a7375 FB |
1364 | offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); |
1365 | /* assert(offset > 0) */ | |
1366 | ||
1367 | /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would | |
ca6d1b13 | 1368 | * be better than static musb->config->num_eps and DYN_FIFO_SIZE... |
550a7375 FB |
1369 | */ |
1370 | ||
1371 | for (i = 0; i < n; i++) { | |
1372 | u8 epn = cfg->hw_ep_num; | |
1373 | ||
ca6d1b13 | 1374 | if (epn >= musb->config->num_eps) { |
550a7375 FB |
1375 | pr_debug("%s: invalid ep %d\n", |
1376 | musb_driver_name, epn); | |
bb1c9ef1 | 1377 | return -EINVAL; |
550a7375 FB |
1378 | } |
1379 | offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); | |
1380 | if (offset < 0) { | |
1381 | pr_debug("%s: mem overrun, ep %d\n", | |
1382 | musb_driver_name, epn); | |
f69dfa1f | 1383 | return offset; |
550a7375 FB |
1384 | } |
1385 | epn++; | |
1386 | musb->nr_endpoints = max(epn, musb->nr_endpoints); | |
1387 | } | |
1388 | ||
1389 | printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", | |
1390 | musb_driver_name, | |
ca6d1b13 FB |
1391 | n + 1, musb->config->num_eps * 2 - 1, |
1392 | offset, (1 << (musb->config->ram_bits + 2))); | |
550a7375 | 1393 | |
550a7375 FB |
1394 | if (!musb->bulk_ep) { |
1395 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1396 | return -EINVAL; | |
1397 | } | |
550a7375 FB |
1398 | |
1399 | return 0; | |
1400 | } | |
1401 | ||
1402 | ||
1403 | /* | |
1404 | * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false | |
1405 | * @param musb the controller | |
1406 | */ | |
41ac7b3a | 1407 | static int ep_config_from_hw(struct musb *musb) |
550a7375 | 1408 | { |
c6cf8b00 | 1409 | u8 epnum = 0; |
550a7375 | 1410 | struct musb_hw_ep *hw_ep; |
a156544b | 1411 | void __iomem *mbase = musb->mregs; |
c6cf8b00 | 1412 | int ret = 0; |
550a7375 | 1413 | |
5c8a86e1 | 1414 | dev_dbg(musb->controller, "<== static silicon ep config\n"); |
550a7375 FB |
1415 | |
1416 | /* FIXME pick up ep0 maxpacket size */ | |
1417 | ||
ca6d1b13 | 1418 | for (epnum = 1; epnum < musb->config->num_eps; epnum++) { |
550a7375 FB |
1419 | musb_ep_select(mbase, epnum); |
1420 | hw_ep = musb->endpoints + epnum; | |
1421 | ||
c6cf8b00 BW |
1422 | ret = musb_read_fifosize(musb, hw_ep, epnum); |
1423 | if (ret < 0) | |
550a7375 | 1424 | break; |
550a7375 FB |
1425 | |
1426 | /* FIXME set up hw_ep->{rx,tx}_double_buffered */ | |
1427 | ||
550a7375 FB |
1428 | /* pick an RX/TX endpoint for bulk */ |
1429 | if (hw_ep->max_packet_sz_tx < 512 | |
1430 | || hw_ep->max_packet_sz_rx < 512) | |
1431 | continue; | |
1432 | ||
1433 | /* REVISIT: this algorithm is lazy, we should at least | |
1434 | * try to pick a double buffered endpoint. | |
1435 | */ | |
1436 | if (musb->bulk_ep) | |
1437 | continue; | |
1438 | musb->bulk_ep = hw_ep; | |
550a7375 FB |
1439 | } |
1440 | ||
550a7375 FB |
1441 | if (!musb->bulk_ep) { |
1442 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1443 | return -EINVAL; | |
1444 | } | |
550a7375 FB |
1445 | |
1446 | return 0; | |
1447 | } | |
1448 | ||
1449 | enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; | |
1450 | ||
1451 | /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; | |
1452 | * configure endpoints, or take their config from silicon | |
1453 | */ | |
41ac7b3a | 1454 | static int musb_core_init(u16 musb_type, struct musb *musb) |
550a7375 | 1455 | { |
550a7375 FB |
1456 | u8 reg; |
1457 | char *type; | |
0ea52ff4 | 1458 | char aInfo[90], aRevision[32], aDate[12]; |
550a7375 FB |
1459 | void __iomem *mbase = musb->mregs; |
1460 | int status = 0; | |
1461 | int i; | |
1462 | ||
1463 | /* log core options (read using indexed model) */ | |
c6cf8b00 | 1464 | reg = musb_read_configdata(mbase); |
550a7375 FB |
1465 | |
1466 | strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); | |
51bf0d0e | 1467 | if (reg & MUSB_CONFIGDATA_DYNFIFO) { |
550a7375 | 1468 | strcat(aInfo, ", dyn FIFOs"); |
51bf0d0e AKG |
1469 | musb->dyn_fifo = true; |
1470 | } | |
550a7375 FB |
1471 | if (reg & MUSB_CONFIGDATA_MPRXE) { |
1472 | strcat(aInfo, ", bulk combine"); | |
550a7375 | 1473 | musb->bulk_combine = true; |
550a7375 FB |
1474 | } |
1475 | if (reg & MUSB_CONFIGDATA_MPTXE) { | |
1476 | strcat(aInfo, ", bulk split"); | |
550a7375 | 1477 | musb->bulk_split = true; |
550a7375 FB |
1478 | } |
1479 | if (reg & MUSB_CONFIGDATA_HBRXE) { | |
1480 | strcat(aInfo, ", HB-ISO Rx"); | |
a483d706 | 1481 | musb->hb_iso_rx = true; |
550a7375 FB |
1482 | } |
1483 | if (reg & MUSB_CONFIGDATA_HBTXE) { | |
1484 | strcat(aInfo, ", HB-ISO Tx"); | |
a483d706 | 1485 | musb->hb_iso_tx = true; |
550a7375 FB |
1486 | } |
1487 | if (reg & MUSB_CONFIGDATA_SOFTCONE) | |
1488 | strcat(aInfo, ", SoftConn"); | |
1489 | ||
1490 | printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", | |
1491 | musb_driver_name, reg, aInfo); | |
1492 | ||
550a7375 | 1493 | aDate[0] = 0; |
550a7375 FB |
1494 | if (MUSB_CONTROLLER_MHDRC == musb_type) { |
1495 | musb->is_multipoint = 1; | |
1496 | type = "M"; | |
1497 | } else { | |
1498 | musb->is_multipoint = 0; | |
1499 | type = ""; | |
550a7375 FB |
1500 | #ifndef CONFIG_USB_OTG_BLACKLIST_HUB |
1501 | printk(KERN_ERR | |
1502 | "%s: kernel must blacklist external hubs\n", | |
1503 | musb_driver_name); | |
550a7375 FB |
1504 | #endif |
1505 | } | |
1506 | ||
1507 | /* log release info */ | |
32c3b94e AG |
1508 | musb->hwvers = musb_read_hwvers(mbase); |
1509 | snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), | |
1510 | MUSB_HWVERS_MINOR(musb->hwvers), | |
1511 | (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); | |
550a7375 FB |
1512 | printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", |
1513 | musb_driver_name, type, aRevision, aDate); | |
1514 | ||
1515 | /* configure ep0 */ | |
c6cf8b00 | 1516 | musb_configure_ep0(musb); |
550a7375 FB |
1517 | |
1518 | /* discover endpoint configuration */ | |
1519 | musb->nr_endpoints = 1; | |
1520 | musb->epmask = 1; | |
1521 | ||
ad517e9e FB |
1522 | if (musb->dyn_fifo) |
1523 | status = ep_config_from_table(musb); | |
1524 | else | |
1525 | status = ep_config_from_hw(musb); | |
550a7375 FB |
1526 | |
1527 | if (status < 0) | |
1528 | return status; | |
1529 | ||
1530 | /* finish init, and print endpoint config */ | |
1531 | for (i = 0; i < musb->nr_endpoints; i++) { | |
1532 | struct musb_hw_ep *hw_ep = musb->endpoints + i; | |
1533 | ||
1b40fc57 | 1534 | hw_ep->fifo = musb->io.fifo_offset(i) + mbase; |
ebf39920 | 1535 | #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010) |
1b40fc57 TL |
1536 | if (musb->io.quirks & MUSB_IN_TUSB) { |
1537 | hw_ep->fifo_async = musb->async + 0x400 + | |
1538 | musb->io.fifo_offset(i); | |
1539 | hw_ep->fifo_sync = musb->sync + 0x400 + | |
1540 | musb->io.fifo_offset(i); | |
1541 | hw_ep->fifo_sync_va = | |
1542 | musb->sync_va + 0x400 + musb->io.fifo_offset(i); | |
1543 | ||
1544 | if (i == 0) | |
1545 | hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; | |
1546 | else | |
1547 | hw_ep->conf = mbase + 0x400 + | |
1548 | (((i - 1) & 0xf) << 2); | |
1549 | } | |
550a7375 FB |
1550 | #endif |
1551 | ||
d026e9c7 | 1552 | hw_ep->regs = musb->io.ep_offset(i, 0) + mbase; |
550a7375 FB |
1553 | hw_ep->rx_reinit = 1; |
1554 | hw_ep->tx_reinit = 1; | |
550a7375 FB |
1555 | |
1556 | if (hw_ep->max_packet_sz_tx) { | |
5c8a86e1 | 1557 | dev_dbg(musb->controller, |
550a7375 FB |
1558 | "%s: hw_ep %d%s, %smax %d\n", |
1559 | musb_driver_name, i, | |
1560 | hw_ep->is_shared_fifo ? "shared" : "tx", | |
1561 | hw_ep->tx_double_buffered | |
1562 | ? "doublebuffer, " : "", | |
1563 | hw_ep->max_packet_sz_tx); | |
1564 | } | |
1565 | if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { | |
5c8a86e1 | 1566 | dev_dbg(musb->controller, |
550a7375 FB |
1567 | "%s: hw_ep %d%s, %smax %d\n", |
1568 | musb_driver_name, i, | |
1569 | "rx", | |
1570 | hw_ep->rx_double_buffered | |
1571 | ? "doublebuffer, " : "", | |
1572 | hw_ep->max_packet_sz_rx); | |
1573 | } | |
1574 | if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) | |
5c8a86e1 | 1575 | dev_dbg(musb->controller, "hw_ep %d not configured\n", i); |
550a7375 FB |
1576 | } |
1577 | ||
1578 | return 0; | |
1579 | } | |
1580 | ||
1581 | /*-------------------------------------------------------------------------*/ | |
1582 | ||
550a7375 FB |
1583 | /* |
1584 | * handle all the irqs defined by the HDRC core. for now we expect: other | |
1585 | * irq sources (phy, dma, etc) will be handled first, musb->int_* values | |
1586 | * will be assigned, and the irq will already have been acked. | |
1587 | * | |
1588 | * called in irq context with spinlock held, irqs blocked | |
1589 | */ | |
1590 | irqreturn_t musb_interrupt(struct musb *musb) | |
1591 | { | |
1592 | irqreturn_t retval = IRQ_NONE; | |
31a0ede0 FB |
1593 | unsigned long status; |
1594 | unsigned long epnum; | |
b11e94d0 | 1595 | u8 devctl; |
31a0ede0 FB |
1596 | |
1597 | if (!musb->int_usb && !musb->int_tx && !musb->int_rx) | |
1598 | return IRQ_NONE; | |
550a7375 FB |
1599 | |
1600 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
550a7375 | 1601 | |
5c8a86e1 | 1602 | dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", |
c03da38d | 1603 | is_host_active(musb) ? "host" : "peripheral", |
550a7375 FB |
1604 | musb->int_usb, musb->int_tx, musb->int_rx); |
1605 | ||
e3c93e1a FB |
1606 | /** |
1607 | * According to Mentor Graphics' documentation, flowchart on page 98, | |
1608 | * IRQ should be handled as follows: | |
1609 | * | |
1610 | * . Resume IRQ | |
1611 | * . Session Request IRQ | |
1612 | * . VBUS Error IRQ | |
1613 | * . Suspend IRQ | |
1614 | * . Connect IRQ | |
1615 | * . Disconnect IRQ | |
1616 | * . Reset/Babble IRQ | |
1617 | * . SOF IRQ (we're not using this one) | |
1618 | * . Endpoint 0 IRQ | |
1619 | * . TX Endpoints | |
1620 | * . RX Endpoints | |
1621 | * | |
1622 | * We will be following that flowchart in order to avoid any problems | |
1623 | * that might arise with internal Finite State Machine. | |
550a7375 | 1624 | */ |
e3c93e1a | 1625 | |
7d9645fd | 1626 | if (musb->int_usb) |
31a0ede0 | 1627 | retval |= musb_stage0_irq(musb, musb->int_usb, devctl); |
550a7375 | 1628 | |
550a7375 | 1629 | if (musb->int_tx & 1) { |
c03da38d | 1630 | if (is_host_active(musb)) |
550a7375 FB |
1631 | retval |= musb_h_ep0_irq(musb); |
1632 | else | |
1633 | retval |= musb_g_ep0_irq(musb); | |
31a0ede0 FB |
1634 | |
1635 | /* we have just handled endpoint 0 IRQ, clear it */ | |
1636 | musb->int_tx &= ~BIT(0); | |
550a7375 FB |
1637 | } |
1638 | ||
31a0ede0 FB |
1639 | status = musb->int_tx; |
1640 | ||
1641 | for_each_set_bit(epnum, &status, 16) { | |
1642 | retval = IRQ_HANDLED; | |
1643 | if (is_host_active(musb)) | |
1644 | musb_host_tx(musb, epnum); | |
1645 | else | |
1646 | musb_g_tx(musb, epnum); | |
550a7375 FB |
1647 | } |
1648 | ||
31a0ede0 | 1649 | status = musb->int_rx; |
e3c93e1a | 1650 | |
31a0ede0 FB |
1651 | for_each_set_bit(epnum, &status, 16) { |
1652 | retval = IRQ_HANDLED; | |
1653 | if (is_host_active(musb)) | |
1654 | musb_host_rx(musb, epnum); | |
1655 | else | |
1656 | musb_g_rx(musb, epnum); | |
550a7375 FB |
1657 | } |
1658 | ||
550a7375 FB |
1659 | return retval; |
1660 | } | |
981430a1 | 1661 | EXPORT_SYMBOL_GPL(musb_interrupt); |
550a7375 FB |
1662 | |
1663 | #ifndef CONFIG_MUSB_PIO_ONLY | |
d3608b6d | 1664 | static bool use_dma = 1; |
550a7375 FB |
1665 | |
1666 | /* "modprobe ... use_dma=0" etc */ | |
1667 | module_param(use_dma, bool, 0); | |
1668 | MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); | |
1669 | ||
1670 | void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) | |
1671 | { | |
550a7375 FB |
1672 | /* called with controller lock already held */ |
1673 | ||
1674 | if (!epnum) { | |
f8e9f34f | 1675 | if (!is_cppi_enabled(musb)) { |
550a7375 | 1676 | /* endpoint 0 */ |
c03da38d | 1677 | if (is_host_active(musb)) |
550a7375 FB |
1678 | musb_h_ep0_irq(musb); |
1679 | else | |
1680 | musb_g_ep0_irq(musb); | |
1681 | } | |
550a7375 FB |
1682 | } else { |
1683 | /* endpoints 1..15 */ | |
1684 | if (transmit) { | |
c03da38d | 1685 | if (is_host_active(musb)) |
a04d46d0 FB |
1686 | musb_host_tx(musb, epnum); |
1687 | else | |
1688 | musb_g_tx(musb, epnum); | |
550a7375 FB |
1689 | } else { |
1690 | /* receive */ | |
c03da38d | 1691 | if (is_host_active(musb)) |
a04d46d0 FB |
1692 | musb_host_rx(musb, epnum); |
1693 | else | |
1694 | musb_g_rx(musb, epnum); | |
550a7375 FB |
1695 | } |
1696 | } | |
1697 | } | |
9a35f876 | 1698 | EXPORT_SYMBOL_GPL(musb_dma_completion); |
550a7375 FB |
1699 | |
1700 | #else | |
1701 | #define use_dma 0 | |
1702 | #endif | |
1703 | ||
1704 | /*-------------------------------------------------------------------------*/ | |
1705 | ||
550a7375 FB |
1706 | static ssize_t |
1707 | musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1708 | { | |
1709 | struct musb *musb = dev_to_musb(dev); | |
1710 | unsigned long flags; | |
1711 | int ret = -EINVAL; | |
1712 | ||
1713 | spin_lock_irqsave(&musb->lock, flags); | |
e47d9254 | 1714 | ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 FB |
1715 | spin_unlock_irqrestore(&musb->lock, flags); |
1716 | ||
1717 | return ret; | |
1718 | } | |
1719 | ||
1720 | static ssize_t | |
1721 | musb_mode_store(struct device *dev, struct device_attribute *attr, | |
1722 | const char *buf, size_t n) | |
1723 | { | |
1724 | struct musb *musb = dev_to_musb(dev); | |
1725 | unsigned long flags; | |
96a274d1 | 1726 | int status; |
550a7375 FB |
1727 | |
1728 | spin_lock_irqsave(&musb->lock, flags); | |
96a274d1 DB |
1729 | if (sysfs_streq(buf, "host")) |
1730 | status = musb_platform_set_mode(musb, MUSB_HOST); | |
1731 | else if (sysfs_streq(buf, "peripheral")) | |
1732 | status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); | |
1733 | else if (sysfs_streq(buf, "otg")) | |
1734 | status = musb_platform_set_mode(musb, MUSB_OTG); | |
1735 | else | |
1736 | status = -EINVAL; | |
550a7375 FB |
1737 | spin_unlock_irqrestore(&musb->lock, flags); |
1738 | ||
96a274d1 | 1739 | return (status == 0) ? n : status; |
550a7375 FB |
1740 | } |
1741 | static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); | |
1742 | ||
1743 | static ssize_t | |
1744 | musb_vbus_store(struct device *dev, struct device_attribute *attr, | |
1745 | const char *buf, size_t n) | |
1746 | { | |
1747 | struct musb *musb = dev_to_musb(dev); | |
1748 | unsigned long flags; | |
1749 | unsigned long val; | |
1750 | ||
1751 | if (sscanf(buf, "%lu", &val) < 1) { | |
b3b1cc3b | 1752 | dev_err(dev, "Invalid VBUS timeout ms value\n"); |
550a7375 FB |
1753 | return -EINVAL; |
1754 | } | |
1755 | ||
1756 | spin_lock_irqsave(&musb->lock, flags); | |
f7f9d63e DB |
1757 | /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ |
1758 | musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; | |
e47d9254 | 1759 | if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON) |
550a7375 FB |
1760 | musb->is_active = 0; |
1761 | musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); | |
1762 | spin_unlock_irqrestore(&musb->lock, flags); | |
1763 | ||
1764 | return n; | |
1765 | } | |
1766 | ||
1767 | static ssize_t | |
1768 | musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1769 | { | |
1770 | struct musb *musb = dev_to_musb(dev); | |
1771 | unsigned long flags; | |
1772 | unsigned long val; | |
1773 | int vbus; | |
1774 | ||
1775 | spin_lock_irqsave(&musb->lock, flags); | |
1776 | val = musb->a_wait_bcon; | |
f7f9d63e DB |
1777 | /* FIXME get_vbus_status() is normally #defined as false... |
1778 | * and is effectively TUSB-specific. | |
1779 | */ | |
550a7375 FB |
1780 | vbus = musb_platform_get_vbus_status(musb); |
1781 | spin_unlock_irqrestore(&musb->lock, flags); | |
1782 | ||
f7f9d63e | 1783 | return sprintf(buf, "Vbus %s, timeout %lu msec\n", |
550a7375 FB |
1784 | vbus ? "on" : "off", val); |
1785 | } | |
1786 | static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); | |
1787 | ||
550a7375 FB |
1788 | /* Gadget drivers can't know that a host is connected so they might want |
1789 | * to start SRP, but users can. This allows userspace to trigger SRP. | |
1790 | */ | |
1791 | static ssize_t | |
1792 | musb_srp_store(struct device *dev, struct device_attribute *attr, | |
1793 | const char *buf, size_t n) | |
1794 | { | |
1795 | struct musb *musb = dev_to_musb(dev); | |
1796 | unsigned short srp; | |
1797 | ||
1798 | if (sscanf(buf, "%hu", &srp) != 1 | |
1799 | || (srp != 1)) { | |
b3b1cc3b | 1800 | dev_err(dev, "SRP: Value must be 1\n"); |
550a7375 FB |
1801 | return -EINVAL; |
1802 | } | |
1803 | ||
1804 | if (srp == 1) | |
1805 | musb_g_wakeup(musb); | |
1806 | ||
1807 | return n; | |
1808 | } | |
1809 | static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); | |
1810 | ||
94375751 FB |
1811 | static struct attribute *musb_attributes[] = { |
1812 | &dev_attr_mode.attr, | |
1813 | &dev_attr_vbus.attr, | |
94375751 | 1814 | &dev_attr_srp.attr, |
94375751 FB |
1815 | NULL |
1816 | }; | |
1817 | ||
1818 | static const struct attribute_group musb_attr_group = { | |
1819 | .attrs = musb_attributes, | |
1820 | }; | |
1821 | ||
550a7375 FB |
1822 | /* Only used to provide driver mode change events */ |
1823 | static void musb_irq_work(struct work_struct *data) | |
1824 | { | |
1825 | struct musb *musb = container_of(data, struct musb, irq_work); | |
550a7375 | 1826 | |
e47d9254 AT |
1827 | if (musb->xceiv->otg->state != musb->xceiv_old_state) { |
1828 | musb->xceiv_old_state = musb->xceiv->otg->state; | |
550a7375 FB |
1829 | sysfs_notify(&musb->controller->kobj, NULL, "mode"); |
1830 | } | |
1831 | } | |
1832 | ||
83b8f5b8 | 1833 | static void musb_recover_from_babble(struct musb *musb) |
ca88fc2e | 1834 | { |
b4dc38fd FB |
1835 | int ret; |
1836 | u8 devctl; | |
ca88fc2e | 1837 | |
0244336f FB |
1838 | musb_disable_interrupts(musb); |
1839 | ||
83b8f5b8 FB |
1840 | /* |
1841 | * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give | |
1842 | * it some slack and wait for 10us. | |
1843 | */ | |
1844 | udelay(10); | |
1845 | ||
b28a6432 | 1846 | ret = musb_platform_recover(musb); |
ba7ee8bb FB |
1847 | if (ret) { |
1848 | musb_enable_interrupts(musb); | |
d871c622 | 1849 | return; |
ba7ee8bb | 1850 | } |
ca88fc2e | 1851 | |
b4dc38fd FB |
1852 | /* drop session bit */ |
1853 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1854 | devctl &= ~MUSB_DEVCTL_SESSION; | |
1855 | musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); | |
ca88fc2e | 1856 | |
b4dc38fd FB |
1857 | /* tell usbcore about it */ |
1858 | musb_root_disconnect(musb); | |
ca88fc2e DM |
1859 | |
1860 | /* | |
d871c622 GC |
1861 | * When a babble condition occurs, the musb controller |
1862 | * removes the session bit and the endpoint config is lost. | |
ca88fc2e DM |
1863 | */ |
1864 | if (musb->dyn_fifo) | |
b4dc38fd | 1865 | ret = ep_config_from_table(musb); |
ca88fc2e | 1866 | else |
b4dc38fd | 1867 | ret = ep_config_from_hw(musb); |
ca88fc2e | 1868 | |
b4dc38fd FB |
1869 | /* restart session */ |
1870 | if (ret == 0) | |
ca88fc2e DM |
1871 | musb_start(musb); |
1872 | } | |
1873 | ||
550a7375 FB |
1874 | /* -------------------------------------------------------------------------- |
1875 | * Init support | |
1876 | */ | |
1877 | ||
41ac7b3a | 1878 | static struct musb *allocate_instance(struct device *dev, |
ca6d1b13 | 1879 | struct musb_hdrc_config *config, void __iomem *mbase) |
550a7375 FB |
1880 | { |
1881 | struct musb *musb; | |
1882 | struct musb_hw_ep *ep; | |
1883 | int epnum; | |
74c2e936 | 1884 | int ret; |
550a7375 | 1885 | |
74c2e936 DM |
1886 | musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL); |
1887 | if (!musb) | |
550a7375 | 1888 | return NULL; |
550a7375 | 1889 | |
550a7375 FB |
1890 | INIT_LIST_HEAD(&musb->control); |
1891 | INIT_LIST_HEAD(&musb->in_bulk); | |
1892 | INIT_LIST_HEAD(&musb->out_bulk); | |
1893 | ||
550a7375 | 1894 | musb->vbuserr_retry = VBUSERR_RETRY_COUNT; |
f7f9d63e | 1895 | musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; |
550a7375 FB |
1896 | musb->mregs = mbase; |
1897 | musb->ctrl_base = mbase; | |
1898 | musb->nIrq = -ENODEV; | |
ca6d1b13 | 1899 | musb->config = config; |
02582b92 | 1900 | BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); |
550a7375 | 1901 | for (epnum = 0, ep = musb->endpoints; |
ca6d1b13 | 1902 | epnum < musb->config->num_eps; |
550a7375 | 1903 | epnum++, ep++) { |
550a7375 FB |
1904 | ep->musb = musb; |
1905 | ep->epnum = epnum; | |
1906 | } | |
1907 | ||
1908 | musb->controller = dev; | |
743411b3 | 1909 | |
74c2e936 DM |
1910 | ret = musb_host_alloc(musb); |
1911 | if (ret < 0) | |
1912 | goto err_free; | |
1913 | ||
1914 | dev_set_drvdata(dev, musb); | |
1915 | ||
550a7375 | 1916 | return musb; |
74c2e936 DM |
1917 | |
1918 | err_free: | |
1919 | return NULL; | |
550a7375 FB |
1920 | } |
1921 | ||
1922 | static void musb_free(struct musb *musb) | |
1923 | { | |
1924 | /* this has multiple entry modes. it handles fault cleanup after | |
1925 | * probe(), where things may be partially set up, as well as rmmod | |
1926 | * cleanup after everything's been de-activated. | |
1927 | */ | |
1928 | ||
1929 | #ifdef CONFIG_SYSFS | |
94375751 | 1930 | sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); |
550a7375 FB |
1931 | #endif |
1932 | ||
97a39896 AKG |
1933 | if (musb->nIrq >= 0) { |
1934 | if (musb->irq_wake) | |
1935 | disable_irq_wake(musb->nIrq); | |
550a7375 FB |
1936 | free_irq(musb->nIrq, musb); |
1937 | } | |
550a7375 | 1938 | |
74c2e936 | 1939 | musb_host_free(musb); |
550a7375 FB |
1940 | } |
1941 | ||
8ed1fb79 DM |
1942 | static void musb_deassert_reset(struct work_struct *work) |
1943 | { | |
1944 | struct musb *musb; | |
1945 | unsigned long flags; | |
1946 | ||
1947 | musb = container_of(work, struct musb, deassert_reset_work.work); | |
1948 | ||
1949 | spin_lock_irqsave(&musb->lock, flags); | |
1950 | ||
1951 | if (musb->port1_status & USB_PORT_STAT_RESET) | |
1952 | musb_port_reset(musb, false); | |
1953 | ||
1954 | spin_unlock_irqrestore(&musb->lock, flags); | |
1955 | } | |
1956 | ||
550a7375 FB |
1957 | /* |
1958 | * Perform generic per-controller initialization. | |
1959 | * | |
28dd924a SS |
1960 | * @dev: the controller (already clocked, etc) |
1961 | * @nIrq: IRQ number | |
1962 | * @ctrl: virtual address of controller registers, | |
550a7375 FB |
1963 | * not yet corrected for platform-specific offsets |
1964 | */ | |
41ac7b3a | 1965 | static int |
550a7375 FB |
1966 | musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) |
1967 | { | |
1968 | int status; | |
1969 | struct musb *musb; | |
c1a7d67c | 1970 | struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); |
550a7375 FB |
1971 | |
1972 | /* The driver might handle more features than the board; OK. | |
1973 | * Fail when the board needs a feature that's not enabled. | |
1974 | */ | |
1975 | if (!plat) { | |
1976 | dev_dbg(dev, "no platform_data?\n"); | |
34e2beb2 SS |
1977 | status = -ENODEV; |
1978 | goto fail0; | |
550a7375 | 1979 | } |
34e2beb2 | 1980 | |
550a7375 | 1981 | /* allocate */ |
ca6d1b13 | 1982 | musb = allocate_instance(dev, plat->config, ctrl); |
34e2beb2 SS |
1983 | if (!musb) { |
1984 | status = -ENOMEM; | |
1985 | goto fail0; | |
1986 | } | |
550a7375 FB |
1987 | |
1988 | spin_lock_init(&musb->lock); | |
550a7375 | 1989 | musb->board_set_power = plat->set_power; |
550a7375 | 1990 | musb->min_power = plat->min_power; |
f7ec9437 | 1991 | musb->ops = plat->platform_ops; |
9ad96e69 | 1992 | musb->port_mode = plat->mode; |
550a7375 | 1993 | |
1b40fc57 TL |
1994 | /* |
1995 | * Initialize the default IO functions. At least omap2430 needs | |
1996 | * these early. We initialize the platform specific IO functions | |
1997 | * later on. | |
1998 | */ | |
1999 | musb_readb = musb_default_readb; | |
2000 | musb_writeb = musb_default_writeb; | |
2001 | musb_readw = musb_default_readw; | |
2002 | musb_writew = musb_default_writew; | |
2003 | musb_readl = musb_default_readl; | |
2004 | musb_writel = musb_default_writel; | |
2005 | ||
3e43a072 FB |
2006 | /* We need musb_read/write functions initialized for PM */ |
2007 | pm_runtime_use_autosuspend(musb->controller); | |
2008 | pm_runtime_set_autosuspend_delay(musb->controller, 200); | |
2009 | pm_runtime_irq_safe(musb->controller); | |
2010 | pm_runtime_enable(musb->controller); | |
2011 | ||
84e250ff | 2012 | /* The musb_platform_init() call: |
baef653a PDS |
2013 | * - adjusts musb->mregs |
2014 | * - sets the musb->isr | |
5ae477b0 | 2015 | * - may initialize an integrated transceiver |
721002ec | 2016 | * - initializes musb->xceiv, usually by otg_get_phy() |
84e250ff | 2017 | * - stops powering VBUS |
84e250ff | 2018 | * |
7c9d440e | 2019 | * There are various transceiver configurations. Blackfin, |
84e250ff DB |
2020 | * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses |
2021 | * external/discrete ones in various flavors (twl4030 family, | |
2022 | * isp1504, non-OTG, etc) mostly hooking up through ULPI. | |
550a7375 | 2023 | */ |
ea65df57 | 2024 | status = musb_platform_init(musb); |
550a7375 | 2025 | if (status < 0) |
03491761 | 2026 | goto fail1; |
34e2beb2 | 2027 | |
550a7375 FB |
2028 | if (!musb->isr) { |
2029 | status = -ENODEV; | |
c04352a5 | 2030 | goto fail2; |
550a7375 FB |
2031 | } |
2032 | ||
1b40fc57 TL |
2033 | if (musb->ops->quirks) |
2034 | musb->io.quirks = musb->ops->quirks; | |
2035 | ||
da96cfc1 | 2036 | /* Most devices use indexed offset or flat offset */ |
d026e9c7 TL |
2037 | if (musb->io.quirks & MUSB_INDEXED_EP) { |
2038 | musb->io.ep_offset = musb_indexed_ep_offset; | |
2039 | musb->io.ep_select = musb_indexed_ep_select; | |
2040 | } else { | |
2041 | musb->io.ep_offset = musb_flat_ep_offset; | |
2042 | musb->io.ep_select = musb_flat_ep_select; | |
2043 | } | |
47a82730 HG |
2044 | /* And override them with platform specific ops if specified. */ |
2045 | if (musb->ops->ep_offset) | |
2046 | musb->io.ep_offset = musb->ops->ep_offset; | |
2047 | if (musb->ops->ep_select) | |
2048 | musb->io.ep_select = musb->ops->ep_select; | |
d026e9c7 | 2049 | |
da96cfc1 BH |
2050 | /* At least tusb6010 has its own offsets */ |
2051 | if (musb->ops->ep_offset) | |
2052 | musb->io.ep_offset = musb->ops->ep_offset; | |
2053 | if (musb->ops->ep_select) | |
2054 | musb->io.ep_select = musb->ops->ep_select; | |
2055 | ||
8a77f05a TL |
2056 | if (musb->ops->fifo_mode) |
2057 | fifo_mode = musb->ops->fifo_mode; | |
2058 | else | |
2059 | fifo_mode = 4; | |
2060 | ||
1b40fc57 TL |
2061 | if (musb->ops->fifo_offset) |
2062 | musb->io.fifo_offset = musb->ops->fifo_offset; | |
2063 | else | |
2064 | musb->io.fifo_offset = musb_default_fifo_offset; | |
2065 | ||
6cc2af6d HG |
2066 | if (musb->ops->busctl_offset) |
2067 | musb->io.busctl_offset = musb->ops->busctl_offset; | |
2068 | else | |
2069 | musb->io.busctl_offset = musb_default_busctl_offset; | |
2070 | ||
1b40fc57 TL |
2071 | if (musb->ops->readb) |
2072 | musb_readb = musb->ops->readb; | |
2073 | if (musb->ops->writeb) | |
2074 | musb_writeb = musb->ops->writeb; | |
2075 | if (musb->ops->readw) | |
2076 | musb_readw = musb->ops->readw; | |
2077 | if (musb->ops->writew) | |
2078 | musb_writew = musb->ops->writew; | |
2079 | if (musb->ops->readl) | |
2080 | musb_readl = musb->ops->readl; | |
2081 | if (musb->ops->writel) | |
2082 | musb_writel = musb->ops->writel; | |
2083 | ||
7f6283ed TL |
2084 | #ifndef CONFIG_MUSB_PIO_ONLY |
2085 | if (!musb->ops->dma_init || !musb->ops->dma_exit) { | |
2086 | dev_err(dev, "DMA controller not set\n"); | |
2087 | goto fail2; | |
2088 | } | |
2089 | musb_dma_controller_create = musb->ops->dma_init; | |
2090 | musb_dma_controller_destroy = musb->ops->dma_exit; | |
2091 | #endif | |
2092 | ||
1b40fc57 TL |
2093 | if (musb->ops->read_fifo) |
2094 | musb->io.read_fifo = musb->ops->read_fifo; | |
2095 | else | |
2096 | musb->io.read_fifo = musb_default_read_fifo; | |
2097 | ||
2098 | if (musb->ops->write_fifo) | |
2099 | musb->io.write_fifo = musb->ops->write_fifo; | |
2100 | else | |
2101 | musb->io.write_fifo = musb_default_write_fifo; | |
2102 | ||
ffb865b1 | 2103 | if (!musb->xceiv->io_ops) { |
bf070bc1 | 2104 | musb->xceiv->io_dev = musb->controller; |
ffb865b1 HK |
2105 | musb->xceiv->io_priv = musb->mregs; |
2106 | musb->xceiv->io_ops = &musb_ulpi_access; | |
2107 | } | |
2108 | ||
c04352a5 GI |
2109 | pm_runtime_get_sync(musb->controller); |
2110 | ||
48054147 | 2111 | if (use_dma && dev->dma_mask) { |
7f6283ed TL |
2112 | musb->dma_controller = |
2113 | musb_dma_controller_create(musb, musb->mregs); | |
48054147 SAS |
2114 | if (IS_ERR(musb->dma_controller)) { |
2115 | status = PTR_ERR(musb->dma_controller); | |
2116 | goto fail2_5; | |
2117 | } | |
2118 | } | |
550a7375 FB |
2119 | |
2120 | /* be sure interrupts are disabled before connecting ISR */ | |
2121 | musb_platform_disable(musb); | |
2122 | musb_generic_disable(musb); | |
2123 | ||
66fadea5 SAS |
2124 | /* Init IRQ workqueue before request_irq */ |
2125 | INIT_WORK(&musb->irq_work, musb_irq_work); | |
8ed1fb79 DM |
2126 | INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset); |
2127 | INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume); | |
66fadea5 | 2128 | |
550a7375 | 2129 | /* setup musb parts of the core (especially endpoints) */ |
ca6d1b13 | 2130 | status = musb_core_init(plat->config->multipoint |
550a7375 FB |
2131 | ? MUSB_CONTROLLER_MHDRC |
2132 | : MUSB_CONTROLLER_HDRC, musb); | |
2133 | if (status < 0) | |
34e2beb2 | 2134 | goto fail3; |
550a7375 | 2135 | |
f7f9d63e | 2136 | setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); |
f7f9d63e | 2137 | |
550a7375 | 2138 | /* attach to the IRQ */ |
427c4f33 | 2139 | if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { |
550a7375 FB |
2140 | dev_err(dev, "request_irq %d failed!\n", nIrq); |
2141 | status = -ENODEV; | |
34e2beb2 | 2142 | goto fail3; |
550a7375 FB |
2143 | } |
2144 | musb->nIrq = nIrq; | |
032ec49f | 2145 | /* FIXME this handles wakeup irqs wrong */ |
c48a5155 FB |
2146 | if (enable_irq_wake(nIrq) == 0) { |
2147 | musb->irq_wake = 1; | |
550a7375 | 2148 | device_init_wakeup(dev, 1); |
c48a5155 FB |
2149 | } else { |
2150 | musb->irq_wake = 0; | |
2151 | } | |
550a7375 | 2152 | |
032ec49f FB |
2153 | /* program PHY to use external vBus if required */ |
2154 | if (plat->extvbus) { | |
2155 | u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); | |
2156 | busctl |= MUSB_ULPI_USE_EXTVBUS; | |
2157 | musb_write_ulpi_buscontrol(musb->mregs, busctl); | |
550a7375 | 2158 | } |
550a7375 | 2159 | |
e5615112 GI |
2160 | if (musb->xceiv->otg->default_a) { |
2161 | MUSB_HST_MODE(musb); | |
e47d9254 | 2162 | musb->xceiv->otg->state = OTG_STATE_A_IDLE; |
e5615112 GI |
2163 | } else { |
2164 | MUSB_DEV_MODE(musb); | |
e47d9254 | 2165 | musb->xceiv->otg->state = OTG_STATE_B_IDLE; |
e5615112 | 2166 | } |
550a7375 | 2167 | |
6c5f6a6f DM |
2168 | switch (musb->port_mode) { |
2169 | case MUSB_PORT_MODE_HOST: | |
2170 | status = musb_host_setup(musb, plat->power); | |
2df6761e FB |
2171 | if (status < 0) |
2172 | goto fail3; | |
2173 | status = musb_platform_set_mode(musb, MUSB_HOST); | |
6c5f6a6f DM |
2174 | break; |
2175 | case MUSB_PORT_MODE_GADGET: | |
2176 | status = musb_gadget_setup(musb); | |
2df6761e FB |
2177 | if (status < 0) |
2178 | goto fail3; | |
2179 | status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); | |
6c5f6a6f DM |
2180 | break; |
2181 | case MUSB_PORT_MODE_DUAL_ROLE: | |
2182 | status = musb_host_setup(musb, plat->power); | |
2183 | if (status < 0) | |
2184 | goto fail3; | |
2185 | status = musb_gadget_setup(musb); | |
2df6761e | 2186 | if (status) { |
0d2dd7ea | 2187 | musb_host_cleanup(musb); |
2df6761e FB |
2188 | goto fail3; |
2189 | } | |
2190 | status = musb_platform_set_mode(musb, MUSB_OTG); | |
6c5f6a6f DM |
2191 | break; |
2192 | default: | |
2193 | dev_err(dev, "unsupported port mode %d\n", musb->port_mode); | |
2194 | break; | |
2195 | } | |
550a7375 | 2196 | |
461972d8 | 2197 | if (status < 0) |
34e2beb2 | 2198 | goto fail3; |
550a7375 | 2199 | |
7f7f9e2a FB |
2200 | status = musb_init_debugfs(musb); |
2201 | if (status < 0) | |
b0f9da7e | 2202 | goto fail4; |
7f7f9e2a | 2203 | |
94375751 | 2204 | status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); |
28c2c51c | 2205 | if (status) |
b0f9da7e | 2206 | goto fail5; |
550a7375 | 2207 | |
c04352a5 GI |
2208 | pm_runtime_put(musb->controller); |
2209 | ||
28c2c51c | 2210 | return 0; |
550a7375 | 2211 | |
b0f9da7e FB |
2212 | fail5: |
2213 | musb_exit_debugfs(musb); | |
2214 | ||
34e2beb2 | 2215 | fail4: |
032ec49f | 2216 | musb_gadget_cleanup(musb); |
0d2dd7ea | 2217 | musb_host_cleanup(musb); |
34e2beb2 SS |
2218 | |
2219 | fail3: | |
66fadea5 | 2220 | cancel_work_sync(&musb->irq_work); |
8ed1fb79 DM |
2221 | cancel_delayed_work_sync(&musb->finish_resume_work); |
2222 | cancel_delayed_work_sync(&musb->deassert_reset_work); | |
f3ce4d5b | 2223 | if (musb->dma_controller) |
7f6283ed | 2224 | musb_dma_controller_destroy(musb->dma_controller); |
48054147 | 2225 | fail2_5: |
c04352a5 GI |
2226 | pm_runtime_put_sync(musb->controller); |
2227 | ||
2228 | fail2: | |
34e2beb2 SS |
2229 | if (musb->irq_wake) |
2230 | device_init_wakeup(dev, 0); | |
550a7375 | 2231 | musb_platform_exit(musb); |
28c2c51c | 2232 | |
34e2beb2 | 2233 | fail1: |
681d1e87 | 2234 | pm_runtime_disable(musb->controller); |
34e2beb2 SS |
2235 | dev_err(musb->controller, |
2236 | "musb_init_controller failed with status %d\n", status); | |
2237 | ||
28c2c51c FB |
2238 | musb_free(musb); |
2239 | ||
34e2beb2 SS |
2240 | fail0: |
2241 | ||
28c2c51c FB |
2242 | return status; |
2243 | ||
550a7375 FB |
2244 | } |
2245 | ||
2246 | /*-------------------------------------------------------------------------*/ | |
2247 | ||
2248 | /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just | |
2249 | * bridge to a platform device; this driver then suffices. | |
2250 | */ | |
41ac7b3a | 2251 | static int musb_probe(struct platform_device *pdev) |
550a7375 FB |
2252 | { |
2253 | struct device *dev = &pdev->dev; | |
fcf173e4 | 2254 | int irq = platform_get_irq_byname(pdev, "mc"); |
550a7375 FB |
2255 | struct resource *iomem; |
2256 | void __iomem *base; | |
2257 | ||
1f79b26c | 2258 | if (irq <= 0) |
550a7375 FB |
2259 | return -ENODEV; |
2260 | ||
1f79b26c | 2261 | iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
b42f7f30 FB |
2262 | base = devm_ioremap_resource(dev, iomem); |
2263 | if (IS_ERR(base)) | |
2264 | return PTR_ERR(base); | |
550a7375 | 2265 | |
b42f7f30 | 2266 | return musb_init_controller(dev, irq, base); |
550a7375 FB |
2267 | } |
2268 | ||
fb4e98ab | 2269 | static int musb_remove(struct platform_device *pdev) |
550a7375 | 2270 | { |
8d2421e6 AKG |
2271 | struct device *dev = &pdev->dev; |
2272 | struct musb *musb = dev_to_musb(dev); | |
550a7375 FB |
2273 | |
2274 | /* this gets called on rmmod. | |
2275 | * - Host mode: host may still be active | |
2276 | * - Peripheral mode: peripheral is deactivated (or never-activated) | |
2277 | * - OTG mode: both roles are deactivated (or never-activated) | |
2278 | */ | |
7f7f9e2a | 2279 | musb_exit_debugfs(musb); |
550a7375 | 2280 | musb_shutdown(pdev); |
461972d8 | 2281 | |
8d1aad74 | 2282 | if (musb->dma_controller) |
7f6283ed | 2283 | musb_dma_controller_destroy(musb->dma_controller); |
8d1aad74 | 2284 | |
66fadea5 | 2285 | cancel_work_sync(&musb->irq_work); |
8ed1fb79 DM |
2286 | cancel_delayed_work_sync(&musb->finish_resume_work); |
2287 | cancel_delayed_work_sync(&musb->deassert_reset_work); | |
550a7375 | 2288 | musb_free(musb); |
8d2421e6 | 2289 | device_init_wakeup(dev, 0); |
550a7375 FB |
2290 | return 0; |
2291 | } | |
2292 | ||
2293 | #ifdef CONFIG_PM | |
2294 | ||
3c8a5fcc | 2295 | static void musb_save_context(struct musb *musb) |
4f712e01 AKG |
2296 | { |
2297 | int i; | |
2298 | void __iomem *musb_base = musb->mregs; | |
ae9b2ad2 | 2299 | void __iomem *epio; |
4f712e01 | 2300 | |
032ec49f FB |
2301 | musb->context.frame = musb_readw(musb_base, MUSB_FRAME); |
2302 | musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); | |
2303 | musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); | |
7421107b | 2304 | musb->context.power = musb_readb(musb_base, MUSB_POWER); |
7421107b FB |
2305 | musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); |
2306 | musb->context.index = musb_readb(musb_base, MUSB_INDEX); | |
2307 | musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); | |
4f712e01 | 2308 | |
ae9b2ad2 | 2309 | for (i = 0; i < musb->config->num_eps; ++i) { |
e4e5b136 FB |
2310 | struct musb_hw_ep *hw_ep; |
2311 | ||
2312 | hw_ep = &musb->endpoints[i]; | |
2313 | if (!hw_ep) | |
2314 | continue; | |
2315 | ||
2316 | epio = hw_ep->regs; | |
2317 | if (!epio) | |
2318 | continue; | |
2319 | ||
ea737554 | 2320 | musb_writeb(musb_base, MUSB_INDEX, i); |
7421107b | 2321 | musb->context.index_regs[i].txmaxp = |
ae9b2ad2 | 2322 | musb_readw(epio, MUSB_TXMAXP); |
7421107b | 2323 | musb->context.index_regs[i].txcsr = |
ae9b2ad2 | 2324 | musb_readw(epio, MUSB_TXCSR); |
7421107b | 2325 | musb->context.index_regs[i].rxmaxp = |
ae9b2ad2 | 2326 | musb_readw(epio, MUSB_RXMAXP); |
7421107b | 2327 | musb->context.index_regs[i].rxcsr = |
ae9b2ad2 | 2328 | musb_readw(epio, MUSB_RXCSR); |
4f712e01 AKG |
2329 | |
2330 | if (musb->dyn_fifo) { | |
7421107b | 2331 | musb->context.index_regs[i].txfifoadd = |
4f712e01 | 2332 | musb_read_txfifoadd(musb_base); |
7421107b | 2333 | musb->context.index_regs[i].rxfifoadd = |
4f712e01 | 2334 | musb_read_rxfifoadd(musb_base); |
7421107b | 2335 | musb->context.index_regs[i].txfifosz = |
4f712e01 | 2336 | musb_read_txfifosz(musb_base); |
7421107b | 2337 | musb->context.index_regs[i].rxfifosz = |
4f712e01 AKG |
2338 | musb_read_rxfifosz(musb_base); |
2339 | } | |
032ec49f FB |
2340 | |
2341 | musb->context.index_regs[i].txtype = | |
2342 | musb_readb(epio, MUSB_TXTYPE); | |
2343 | musb->context.index_regs[i].txinterval = | |
2344 | musb_readb(epio, MUSB_TXINTERVAL); | |
2345 | musb->context.index_regs[i].rxtype = | |
2346 | musb_readb(epio, MUSB_RXTYPE); | |
2347 | musb->context.index_regs[i].rxinterval = | |
2348 | musb_readb(epio, MUSB_RXINTERVAL); | |
2349 | ||
2350 | musb->context.index_regs[i].txfunaddr = | |
6cc2af6d | 2351 | musb_read_txfunaddr(musb, i); |
032ec49f | 2352 | musb->context.index_regs[i].txhubaddr = |
6cc2af6d | 2353 | musb_read_txhubaddr(musb, i); |
032ec49f | 2354 | musb->context.index_regs[i].txhubport = |
6cc2af6d | 2355 | musb_read_txhubport(musb, i); |
032ec49f FB |
2356 | |
2357 | musb->context.index_regs[i].rxfunaddr = | |
6cc2af6d | 2358 | musb_read_rxfunaddr(musb, i); |
032ec49f | 2359 | musb->context.index_regs[i].rxhubaddr = |
6cc2af6d | 2360 | musb_read_rxhubaddr(musb, i); |
032ec49f | 2361 | musb->context.index_regs[i].rxhubport = |
6cc2af6d | 2362 | musb_read_rxhubport(musb, i); |
4f712e01 | 2363 | } |
4f712e01 AKG |
2364 | } |
2365 | ||
3c8a5fcc | 2366 | static void musb_restore_context(struct musb *musb) |
4f712e01 AKG |
2367 | { |
2368 | int i; | |
2369 | void __iomem *musb_base = musb->mregs; | |
ae9b2ad2 | 2370 | void __iomem *epio; |
33f8d75f | 2371 | u8 power; |
4f712e01 | 2372 | |
032ec49f FB |
2373 | musb_writew(musb_base, MUSB_FRAME, musb->context.frame); |
2374 | musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); | |
2375 | musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); | |
33f8d75f RQ |
2376 | |
2377 | /* Don't affect SUSPENDM/RESUME bits in POWER reg */ | |
2378 | power = musb_readb(musb_base, MUSB_POWER); | |
2379 | power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME; | |
2380 | musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME); | |
2381 | power |= musb->context.power; | |
2382 | musb_writeb(musb_base, MUSB_POWER, power); | |
2383 | ||
b18d26f6 | 2384 | musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe); |
af5ec14d | 2385 | musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe); |
7421107b FB |
2386 | musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); |
2387 | musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); | |
4f712e01 | 2388 | |
ae9b2ad2 | 2389 | for (i = 0; i < musb->config->num_eps; ++i) { |
e4e5b136 FB |
2390 | struct musb_hw_ep *hw_ep; |
2391 | ||
2392 | hw_ep = &musb->endpoints[i]; | |
2393 | if (!hw_ep) | |
2394 | continue; | |
2395 | ||
2396 | epio = hw_ep->regs; | |
2397 | if (!epio) | |
2398 | continue; | |
2399 | ||
ea737554 | 2400 | musb_writeb(musb_base, MUSB_INDEX, i); |
ae9b2ad2 | 2401 | musb_writew(epio, MUSB_TXMAXP, |
7421107b | 2402 | musb->context.index_regs[i].txmaxp); |
ae9b2ad2 | 2403 | musb_writew(epio, MUSB_TXCSR, |
7421107b | 2404 | musb->context.index_regs[i].txcsr); |
ae9b2ad2 | 2405 | musb_writew(epio, MUSB_RXMAXP, |
7421107b | 2406 | musb->context.index_regs[i].rxmaxp); |
ae9b2ad2 | 2407 | musb_writew(epio, MUSB_RXCSR, |
7421107b | 2408 | musb->context.index_regs[i].rxcsr); |
4f712e01 AKG |
2409 | |
2410 | if (musb->dyn_fifo) { | |
2411 | musb_write_txfifosz(musb_base, | |
7421107b | 2412 | musb->context.index_regs[i].txfifosz); |
4f712e01 | 2413 | musb_write_rxfifosz(musb_base, |
7421107b | 2414 | musb->context.index_regs[i].rxfifosz); |
4f712e01 | 2415 | musb_write_txfifoadd(musb_base, |
7421107b | 2416 | musb->context.index_regs[i].txfifoadd); |
4f712e01 | 2417 | musb_write_rxfifoadd(musb_base, |
7421107b | 2418 | musb->context.index_regs[i].rxfifoadd); |
4f712e01 AKG |
2419 | } |
2420 | ||
032ec49f | 2421 | musb_writeb(epio, MUSB_TXTYPE, |
7421107b | 2422 | musb->context.index_regs[i].txtype); |
032ec49f | 2423 | musb_writeb(epio, MUSB_TXINTERVAL, |
7421107b | 2424 | musb->context.index_regs[i].txinterval); |
032ec49f | 2425 | musb_writeb(epio, MUSB_RXTYPE, |
7421107b | 2426 | musb->context.index_regs[i].rxtype); |
032ec49f | 2427 | musb_writeb(epio, MUSB_RXINTERVAL, |
4f712e01 | 2428 | |
032ec49f | 2429 | musb->context.index_regs[i].rxinterval); |
6cc2af6d | 2430 | musb_write_txfunaddr(musb, i, |
7421107b | 2431 | musb->context.index_regs[i].txfunaddr); |
6cc2af6d | 2432 | musb_write_txhubaddr(musb, i, |
7421107b | 2433 | musb->context.index_regs[i].txhubaddr); |
6cc2af6d | 2434 | musb_write_txhubport(musb, i, |
7421107b | 2435 | musb->context.index_regs[i].txhubport); |
4f712e01 | 2436 | |
6cc2af6d | 2437 | musb_write_rxfunaddr(musb, i, |
7421107b | 2438 | musb->context.index_regs[i].rxfunaddr); |
6cc2af6d | 2439 | musb_write_rxhubaddr(musb, i, |
7421107b | 2440 | musb->context.index_regs[i].rxhubaddr); |
6cc2af6d | 2441 | musb_write_rxhubport(musb, i, |
7421107b | 2442 | musb->context.index_regs[i].rxhubport); |
4f712e01 | 2443 | } |
3c5fec75 | 2444 | musb_writeb(musb_base, MUSB_INDEX, musb->context.index); |
4f712e01 AKG |
2445 | } |
2446 | ||
48fea965 | 2447 | static int musb_suspend(struct device *dev) |
550a7375 | 2448 | { |
8220796d | 2449 | struct musb *musb = dev_to_musb(dev); |
550a7375 | 2450 | unsigned long flags; |
550a7375 | 2451 | |
6fc6f4b8 PH |
2452 | musb_platform_disable(musb); |
2453 | musb_generic_disable(musb); | |
2454 | ||
550a7375 FB |
2455 | spin_lock_irqsave(&musb->lock, flags); |
2456 | ||
2457 | if (is_peripheral_active(musb)) { | |
2458 | /* FIXME force disconnect unless we know USB will wake | |
2459 | * the system up quickly enough to respond ... | |
2460 | */ | |
2461 | } else if (is_host_active(musb)) { | |
2462 | /* we know all the children are suspended; sometimes | |
2463 | * they will even be wakeup-enabled. | |
2464 | */ | |
2465 | } | |
2466 | ||
c338412b DM |
2467 | musb_save_context(musb); |
2468 | ||
550a7375 FB |
2469 | spin_unlock_irqrestore(&musb->lock, flags); |
2470 | return 0; | |
2471 | } | |
2472 | ||
3e87d9a3 | 2473 | static int musb_resume(struct device *dev) |
550a7375 | 2474 | { |
c338412b | 2475 | struct musb *musb = dev_to_musb(dev); |
b87fd2f7 SAS |
2476 | u8 devctl; |
2477 | u8 mask; | |
c338412b DM |
2478 | |
2479 | /* | |
2480 | * For static cmos like DaVinci, register values were preserved | |
0ec8fd70 KK |
2481 | * unless for some reason the whole soc powered down or the USB |
2482 | * module got reset through the PSC (vs just being disabled). | |
c338412b DM |
2483 | * |
2484 | * For the DSPS glue layer though, a full register restore has to | |
2485 | * be done. As it shouldn't harm other platforms, we do it | |
2486 | * unconditionally. | |
550a7375 | 2487 | */ |
c338412b DM |
2488 | |
2489 | musb_restore_context(musb); | |
2490 | ||
b87fd2f7 SAS |
2491 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); |
2492 | mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV; | |
2493 | if ((devctl & mask) != (musb->context.devctl & mask)) | |
2494 | musb->port1_status = 0; | |
baadd52f SAS |
2495 | if (musb->need_finish_resume) { |
2496 | musb->need_finish_resume = 0; | |
2497 | schedule_delayed_work(&musb->finish_resume_work, | |
309be239 | 2498 | msecs_to_jiffies(USB_RESUME_TIMEOUT)); |
baadd52f | 2499 | } |
a1fc1920 SAS |
2500 | |
2501 | /* | |
2502 | * The USB HUB code expects the device to be in RPM_ACTIVE once it came | |
2503 | * out of suspend | |
2504 | */ | |
2505 | pm_runtime_disable(dev); | |
2506 | pm_runtime_set_active(dev); | |
2507 | pm_runtime_enable(dev); | |
6fc6f4b8 PH |
2508 | |
2509 | musb_start(musb); | |
2510 | ||
550a7375 FB |
2511 | return 0; |
2512 | } | |
2513 | ||
7acc6197 HH |
2514 | static int musb_runtime_suspend(struct device *dev) |
2515 | { | |
2516 | struct musb *musb = dev_to_musb(dev); | |
2517 | ||
2518 | musb_save_context(musb); | |
2519 | ||
2520 | return 0; | |
2521 | } | |
2522 | ||
2523 | static int musb_runtime_resume(struct device *dev) | |
2524 | { | |
2525 | struct musb *musb = dev_to_musb(dev); | |
2526 | static int first = 1; | |
2527 | ||
2528 | /* | |
2529 | * When pm_runtime_get_sync called for the first time in driver | |
2530 | * init, some of the structure is still not initialized which is | |
2531 | * used in restore function. But clock needs to be | |
2532 | * enabled before any register access, so | |
2533 | * pm_runtime_get_sync has to be called. | |
2534 | * Also context restore without save does not make | |
2535 | * any sense | |
2536 | */ | |
2537 | if (!first) | |
2538 | musb_restore_context(musb); | |
2539 | first = 0; | |
2540 | ||
9298b4aa BL |
2541 | if (musb->need_finish_resume) { |
2542 | musb->need_finish_resume = 0; | |
2543 | schedule_delayed_work(&musb->finish_resume_work, | |
309be239 | 2544 | msecs_to_jiffies(USB_RESUME_TIMEOUT)); |
9298b4aa BL |
2545 | } |
2546 | ||
7acc6197 HH |
2547 | return 0; |
2548 | } | |
2549 | ||
47145210 | 2550 | static const struct dev_pm_ops musb_dev_pm_ops = { |
48fea965 | 2551 | .suspend = musb_suspend, |
3e87d9a3 | 2552 | .resume = musb_resume, |
7acc6197 HH |
2553 | .runtime_suspend = musb_runtime_suspend, |
2554 | .runtime_resume = musb_runtime_resume, | |
48fea965 MD |
2555 | }; |
2556 | ||
2557 | #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) | |
550a7375 | 2558 | #else |
48fea965 | 2559 | #define MUSB_DEV_PM_OPS NULL |
550a7375 FB |
2560 | #endif |
2561 | ||
2562 | static struct platform_driver musb_driver = { | |
2563 | .driver = { | |
2564 | .name = (char *)musb_driver_name, | |
2565 | .bus = &platform_bus_type, | |
48fea965 | 2566 | .pm = MUSB_DEV_PM_OPS, |
550a7375 | 2567 | }, |
e9e8c85e | 2568 | .probe = musb_probe, |
7690417d | 2569 | .remove = musb_remove, |
550a7375 | 2570 | .shutdown = musb_shutdown, |
550a7375 FB |
2571 | }; |
2572 | ||
89f836a8 | 2573 | module_platform_driver(musb_driver); |