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USB: Add MUSB and TUSB support
[deliverable/linux.git] / drivers / usb / musb / musb_core.c
CommitLineData
550a7375
FB		 1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - <asm/arch/hdrc_cnf.h> for SOC or family details
86 * - platform_device for addressing, irq, and platform_data
87 * - platform_data is mostly for board-specific informarion
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
96#include <linux/init.h>
97#include <linux/list.h>
98#include <linux/kobject.h>
99#include <linux/platform_device.h>
100#include <linux/io.h>
101
102#ifdef CONFIG_ARM
103#include <asm/arch/hardware.h>
104#include <asm/arch/memory.h>
105#include <asm/mach-types.h>
106#endif
107
108#include "musb_core.h"
109
110
111#ifdef CONFIG_ARCH_DAVINCI
112#include "davinci.h"
113#endif
114
115
116
117#if MUSB_DEBUG > 0
118unsigned debug = MUSB_DEBUG;
119module_param(debug, uint, 0);
120MODULE_PARM_DESC(debug, "initial debug message level");
121
122#define MUSB_VERSION_SUFFIX "/dbg"
123#endif
124
125#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
126#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
127
128#define MUSB_VERSION_BASE "6.0"
129
130#ifndef MUSB_VERSION_SUFFIX
131#define MUSB_VERSION_SUFFIX ""
132#endif
133#define MUSB_VERSION MUSB_VERSION_BASE MUSB_VERSION_SUFFIX
134
135#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
136
137#define MUSB_DRIVER_NAME "musb_hdrc"
138const char musb_driver_name[] = MUSB_DRIVER_NAME;
139
140MODULE_DESCRIPTION(DRIVER_INFO);
141MODULE_AUTHOR(DRIVER_AUTHOR);
142MODULE_LICENSE("GPL");
143MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
144
145
146/*-------------------------------------------------------------------------*/
147
148static inline struct musb *dev_to_musb(struct device *dev)
149{
150#ifdef CONFIG_USB_MUSB_HDRC_HCD
151 /* usbcore insists dev->driver_data is a "struct hcd *" */
152 return hcd_to_musb(dev_get_drvdata(dev));
153#else
154 return dev_get_drvdata(dev);
155#endif
156}
157
158/*-------------------------------------------------------------------------*/
159
160#ifndef CONFIG_USB_TUSB6010
161/*
162 * Load an endpoint's FIFO
163 */
164void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
165{
166 void __iomem *fifo = hw_ep->fifo;
167
168 prefetch((u8 *)src);
169
170 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
171 'T', hw_ep->epnum, fifo, len, src);
172
173 /* we can't assume unaligned reads work */
174 if (likely((0x01 & (unsigned long) src) == 0)) {
175 u16 index = 0;
176
177 /* best case is 32bit-aligned source address */
178 if ((0x02 & (unsigned long) src) == 0) {
179 if (len >= 4) {
180 writesl(fifo, src + index, len >> 2);
181 index += len & ~0x03;
182 }
183 if (len & 0x02) {
184 musb_writew(fifo, 0, *(u16 *)&src[index]);
185 index += 2;
186 }
187 } else {
188 if (len >= 2) {
189 writesw(fifo, src + index, len >> 1);
190 index += len & ~0x01;
191 }
192 }
193 if (len & 0x01)
194 musb_writeb(fifo, 0, src[index]);
195 } else {
196 /* byte aligned */
197 writesb(fifo, src, len);
198 }
199}
200
201/*
202 * Unload an endpoint's FIFO
203 */
204void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
205{
206 void __iomem *fifo = hw_ep->fifo;
207
208 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
209 'R', hw_ep->epnum, fifo, len, dst);
210
211 /* we can't assume unaligned writes work */
212 if (likely((0x01 & (unsigned long) dst) == 0)) {
213 u16 index = 0;
214
215 /* best case is 32bit-aligned destination address */
216 if ((0x02 & (unsigned long) dst) == 0) {
217 if (len >= 4) {
218 readsl(fifo, dst, len >> 2);
219 index = len & ~0x03;
220 }
221 if (len & 0x02) {
222 *(u16 *)&dst[index] = musb_readw(fifo, 0);
223 index += 2;
224 }
225 } else {
226 if (len >= 2) {
227 readsw(fifo, dst, len >> 1);
228 index = len & ~0x01;
229 }
230 }
231 if (len & 0x01)
232 dst[index] = musb_readb(fifo, 0);
233 } else {
234 /* byte aligned */
235 readsb(fifo, dst, len);
236 }
237}
238
239#endif /* normal PIO */
240
241
242/*-------------------------------------------------------------------------*/
243
244/* for high speed test mode; see USB 2.0 spec 7.1.20 */
245static const u8 musb_test_packet[53] = {
246 /* implicit SYNC then DATA0 to start */
247
248 /* JKJKJKJK x9 */
249 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
250 /* JJKKJJKK x8 */
251 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
252 /* JJJJKKKK x8 */
253 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
254 /* JJJJJJJKKKKKKK x8 */
255 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
256 /* JJJJJJJK x8 */
257 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
258 /* JKKKKKKK x10, JK */
259 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
260
261 /* implicit CRC16 then EOP to end */
262};
263
264void musb_load_testpacket(struct musb *musb)
265{
266 void __iomem *regs = musb->endpoints[0].regs;
267
268 musb_ep_select(musb->mregs, 0);
269 musb_write_fifo(musb->control_ep,
270 sizeof(musb_test_packet), musb_test_packet);
271 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
272}
273
274/*-------------------------------------------------------------------------*/
275
276const char *otg_state_string(struct musb *musb)
277{
278 switch (musb->xceiv.state) {
279 case OTG_STATE_A_IDLE: return "a_idle";
280 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
281 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
282 case OTG_STATE_A_HOST: return "a_host";
283 case OTG_STATE_A_SUSPEND: return "a_suspend";
284 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
285 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
286 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
287 case OTG_STATE_B_IDLE: return "b_idle";
288 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
289 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
290 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
291 case OTG_STATE_B_HOST: return "b_host";
292 default: return "UNDEFINED";
293 }
294}
295
296#ifdef CONFIG_USB_MUSB_OTG
297
298/*
299 * See also USB_OTG_1-3.pdf 6.6.5 Timers
300 * REVISIT: Are the other timers done in the hardware?
301 */
302#define TB_ASE0_BRST 100 /* Min 3.125 ms */
303
304/*
305 * Handles OTG hnp timeouts, such as b_ase0_brst
306 */
307void musb_otg_timer_func(unsigned long data)
308{
309 struct musb *musb = (struct musb *)data;
310 unsigned long flags;
311
312 spin_lock_irqsave(&musb->lock, flags);
313 switch (musb->xceiv.state) {
314 case OTG_STATE_B_WAIT_ACON:
315 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
316 musb_g_disconnect(musb);
317 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
318 musb->is_active = 0;
319 break;
320 case OTG_STATE_A_WAIT_BCON:
321 DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n");
322 musb_hnp_stop(musb);
323 break;
324 default:
325 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
326 }
327 musb->ignore_disconnect = 0;
328 spin_unlock_irqrestore(&musb->lock, flags);
329}
330
331static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
332
333/*
334 * Stops the B-device HNP state. Caller must take care of locking.
335 */
336void musb_hnp_stop(struct musb *musb)
337{
338 struct usb_hcd *hcd = musb_to_hcd(musb);
339 void __iomem *mbase = musb->mregs;
340 u8 reg;
341
342 switch (musb->xceiv.state) {
343 case OTG_STATE_A_PERIPHERAL:
344 case OTG_STATE_A_WAIT_VFALL:
345 case OTG_STATE_A_WAIT_BCON:
346 DBG(1, "HNP: Switching back to A-host\n");
347 musb_g_disconnect(musb);
348 musb->xceiv.state = OTG_STATE_A_IDLE;
349 MUSB_HST_MODE(musb);
350 musb->is_active = 0;
351 break;
352 case OTG_STATE_B_HOST:
353 DBG(1, "HNP: Disabling HR\n");
354 hcd->self.is_b_host = 0;
355 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
356 MUSB_DEV_MODE(musb);
357 reg = musb_readb(mbase, MUSB_POWER);
358 reg |= MUSB_POWER_SUSPENDM;
359 musb_writeb(mbase, MUSB_POWER, reg);
360 /* REVISIT: Start SESSION_REQUEST here? */
361 break;
362 default:
363 DBG(1, "HNP: Stopping in unknown state %s\n",
364 otg_state_string(musb));
365 }
366
367 /*
368 * When returning to A state after HNP, avoid hub_port_rebounce(),
369 * which cause occasional OPT A "Did not receive reset after connect"
370 * errors.
371 */
372 musb->port1_status &=
373 ~(1 << USB_PORT_FEAT_C_CONNECTION);
374}
375
376#endif
377
378/*
379 * Interrupt Service Routine to record USB "global" interrupts.
380 * Since these do not happen often and signify things of
381 * paramount importance, it seems OK to check them individually;
382 * the order of the tests is specified in the manual
383 *
384 * @param musb instance pointer
385 * @param int_usb register contents
386 * @param devctl
387 * @param power
388 */
389
390#define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
391 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
392 | MUSB_INTR_RESET)
393
394static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
395 u8 devctl, u8 power)
396{
397 irqreturn_t handled = IRQ_NONE;
398 void __iomem *mbase = musb->mregs;
399
400 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
401 int_usb);
402
403 /* in host mode, the peripheral may issue remote wakeup.
404 * in peripheral mode, the host may resume the link.
405 * spurious RESUME irqs happen too, paired with SUSPEND.
406 */
407 if (int_usb & MUSB_INTR_RESUME) {
408 handled = IRQ_HANDLED;
409 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
410
411 if (devctl & MUSB_DEVCTL_HM) {
412#ifdef CONFIG_USB_MUSB_HDRC_HCD
413 switch (musb->xceiv.state) {
414 case OTG_STATE_A_SUSPEND:
415 /* remote wakeup? later, GetPortStatus
416 * will stop RESUME signaling
417 */
418
419 if (power & MUSB_POWER_SUSPENDM) {
420 /* spurious */
421 musb->int_usb &= ~MUSB_INTR_SUSPEND;
422 DBG(2, "Spurious SUSPENDM\n");
423 break;
424 }
425
426 power &= ~MUSB_POWER_SUSPENDM;
427 musb_writeb(mbase, MUSB_POWER,
428 power | MUSB_POWER_RESUME);
429
430 musb->port1_status |=
431 (USB_PORT_STAT_C_SUSPEND << 16)
432 | MUSB_PORT_STAT_RESUME;
433 musb->rh_timer = jiffies
434 + msecs_to_jiffies(20);
435
436 musb->xceiv.state = OTG_STATE_A_HOST;
437 musb->is_active = 1;
438 usb_hcd_resume_root_hub(musb_to_hcd(musb));
439 break;
440 case OTG_STATE_B_WAIT_ACON:
441 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
442 musb->is_active = 1;
443 MUSB_DEV_MODE(musb);
444 break;
445 default:
446 WARNING("bogus %s RESUME (%s)\n",
447 "host",
448 otg_state_string(musb));
449 }
450#endif
451 } else {
452 switch (musb->xceiv.state) {
453#ifdef CONFIG_USB_MUSB_HDRC_HCD
454 case OTG_STATE_A_SUSPEND:
455 /* possibly DISCONNECT is upcoming */
456 musb->xceiv.state = OTG_STATE_A_HOST;
457 usb_hcd_resume_root_hub(musb_to_hcd(musb));
458 break;
459#endif
460#ifdef CONFIG_USB_GADGET_MUSB_HDRC
461 case OTG_STATE_B_WAIT_ACON:
462 case OTG_STATE_B_PERIPHERAL:
463 /* disconnect while suspended? we may
464 * not get a disconnect irq...
465 */
466 if ((devctl & MUSB_DEVCTL_VBUS)
467 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
468 ) {
469 musb->int_usb |= MUSB_INTR_DISCONNECT;
470 musb->int_usb &= ~MUSB_INTR_SUSPEND;
471 break;
472 }
473 musb_g_resume(musb);
474 break;
475 case OTG_STATE_B_IDLE:
476 musb->int_usb &= ~MUSB_INTR_SUSPEND;
477 break;
478#endif
479 default:
480 WARNING("bogus %s RESUME (%s)\n",
481 "peripheral",
482 otg_state_string(musb));
483 }
484 }
485 }
486
487#ifdef CONFIG_USB_MUSB_HDRC_HCD
488 /* see manual for the order of the tests */
489 if (int_usb & MUSB_INTR_SESSREQ) {
490 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
491
492 /* IRQ arrives from ID pin sense or (later, if VBUS power
493 * is removed) SRP. responses are time critical:
494 * - turn on VBUS (with silicon-specific mechanism)
495 * - go through A_WAIT_VRISE
496 * - ... to A_WAIT_BCON.
497 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
498 */
499 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
500 musb->ep0_stage = MUSB_EP0_START;
501 musb->xceiv.state = OTG_STATE_A_IDLE;
502 MUSB_HST_MODE(musb);
503 musb_set_vbus(musb, 1);
504
505 handled = IRQ_HANDLED;
506 }
507
508 if (int_usb & MUSB_INTR_VBUSERROR) {
509 int ignore = 0;
510
511 /* During connection as an A-Device, we may see a short
512 * current spikes causing voltage drop, because of cable
513 * and peripheral capacitance combined with vbus draw.
514 * (So: less common with truly self-powered devices, where
515 * vbus doesn't act like a power supply.)
516 *
517 * Such spikes are short; usually less than ~500 usec, max
518 * of ~2 msec. That is, they're not sustained overcurrent
519 * errors, though they're reported using VBUSERROR irqs.
520 *
521 * Workarounds: (a) hardware: use self powered devices.
522 * (b) software: ignore non-repeated VBUS errors.
523 *
524 * REVISIT: do delays from lots of DEBUG_KERNEL checks
525 * make trouble here, keeping VBUS < 4.4V ?
526 */
527 switch (musb->xceiv.state) {
528 case OTG_STATE_A_HOST:
529 /* recovery is dicey once we've gotten past the
530 * initial stages of enumeration, but if VBUS
531 * stayed ok at the other end of the link, and
532 * another reset is due (at least for high speed,
533 * to redo the chirp etc), it might work OK...
534 */
535 case OTG_STATE_A_WAIT_BCON:
536 case OTG_STATE_A_WAIT_VRISE:
537 if (musb->vbuserr_retry) {
538 musb->vbuserr_retry--;
539 ignore = 1;
540 devctl |= MUSB_DEVCTL_SESSION;
541 musb_writeb(mbase, MUSB_DEVCTL, devctl);
542 } else {
543 musb->port1_status |=
544 (1 << USB_PORT_FEAT_OVER_CURRENT)
545 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
546 }
547 break;
548 default:
549 break;
550 }
551
552 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
553 otg_state_string(musb),
554 devctl,
555 ({ char *s;
556 switch (devctl & MUSB_DEVCTL_VBUS) {
557 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
558 s = "<SessEnd"; break;
559 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
560 s = "<AValid"; break;
561 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
562 s = "<VBusValid"; break;
563 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
564 default:
565 s = "VALID"; break;
566 }; s; }),
567 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
568 musb->port1_status);
569
570 /* go through A_WAIT_VFALL then start a new session */
571 if (!ignore)
572 musb_set_vbus(musb, 0);
573 handled = IRQ_HANDLED;
574 }
575
576 if (int_usb & MUSB_INTR_CONNECT) {
577 struct usb_hcd *hcd = musb_to_hcd(musb);
578
579 handled = IRQ_HANDLED;
580 musb->is_active = 1;
581 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
582
583 musb->ep0_stage = MUSB_EP0_START;
584
585#ifdef CONFIG_USB_MUSB_OTG
586 /* flush endpoints when transitioning from Device Mode */
587 if (is_peripheral_active(musb)) {
588 /* REVISIT HNP; just force disconnect */
589 }
590 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
591 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
592 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
593#endif
594 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
595 |USB_PORT_STAT_HIGH_SPEED
596 |USB_PORT_STAT_ENABLE
597 );
598 musb->port1_status |= USB_PORT_STAT_CONNECTION
599 |(USB_PORT_STAT_C_CONNECTION << 16);
600
601 /* high vs full speed is just a guess until after reset */
602 if (devctl & MUSB_DEVCTL_LSDEV)
603 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
604
605 if (hcd->status_urb)
606 usb_hcd_poll_rh_status(hcd);
607 else
608 usb_hcd_resume_root_hub(hcd);
609
610 MUSB_HST_MODE(musb);
611
612 /* indicate new connection to OTG machine */
613 switch (musb->xceiv.state) {
614 case OTG_STATE_B_PERIPHERAL:
615 if (int_usb & MUSB_INTR_SUSPEND) {
616 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
617 musb->xceiv.state = OTG_STATE_B_HOST;
618 hcd->self.is_b_host = 1;
619 int_usb &= ~MUSB_INTR_SUSPEND;
620 } else
621 DBG(1, "CONNECT as b_peripheral???\n");
622 break;
623 case OTG_STATE_B_WAIT_ACON:
624 DBG(1, "HNP: Waiting to switch to b_host state\n");
625 musb->xceiv.state = OTG_STATE_B_HOST;
626 hcd->self.is_b_host = 1;
627 break;
628 default:
629 if ((devctl & MUSB_DEVCTL_VBUS)
630 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
631 musb->xceiv.state = OTG_STATE_A_HOST;
632 hcd->self.is_b_host = 0;
633 }
634 break;
635 }
636 DBG(1, "CONNECT (%s) devctl %02x\n",
637 otg_state_string(musb), devctl);
638 }
639#endif /* CONFIG_USB_MUSB_HDRC_HCD */
640
641 /* mentor saves a bit: bus reset and babble share the same irq.
642 * only host sees babble; only peripheral sees bus reset.
643 */
644 if (int_usb & MUSB_INTR_RESET) {
645 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
646 /*
647 * Looks like non-HS BABBLE can be ignored, but
648 * HS BABBLE is an error condition. For HS the solution
649 * is to avoid babble in the first place and fix what
650 * caused BABBLE. When HS BABBLE happens we can only
651 * stop the session.
652 */
653 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
654 DBG(1, "BABBLE devctl: %02x\n", devctl);
655 else {
656 ERR("Stopping host session -- babble\n");
657 musb_writeb(mbase, MUSB_DEVCTL, 0);
658 }
659 } else if (is_peripheral_capable()) {
660 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
661 switch (musb->xceiv.state) {
662#ifdef CONFIG_USB_OTG
663 case OTG_STATE_A_SUSPEND:
664 /* We need to ignore disconnect on suspend
665 * otherwise tusb 2.0 won't reconnect after a
666 * power cycle, which breaks otg compliance.
667 */
668 musb->ignore_disconnect = 1;
669 musb_g_reset(musb);
670 /* FALLTHROUGH */
671 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
672 DBG(1, "HNP: Setting timer as %s\n",
673 otg_state_string(musb));
674 musb_otg_timer.data = (unsigned long)musb;
675 mod_timer(&musb_otg_timer, jiffies
676 + msecs_to_jiffies(100));
677 break;
678 case OTG_STATE_A_PERIPHERAL:
679 musb_hnp_stop(musb);
680 break;
681 case OTG_STATE_B_WAIT_ACON:
682 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
683 otg_state_string(musb));
684 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
685 musb_g_reset(musb);
686 break;
687#endif
688 case OTG_STATE_B_IDLE:
689 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
690 /* FALLTHROUGH */
691 case OTG_STATE_B_PERIPHERAL:
692 musb_g_reset(musb);
693 break;
694 default:
695 DBG(1, "Unhandled BUS RESET as %s\n",
696 otg_state_string(musb));
697 }
698 }
699
700 handled = IRQ_HANDLED;
701 }
702 schedule_work(&musb->irq_work);
703
704 return handled;
705}
706
707/*
708 * Interrupt Service Routine to record USB "global" interrupts.
709 * Since these do not happen often and signify things of
710 * paramount importance, it seems OK to check them individually;
711 * the order of the tests is specified in the manual
712 *
713 * @param musb instance pointer
714 * @param int_usb register contents
715 * @param devctl
716 * @param power
717 */
718static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
719 u8 devctl, u8 power)
720{
721 irqreturn_t handled = IRQ_NONE;
722
723#if 0
724/* REVISIT ... this would be for multiplexing periodic endpoints, or
725 * supporting transfer phasing to prevent exceeding ISO bandwidth
726 * limits of a given frame or microframe.
727 *
728 * It's not needed for peripheral side, which dedicates endpoints;
729 * though it _might_ use SOF irqs for other purposes.
730 *
731 * And it's not currently needed for host side, which also dedicates
732 * endpoints, relies on TX/RX interval registers, and isn't claimed
733 * to support ISO transfers yet.
734 */
735 if (int_usb & MUSB_INTR_SOF) {
736 void __iomem *mbase = musb->mregs;
737 struct musb_hw_ep *ep;
738 u8 epnum;
739 u16 frame;
740
741 DBG(6, "START_OF_FRAME\n");
742 handled = IRQ_HANDLED;
743
744 /* start any periodic Tx transfers waiting for current frame */
745 frame = musb_readw(mbase, MUSB_FRAME);
746 ep = musb->endpoints;
747 for (epnum = 1; (epnum < musb->nr_endpoints)
748 && (musb->epmask >= (1 << epnum));
749 epnum++, ep++) {
750 /*
751 * FIXME handle framecounter wraps (12 bits)
752 * eliminate duplicated StartUrb logic
753 */
754 if (ep->dwWaitFrame >= frame) {
755 ep->dwWaitFrame = 0;
756 pr_debug("SOF --> periodic TX%s on %d\n",
757 ep->tx_channel ? " DMA" : "",
758 epnum);
759 if (!ep->tx_channel)
760 musb_h_tx_start(musb, epnum);
761 else
762 cppi_hostdma_start(musb, epnum);
763 }
764 } /* end of for loop */
765 }
766#endif
767
768 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
769 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
770 otg_state_string(musb),
771 MUSB_MODE(musb), devctl);
772 handled = IRQ_HANDLED;
773
774 switch (musb->xceiv.state) {
775#ifdef CONFIG_USB_MUSB_HDRC_HCD
776 case OTG_STATE_A_HOST:
777 case OTG_STATE_A_SUSPEND:
778 musb_root_disconnect(musb);
779 if (musb->a_wait_bcon != 0)
780 musb_platform_try_idle(musb, jiffies
781 + msecs_to_jiffies(musb->a_wait_bcon));
782 break;
783#endif /* HOST */
784#ifdef CONFIG_USB_MUSB_OTG
785 case OTG_STATE_B_HOST:
786 musb_hnp_stop(musb);
787 break;
788 case OTG_STATE_A_PERIPHERAL:
789 musb_hnp_stop(musb);
790 musb_root_disconnect(musb);
791 /* FALLTHROUGH */
792 case OTG_STATE_B_WAIT_ACON:
793 /* FALLTHROUGH */
794#endif /* OTG */
795#ifdef CONFIG_USB_GADGET_MUSB_HDRC
796 case OTG_STATE_B_PERIPHERAL:
797 case OTG_STATE_B_IDLE:
798 musb_g_disconnect(musb);
799 break;
800#endif /* GADGET */
801 default:
802 WARNING("unhandled DISCONNECT transition (%s)\n",
803 otg_state_string(musb));
804 break;
805 }
806
807 schedule_work(&musb->irq_work);
808 }
809
810 if (int_usb & MUSB_INTR_SUSPEND) {
811 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
812 otg_state_string(musb), devctl, power);
813 handled = IRQ_HANDLED;
814
815 switch (musb->xceiv.state) {
816#ifdef CONFIG_USB_MUSB_OTG
817 case OTG_STATE_A_PERIPHERAL:
818 /*
819 * We cannot stop HNP here, devctl BDEVICE might be
820 * still set.
821 */
822 break;
823#endif
824 case OTG_STATE_B_PERIPHERAL:
825 musb_g_suspend(musb);
826 musb->is_active = is_otg_enabled(musb)
827 && musb->xceiv.gadget->b_hnp_enable;
828 if (musb->is_active) {
829#ifdef CONFIG_USB_MUSB_OTG
830 musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
831 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
832 musb_otg_timer.data = (unsigned long)musb;
833 mod_timer(&musb_otg_timer, jiffies
834 + msecs_to_jiffies(TB_ASE0_BRST));
835#endif
836 }
837 break;
838 case OTG_STATE_A_WAIT_BCON:
839 if (musb->a_wait_bcon != 0)
840 musb_platform_try_idle(musb, jiffies
841 + msecs_to_jiffies(musb->a_wait_bcon));
842 break;
843 case OTG_STATE_A_HOST:
844 musb->xceiv.state = OTG_STATE_A_SUSPEND;
845 musb->is_active = is_otg_enabled(musb)
846 && musb->xceiv.host->b_hnp_enable;
847 break;
848 case OTG_STATE_B_HOST:
849 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
850 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
851 break;
852 default:
853 /* "should not happen" */
854 musb->is_active = 0;
855 break;
856 }
857 schedule_work(&musb->irq_work);
858 }
859
860
861 return handled;
862}
863
864/*-------------------------------------------------------------------------*/
865
866/*
867* Program the HDRC to start (enable interrupts, dma, etc.).
868*/
869void musb_start(struct musb *musb)
870{
871 void __iomem *regs = musb->mregs;
872 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
873
874 DBG(2, "<== devctl %02x\n", devctl);
875
876 /* Set INT enable registers, enable interrupts */
877 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
878 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
879 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
880
881 musb_writeb(regs, MUSB_TESTMODE, 0);
882
883 /* put into basic highspeed mode and start session */
884 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
885 | MUSB_POWER_SOFTCONN
886 | MUSB_POWER_HSENAB
887 /* ENSUSPEND wedges tusb */
888 /* | MUSB_POWER_ENSUSPEND */
889 );
890
891 musb->is_active = 0;
892 devctl = musb_readb(regs, MUSB_DEVCTL);
893 devctl &= ~MUSB_DEVCTL_SESSION;
894
895 if (is_otg_enabled(musb)) {
896 /* session started after:
897 * (a) ID-grounded irq, host mode;
898 * (b) vbus present/connect IRQ, peripheral mode;
899 * (c) peripheral initiates, using SRP
900 */
901 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
902 musb->is_active = 1;
903 else
904 devctl |= MUSB_DEVCTL_SESSION;
905
906 } else if (is_host_enabled(musb)) {
907 /* assume ID pin is hard-wired to ground */
908 devctl |= MUSB_DEVCTL_SESSION;
909
910 } else /* peripheral is enabled */ {
911 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
912 musb->is_active = 1;
913 }
914 musb_platform_enable(musb);
915 musb_writeb(regs, MUSB_DEVCTL, devctl);
916}
917
918
919static void musb_generic_disable(struct musb *musb)
920{
921 void __iomem *mbase = musb->mregs;
922 u16 temp;
923
924 /* disable interrupts */
925 musb_writeb(mbase, MUSB_INTRUSBE, 0);
926 musb_writew(mbase, MUSB_INTRTXE, 0);
927 musb_writew(mbase, MUSB_INTRRXE, 0);
928
929 /* off */
930 musb_writeb(mbase, MUSB_DEVCTL, 0);
931
932 /* flush pending interrupts */
933 temp = musb_readb(mbase, MUSB_INTRUSB);
934 temp = musb_readw(mbase, MUSB_INTRTX);
935 temp = musb_readw(mbase, MUSB_INTRRX);
936
937}
938
939/*
940 * Make the HDRC stop (disable interrupts, etc.);
941 * reversible by musb_start
942 * called on gadget driver unregister
943 * with controller locked, irqs blocked
944 * acts as a NOP unless some role activated the hardware
945 */
946void musb_stop(struct musb *musb)
947{
948 /* stop IRQs, timers, ... */
949 musb_platform_disable(musb);
950 musb_generic_disable(musb);
951 DBG(3, "HDRC disabled\n");
952
953 /* FIXME
954 * - mark host and/or peripheral drivers unusable/inactive
955 * - disable DMA (and enable it in HdrcStart)
956 * - make sure we can musb_start() after musb_stop(); with
957 * OTG mode, gadget driver module rmmod/modprobe cycles that
958 * - ...
959 */
960 musb_platform_try_idle(musb, 0);
961}
962
963static void musb_shutdown(struct platform_device *pdev)
964{
965 struct musb *musb = dev_to_musb(&pdev->dev);
966 unsigned long flags;
967
968 spin_lock_irqsave(&musb->lock, flags);
969 musb_platform_disable(musb);
970 musb_generic_disable(musb);
971 if (musb->clock) {
972 clk_put(musb->clock);
973 musb->clock = NULL;
974 }
975 spin_unlock_irqrestore(&musb->lock, flags);
976
977 /* FIXME power down */
978}
979
980
981/*-------------------------------------------------------------------------*/
982
983/*
984 * The silicon either has hard-wired endpoint configurations, or else
985 * "dynamic fifo" sizing. The driver has support for both, though at this
986 * writing only the dynamic sizing is very well tested. We use normal
987 * idioms to so both modes are compile-tested, but dead code elimination
988 * leaves only the relevant one in the object file.
989 *
990 * We don't currently use dynamic fifo setup capability to do anything
991 * more than selecting one of a bunch of predefined configurations.
992 */
993#ifdef MUSB_C_DYNFIFO_DEF
994#define can_dynfifo() 1
995#else
996#define can_dynfifo() 0
997#endif
998
999#if defined(CONFIG_USB_TUSB6010) || \
1000 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
1001static ushort __initdata fifo_mode = 4;
1002#else
1003static ushort __initdata fifo_mode = 2;
1004#endif
1005
1006/* "modprobe ... fifo_mode=1" etc */
1007module_param(fifo_mode, ushort, 0);
1008MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1009
1010
1011#define DYN_FIFO_SIZE (1<<(MUSB_C_RAM_BITS+2))
1012
1013enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
1014enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
1015
1016struct fifo_cfg {
1017 u8 hw_ep_num;
1018 enum fifo_style style;
1019 enum buf_mode mode;
1020 u16 maxpacket;
1021};
1022
1023/*
1024 * tables defining fifo_mode values. define more if you like.
1025 * for host side, make sure both halves of ep1 are set up.
1026 */
1027
1028/* mode 0 - fits in 2KB */
1029static struct fifo_cfg __initdata mode_0_cfg[] = {
1030{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1031{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1032{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1033{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1034{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1035};
1036
1037/* mode 1 - fits in 4KB */
1038static struct fifo_cfg __initdata mode_1_cfg[] = {
1039{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1040{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1041{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1042{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1043{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1044};
1045
1046/* mode 2 - fits in 4KB */
1047static struct fifo_cfg __initdata mode_2_cfg[] = {
1048{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1049{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1050{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1051{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1052{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1053{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1054};
1055
1056/* mode 3 - fits in 4KB */
1057static struct fifo_cfg __initdata mode_3_cfg[] = {
1058{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1059{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1060{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1061{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1062{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1063{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1064};
1065
1066/* mode 4 - fits in 16KB */
1067static struct fifo_cfg __initdata mode_4_cfg[] = {
1068{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1069{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1070{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1071{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1072{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1073{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1074{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1075{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1076{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1077{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1078{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1079{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1080{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1081{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1082{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1083{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1084{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1085{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1086{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1087{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
1088{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
1089{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
1090{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
1091{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
1092{ .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
1093{ .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
1094{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1095{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1096};
1097
1098
1099/*
1100 * configure a fifo; for non-shared endpoints, this may be called
1101 * once for a tx fifo and once for an rx fifo.
1102 *
1103 * returns negative errno or offset for next fifo.
1104 */
1105static int __init
1106fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1107 const struct fifo_cfg *cfg, u16 offset)
1108{
1109 void __iomem *mbase = musb->mregs;
1110 int size = 0;
1111 u16 maxpacket = cfg->maxpacket;
1112 u16 c_off = offset >> 3;
1113 u8 c_size;
1114
1115 /* expect hw_ep has already been zero-initialized */
1116
1117 size = ffs(max(maxpacket, (u16) 8)) - 1;
1118 maxpacket = 1 << size;
1119
1120 c_size = size - 3;
1121 if (cfg->mode == BUF_DOUBLE) {
1122 if ((offset + (maxpacket << 1)) > DYN_FIFO_SIZE)
1123 return -EMSGSIZE;
1124 c_size |= MUSB_FIFOSZ_DPB;
1125 } else {
1126 if ((offset + maxpacket) > DYN_FIFO_SIZE)
1127 return -EMSGSIZE;
1128 }
1129
1130 /* configure the FIFO */
1131 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1132
1133#ifdef CONFIG_USB_MUSB_HDRC_HCD
1134 /* EP0 reserved endpoint for control, bidirectional;
1135 * EP1 reserved for bulk, two unidirection halves.
1136 */
1137 if (hw_ep->epnum == 1)
1138 musb->bulk_ep = hw_ep;
1139 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1140#endif
1141 switch (cfg->style) {
1142 case FIFO_TX:
1143 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1144 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1145 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1146 hw_ep->max_packet_sz_tx = maxpacket;
1147 break;
1148 case FIFO_RX:
1149 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1150 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1151 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1152 hw_ep->max_packet_sz_rx = maxpacket;
1153 break;
1154 case FIFO_RXTX:
1155 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1156 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1157 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1158 hw_ep->max_packet_sz_rx = maxpacket;
1159
1160 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1161 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1162 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1163 hw_ep->max_packet_sz_tx = maxpacket;
1164
1165 hw_ep->is_shared_fifo = true;
1166 break;
1167 }
1168
1169 /* NOTE rx and tx endpoint irqs aren't managed separately,
1170 * which happens to be ok
1171 */
1172 musb->epmask |= (1 << hw_ep->epnum);
1173
1174 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1175}
1176
1177static struct fifo_cfg __initdata ep0_cfg = {
1178 .style = FIFO_RXTX, .maxpacket = 64,
1179};
1180
1181static int __init ep_config_from_table(struct musb *musb)
1182{
1183 const struct fifo_cfg *cfg;
1184 unsigned i, n;
1185 int offset;
1186 struct musb_hw_ep *hw_ep = musb->endpoints;
1187
1188 switch (fifo_mode) {
1189 default:
1190 fifo_mode = 0;
1191 /* FALLTHROUGH */
1192 case 0:
1193 cfg = mode_0_cfg;
1194 n = ARRAY_SIZE(mode_0_cfg);
1195 break;
1196 case 1:
1197 cfg = mode_1_cfg;
1198 n = ARRAY_SIZE(mode_1_cfg);
1199 break;
1200 case 2:
1201 cfg = mode_2_cfg;
1202 n = ARRAY_SIZE(mode_2_cfg);
1203 break;
1204 case 3:
1205 cfg = mode_3_cfg;
1206 n = ARRAY_SIZE(mode_3_cfg);
1207 break;
1208 case 4:
1209 cfg = mode_4_cfg;
1210 n = ARRAY_SIZE(mode_4_cfg);
1211 break;
1212 }
1213
1214 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1215 musb_driver_name, fifo_mode);
1216
1217
1218 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1219 /* assert(offset > 0) */
1220
1221 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1222 * be better than static MUSB_C_NUM_EPS and DYN_FIFO_SIZE...
1223 */
1224
1225 for (i = 0; i < n; i++) {
1226 u8 epn = cfg->hw_ep_num;
1227
1228 if (epn >= MUSB_C_NUM_EPS) {
1229 pr_debug("%s: invalid ep %d\n",
1230 musb_driver_name, epn);
1231 continue;
1232 }
1233 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1234 if (offset < 0) {
1235 pr_debug("%s: mem overrun, ep %d\n",
1236 musb_driver_name, epn);
1237 return -EINVAL;
1238 }
1239 epn++;
1240 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1241 }
1242
1243 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1244 musb_driver_name,
1245 n + 1, MUSB_C_NUM_EPS * 2 - 1,
1246 offset, DYN_FIFO_SIZE);
1247
1248#ifdef CONFIG_USB_MUSB_HDRC_HCD
1249 if (!musb->bulk_ep) {
1250 pr_debug("%s: missing bulk\n", musb_driver_name);
1251 return -EINVAL;
1252 }
1253#endif
1254
1255 return 0;
1256}
1257
1258
1259/*
1260 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1261 * @param musb the controller
1262 */
1263static int __init ep_config_from_hw(struct musb *musb)
1264{
1265 u8 epnum = 0, reg;
1266 struct musb_hw_ep *hw_ep;
1267 void *mbase = musb->mregs;
1268
1269 DBG(2, "<== static silicon ep config\n");
1270
1271 /* FIXME pick up ep0 maxpacket size */
1272
1273 for (epnum = 1; epnum < MUSB_C_NUM_EPS; epnum++) {
1274 musb_ep_select(mbase, epnum);
1275 hw_ep = musb->endpoints + epnum;
1276
1277 /* read from core using indexed model */
1278 reg = musb_readb(hw_ep->regs, 0x10 + MUSB_FIFOSIZE);
1279 if (!reg) {
1280 /* 0's returned when no more endpoints */
1281 break;
1282 }
1283 musb->nr_endpoints++;
1284 musb->epmask |= (1 << epnum);
1285
1286 hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f);
1287
1288 /* shared TX/RX FIFO? */
1289 if ((reg & 0xf0) == 0xf0) {
1290 hw_ep->max_packet_sz_rx = hw_ep->max_packet_sz_tx;
1291 hw_ep->is_shared_fifo = true;
1292 continue;
1293 } else {
1294 hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4);
1295 hw_ep->is_shared_fifo = false;
1296 }
1297
1298 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1299
1300#ifdef CONFIG_USB_MUSB_HDRC_HCD
1301 /* pick an RX/TX endpoint for bulk */
1302 if (hw_ep->max_packet_sz_tx < 512
1303 || hw_ep->max_packet_sz_rx < 512)
1304 continue;
1305
1306 /* REVISIT: this algorithm is lazy, we should at least
1307 * try to pick a double buffered endpoint.
1308 */
1309 if (musb->bulk_ep)
1310 continue;
1311 musb->bulk_ep = hw_ep;
1312#endif
1313 }
1314
1315#ifdef CONFIG_USB_MUSB_HDRC_HCD
1316 if (!musb->bulk_ep) {
1317 pr_debug("%s: missing bulk\n", musb_driver_name);
1318 return -EINVAL;
1319 }
1320#endif
1321
1322 return 0;
1323}
1324
1325enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1326
1327/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1328 * configure endpoints, or take their config from silicon
1329 */
1330static int __init musb_core_init(u16 musb_type, struct musb *musb)
1331{
1332#ifdef MUSB_AHB_ID
1333 u32 data;
1334#endif
1335 u8 reg;
1336 char *type;
1337 u16 hwvers, rev_major, rev_minor;
1338 char aInfo[78], aRevision[32], aDate[12];
1339 void __iomem *mbase = musb->mregs;
1340 int status = 0;
1341 int i;
1342
1343 /* log core options (read using indexed model) */
1344 musb_ep_select(mbase, 0);
1345 reg = musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
1346
1347 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1348 if (reg & MUSB_CONFIGDATA_DYNFIFO)
1349 strcat(aInfo, ", dyn FIFOs");
1350 if (reg & MUSB_CONFIGDATA_MPRXE) {
1351 strcat(aInfo, ", bulk combine");
1352#ifdef C_MP_RX
1353 musb->bulk_combine = true;
1354#else
1355 strcat(aInfo, " (X)"); /* no driver support */
1356#endif
1357 }
1358 if (reg & MUSB_CONFIGDATA_MPTXE) {
1359 strcat(aInfo, ", bulk split");
1360#ifdef C_MP_TX
1361 musb->bulk_split = true;
1362#else
1363 strcat(aInfo, " (X)"); /* no driver support */
1364#endif
1365 }
1366 if (reg & MUSB_CONFIGDATA_HBRXE) {
1367 strcat(aInfo, ", HB-ISO Rx");
1368 strcat(aInfo, " (X)"); /* no driver support */
1369 }
1370 if (reg & MUSB_CONFIGDATA_HBTXE) {
1371 strcat(aInfo, ", HB-ISO Tx");
1372 strcat(aInfo, " (X)"); /* no driver support */
1373 }
1374 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1375 strcat(aInfo, ", SoftConn");
1376
1377 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1378 musb_driver_name, reg, aInfo);
1379
1380#ifdef MUSB_AHB_ID
1381 data = musb_readl(mbase, 0x404);
1382 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1383 (data >> 16) & 0xff, (data >> 24) & 0xff);
1384 /* FIXME ID2 and ID3 are unused */
1385 data = musb_readl(mbase, 0x408);
1386 printk(KERN_DEBUG "ID2=%lx\n", (long unsigned)data);
1387 data = musb_readl(mbase, 0x40c);
1388 printk(KERN_DEBUG "ID3=%lx\n", (long unsigned)data);
1389 reg = musb_readb(mbase, 0x400);
1390 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1391#else
1392 aDate[0] = 0;
1393#endif
1394 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1395 musb->is_multipoint = 1;
1396 type = "M";
1397 } else {
1398 musb->is_multipoint = 0;
1399 type = "";
1400#ifdef CONFIG_USB_MUSB_HDRC_HCD
1401#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1402 printk(KERN_ERR
1403 "%s: kernel must blacklist external hubs\n",
1404 musb_driver_name);
1405#endif
1406#endif
1407 }
1408
1409 /* log release info */
1410 hwvers = musb_readw(mbase, MUSB_HWVERS);
1411 rev_major = (hwvers >> 10) & 0x1f;
1412 rev_minor = hwvers & 0x3ff;
1413 snprintf(aRevision, 32, "%d.%d%s", rev_major,
1414 rev_minor, (hwvers & 0x8000) ? "RC" : "");
1415 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1416 musb_driver_name, type, aRevision, aDate);
1417
1418 /* configure ep0 */
1419 musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
1420 musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
1421
1422 /* discover endpoint configuration */
1423 musb->nr_endpoints = 1;
1424 musb->epmask = 1;
1425
1426 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1427 if (can_dynfifo())
1428 status = ep_config_from_table(musb);
1429 else {
1430 ERR("reconfigure software for Dynamic FIFOs\n");
1431 status = -ENODEV;
1432 }
1433 } else {
1434 if (!can_dynfifo())
1435 status = ep_config_from_hw(musb);
1436 else {
1437 ERR("reconfigure software for static FIFOs\n");
1438 return -ENODEV;
1439 }
1440 }
1441
1442 if (status < 0)
1443 return status;
1444
1445 /* finish init, and print endpoint config */
1446 for (i = 0; i < musb->nr_endpoints; i++) {
1447 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1448
1449 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1450#ifdef CONFIG_USB_TUSB6010
1451 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1452 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1453 hw_ep->fifo_sync_va =
1454 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1455
1456 if (i == 0)
1457 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1458 else
1459 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1460#endif
1461
1462 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1463#ifdef CONFIG_USB_MUSB_HDRC_HCD
1464 hw_ep->target_regs = MUSB_BUSCTL_OFFSET(i, 0) + mbase;
1465 hw_ep->rx_reinit = 1;
1466 hw_ep->tx_reinit = 1;
1467#endif
1468
1469 if (hw_ep->max_packet_sz_tx) {
1470 printk(KERN_DEBUG
1471 "%s: hw_ep %d%s, %smax %d\n",
1472 musb_driver_name, i,
1473 hw_ep->is_shared_fifo ? "shared" : "tx",
1474 hw_ep->tx_double_buffered
1475 ? "doublebuffer, " : "",
1476 hw_ep->max_packet_sz_tx);
1477 }
1478 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1479 printk(KERN_DEBUG
1480 "%s: hw_ep %d%s, %smax %d\n",
1481 musb_driver_name, i,
1482 "rx",
1483 hw_ep->rx_double_buffered
1484 ? "doublebuffer, " : "",
1485 hw_ep->max_packet_sz_rx);
1486 }
1487 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1488 DBG(1, "hw_ep %d not configured\n", i);
1489 }
1490
1491 return 0;
1492}
1493
1494/*-------------------------------------------------------------------------*/
1495
1496#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1497
1498static irqreturn_t generic_interrupt(int irq, void *__hci)
1499{
1500 unsigned long flags;
1501 irqreturn_t retval = IRQ_NONE;
1502 struct musb *musb = __hci;
1503
1504 spin_lock_irqsave(&musb->lock, flags);
1505
1506 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1507 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1508 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1509
1510 if (musb->int_usb || musb->int_tx || musb->int_rx)
1511 retval = musb_interrupt(musb);
1512
1513 spin_unlock_irqrestore(&musb->lock, flags);
1514
1515 /* REVISIT we sometimes get spurious IRQs on g_ep0
1516 * not clear why...
1517 */
1518 if (retval != IRQ_HANDLED)
1519 DBG(5, "spurious?\n");
1520
1521 return IRQ_HANDLED;
1522}
1523
1524#else
1525#define generic_interrupt NULL
1526#endif
1527
1528/*
1529 * handle all the irqs defined by the HDRC core. for now we expect: other
1530 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1531 * will be assigned, and the irq will already have been acked.
1532 *
1533 * called in irq context with spinlock held, irqs blocked
1534 */
1535irqreturn_t musb_interrupt(struct musb *musb)
1536{
1537 irqreturn_t retval = IRQ_NONE;
1538 u8 devctl, power;
1539 int ep_num;
1540 u32 reg;
1541
1542 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1543 power = musb_readb(musb->mregs, MUSB_POWER);
1544
1545 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1546 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1547 musb->int_usb, musb->int_tx, musb->int_rx);
1548
1549 /* the core can interrupt us for multiple reasons; docs have
1550 * a generic interrupt flowchart to follow
1551 */
1552 if (musb->int_usb & STAGE0_MASK)
1553 retval |= musb_stage0_irq(musb, musb->int_usb,
1554 devctl, power);
1555
1556 /* "stage 1" is handling endpoint irqs */
1557
1558 /* handle endpoint 0 first */
1559 if (musb->int_tx & 1) {
1560 if (devctl & MUSB_DEVCTL_HM)
1561 retval |= musb_h_ep0_irq(musb);
1562 else
1563 retval |= musb_g_ep0_irq(musb);
1564 }
1565
1566 /* RX on endpoints 1-15 */
1567 reg = musb->int_rx >> 1;
1568 ep_num = 1;
1569 while (reg) {
1570 if (reg & 1) {
1571 /* musb_ep_select(musb->mregs, ep_num); */
1572 /* REVISIT just retval = ep->rx_irq(...) */
1573 retval = IRQ_HANDLED;
1574 if (devctl & MUSB_DEVCTL_HM) {
1575 if (is_host_capable())
1576 musb_host_rx(musb, ep_num);
1577 } else {
1578 if (is_peripheral_capable())
1579 musb_g_rx(musb, ep_num);
1580 }
1581 }
1582
1583 reg >>= 1;
1584 ep_num++;
1585 }
1586
1587 /* TX on endpoints 1-15 */
1588 reg = musb->int_tx >> 1;
1589 ep_num = 1;
1590 while (reg) {
1591 if (reg & 1) {
1592 /* musb_ep_select(musb->mregs, ep_num); */
1593 /* REVISIT just retval |= ep->tx_irq(...) */
1594 retval = IRQ_HANDLED;
1595 if (devctl & MUSB_DEVCTL_HM) {
1596 if (is_host_capable())
1597 musb_host_tx(musb, ep_num);
1598 } else {
1599 if (is_peripheral_capable())
1600 musb_g_tx(musb, ep_num);
1601 }
1602 }
1603 reg >>= 1;
1604 ep_num++;
1605 }
1606
1607 /* finish handling "global" interrupts after handling fifos */
1608 if (musb->int_usb)
1609 retval |= musb_stage2_irq(musb,
1610 musb->int_usb, devctl, power);
1611
1612 return retval;
1613}
1614
1615
1616#ifndef CONFIG_MUSB_PIO_ONLY
1617static int __initdata use_dma = 1;
1618
1619/* "modprobe ... use_dma=0" etc */
1620module_param(use_dma, bool, 0);
1621MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1622
1623void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1624{
1625 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1626
1627 /* called with controller lock already held */
1628
1629 if (!epnum) {
1630#ifndef CONFIG_USB_TUSB_OMAP_DMA
1631 if (!is_cppi_enabled()) {
1632 /* endpoint 0 */
1633 if (devctl & MUSB_DEVCTL_HM)
1634 musb_h_ep0_irq(musb);
1635 else
1636 musb_g_ep0_irq(musb);
1637 }
1638#endif
1639 } else {
1640 /* endpoints 1..15 */
1641 if (transmit) {
1642 if (devctl & MUSB_DEVCTL_HM) {
1643 if (is_host_capable())
1644 musb_host_tx(musb, epnum);
1645 } else {
1646 if (is_peripheral_capable())
1647 musb_g_tx(musb, epnum);
1648 }
1649 } else {
1650 /* receive */
1651 if (devctl & MUSB_DEVCTL_HM) {
1652 if (is_host_capable())
1653 musb_host_rx(musb, epnum);
1654 } else {
1655 if (is_peripheral_capable())
1656 musb_g_rx(musb, epnum);
1657 }
1658 }
1659 }
1660}
1661
1662#else
1663#define use_dma 0
1664#endif
1665
1666/*-------------------------------------------------------------------------*/
1667
1668#ifdef CONFIG_SYSFS
1669
1670static ssize_t
1671musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1672{
1673 struct musb *musb = dev_to_musb(dev);
1674 unsigned long flags;
1675 int ret = -EINVAL;
1676
1677 spin_lock_irqsave(&musb->lock, flags);
1678 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1679 spin_unlock_irqrestore(&musb->lock, flags);
1680
1681 return ret;
1682}
1683
1684static ssize_t
1685musb_mode_store(struct device *dev, struct device_attribute *attr,
1686 const char *buf, size_t n)
1687{
1688 struct musb *musb = dev_to_musb(dev);
1689 unsigned long flags;
1690
1691 spin_lock_irqsave(&musb->lock, flags);
1692 if (!strncmp(buf, "host", 4))
1693 musb_platform_set_mode(musb, MUSB_HOST);
1694 if (!strncmp(buf, "peripheral", 10))
1695 musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1696 if (!strncmp(buf, "otg", 3))
1697 musb_platform_set_mode(musb, MUSB_OTG);
1698 spin_unlock_irqrestore(&musb->lock, flags);
1699
1700 return n;
1701}
1702static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1703
1704static ssize_t
1705musb_vbus_store(struct device *dev, struct device_attribute *attr,
1706 const char *buf, size_t n)
1707{
1708 struct musb *musb = dev_to_musb(dev);
1709 unsigned long flags;
1710 unsigned long val;
1711
1712 if (sscanf(buf, "%lu", &val) < 1) {
1713 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
1714 return -EINVAL;
1715 }
1716
1717 spin_lock_irqsave(&musb->lock, flags);
1718 musb->a_wait_bcon = val;
1719 if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON)
1720 musb->is_active = 0;
1721 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1722 spin_unlock_irqrestore(&musb->lock, flags);
1723
1724 return n;
1725}
1726
1727static ssize_t
1728musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1729{
1730 struct musb *musb = dev_to_musb(dev);
1731 unsigned long flags;
1732 unsigned long val;
1733 int vbus;
1734
1735 spin_lock_irqsave(&musb->lock, flags);
1736 val = musb->a_wait_bcon;
1737 vbus = musb_platform_get_vbus_status(musb);
1738 spin_unlock_irqrestore(&musb->lock, flags);
1739
1740 return sprintf(buf, "Vbus %s, timeout %lu\n",
1741 vbus ? "on" : "off", val);
1742}
1743static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1744
1745#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1746
1747/* Gadget drivers can't know that a host is connected so they might want
1748 * to start SRP, but users can. This allows userspace to trigger SRP.
1749 */
1750static ssize_t
1751musb_srp_store(struct device *dev, struct device_attribute *attr,
1752 const char *buf, size_t n)
1753{
1754 struct musb *musb = dev_to_musb(dev);
1755 unsigned short srp;
1756
1757 if (sscanf(buf, "%hu", &srp) != 1
1758 || (srp != 1)) {
1759 printk(KERN_ERR "SRP: Value must be 1\n");
1760 return -EINVAL;
1761 }
1762
1763 if (srp == 1)
1764 musb_g_wakeup(musb);
1765
1766 return n;
1767}
1768static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1769
1770#endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1771
1772#endif /* sysfs */
1773
1774/* Only used to provide driver mode change events */
1775static void musb_irq_work(struct work_struct *data)
1776{
1777 struct musb *musb = container_of(data, struct musb, irq_work);
1778 static int old_state;
1779
1780 if (musb->xceiv.state != old_state) {
1781 old_state = musb->xceiv.state;
1782 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1783 }
1784}
1785
1786/* --------------------------------------------------------------------------
1787 * Init support
1788 */
1789
1790static struct musb *__init
1791allocate_instance(struct device *dev, void __iomem *mbase)
1792{
1793 struct musb *musb;
1794 struct musb_hw_ep *ep;
1795 int epnum;
1796#ifdef CONFIG_USB_MUSB_HDRC_HCD
1797 struct usb_hcd *hcd;
1798
1799 hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id);
1800 if (!hcd)
1801 return NULL;
1802 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1803
1804 musb = hcd_to_musb(hcd);
1805 INIT_LIST_HEAD(&musb->control);
1806 INIT_LIST_HEAD(&musb->in_bulk);
1807 INIT_LIST_HEAD(&musb->out_bulk);
1808
1809 hcd->uses_new_polling = 1;
1810
1811 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1812#else
1813 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1814 if (!musb)
1815 return NULL;
1816 dev_set_drvdata(dev, musb);
1817
1818#endif
1819
1820 musb->mregs = mbase;
1821 musb->ctrl_base = mbase;
1822 musb->nIrq = -ENODEV;
1823 for (epnum = 0, ep = musb->endpoints;
1824 epnum < MUSB_C_NUM_EPS;
1825 epnum++, ep++) {
1826
1827 ep->musb = musb;
1828 ep->epnum = epnum;
1829 }
1830
1831 musb->controller = dev;
1832 return musb;
1833}
1834
1835static void musb_free(struct musb *musb)
1836{
1837 /* this has multiple entry modes. it handles fault cleanup after
1838 * probe(), where things may be partially set up, as well as rmmod
1839 * cleanup after everything's been de-activated.
1840 */
1841
1842#ifdef CONFIG_SYSFS
1843 device_remove_file(musb->controller, &dev_attr_mode);
1844 device_remove_file(musb->controller, &dev_attr_vbus);
1845#ifdef CONFIG_USB_MUSB_OTG
1846 device_remove_file(musb->controller, &dev_attr_srp);
1847#endif
1848#endif
1849
1850#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1851 musb_gadget_cleanup(musb);
1852#endif
1853
1854 if (musb->nIrq >= 0) {
1855 disable_irq_wake(musb->nIrq);
1856 free_irq(musb->nIrq, musb);
1857 }
1858 if (is_dma_capable() && musb->dma_controller) {
1859 struct dma_controller *c = musb->dma_controller;
1860
1861 (void) c->stop(c);
1862 dma_controller_destroy(c);
1863 }
1864
1865 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1866 musb_platform_exit(musb);
1867 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1868
1869 if (musb->clock) {
1870 clk_disable(musb->clock);
1871 clk_put(musb->clock);
1872 }
1873
1874#ifdef CONFIG_USB_MUSB_OTG
1875 put_device(musb->xceiv.dev);
1876#endif
1877
1878#ifdef CONFIG_USB_MUSB_HDRC_HCD
1879 usb_put_hcd(musb_to_hcd(musb));
1880#else
1881 kfree(musb);
1882#endif
1883}
1884
1885/*
1886 * Perform generic per-controller initialization.
1887 *
1888 * @pDevice: the controller (already clocked, etc)
1889 * @nIrq: irq
1890 * @mregs: virtual address of controller registers,
1891 * not yet corrected for platform-specific offsets
1892 */
1893static int __init
1894musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1895{
1896 int status;
1897 struct musb *musb;
1898 struct musb_hdrc_platform_data *plat = dev->platform_data;
1899
1900 /* The driver might handle more features than the board; OK.
1901 * Fail when the board needs a feature that's not enabled.
1902 */
1903 if (!plat) {
1904 dev_dbg(dev, "no platform_data?\n");
1905 return -ENODEV;
1906 }
1907 switch (plat->mode) {
1908 case MUSB_HOST:
1909#ifdef CONFIG_USB_MUSB_HDRC_HCD
1910 break;
1911#else
1912 goto bad_config;
1913#endif
1914 case MUSB_PERIPHERAL:
1915#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1916 break;
1917#else
1918 goto bad_config;
1919#endif
1920 case MUSB_OTG:
1921#ifdef CONFIG_USB_MUSB_OTG
1922 break;
1923#else
1924bad_config:
1925#endif
1926 default:
1927 dev_err(dev, "incompatible Kconfig role setting\n");
1928 return -EINVAL;
1929 }
1930
1931 /* allocate */
1932 musb = allocate_instance(dev, ctrl);
1933 if (!musb)
1934 return -ENOMEM;
1935
1936 spin_lock_init(&musb->lock);
1937 musb->board_mode = plat->mode;
1938 musb->board_set_power = plat->set_power;
1939 musb->set_clock = plat->set_clock;
1940 musb->min_power = plat->min_power;
1941
1942 /* Clock usage is chip-specific ... functional clock (DaVinci,
1943 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1944 * code does is make sure a clock handle is available; platform
1945 * code manages it during start/stop and suspend/resume.
1946 */
1947 if (plat->clock) {
1948 musb->clock = clk_get(dev, plat->clock);
1949 if (IS_ERR(musb->clock)) {
1950 status = PTR_ERR(musb->clock);
1951 musb->clock = NULL;
1952 goto fail;
1953 }
1954 }
1955
1956 /* assume vbus is off */
1957
1958 /* platform adjusts musb->mregs and musb->isr if needed,
1959 * and activates clocks
1960 */
1961 musb->isr = generic_interrupt;
1962 status = musb_platform_init(musb);
1963
1964 if (status < 0)
1965 goto fail;
1966 if (!musb->isr) {
1967 status = -ENODEV;
1968 goto fail2;
1969 }
1970
1971#ifndef CONFIG_MUSB_PIO_ONLY
1972 if (use_dma && dev->dma_mask) {
1973 struct dma_controller *c;
1974
1975 c = dma_controller_create(musb, musb->mregs);
1976 musb->dma_controller = c;
1977 if (c)
1978 (void) c->start(c);
1979 }
1980#endif
1981 /* ideally this would be abstracted in platform setup */
1982 if (!is_dma_capable() || !musb->dma_controller)
1983 dev->dma_mask = NULL;
1984
1985 /* be sure interrupts are disabled before connecting ISR */
1986 musb_platform_disable(musb);
1987 musb_generic_disable(musb);
1988
1989 /* setup musb parts of the core (especially endpoints) */
1990 status = musb_core_init(plat->multipoint
1991 ? MUSB_CONTROLLER_MHDRC
1992 : MUSB_CONTROLLER_HDRC, musb);
1993 if (status < 0)
1994 goto fail2;
1995
1996 /* Init IRQ workqueue before request_irq */
1997 INIT_WORK(&musb->irq_work, musb_irq_work);
1998
1999 /* attach to the IRQ */
2000 if (request_irq(nIrq, musb->isr, 0, dev->bus_id, musb)) {
2001 dev_err(dev, "request_irq %d failed!\n", nIrq);
2002 status = -ENODEV;
2003 goto fail2;
2004 }
2005 musb->nIrq = nIrq;
2006/* FIXME this handles wakeup irqs wrong */
2007 if (enable_irq_wake(nIrq) == 0)
2008 device_init_wakeup(dev, 1);
2009
2010 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
2011 musb_driver_name,
2012 ({char *s;
2013 switch (musb->board_mode) {
2014 case MUSB_HOST: s = "Host"; break;
2015 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2016 default: s = "OTG"; break;
2017 }; s; }),
2018 ctrl,
2019 (is_dma_capable() && musb->dma_controller)
2020 ? "DMA" : "PIO",
2021 musb->nIrq);
2022
2023#ifdef CONFIG_USB_MUSB_HDRC_HCD
2024 /* host side needs more setup, except for no-host modes */
2025 if (musb->board_mode != MUSB_PERIPHERAL) {
2026 struct usb_hcd *hcd = musb_to_hcd(musb);
2027
2028 if (musb->board_mode == MUSB_OTG)
2029 hcd->self.otg_port = 1;
2030 musb->xceiv.host = &hcd->self;
2031 hcd->power_budget = 2 * (plat->power ? : 250);
2032 }
2033#endif /* CONFIG_USB_MUSB_HDRC_HCD */
2034
2035 /* For the host-only role, we can activate right away.
2036 * (We expect the ID pin to be forcibly grounded!!)
2037 * Otherwise, wait till the gadget driver hooks up.
2038 */
2039 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2040 MUSB_HST_MODE(musb);
2041 musb->xceiv.default_a = 1;
2042 musb->xceiv.state = OTG_STATE_A_IDLE;
2043
2044 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2045
2046 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2047 "HOST", status,
2048 musb_readb(musb->mregs, MUSB_DEVCTL),
2049 (musb_readb(musb->mregs, MUSB_DEVCTL)
2050 & MUSB_DEVCTL_BDEVICE
2051 ? 'B' : 'A'));
2052
2053 } else /* peripheral is enabled */ {
2054 MUSB_DEV_MODE(musb);
2055 musb->xceiv.default_a = 0;
2056 musb->xceiv.state = OTG_STATE_B_IDLE;
2057
2058 status = musb_gadget_setup(musb);
2059
2060 DBG(1, "%s mode, status %d, dev%02x\n",
2061 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2062 status,
2063 musb_readb(musb->mregs, MUSB_DEVCTL));
2064
2065 }
2066
2067 if (status == 0)
2068 musb_debug_create("driver/musb_hdrc", musb);
2069 else {
2070fail:
2071 if (musb->clock)
2072 clk_put(musb->clock);
2073 device_init_wakeup(dev, 0);
2074 musb_free(musb);
2075 return status;
2076 }
2077
2078#ifdef CONFIG_SYSFS
2079 status = device_create_file(dev, &dev_attr_mode);
2080 status = device_create_file(dev, &dev_attr_vbus);
2081#ifdef CONFIG_USB_GADGET_MUSB_HDRC
2082 status = device_create_file(dev, &dev_attr_srp);
2083#endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2084 status = 0;
2085#endif
2086
2087 return status;
2088
2089fail2:
2090 musb_platform_exit(musb);
2091 goto fail;
2092}
2093
2094/*-------------------------------------------------------------------------*/
2095
2096/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2097 * bridge to a platform device; this driver then suffices.
2098 */
2099
2100#ifndef CONFIG_MUSB_PIO_ONLY
2101static u64 *orig_dma_mask;
2102#endif
2103
2104static int __init musb_probe(struct platform_device *pdev)
2105{
2106 struct device *dev = &pdev->dev;
2107 int irq = platform_get_irq(pdev, 0);
2108 struct resource *iomem;
2109 void __iomem *base;
2110
2111 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2112 if (!iomem || irq == 0)
2113 return -ENODEV;
2114
2115 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2116 if (!base) {
2117 dev_err(dev, "ioremap failed\n");
2118 return -ENOMEM;
2119 }
2120
2121#ifndef CONFIG_MUSB_PIO_ONLY
2122 /* clobbered by use_dma=n */
2123 orig_dma_mask = dev->dma_mask;
2124#endif
2125 return musb_init_controller(dev, irq, base);
2126}
2127
2128static int __devexit musb_remove(struct platform_device *pdev)
2129{
2130 struct musb *musb = dev_to_musb(&pdev->dev);
2131 void __iomem *ctrl_base = musb->ctrl_base;
2132
2133 /* this gets called on rmmod.
2134 * - Host mode: host may still be active
2135 * - Peripheral mode: peripheral is deactivated (or never-activated)
2136 * - OTG mode: both roles are deactivated (or never-activated)
2137 */
2138 musb_shutdown(pdev);
2139 musb_debug_delete("driver/musb_hdrc", musb);
2140#ifdef CONFIG_USB_MUSB_HDRC_HCD
2141 if (musb->board_mode == MUSB_HOST)
2142 usb_remove_hcd(musb_to_hcd(musb));
2143#endif
2144 musb_free(musb);
2145 iounmap(ctrl_base);
2146 device_init_wakeup(&pdev->dev, 0);
2147#ifndef CONFIG_MUSB_PIO_ONLY
2148 pdev->dev.dma_mask = orig_dma_mask;
2149#endif
2150 return 0;
2151}
2152
2153#ifdef CONFIG_PM
2154
2155static int musb_suspend(struct platform_device *pdev, pm_message_t message)
2156{
2157 unsigned long flags;
2158 struct musb *musb = dev_to_musb(&pdev->dev);
2159
2160 if (!musb->clock)
2161 return 0;
2162
2163 spin_lock_irqsave(&musb->lock, flags);
2164
2165 if (is_peripheral_active(musb)) {
2166 /* FIXME force disconnect unless we know USB will wake
2167 * the system up quickly enough to respond ...
2168 */
2169 } else if (is_host_active(musb)) {
2170 /* we know all the children are suspended; sometimes
2171 * they will even be wakeup-enabled.
2172 */
2173 }
2174
2175 if (musb->set_clock)
2176 musb->set_clock(musb->clock, 0);
2177 else
2178 clk_disable(musb->clock);
2179 spin_unlock_irqrestore(&musb->lock, flags);
2180 return 0;
2181}
2182
2183static int musb_resume(struct platform_device *pdev)
2184{
2185 unsigned long flags;
2186 struct musb *musb = dev_to_musb(&pdev->dev);
2187
2188 if (!musb->clock)
2189 return 0;
2190
2191 spin_lock_irqsave(&musb->lock, flags);
2192
2193 if (musb->set_clock)
2194 musb->set_clock(musb->clock, 1);
2195 else
2196 clk_enable(musb->clock);
2197
2198 /* for static cmos like DaVinci, register values were preserved
2199 * unless for some reason the whole soc powered down and we're
2200 * not treating that as a whole-system restart (e.g. swsusp)
2201 */
2202 spin_unlock_irqrestore(&musb->lock, flags);
2203 return 0;
2204}
2205
2206#else
2207#define musb_suspend NULL
2208#define musb_resume NULL
2209#endif
2210
2211static struct platform_driver musb_driver = {
2212 .driver = {
2213 .name = (char *)musb_driver_name,
2214 .bus = &platform_bus_type,
2215 .owner = THIS_MODULE,
2216 },
2217 .remove = __devexit_p(musb_remove),
2218 .shutdown = musb_shutdown,
2219 .suspend = musb_suspend,
2220 .resume = musb_resume,
2221};
2222
2223/*-------------------------------------------------------------------------*/
2224
2225static int __init musb_init(void)
2226{
2227#ifdef CONFIG_USB_MUSB_HDRC_HCD
2228 if (usb_disabled())
2229 return 0;
2230#endif
2231
2232 pr_info("%s: version " MUSB_VERSION ", "
2233#ifdef CONFIG_MUSB_PIO_ONLY
2234 "pio"
2235#elif defined(CONFIG_USB_TI_CPPI_DMA)
2236 "cppi-dma"
2237#elif defined(CONFIG_USB_INVENTRA_DMA)
2238 "musb-dma"
2239#elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2240 "tusb-omap-dma"
2241#else
2242 "?dma?"
2243#endif
2244 ", "
2245#ifdef CONFIG_USB_MUSB_OTG
2246 "otg (peripheral+host)"
2247#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2248 "peripheral"
2249#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2250 "host"
2251#endif
2252 ", debug=%d\n",
2253 musb_driver_name, debug);
2254 return platform_driver_probe(&musb_driver, musb_probe);
2255}
2256
2257/* make us init after usbcore and before usb
2258 * gadget and host-side drivers start to register
2259 */
2260subsys_initcall(musb_init);
2261
2262static void __exit musb_cleanup(void)
2263{
2264 platform_driver_unregister(&musb_driver);
2265}
2266module_exit(musb_cleanup);
Linux kernel - Deliverables
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