projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
usb: musb: dsps: remove duplicate check on resource
[deliverable/linux.git] / drivers / usb / musb / musb_core.c
CommitLineData
550a7375
FB		 1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
550a7375 85 * - platform_device for addressing, irq, and platform_data
5ae477b0 86 * - platform_data is mostly for board-specific information
c767c1c6 87 * (plus recentrly, SOC or family details)
550a7375
FB		 88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
550a7375
FB		 96#include <linux/list.h>
97#include <linux/kobject.h>
9303961f 98#include <linux/prefetch.h>
550a7375
FB		 99#include <linux/platform_device.h>
100#include <linux/io.h>
8d2421e6 101#include <linux/dma-mapping.h>
550a7375 102
550a7375
FB		 103#include "musb_core.h"
104
f7f9d63e 105#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
550a7375
FB		 106
107
550a7375
FB		 108#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110
e8164f64 111#define MUSB_VERSION "6.0"
550a7375
FB		 112
113#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114
05ac10dd 115#define MUSB_DRIVER_NAME "musb-hdrc"
550a7375
FB		 116const char musb_driver_name[] = MUSB_DRIVER_NAME;
117
118MODULE_DESCRIPTION(DRIVER_INFO);
119MODULE_AUTHOR(DRIVER_AUTHOR);
120MODULE_LICENSE("GPL");
121MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122
123
124/*-------------------------------------------------------------------------*/
125
126static inline struct musb *dev_to_musb(struct device *dev)
127{
550a7375 128 return dev_get_drvdata(dev);
550a7375
FB		 129}
130
131/*-------------------------------------------------------------------------*/
132
ffb865b1 133#ifndef CONFIG_BLACKFIN
b96d3b08 134static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
ffb865b1 135{
b96d3b08 136 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 137 int i = 0;
138 u8 r;
139 u8 power;
bf070bc1
GI		 140 int ret;
141
142 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 143
144 /* Make sure the transceiver is not in low power mode */
145 power = musb_readb(addr, MUSB_POWER);
146 power &= ~MUSB_POWER_SUSPENDM;
147 musb_writeb(addr, MUSB_POWER, power);
148
149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
151 */
152
153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
156
157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158 & MUSB_ULPI_REG_CMPLT)) {
159 i++;
bf070bc1
GI		 160 if (i == 10000) {
161 ret = -ETIMEDOUT;
162 goto out;
163 }
ffb865b1
HK		 164
165 }
166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167 r &= ~MUSB_ULPI_REG_CMPLT;
168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
169
bf070bc1
GI		 170 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
171
172out:
173 pm_runtime_put(phy->io_dev);
174
175 return ret;
ffb865b1
HK		 176}
177
b96d3b08 178static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
ffb865b1 179{
b96d3b08 180 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 181 int i = 0;
182 u8 r = 0;
183 u8 power;
bf070bc1
GI		 184 int ret = 0;
185
186 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 187
188 /* Make sure the transceiver is not in low power mode */
189 power = musb_readb(addr, MUSB_POWER);
190 power &= ~MUSB_POWER_SUSPENDM;
191 musb_writeb(addr, MUSB_POWER, power);
192
193 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
194 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
195 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
196
197 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
198 & MUSB_ULPI_REG_CMPLT)) {
199 i++;
bf070bc1
GI		 200 if (i == 10000) {
201 ret = -ETIMEDOUT;
202 goto out;
203 }
ffb865b1
HK		 204 }
205
206 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
207 r &= ~MUSB_ULPI_REG_CMPLT;
208 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
209
bf070bc1
GI		 210out:
211 pm_runtime_put(phy->io_dev);
212
213 return ret;
ffb865b1
HK		 214}
215#else
f2263db7
MF		 216#define musb_ulpi_read NULL
217#define musb_ulpi_write NULL
ffb865b1
HK		 218#endif
219
b96d3b08 220static struct usb_phy_io_ops musb_ulpi_access = {
ffb865b1
HK		 221 .read = musb_ulpi_read,
222 .write = musb_ulpi_write,
223};
224
225/*-------------------------------------------------------------------------*/
226
7c925546 227#if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
c6cf8b00 228
550a7375
FB		 229/*
230 * Load an endpoint's FIFO
231 */
232void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
233{
5c8a86e1 234 struct musb *musb = hw_ep->musb;
550a7375
FB		 235 void __iomem *fifo = hw_ep->fifo;
236
603fe2b2
AKG		 237 if (unlikely(len == 0))
238 return;
239
550a7375
FB		 240 prefetch((u8 *)src);
241
5c8a86e1 242 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 243 'T', hw_ep->epnum, fifo, len, src);
244
245 /* we can't assume unaligned reads work */
246 if (likely((0x01 & (unsigned long) src) == 0)) {
247 u16 index = 0;
248
249 /* best case is 32bit-aligned source address */
250 if ((0x02 & (unsigned long) src) == 0) {
251 if (len >= 4) {
2bf0a8f6 252 iowrite32_rep(fifo, src + index, len >> 2);
550a7375
FB		 253 index += len & ~0x03;
254 }
255 if (len & 0x02) {
256 musb_writew(fifo, 0, *(u16 *)&src[index]);
257 index += 2;
258 }
259 } else {
260 if (len >= 2) {
2bf0a8f6 261 iowrite16_rep(fifo, src + index, len >> 1);
550a7375
FB		 262 index += len & ~0x01;
263 }
264 }
265 if (len & 0x01)
266 musb_writeb(fifo, 0, src[index]);
267 } else {
268 /* byte aligned */
2bf0a8f6 269 iowrite8_rep(fifo, src, len);
550a7375
FB		 270 }
271}
272
843bb1d0 273#if !defined(CONFIG_USB_MUSB_AM35X)
550a7375
FB		 274/*
275 * Unload an endpoint's FIFO
276 */
277void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
278{
5c8a86e1 279 struct musb *musb = hw_ep->musb;
550a7375
FB		 280 void __iomem *fifo = hw_ep->fifo;
281
603fe2b2
AKG		 282 if (unlikely(len == 0))
283 return;
284
5c8a86e1 285 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 286 'R', hw_ep->epnum, fifo, len, dst);
287
288 /* we can't assume unaligned writes work */
289 if (likely((0x01 & (unsigned long) dst) == 0)) {
290 u16 index = 0;
291
292 /* best case is 32bit-aligned destination address */
293 if ((0x02 & (unsigned long) dst) == 0) {
294 if (len >= 4) {
2bf0a8f6 295 ioread32_rep(fifo, dst, len >> 2);
550a7375
FB		 296 index = len & ~0x03;
297 }
298 if (len & 0x02) {
299 *(u16 *)&dst[index] = musb_readw(fifo, 0);
300 index += 2;
301 }
302 } else {
303 if (len >= 2) {
2bf0a8f6 304 ioread16_rep(fifo, dst, len >> 1);
550a7375
FB		 305 index = len & ~0x01;
306 }
307 }
308 if (len & 0x01)
309 dst[index] = musb_readb(fifo, 0);
310 } else {
311 /* byte aligned */
2bf0a8f6 312 ioread8_rep(fifo, dst, len);
550a7375
FB		 313 }
314}
843bb1d0 315#endif
550a7375
FB		 316
317#endif /* normal PIO */
318
319
320/*-------------------------------------------------------------------------*/
321
322/* for high speed test mode; see USB 2.0 spec 7.1.20 */
323static const u8 musb_test_packet[53] = {
324 /* implicit SYNC then DATA0 to start */
325
326 /* JKJKJKJK x9 */
327 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
328 /* JJKKJJKK x8 */
329 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
330 /* JJJJKKKK x8 */
331 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
332 /* JJJJJJJKKKKKKK x8 */
333 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
334 /* JJJJJJJK x8 */
335 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
336 /* JKKKKKKK x10, JK */
337 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
338
339 /* implicit CRC16 then EOP to end */
340};
341
342void musb_load_testpacket(struct musb *musb)
343{
344 void __iomem *regs = musb->endpoints[0].regs;
345
346 musb_ep_select(musb->mregs, 0);
347 musb_write_fifo(musb->control_ep,
348 sizeof(musb_test_packet), musb_test_packet);
349 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
350}
351
352/*-------------------------------------------------------------------------*/
353
550a7375
FB		 354/*
355 * Handles OTG hnp timeouts, such as b_ase0_brst
356 */
a156544b 357static void musb_otg_timer_func(unsigned long data)
550a7375
FB		 358{
359 struct musb *musb = (struct musb *)data;
360 unsigned long flags;
361
362 spin_lock_irqsave(&musb->lock, flags);
84e250ff 363 switch (musb->xceiv->state) {
550a7375 364 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 365 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
550a7375 366 musb_g_disconnect(musb);
84e250ff 367 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 368 musb->is_active = 0;
369 break;
ab983f2a 370 case OTG_STATE_A_SUSPEND:
550a7375 371 case OTG_STATE_A_WAIT_BCON:
5c8a86e1 372 dev_dbg(musb->controller, "HNP: %s timeout\n",
42c0bf1c 373 usb_otg_state_string(musb->xceiv->state));
743411b3 374 musb_platform_set_vbus(musb, 0);
ab983f2a 375 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
550a7375
FB		 376 break;
377 default:
5c8a86e1 378 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
42c0bf1c 379 usb_otg_state_string(musb->xceiv->state));
550a7375 380 }
550a7375
FB		 381 spin_unlock_irqrestore(&musb->lock, flags);
382}
383
550a7375 384/*
f7f9d63e 385 * Stops the HNP transition. Caller must take care of locking.
550a7375
FB		 386 */
387void musb_hnp_stop(struct musb *musb)
388{
8b125df5 389 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 390 void __iomem *mbase = musb->mregs;
391 u8 reg;
392
42c0bf1c
FB		 393 dev_dbg(musb->controller, "HNP: stop from %s\n",
394 usb_otg_state_string(musb->xceiv->state));
ab983f2a 395
84e250ff 396 switch (musb->xceiv->state) {
550a7375 397 case OTG_STATE_A_PERIPHERAL:
550a7375 398 musb_g_disconnect(musb);
5c8a86e1 399 dev_dbg(musb->controller, "HNP: back to %s\n",
42c0bf1c 400 usb_otg_state_string(musb->xceiv->state));
550a7375
FB		 401 break;
402 case OTG_STATE_B_HOST:
5c8a86e1 403 dev_dbg(musb->controller, "HNP: Disabling HR\n");
74c2e936
DM		 404 if (hcd)
405 hcd->self.is_b_host = 0;
84e250ff 406 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 407 MUSB_DEV_MODE(musb);
408 reg = musb_readb(mbase, MUSB_POWER);
409 reg |= MUSB_POWER_SUSPENDM;
410 musb_writeb(mbase, MUSB_POWER, reg);
411 /* REVISIT: Start SESSION_REQUEST here? */
412 break;
413 default:
5c8a86e1 414 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
42c0bf1c 415 usb_otg_state_string(musb->xceiv->state));
550a7375
FB		 416 }
417
418 /*
419 * When returning to A state after HNP, avoid hub_port_rebounce(),
420 * which cause occasional OPT A "Did not receive reset after connect"
421 * errors.
422 */
749da5f8 423 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
550a7375
FB		 424}
425
550a7375
FB		 426/*
427 * Interrupt Service Routine to record USB "global" interrupts.
428 * Since these do not happen often and signify things of
429 * paramount importance, it seems OK to check them individually;
430 * the order of the tests is specified in the manual
431 *
432 * @param musb instance pointer
433 * @param int_usb register contents
434 * @param devctl
435 * @param power
436 */
437
550a7375 438static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
b11e94d0 439 u8 devctl)
550a7375
FB		 440{
441 irqreturn_t handled = IRQ_NONE;
550a7375 442
b11e94d0 443 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
550a7375
FB		 444 int_usb);
445
446 /* in host mode, the peripheral may issue remote wakeup.
447 * in peripheral mode, the host may resume the link.
448 * spurious RESUME irqs happen too, paired with SUSPEND.
449 */
450 if (int_usb & MUSB_INTR_RESUME) {
451 handled = IRQ_HANDLED;
42c0bf1c 452 dev_dbg(musb->controller, "RESUME (%s)\n", usb_otg_state_string(musb->xceiv->state));
550a7375
FB		 453
454 if (devctl & MUSB_DEVCTL_HM) {
aa471456 455 void __iomem *mbase = musb->mregs;
b11e94d0 456 u8 power;
aa471456 457
84e250ff 458 switch (musb->xceiv->state) {
550a7375
FB		 459 case OTG_STATE_A_SUSPEND:
460 /* remote wakeup? later, GetPortStatus
461 * will stop RESUME signaling
462 */
463
b11e94d0 464 power = musb_readb(musb->mregs, MUSB_POWER);
550a7375
FB		 465 if (power & MUSB_POWER_SUSPENDM) {
466 /* spurious */
467 musb->int_usb &= ~MUSB_INTR_SUSPEND;
5c8a86e1 468 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
550a7375
FB		 469 break;
470 }
471
472 power &= ~MUSB_POWER_SUSPENDM;
473 musb_writeb(mbase, MUSB_POWER,
474 power | MUSB_POWER_RESUME);
475
476 musb->port1_status |=
477 (USB_PORT_STAT_C_SUSPEND << 16)
478 | MUSB_PORT_STAT_RESUME;
30d361bf
DM		 479 musb->rh_timer = jiffies
480 + msecs_to_jiffies(20);
8ed1fb79 481 schedule_delayed_work(
9ccfaf74
DM		 482 &musb->finish_resume_work,
483 msecs_to_jiffies(20));
550a7375 484
84e250ff 485 musb->xceiv->state = OTG_STATE_A_HOST;
550a7375 486 musb->is_active = 1;
0b3eba44 487 musb_host_resume_root_hub(musb);
550a7375
FB		 488 break;
489 case OTG_STATE_B_WAIT_ACON:
84e250ff 490 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 491 musb->is_active = 1;
492 MUSB_DEV_MODE(musb);
493 break;
494 default:
495 WARNING("bogus %s RESUME (%s)\n",
496 "host",
42c0bf1c 497 usb_otg_state_string(musb->xceiv->state));
550a7375 498 }
550a7375 499 } else {
84e250ff 500 switch (musb->xceiv->state) {
550a7375
FB		 501 case OTG_STATE_A_SUSPEND:
502 /* possibly DISCONNECT is upcoming */
84e250ff 503 musb->xceiv->state = OTG_STATE_A_HOST;
0b3eba44 504 musb_host_resume_root_hub(musb);
550a7375 505 break;
550a7375
FB		 506 case OTG_STATE_B_WAIT_ACON:
507 case OTG_STATE_B_PERIPHERAL:
508 /* disconnect while suspended? we may
509 * not get a disconnect irq...
510 */
511 if ((devctl & MUSB_DEVCTL_VBUS)
512 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
513 ) {
514 musb->int_usb |= MUSB_INTR_DISCONNECT;
515 musb->int_usb &= ~MUSB_INTR_SUSPEND;
516 break;
517 }
518 musb_g_resume(musb);
519 break;
520 case OTG_STATE_B_IDLE:
521 musb->int_usb &= ~MUSB_INTR_SUSPEND;
522 break;
550a7375
FB		 523 default:
524 WARNING("bogus %s RESUME (%s)\n",
525 "peripheral",
42c0bf1c 526 usb_otg_state_string(musb->xceiv->state));
550a7375
FB		 527 }
528 }
529 }
530
550a7375
FB		 531 /* see manual for the order of the tests */
532 if (int_usb & MUSB_INTR_SESSREQ) {
aa471456
FB		 533 void __iomem *mbase = musb->mregs;
534
19aab56c
HK		 535 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
536 && (devctl & MUSB_DEVCTL_BDEVICE)) {
5c8a86e1 537 dev_dbg(musb->controller, "SessReq while on B state\n");
a6038ee7
HK		 538 return IRQ_HANDLED;
539 }
540
5c8a86e1 541 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
42c0bf1c 542 usb_otg_state_string(musb->xceiv->state));
550a7375
FB		 543
544 /* IRQ arrives from ID pin sense or (later, if VBUS power
545 * is removed) SRP. responses are time critical:
546 * - turn on VBUS (with silicon-specific mechanism)
547 * - go through A_WAIT_VRISE
548 * - ... to A_WAIT_BCON.
549 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
550 */
551 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
552 musb->ep0_stage = MUSB_EP0_START;
84e250ff 553 musb->xceiv->state = OTG_STATE_A_IDLE;
550a7375 554 MUSB_HST_MODE(musb);
743411b3 555 musb_platform_set_vbus(musb, 1);
550a7375
FB		 556
557 handled = IRQ_HANDLED;
558 }
559
560 if (int_usb & MUSB_INTR_VBUSERROR) {
561 int ignore = 0;
562
563 /* During connection as an A-Device, we may see a short
564 * current spikes causing voltage drop, because of cable
565 * and peripheral capacitance combined with vbus draw.
566 * (So: less common with truly self-powered devices, where
567 * vbus doesn't act like a power supply.)
568 *
569 * Such spikes are short; usually less than ~500 usec, max
570 * of ~2 msec. That is, they're not sustained overcurrent
571 * errors, though they're reported using VBUSERROR irqs.
572 *
573 * Workarounds: (a) hardware: use self powered devices.
574 * (b) software: ignore non-repeated VBUS errors.
575 *
576 * REVISIT: do delays from lots of DEBUG_KERNEL checks
577 * make trouble here, keeping VBUS < 4.4V ?
578 */
84e250ff 579 switch (musb->xceiv->state) {
550a7375
FB		 580 case OTG_STATE_A_HOST:
581 /* recovery is dicey once we've gotten past the
582 * initial stages of enumeration, but if VBUS
583 * stayed ok at the other end of the link, and
584 * another reset is due (at least for high speed,
585 * to redo the chirp etc), it might work OK...
586 */
587 case OTG_STATE_A_WAIT_BCON:
588 case OTG_STATE_A_WAIT_VRISE:
589 if (musb->vbuserr_retry) {
aa471456
FB		 590 void __iomem *mbase = musb->mregs;
591
550a7375
FB		 592 musb->vbuserr_retry--;
593 ignore = 1;
594 devctl |= MUSB_DEVCTL_SESSION;
595 musb_writeb(mbase, MUSB_DEVCTL, devctl);
596 } else {
597 musb->port1_status |=
749da5f8
AS		 598 USB_PORT_STAT_OVERCURRENT
599 | (USB_PORT_STAT_C_OVERCURRENT << 16);
550a7375
FB		 600 }
601 break;
602 default:
603 break;
604 }
605
54485116
GI		 606 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
607 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
42c0bf1c 608 usb_otg_state_string(musb->xceiv->state),
550a7375
FB		 609 devctl,
610 ({ char *s;
611 switch (devctl & MUSB_DEVCTL_VBUS) {
612 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
613 s = "<SessEnd"; break;
614 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
615 s = "<AValid"; break;
616 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
617 s = "<VBusValid"; break;
618 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
619 default:
620 s = "VALID"; break;
2b84f92b 621 } s; }),
550a7375
FB		 622 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
623 musb->port1_status);
624
625 /* go through A_WAIT_VFALL then start a new session */
626 if (!ignore)
743411b3 627 musb_platform_set_vbus(musb, 0);
550a7375
FB		 628 handled = IRQ_HANDLED;
629 }
630
1c25fda4 631 if (int_usb & MUSB_INTR_SUSPEND) {
b11e94d0 632 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
42c0bf1c 633 usb_otg_state_string(musb->xceiv->state), devctl);
1c25fda4
AM		 634 handled = IRQ_HANDLED;
635
636 switch (musb->xceiv->state) {
1c25fda4
AM		 637 case OTG_STATE_A_PERIPHERAL:
638 /* We also come here if the cable is removed, since
639 * this silicon doesn't report ID-no-longer-grounded.
640 *
641 * We depend on T(a_wait_bcon) to shut us down, and
642 * hope users don't do anything dicey during this
643 * undesired detour through A_WAIT_BCON.
644 */
645 musb_hnp_stop(musb);
0b3eba44 646 musb_host_resume_root_hub(musb);
1c25fda4
AM		 647 musb_root_disconnect(musb);
648 musb_platform_try_idle(musb, jiffies
649 + msecs_to_jiffies(musb->a_wait_bcon
650 ? : OTG_TIME_A_WAIT_BCON));
651
652 break;
1c25fda4
AM		 653 case OTG_STATE_B_IDLE:
654 if (!musb->is_active)
655 break;
656 case OTG_STATE_B_PERIPHERAL:
657 musb_g_suspend(musb);
eee3f15d 658 musb->is_active = musb->g.b_hnp_enable;
1c25fda4 659 if (musb->is_active) {
1c25fda4 660 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
5c8a86e1 661 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
1c25fda4
AM		 662 mod_timer(&musb->otg_timer, jiffies
663 + msecs_to_jiffies(
664 OTG_TIME_B_ASE0_BRST));
1c25fda4
AM		 665 }
666 break;
667 case OTG_STATE_A_WAIT_BCON:
668 if (musb->a_wait_bcon != 0)
669 musb_platform_try_idle(musb, jiffies
670 + msecs_to_jiffies(musb->a_wait_bcon));
671 break;
672 case OTG_STATE_A_HOST:
673 musb->xceiv->state = OTG_STATE_A_SUSPEND;
eee3f15d 674 musb->is_active = musb->hcd->self.b_hnp_enable;
1c25fda4
AM		 675 break;
676 case OTG_STATE_B_HOST:
677 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
5c8a86e1 678 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
1c25fda4
AM		 679 break;
680 default:
681 /* "should not happen" */
682 musb->is_active = 0;
683 break;
684 }
685 }
686
550a7375 687 if (int_usb & MUSB_INTR_CONNECT) {
8b125df5 688 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 689
690 handled = IRQ_HANDLED;
691 musb->is_active = 1;
550a7375
FB		 692
693 musb->ep0_stage = MUSB_EP0_START;
694
550a7375
FB		 695 /* flush endpoints when transitioning from Device Mode */
696 if (is_peripheral_active(musb)) {
697 /* REVISIT HNP; just force disconnect */
698 }
b18d26f6
SAS		 699 musb->intrtxe = musb->epmask;
700 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
af5ec14d
SAS		 701 musb->intrrxe = musb->epmask & 0xfffe;
702 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
d709d22e 703 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 704 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
705 |USB_PORT_STAT_HIGH_SPEED
706 |USB_PORT_STAT_ENABLE
707 );
708 musb->port1_status |= USB_PORT_STAT_CONNECTION
709 |(USB_PORT_STAT_C_CONNECTION << 16);
710
711 /* high vs full speed is just a guess until after reset */
712 if (devctl & MUSB_DEVCTL_LSDEV)
713 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
714
550a7375 715 /* indicate new connection to OTG machine */
84e250ff 716 switch (musb->xceiv->state) {
550a7375
FB		 717 case OTG_STATE_B_PERIPHERAL:
718 if (int_usb & MUSB_INTR_SUSPEND) {
5c8a86e1 719 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
550a7375 720 int_usb &= ~MUSB_INTR_SUSPEND;
1de00dae 721 goto b_host;
550a7375 722 } else
5c8a86e1 723 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
550a7375
FB		 724 break;
725 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 726 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
1de00dae 727b_host:
84e250ff 728 musb->xceiv->state = OTG_STATE_B_HOST;
74c2e936
DM		 729 if (musb->hcd)
730 musb->hcd->self.is_b_host = 1;
1de00dae 731 del_timer(&musb->otg_timer);
550a7375
FB		 732 break;
733 default:
734 if ((devctl & MUSB_DEVCTL_VBUS)
735 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
84e250ff 736 musb->xceiv->state = OTG_STATE_A_HOST;
0b3eba44
DM		 737 if (hcd)
738 hcd->self.is_b_host = 0;
550a7375
FB		 739 }
740 break;
741 }
1de00dae 742
0b3eba44 743 musb_host_poke_root_hub(musb);
1de00dae 744
5c8a86e1 745 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
42c0bf1c 746 usb_otg_state_string(musb->xceiv->state), devctl);
550a7375 747 }
550a7375 748
6d349671 749 if (int_usb & MUSB_INTR_DISCONNECT) {
5c8a86e1 750 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
42c0bf1c 751 usb_otg_state_string(musb->xceiv->state),
1c25fda4
AM		 752 MUSB_MODE(musb), devctl);
753 handled = IRQ_HANDLED;
754
755 switch (musb->xceiv->state) {
1c25fda4
AM		 756 case OTG_STATE_A_HOST:
757 case OTG_STATE_A_SUSPEND:
0b3eba44 758 musb_host_resume_root_hub(musb);
1c25fda4 759 musb_root_disconnect(musb);
032ec49f 760 if (musb->a_wait_bcon != 0)
1c25fda4
AM		 761 musb_platform_try_idle(musb, jiffies
762 + msecs_to_jiffies(musb->a_wait_bcon));
763 break;
1c25fda4
AM		 764 case OTG_STATE_B_HOST:
765 /* REVISIT this behaves for "real disconnect"
766 * cases; make sure the other transitions from
767 * from B_HOST act right too. The B_HOST code
768 * in hnp_stop() is currently not used...
769 */
770 musb_root_disconnect(musb);
74c2e936
DM		 771 if (musb->hcd)
772 musb->hcd->self.is_b_host = 0;
1c25fda4
AM		 773 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
774 MUSB_DEV_MODE(musb);
775 musb_g_disconnect(musb);
776 break;
777 case OTG_STATE_A_PERIPHERAL:
778 musb_hnp_stop(musb);
779 musb_root_disconnect(musb);
780 /* FALLTHROUGH */
781 case OTG_STATE_B_WAIT_ACON:
782 /* FALLTHROUGH */
1c25fda4
AM		 783 case OTG_STATE_B_PERIPHERAL:
784 case OTG_STATE_B_IDLE:
785 musb_g_disconnect(musb);
786 break;
1c25fda4
AM		 787 default:
788 WARNING("unhandled DISCONNECT transition (%s)\n",
42c0bf1c 789 usb_otg_state_string(musb->xceiv->state));
1c25fda4
AM		 790 break;
791 }
792 }
793
550a7375
FB		 794 /* mentor saves a bit: bus reset and babble share the same irq.
795 * only host sees babble; only peripheral sees bus reset.
796 */
797 if (int_usb & MUSB_INTR_RESET) {
1c25fda4 798 handled = IRQ_HANDLED;
a04d46d0 799 if ((devctl & MUSB_DEVCTL_HM) != 0) {
550a7375
FB		 800 /*
801 * Looks like non-HS BABBLE can be ignored, but
802 * HS BABBLE is an error condition. For HS the solution
803 * is to avoid babble in the first place and fix what
804 * caused BABBLE. When HS BABBLE happens we can only
805 * stop the session.
806 */
807 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
5c8a86e1 808 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
550a7375
FB		 809 else {
810 ERR("Stopping host session -- babble\n");
1c25fda4 811 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
550a7375 812 }
a04d46d0 813 } else {
5c8a86e1 814 dev_dbg(musb->controller, "BUS RESET as %s\n",
42c0bf1c 815 usb_otg_state_string(musb->xceiv->state));
84e250ff 816 switch (musb->xceiv->state) {
550a7375 817 case OTG_STATE_A_SUSPEND:
550a7375
FB		 818 musb_g_reset(musb);
819 /* FALLTHROUGH */
820 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
f7f9d63e 821 /* never use invalid T(a_wait_bcon) */
5c8a86e1 822 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
42c0bf1c 823 usb_otg_state_string(musb->xceiv->state),
3df00453 824 TA_WAIT_BCON(musb));
f7f9d63e
DB		 825 mod_timer(&musb->otg_timer, jiffies
826 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
550a7375
FB		 827 break;
828 case OTG_STATE_A_PERIPHERAL:
1de00dae
DB		 829 del_timer(&musb->otg_timer);
830 musb_g_reset(musb);
550a7375
FB		 831 break;
832 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 833 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
42c0bf1c 834 usb_otg_state_string(musb->xceiv->state));
84e250ff 835 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 836 musb_g_reset(musb);
837 break;
550a7375 838 case OTG_STATE_B_IDLE:
84e250ff 839 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 840 /* FALLTHROUGH */
841 case OTG_STATE_B_PERIPHERAL:
842 musb_g_reset(musb);
843 break;
844 default:
5c8a86e1 845 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
42c0bf1c 846 usb_otg_state_string(musb->xceiv->state));
550a7375
FB		 847 }
848 }
550a7375 849 }
550a7375 850
ca88fc2e 851 /* handle babble condition */
97b4129e 852 if (int_usb & MUSB_INTR_BABBLE && is_host_active(musb))
675ae763
GC		 853 schedule_delayed_work(&musb->recover_work,
854 msecs_to_jiffies(100));
ca88fc2e 855
550a7375
FB		 856#if 0
857/* REVISIT ... this would be for multiplexing periodic endpoints, or
858 * supporting transfer phasing to prevent exceeding ISO bandwidth
859 * limits of a given frame or microframe.
860 *
861 * It's not needed for peripheral side, which dedicates endpoints;
862 * though it _might_ use SOF irqs for other purposes.
863 *
864 * And it's not currently needed for host side, which also dedicates
865 * endpoints, relies on TX/RX interval registers, and isn't claimed
866 * to support ISO transfers yet.
867 */
868 if (int_usb & MUSB_INTR_SOF) {
869 void __iomem *mbase = musb->mregs;
870 struct musb_hw_ep *ep;
871 u8 epnum;
872 u16 frame;
873
5c8a86e1 874 dev_dbg(musb->controller, "START_OF_FRAME\n");
550a7375
FB		 875 handled = IRQ_HANDLED;
876
877 /* start any periodic Tx transfers waiting for current frame */
878 frame = musb_readw(mbase, MUSB_FRAME);
879 ep = musb->endpoints;
880 for (epnum = 1; (epnum < musb->nr_endpoints)
881 && (musb->epmask >= (1 << epnum));
882 epnum++, ep++) {
883 /*
884 * FIXME handle framecounter wraps (12 bits)
885 * eliminate duplicated StartUrb logic
886 */
887 if (ep->dwWaitFrame >= frame) {
888 ep->dwWaitFrame = 0;
889 pr_debug("SOF --> periodic TX%s on %d\n",
890 ep->tx_channel ? " DMA" : "",
891 epnum);
892 if (!ep->tx_channel)
893 musb_h_tx_start(musb, epnum);
894 else
895 cppi_hostdma_start(musb, epnum);
896 }
897 } /* end of for loop */
898 }
899#endif
900
1c25fda4 901 schedule_work(&musb->irq_work);
550a7375
FB		 902
903 return handled;
904}
905
906/*-------------------------------------------------------------------------*/
907
550a7375
FB		 908static void musb_generic_disable(struct musb *musb)
909{
910 void __iomem *mbase = musb->mregs;
911 u16 temp;
912
913 /* disable interrupts */
914 musb_writeb(mbase, MUSB_INTRUSBE, 0);
b18d26f6 915 musb->intrtxe = 0;
550a7375 916 musb_writew(mbase, MUSB_INTRTXE, 0);
af5ec14d 917 musb->intrrxe = 0;
550a7375
FB		 918 musb_writew(mbase, MUSB_INTRRXE, 0);
919
920 /* off */
921 musb_writeb(mbase, MUSB_DEVCTL, 0);
922
923 /* flush pending interrupts */
924 temp = musb_readb(mbase, MUSB_INTRUSB);
925 temp = musb_readw(mbase, MUSB_INTRTX);
926 temp = musb_readw(mbase, MUSB_INTRRX);
927
928}
929
001dd84a
SAS		 930/*
931 * Program the HDRC to start (enable interrupts, dma, etc.).
932 */
933void musb_start(struct musb *musb)
934{
935 void __iomem *regs = musb->mregs;
936 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
937
938 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
939
940 /* Set INT enable registers, enable interrupts */
941 musb->intrtxe = musb->epmask;
942 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
943 musb->intrrxe = musb->epmask & 0xfffe;
944 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
945 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
946
947 musb_writeb(regs, MUSB_TESTMODE, 0);
948
949 /* put into basic highspeed mode and start session */
950 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
951 | MUSB_POWER_HSENAB
952 /* ENSUSPEND wedges tusb */
953 /* | MUSB_POWER_ENSUSPEND */
954 );
955
956 musb->is_active = 0;
957 devctl = musb_readb(regs, MUSB_DEVCTL);
958 devctl &= ~MUSB_DEVCTL_SESSION;
959
960 /* session started after:
961 * (a) ID-grounded irq, host mode;
962 * (b) vbus present/connect IRQ, peripheral mode;
963 * (c) peripheral initiates, using SRP
964 */
965 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
966 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
967 musb->is_active = 1;
968 } else {
969 devctl |= MUSB_DEVCTL_SESSION;
970 }
971
972 musb_platform_enable(musb);
973 musb_writeb(regs, MUSB_DEVCTL, devctl);
974}
975
550a7375
FB		 976/*
977 * Make the HDRC stop (disable interrupts, etc.);
978 * reversible by musb_start
979 * called on gadget driver unregister
980 * with controller locked, irqs blocked
981 * acts as a NOP unless some role activated the hardware
982 */
983void musb_stop(struct musb *musb)
984{
985 /* stop IRQs, timers, ... */
986 musb_platform_disable(musb);
987 musb_generic_disable(musb);
5c8a86e1 988 dev_dbg(musb->controller, "HDRC disabled\n");
550a7375
FB		 989
990 /* FIXME
991 * - mark host and/or peripheral drivers unusable/inactive
992 * - disable DMA (and enable it in HdrcStart)
993 * - make sure we can musb_start() after musb_stop(); with
994 * OTG mode, gadget driver module rmmod/modprobe cycles that
995 * - ...
996 */
997 musb_platform_try_idle(musb, 0);
998}
999
1000static void musb_shutdown(struct platform_device *pdev)
1001{
1002 struct musb *musb = dev_to_musb(&pdev->dev);
1003 unsigned long flags;
1004
4f9edd2d 1005 pm_runtime_get_sync(musb->controller);
24307cae 1006
2cc65fea 1007 musb_host_cleanup(musb);
24307cae
GI		 1008 musb_gadget_cleanup(musb);
1009
550a7375
FB		 1010 spin_lock_irqsave(&musb->lock, flags);
1011 musb_platform_disable(musb);
1012 musb_generic_disable(musb);
550a7375
FB		 1013 spin_unlock_irqrestore(&musb->lock, flags);
1014
120d074c
GI		 1015 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1016 musb_platform_exit(musb);
120d074c 1017
4f9edd2d 1018 pm_runtime_put(musb->controller);
550a7375
FB		 1019 /* FIXME power down */
1020}
1021
1022
1023/*-------------------------------------------------------------------------*/
1024
1025/*
1026 * The silicon either has hard-wired endpoint configurations, or else
1027 * "dynamic fifo" sizing. The driver has support for both, though at this
c767c1c6
DB		 1028 * writing only the dynamic sizing is very well tested. Since we switched
1029 * away from compile-time hardware parameters, we can no longer rely on
1030 * dead code elimination to leave only the relevant one in the object file.
550a7375
FB		 1031 *
1032 * We don't currently use dynamic fifo setup capability to do anything
1033 * more than selecting one of a bunch of predefined configurations.
1034 */
ee34e51a
FB		 1035#if defined(CONFIG_USB_MUSB_TUSB6010) \
1036 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1037 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1038 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1039 || defined(CONFIG_USB_MUSB_AM35X) \
9ecb8875
AKG		 1040 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \
1041 || defined(CONFIG_USB_MUSB_DSPS) \
1042 || defined(CONFIG_USB_MUSB_DSPS_MODULE)
d3608b6d 1043static ushort fifo_mode = 4;
ee34e51a
FB		 1044#elif defined(CONFIG_USB_MUSB_UX500) \
1045 || defined(CONFIG_USB_MUSB_UX500_MODULE)
d3608b6d 1046static ushort fifo_mode = 5;
550a7375 1047#else
d3608b6d 1048static ushort fifo_mode = 2;
550a7375
FB		 1049#endif
1050
1051/* "modprobe ... fifo_mode=1" etc */
1052module_param(fifo_mode, ushort, 0);
1053MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1054
550a7375
FB		 1055/*
1056 * tables defining fifo_mode values. define more if you like.
1057 * for host side, make sure both halves of ep1 are set up.
1058 */
1059
1060/* mode 0 - fits in 2KB */
d3608b6d 1061static struct musb_fifo_cfg mode_0_cfg[] = {
550a7375
FB		 1062{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1063{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1064{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1065{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1066{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1067};
1068
1069/* mode 1 - fits in 4KB */
d3608b6d 1070static struct musb_fifo_cfg mode_1_cfg[] = {
550a7375
FB		 1071{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1072{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1073{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1074{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1075{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1076};
1077
1078/* mode 2 - fits in 4KB */
d3608b6d 1079static struct musb_fifo_cfg mode_2_cfg[] = {
550a7375
FB		 1080{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1081{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1082{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1083{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1084{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1085{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1086};
1087
1088/* mode 3 - fits in 4KB */
d3608b6d 1089static struct musb_fifo_cfg mode_3_cfg[] = {
550a7375
FB		 1090{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1091{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1092{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1093{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1094{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1095{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1096};
1097
1098/* mode 4 - fits in 16KB */
d3608b6d 1099static struct musb_fifo_cfg mode_4_cfg[] = {
550a7375
FB		 1100{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1101{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1102{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1103{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1104{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1105{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1106{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1107{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1108{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1109{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1110{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1111{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1112{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1113{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1114{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1115{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1116{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1117{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
a483d706
AKG		 1118{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1119{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1120{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1121{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1122{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1123{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1124{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
550a7375
FB		 1125{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1126{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1127};
1128
3b151526 1129/* mode 5 - fits in 8KB */
d3608b6d 1130static struct musb_fifo_cfg mode_5_cfg[] = {
3b151526
AKG		 1131{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1132{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1133{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1134{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1135{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1136{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1137{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1138{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1139{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1140{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1141{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1142{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1143{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1144{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1145{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1146{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1147{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1148{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1149{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1150{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1151{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1152{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1153{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1154{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1155{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1156{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1157{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1158};
550a7375
FB		 1159
1160/*
1161 * configure a fifo; for non-shared endpoints, this may be called
1162 * once for a tx fifo and once for an rx fifo.
1163 *
1164 * returns negative errno or offset for next fifo.
1165 */
41ac7b3a 1166static int
550a7375 1167fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
e6c213b2 1168 const struct musb_fifo_cfg *cfg, u16 offset)
550a7375
FB		 1169{
1170 void __iomem *mbase = musb->mregs;
1171 int size = 0;
1172 u16 maxpacket = cfg->maxpacket;
1173 u16 c_off = offset >> 3;
1174 u8 c_size;
1175
1176 /* expect hw_ep has already been zero-initialized */
1177
1178 size = ffs(max(maxpacket, (u16) 8)) - 1;
1179 maxpacket = 1 << size;
1180
1181 c_size = size - 3;
1182 if (cfg->mode == BUF_DOUBLE) {
ca6d1b13
FB		 1183 if ((offset + (maxpacket << 1)) >
1184 (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1185 return -EMSGSIZE;
1186 c_size |= MUSB_FIFOSZ_DPB;
1187 } else {
ca6d1b13 1188 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1189 return -EMSGSIZE;
1190 }
1191
1192 /* configure the FIFO */
1193 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1194
550a7375 1195 /* EP0 reserved endpoint for control, bidirectional;
5ae477b0 1196 * EP1 reserved for bulk, two unidirectional halves.
550a7375
FB		 1197 */
1198 if (hw_ep->epnum == 1)
1199 musb->bulk_ep = hw_ep;
1200 /* REVISIT error check: be sure ep0 can both rx and tx ... */
550a7375
FB		 1201 switch (cfg->style) {
1202 case FIFO_TX:
c6cf8b00
BW		 1203 musb_write_txfifosz(mbase, c_size);
1204 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1205 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1206 hw_ep->max_packet_sz_tx = maxpacket;
1207 break;
1208 case FIFO_RX:
c6cf8b00
BW		 1209 musb_write_rxfifosz(mbase, c_size);
1210 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1211 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1212 hw_ep->max_packet_sz_rx = maxpacket;
1213 break;
1214 case FIFO_RXTX:
c6cf8b00
BW		 1215 musb_write_txfifosz(mbase, c_size);
1216 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1217 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1218 hw_ep->max_packet_sz_rx = maxpacket;
1219
c6cf8b00
BW		 1220 musb_write_rxfifosz(mbase, c_size);
1221 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1222 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1223 hw_ep->max_packet_sz_tx = maxpacket;
1224
1225 hw_ep->is_shared_fifo = true;
1226 break;
1227 }
1228
1229 /* NOTE rx and tx endpoint irqs aren't managed separately,
1230 * which happens to be ok
1231 */
1232 musb->epmask |= (1 << hw_ep->epnum);
1233
1234 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1235}
1236
d3608b6d 1237static struct musb_fifo_cfg ep0_cfg = {
550a7375
FB		 1238 .style = FIFO_RXTX, .maxpacket = 64,
1239};
1240
41ac7b3a 1241static int ep_config_from_table(struct musb *musb)
550a7375 1242{
e6c213b2 1243 const struct musb_fifo_cfg *cfg;
550a7375
FB		 1244 unsigned i, n;
1245 int offset;
1246 struct musb_hw_ep *hw_ep = musb->endpoints;
1247
e6c213b2
FB		 1248 if (musb->config->fifo_cfg) {
1249 cfg = musb->config->fifo_cfg;
1250 n = musb->config->fifo_cfg_size;
1251 goto done;
1252 }
1253
550a7375
FB		 1254 switch (fifo_mode) {
1255 default:
1256 fifo_mode = 0;
1257 /* FALLTHROUGH */
1258 case 0:
1259 cfg = mode_0_cfg;
1260 n = ARRAY_SIZE(mode_0_cfg);
1261 break;
1262 case 1:
1263 cfg = mode_1_cfg;
1264 n = ARRAY_SIZE(mode_1_cfg);
1265 break;
1266 case 2:
1267 cfg = mode_2_cfg;
1268 n = ARRAY_SIZE(mode_2_cfg);
1269 break;
1270 case 3:
1271 cfg = mode_3_cfg;
1272 n = ARRAY_SIZE(mode_3_cfg);
1273 break;
1274 case 4:
1275 cfg = mode_4_cfg;
1276 n = ARRAY_SIZE(mode_4_cfg);
1277 break;
3b151526
AKG		 1278 case 5:
1279 cfg = mode_5_cfg;
1280 n = ARRAY_SIZE(mode_5_cfg);
1281 break;
550a7375
FB		 1282 }
1283
1284 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1285 musb_driver_name, fifo_mode);
1286
1287
e6c213b2 1288done:
550a7375
FB		 1289 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1290 /* assert(offset > 0) */
1291
1292 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
ca6d1b13 1293 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
550a7375
FB		 1294 */
1295
1296 for (i = 0; i < n; i++) {
1297 u8 epn = cfg->hw_ep_num;
1298
ca6d1b13 1299 if (epn >= musb->config->num_eps) {
550a7375
FB		 1300 pr_debug("%s: invalid ep %d\n",
1301 musb_driver_name, epn);
bb1c9ef1 1302 return -EINVAL;
550a7375
FB		 1303 }
1304 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1305 if (offset < 0) {
1306 pr_debug("%s: mem overrun, ep %d\n",
1307 musb_driver_name, epn);
f69dfa1f 1308 return offset;
550a7375
FB		 1309 }
1310 epn++;
1311 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1312 }
1313
1314 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1315 musb_driver_name,
ca6d1b13
FB		 1316 n + 1, musb->config->num_eps * 2 - 1,
1317 offset, (1 << (musb->config->ram_bits + 2)));
550a7375 1318
550a7375
FB		 1319 if (!musb->bulk_ep) {
1320 pr_debug("%s: missing bulk\n", musb_driver_name);
1321 return -EINVAL;
1322 }
550a7375
FB		 1323
1324 return 0;
1325}
1326
1327
1328/*
1329 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1330 * @param musb the controller
1331 */
41ac7b3a 1332static int ep_config_from_hw(struct musb *musb)
550a7375 1333{
c6cf8b00 1334 u8 epnum = 0;
550a7375 1335 struct musb_hw_ep *hw_ep;
a156544b 1336 void __iomem *mbase = musb->mregs;
c6cf8b00 1337 int ret = 0;
550a7375 1338
5c8a86e1 1339 dev_dbg(musb->controller, "<== static silicon ep config\n");
550a7375
FB		 1340
1341 /* FIXME pick up ep0 maxpacket size */
1342
ca6d1b13 1343 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
550a7375
FB		 1344 musb_ep_select(mbase, epnum);
1345 hw_ep = musb->endpoints + epnum;
1346
c6cf8b00
BW		 1347 ret = musb_read_fifosize(musb, hw_ep, epnum);
1348 if (ret < 0)
550a7375 1349 break;
550a7375
FB		 1350
1351 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1352
550a7375
FB		 1353 /* pick an RX/TX endpoint for bulk */
1354 if (hw_ep->max_packet_sz_tx < 512
1355 || hw_ep->max_packet_sz_rx < 512)
1356 continue;
1357
1358 /* REVISIT: this algorithm is lazy, we should at least
1359 * try to pick a double buffered endpoint.
1360 */
1361 if (musb->bulk_ep)
1362 continue;
1363 musb->bulk_ep = hw_ep;
550a7375
FB		 1364 }
1365
550a7375
FB		 1366 if (!musb->bulk_ep) {
1367 pr_debug("%s: missing bulk\n", musb_driver_name);
1368 return -EINVAL;
1369 }
550a7375
FB		 1370
1371 return 0;
1372}
1373
1374enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1375
1376/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1377 * configure endpoints, or take their config from silicon
1378 */
41ac7b3a 1379static int musb_core_init(u16 musb_type, struct musb *musb)
550a7375 1380{
550a7375
FB		 1381 u8 reg;
1382 char *type;
0ea52ff4 1383 char aInfo[90], aRevision[32], aDate[12];
550a7375
FB		 1384 void __iomem *mbase = musb->mregs;
1385 int status = 0;
1386 int i;
1387
1388 /* log core options (read using indexed model) */
c6cf8b00 1389 reg = musb_read_configdata(mbase);
550a7375
FB		 1390
1391 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
51bf0d0e 1392 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
550a7375 1393 strcat(aInfo, ", dyn FIFOs");
51bf0d0e
AKG		 1394 musb->dyn_fifo = true;
1395 }
550a7375
FB		 1396 if (reg & MUSB_CONFIGDATA_MPRXE) {
1397 strcat(aInfo, ", bulk combine");
550a7375 1398 musb->bulk_combine = true;
550a7375
FB		 1399 }
1400 if (reg & MUSB_CONFIGDATA_MPTXE) {
1401 strcat(aInfo, ", bulk split");
550a7375 1402 musb->bulk_split = true;
550a7375
FB		 1403 }
1404 if (reg & MUSB_CONFIGDATA_HBRXE) {
1405 strcat(aInfo, ", HB-ISO Rx");
a483d706 1406 musb->hb_iso_rx = true;
550a7375
FB		 1407 }
1408 if (reg & MUSB_CONFIGDATA_HBTXE) {
1409 strcat(aInfo, ", HB-ISO Tx");
a483d706 1410 musb->hb_iso_tx = true;
550a7375
FB		 1411 }
1412 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1413 strcat(aInfo, ", SoftConn");
1414
1415 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1416 musb_driver_name, reg, aInfo);
1417
550a7375 1418 aDate[0] = 0;
550a7375
FB		 1419 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1420 musb->is_multipoint = 1;
1421 type = "M";
1422 } else {
1423 musb->is_multipoint = 0;
1424 type = "";
550a7375
FB		 1425#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1426 printk(KERN_ERR
1427 "%s: kernel must blacklist external hubs\n",
1428 musb_driver_name);
550a7375
FB		 1429#endif
1430 }
1431
1432 /* log release info */
32c3b94e
AG		 1433 musb->hwvers = musb_read_hwvers(mbase);
1434 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1435 MUSB_HWVERS_MINOR(musb->hwvers),
1436 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
550a7375
FB		 1437 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1438 musb_driver_name, type, aRevision, aDate);
1439
1440 /* configure ep0 */
c6cf8b00 1441 musb_configure_ep0(musb);
550a7375
FB		 1442
1443 /* discover endpoint configuration */
1444 musb->nr_endpoints = 1;
1445 musb->epmask = 1;
1446
ad517e9e
FB		 1447 if (musb->dyn_fifo)
1448 status = ep_config_from_table(musb);
1449 else
1450 status = ep_config_from_hw(musb);
550a7375
FB		 1451
1452 if (status < 0)
1453 return status;
1454
1455 /* finish init, and print endpoint config */
1456 for (i = 0; i < musb->nr_endpoints; i++) {
1457 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1458
1459 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
9a35f876 1460#if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
550a7375
FB		 1461 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1462 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1463 hw_ep->fifo_sync_va =
1464 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1465
1466 if (i == 0)
1467 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1468 else
1469 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1470#endif
1471
1472 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
c6cf8b00 1473 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
550a7375
FB		 1474 hw_ep->rx_reinit = 1;
1475 hw_ep->tx_reinit = 1;
550a7375
FB		 1476
1477 if (hw_ep->max_packet_sz_tx) {
5c8a86e1 1478 dev_dbg(musb->controller,
550a7375
FB		 1479 "%s: hw_ep %d%s, %smax %d\n",
1480 musb_driver_name, i,
1481 hw_ep->is_shared_fifo ? "shared" : "tx",
1482 hw_ep->tx_double_buffered
1483 ? "doublebuffer, " : "",
1484 hw_ep->max_packet_sz_tx);
1485 }
1486 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
5c8a86e1 1487 dev_dbg(musb->controller,
550a7375
FB		 1488 "%s: hw_ep %d%s, %smax %d\n",
1489 musb_driver_name, i,
1490 "rx",
1491 hw_ep->rx_double_buffered
1492 ? "doublebuffer, " : "",
1493 hw_ep->max_packet_sz_rx);
1494 }
1495 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
5c8a86e1 1496 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
550a7375
FB		 1497 }
1498
1499 return 0;
1500}
1501
1502/*-------------------------------------------------------------------------*/
1503
550a7375
FB		 1504/*
1505 * handle all the irqs defined by the HDRC core. for now we expect: other
1506 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1507 * will be assigned, and the irq will already have been acked.
1508 *
1509 * called in irq context with spinlock held, irqs blocked
1510 */
1511irqreturn_t musb_interrupt(struct musb *musb)
1512{
1513 irqreturn_t retval = IRQ_NONE;
b11e94d0 1514 u8 devctl;
550a7375
FB		 1515 int ep_num;
1516 u32 reg;
1517
1518 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
550a7375 1519
5c8a86e1 1520 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
c03da38d 1521 is_host_active(musb) ? "host" : "peripheral",
550a7375
FB		 1522 musb->int_usb, musb->int_tx, musb->int_rx);
1523
1524 /* the core can interrupt us for multiple reasons; docs have
1525 * a generic interrupt flowchart to follow
1526 */
7d9645fd 1527 if (musb->int_usb)
550a7375 1528 retval |= musb_stage0_irq(musb, musb->int_usb,
b11e94d0 1529 devctl);
550a7375
FB		 1530
1531 /* "stage 1" is handling endpoint irqs */
1532
1533 /* handle endpoint 0 first */
1534 if (musb->int_tx & 1) {
c03da38d 1535 if (is_host_active(musb))
550a7375
FB		 1536 retval |= musb_h_ep0_irq(musb);
1537 else
1538 retval |= musb_g_ep0_irq(musb);
1539 }
1540
1541 /* RX on endpoints 1-15 */
1542 reg = musb->int_rx >> 1;
1543 ep_num = 1;
1544 while (reg) {
1545 if (reg & 1) {
1546 /* musb_ep_select(musb->mregs, ep_num); */
1547 /* REVISIT just retval = ep->rx_irq(...) */
1548 retval = IRQ_HANDLED;
c03da38d 1549 if (is_host_active(musb))
a04d46d0
FB		 1550 musb_host_rx(musb, ep_num);
1551 else
1552 musb_g_rx(musb, ep_num);
550a7375
FB		 1553 }
1554
1555 reg >>= 1;
1556 ep_num++;
1557 }
1558
1559 /* TX on endpoints 1-15 */
1560 reg = musb->int_tx >> 1;
1561 ep_num = 1;
1562 while (reg) {
1563 if (reg & 1) {
1564 /* musb_ep_select(musb->mregs, ep_num); */
1565 /* REVISIT just retval |= ep->tx_irq(...) */
1566 retval = IRQ_HANDLED;
c03da38d 1567 if (is_host_active(musb))
a04d46d0
FB		 1568 musb_host_tx(musb, ep_num);
1569 else
1570 musb_g_tx(musb, ep_num);
550a7375
FB		 1571 }
1572 reg >>= 1;
1573 ep_num++;
1574 }
1575
550a7375
FB		 1576 return retval;
1577}
981430a1 1578EXPORT_SYMBOL_GPL(musb_interrupt);
550a7375
FB		 1579
1580#ifndef CONFIG_MUSB_PIO_ONLY
d3608b6d 1581static bool use_dma = 1;
550a7375
FB		 1582
1583/* "modprobe ... use_dma=0" etc */
1584module_param(use_dma, bool, 0);
1585MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1586
1587void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1588{
550a7375
FB		 1589 /* called with controller lock already held */
1590
1591 if (!epnum) {
1592#ifndef CONFIG_USB_TUSB_OMAP_DMA
1593 if (!is_cppi_enabled()) {
1594 /* endpoint 0 */
c03da38d 1595 if (is_host_active(musb))
550a7375
FB		 1596 musb_h_ep0_irq(musb);
1597 else
1598 musb_g_ep0_irq(musb);
1599 }
1600#endif
1601 } else {
1602 /* endpoints 1..15 */
1603 if (transmit) {
c03da38d 1604 if (is_host_active(musb))
a04d46d0
FB		 1605 musb_host_tx(musb, epnum);
1606 else
1607 musb_g_tx(musb, epnum);
550a7375
FB		 1608 } else {
1609 /* receive */
c03da38d 1610 if (is_host_active(musb))
a04d46d0
FB		 1611 musb_host_rx(musb, epnum);
1612 else
1613 musb_g_rx(musb, epnum);
550a7375
FB		 1614 }
1615 }
1616}
9a35f876 1617EXPORT_SYMBOL_GPL(musb_dma_completion);
550a7375
FB		 1618
1619#else
1620#define use_dma 0
1621#endif
1622
1623/*-------------------------------------------------------------------------*/
1624
550a7375
FB		 1625static ssize_t
1626musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1627{
1628 struct musb *musb = dev_to_musb(dev);
1629 unsigned long flags;
1630 int ret = -EINVAL;
1631
1632 spin_lock_irqsave(&musb->lock, flags);
42c0bf1c 1633 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->state));
550a7375
FB		 1634 spin_unlock_irqrestore(&musb->lock, flags);
1635
1636 return ret;
1637}
1638
1639static ssize_t
1640musb_mode_store(struct device *dev, struct device_attribute *attr,
1641 const char *buf, size_t n)
1642{
1643 struct musb *musb = dev_to_musb(dev);
1644 unsigned long flags;
96a274d1 1645 int status;
550a7375
FB		 1646
1647 spin_lock_irqsave(&musb->lock, flags);
96a274d1
DB		 1648 if (sysfs_streq(buf, "host"))
1649 status = musb_platform_set_mode(musb, MUSB_HOST);
1650 else if (sysfs_streq(buf, "peripheral"))
1651 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1652 else if (sysfs_streq(buf, "otg"))
1653 status = musb_platform_set_mode(musb, MUSB_OTG);
1654 else
1655 status = -EINVAL;
550a7375
FB		 1656 spin_unlock_irqrestore(&musb->lock, flags);
1657
96a274d1 1658 return (status == 0) ? n : status;
550a7375
FB		 1659}
1660static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1661
1662static ssize_t
1663musb_vbus_store(struct device *dev, struct device_attribute *attr,
1664 const char *buf, size_t n)
1665{
1666 struct musb *musb = dev_to_musb(dev);
1667 unsigned long flags;
1668 unsigned long val;
1669
1670 if (sscanf(buf, "%lu", &val) < 1) {
b3b1cc3b 1671 dev_err(dev, "Invalid VBUS timeout ms value\n");
550a7375
FB		 1672 return -EINVAL;
1673 }
1674
1675 spin_lock_irqsave(&musb->lock, flags);
f7f9d63e
DB		 1676 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1677 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
84e250ff 1678 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
550a7375
FB		 1679 musb->is_active = 0;
1680 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1681 spin_unlock_irqrestore(&musb->lock, flags);
1682
1683 return n;
1684}
1685
1686static ssize_t
1687musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1688{
1689 struct musb *musb = dev_to_musb(dev);
1690 unsigned long flags;
1691 unsigned long val;
1692 int vbus;
1693
1694 spin_lock_irqsave(&musb->lock, flags);
1695 val = musb->a_wait_bcon;
f7f9d63e
DB		 1696 /* FIXME get_vbus_status() is normally #defined as false...
1697 * and is effectively TUSB-specific.
1698 */
550a7375
FB		 1699 vbus = musb_platform_get_vbus_status(musb);
1700 spin_unlock_irqrestore(&musb->lock, flags);
1701
f7f9d63e 1702 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
550a7375
FB		 1703 vbus ? "on" : "off", val);
1704}
1705static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1706
550a7375
FB		 1707/* Gadget drivers can't know that a host is connected so they might want
1708 * to start SRP, but users can. This allows userspace to trigger SRP.
1709 */
1710static ssize_t
1711musb_srp_store(struct device *dev, struct device_attribute *attr,
1712 const char *buf, size_t n)
1713{
1714 struct musb *musb = dev_to_musb(dev);
1715 unsigned short srp;
1716
1717 if (sscanf(buf, "%hu", &srp) != 1
1718 || (srp != 1)) {
b3b1cc3b 1719 dev_err(dev, "SRP: Value must be 1\n");
550a7375
FB		 1720 return -EINVAL;
1721 }
1722
1723 if (srp == 1)
1724 musb_g_wakeup(musb);
1725
1726 return n;
1727}
1728static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1729
94375751
FB		 1730static struct attribute *musb_attributes[] = {
1731 &dev_attr_mode.attr,
1732 &dev_attr_vbus.attr,
94375751 1733 &dev_attr_srp.attr,
94375751
FB		 1734 NULL
1735};
1736
1737static const struct attribute_group musb_attr_group = {
1738 .attrs = musb_attributes,
1739};
1740
550a7375
FB		 1741/* Only used to provide driver mode change events */
1742static void musb_irq_work(struct work_struct *data)
1743{
1744 struct musb *musb = container_of(data, struct musb, irq_work);
550a7375 1745
8d2421e6
AKG		 1746 if (musb->xceiv->state != musb->xceiv_old_state) {
1747 musb->xceiv_old_state = musb->xceiv->state;
550a7375
FB		 1748 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1749 }
1750}
1751
ca88fc2e
DM		 1752/* Recover from babble interrupt conditions */
1753static void musb_recover_work(struct work_struct *data)
1754{
675ae763 1755 struct musb *musb = container_of(data, struct musb, recover_work.work);
d871c622 1756 int status, ret;
ca88fc2e 1757
d871c622
GC		 1758 ret = musb_platform_reset(musb);
1759 if (ret)
1760 return;
ca88fc2e
DM		 1761
1762 usb_phy_vbus_off(musb->xceiv);
675ae763 1763 usleep_range(100, 200);
ca88fc2e
DM		 1764
1765 usb_phy_vbus_on(musb->xceiv);
675ae763 1766 usleep_range(100, 200);
ca88fc2e
DM		 1767
1768 /*
d871c622
GC		 1769 * When a babble condition occurs, the musb controller
1770 * removes the session bit and the endpoint config is lost.
ca88fc2e
DM		 1771 */
1772 if (musb->dyn_fifo)
1773 status = ep_config_from_table(musb);
1774 else
1775 status = ep_config_from_hw(musb);
1776
1777 /* start the session again */
1778 if (status == 0)
1779 musb_start(musb);
1780}
1781
550a7375
FB		 1782/* --------------------------------------------------------------------------
1783 * Init support
1784 */
1785
41ac7b3a 1786static struct musb *allocate_instance(struct device *dev,
ca6d1b13 1787 struct musb_hdrc_config *config, void __iomem *mbase)
550a7375
FB		 1788{
1789 struct musb *musb;
1790 struct musb_hw_ep *ep;
1791 int epnum;
74c2e936 1792 int ret;
550a7375 1793
74c2e936
DM		 1794 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1795 if (!musb)
550a7375 1796 return NULL;
550a7375 1797
550a7375
FB		 1798 INIT_LIST_HEAD(&musb->control);
1799 INIT_LIST_HEAD(&musb->in_bulk);
1800 INIT_LIST_HEAD(&musb->out_bulk);
1801
550a7375 1802 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
f7f9d63e 1803 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
550a7375
FB		 1804 musb->mregs = mbase;
1805 musb->ctrl_base = mbase;
1806 musb->nIrq = -ENODEV;
ca6d1b13 1807 musb->config = config;
02582b92 1808 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
550a7375 1809 for (epnum = 0, ep = musb->endpoints;
ca6d1b13 1810 epnum < musb->config->num_eps;
550a7375 1811 epnum++, ep++) {
550a7375
FB		 1812 ep->musb = musb;
1813 ep->epnum = epnum;
1814 }
1815
1816 musb->controller = dev;
743411b3 1817
74c2e936
DM		 1818 ret = musb_host_alloc(musb);
1819 if (ret < 0)
1820 goto err_free;
1821
1822 dev_set_drvdata(dev, musb);
1823
550a7375 1824 return musb;
74c2e936
DM		 1825
1826err_free:
1827 return NULL;
550a7375
FB		 1828}
1829
1830static void musb_free(struct musb *musb)
1831{
1832 /* this has multiple entry modes. it handles fault cleanup after
1833 * probe(), where things may be partially set up, as well as rmmod
1834 * cleanup after everything's been de-activated.
1835 */
1836
1837#ifdef CONFIG_SYSFS
94375751 1838 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
550a7375
FB		 1839#endif
1840
97a39896
AKG		 1841 if (musb->nIrq >= 0) {
1842 if (musb->irq_wake)
1843 disable_irq_wake(musb->nIrq);
550a7375
FB		 1844 free_irq(musb->nIrq, musb);
1845 }
550a7375 1846
74c2e936 1847 musb_host_free(musb);
550a7375
FB		 1848}
1849
8ed1fb79
DM		 1850static void musb_deassert_reset(struct work_struct *work)
1851{
1852 struct musb *musb;
1853 unsigned long flags;
1854
1855 musb = container_of(work, struct musb, deassert_reset_work.work);
1856
1857 spin_lock_irqsave(&musb->lock, flags);
1858
1859 if (musb->port1_status & USB_PORT_STAT_RESET)
1860 musb_port_reset(musb, false);
1861
1862 spin_unlock_irqrestore(&musb->lock, flags);
1863}
1864
550a7375
FB		 1865/*
1866 * Perform generic per-controller initialization.
1867 *
28dd924a
SS		 1868 * @dev: the controller (already clocked, etc)
1869 * @nIrq: IRQ number
1870 * @ctrl: virtual address of controller registers,
550a7375
FB		 1871 * not yet corrected for platform-specific offsets
1872 */
41ac7b3a 1873static int
550a7375
FB		 1874musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1875{
1876 int status;
1877 struct musb *musb;
c1a7d67c 1878 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
550a7375
FB		 1879
1880 /* The driver might handle more features than the board; OK.
1881 * Fail when the board needs a feature that's not enabled.
1882 */
1883 if (!plat) {
1884 dev_dbg(dev, "no platform_data?\n");
34e2beb2
SS		 1885 status = -ENODEV;
1886 goto fail0;
550a7375 1887 }
34e2beb2 1888
550a7375 1889 /* allocate */
ca6d1b13 1890 musb = allocate_instance(dev, plat->config, ctrl);
34e2beb2
SS		 1891 if (!musb) {
1892 status = -ENOMEM;
1893 goto fail0;
1894 }
550a7375 1895
7acc6197
HH		 1896 pm_runtime_use_autosuspend(musb->controller);
1897 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1898 pm_runtime_enable(musb->controller);
1899
550a7375 1900 spin_lock_init(&musb->lock);
550a7375 1901 musb->board_set_power = plat->set_power;
550a7375 1902 musb->min_power = plat->min_power;
f7ec9437 1903 musb->ops = plat->platform_ops;
9ad96e69 1904 musb->port_mode = plat->mode;
550a7375 1905
84e250ff 1906 /* The musb_platform_init() call:
baef653a
PDS		 1907 * - adjusts musb->mregs
1908 * - sets the musb->isr
5ae477b0 1909 * - may initialize an integrated transceiver
721002ec 1910 * - initializes musb->xceiv, usually by otg_get_phy()
84e250ff 1911 * - stops powering VBUS
84e250ff 1912 *
7c9d440e 1913 * There are various transceiver configurations. Blackfin,
84e250ff
DB		 1914 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1915 * external/discrete ones in various flavors (twl4030 family,
1916 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
550a7375 1917 */
ea65df57 1918 status = musb_platform_init(musb);
550a7375 1919 if (status < 0)
03491761 1920 goto fail1;
34e2beb2 1921
550a7375
FB		 1922 if (!musb->isr) {
1923 status = -ENODEV;
c04352a5 1924 goto fail2;
550a7375
FB		 1925 }
1926
ffb865b1 1927 if (!musb->xceiv->io_ops) {
bf070bc1 1928 musb->xceiv->io_dev = musb->controller;
ffb865b1
HK		 1929 musb->xceiv->io_priv = musb->mregs;
1930 musb->xceiv->io_ops = &musb_ulpi_access;
1931 }
1932
c04352a5
GI		 1933 pm_runtime_get_sync(musb->controller);
1934
48054147 1935 if (use_dma && dev->dma_mask) {
66c01883 1936 musb->dma_controller = dma_controller_create(musb, musb->mregs);
48054147
SAS		 1937 if (IS_ERR(musb->dma_controller)) {
1938 status = PTR_ERR(musb->dma_controller);
1939 goto fail2_5;
1940 }
1941 }
550a7375
FB		 1942
1943 /* be sure interrupts are disabled before connecting ISR */
1944 musb_platform_disable(musb);
1945 musb_generic_disable(musb);
1946
66fadea5
SAS		 1947 /* Init IRQ workqueue before request_irq */
1948 INIT_WORK(&musb->irq_work, musb_irq_work);
675ae763 1949 INIT_DELAYED_WORK(&musb->recover_work, musb_recover_work);
8ed1fb79
DM		 1950 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
1951 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
66fadea5 1952
550a7375 1953 /* setup musb parts of the core (especially endpoints) */
ca6d1b13 1954 status = musb_core_init(plat->config->multipoint
550a7375
FB		 1955 ? MUSB_CONTROLLER_MHDRC
1956 : MUSB_CONTROLLER_HDRC, musb);
1957 if (status < 0)
34e2beb2 1958 goto fail3;
550a7375 1959
f7f9d63e 1960 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
f7f9d63e 1961
550a7375 1962 /* attach to the IRQ */
427c4f33 1963 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
550a7375
FB		 1964 dev_err(dev, "request_irq %d failed!\n", nIrq);
1965 status = -ENODEV;
34e2beb2 1966 goto fail3;
550a7375
FB		 1967 }
1968 musb->nIrq = nIrq;
032ec49f 1969 /* FIXME this handles wakeup irqs wrong */
c48a5155
FB		 1970 if (enable_irq_wake(nIrq) == 0) {
1971 musb->irq_wake = 1;
550a7375 1972 device_init_wakeup(dev, 1);
c48a5155
FB		 1973 } else {
1974 musb->irq_wake = 0;
1975 }
550a7375 1976
032ec49f
FB		 1977 /* program PHY to use external vBus if required */
1978 if (plat->extvbus) {
1979 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
1980 busctl |= MUSB_ULPI_USE_EXTVBUS;
1981 musb_write_ulpi_buscontrol(musb->mregs, busctl);
550a7375 1982 }
550a7375 1983
e5615112
GI		 1984 if (musb->xceiv->otg->default_a) {
1985 MUSB_HST_MODE(musb);
1986 musb->xceiv->state = OTG_STATE_A_IDLE;
1987 } else {
1988 MUSB_DEV_MODE(musb);
1989 musb->xceiv->state = OTG_STATE_B_IDLE;
1990 }
550a7375 1991
6c5f6a6f
DM		 1992 switch (musb->port_mode) {
1993 case MUSB_PORT_MODE_HOST:
1994 status = musb_host_setup(musb, plat->power);
2df6761e
FB		 1995 if (status < 0)
1996 goto fail3;
1997 status = musb_platform_set_mode(musb, MUSB_HOST);
6c5f6a6f
DM		 1998 break;
1999 case MUSB_PORT_MODE_GADGET:
2000 status = musb_gadget_setup(musb);
2df6761e
FB		 2001 if (status < 0)
2002 goto fail3;
2003 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
6c5f6a6f
DM		 2004 break;
2005 case MUSB_PORT_MODE_DUAL_ROLE:
2006 status = musb_host_setup(musb, plat->power);
2007 if (status < 0)
2008 goto fail3;
2009 status = musb_gadget_setup(musb);
2df6761e 2010 if (status) {
0d2dd7ea 2011 musb_host_cleanup(musb);
2df6761e
FB		 2012 goto fail3;
2013 }
2014 status = musb_platform_set_mode(musb, MUSB_OTG);
6c5f6a6f
DM		 2015 break;
2016 default:
2017 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2018 break;
2019 }
550a7375 2020
461972d8 2021 if (status < 0)
34e2beb2 2022 goto fail3;
550a7375 2023
7f7f9e2a
FB		 2024 status = musb_init_debugfs(musb);
2025 if (status < 0)
b0f9da7e 2026 goto fail4;
7f7f9e2a 2027
94375751 2028 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
28c2c51c 2029 if (status)
b0f9da7e 2030 goto fail5;
550a7375 2031
c04352a5
GI		 2032 pm_runtime_put(musb->controller);
2033
28c2c51c 2034 return 0;
550a7375 2035
b0f9da7e
FB		 2036fail5:
2037 musb_exit_debugfs(musb);
2038
34e2beb2 2039fail4:
032ec49f 2040 musb_gadget_cleanup(musb);
0d2dd7ea 2041 musb_host_cleanup(musb);
34e2beb2
SS		 2042
2043fail3:
66fadea5 2044 cancel_work_sync(&musb->irq_work);
675ae763 2045 cancel_delayed_work_sync(&musb->recover_work);
8ed1fb79
DM		 2046 cancel_delayed_work_sync(&musb->finish_resume_work);
2047 cancel_delayed_work_sync(&musb->deassert_reset_work);
f3ce4d5b
SAS		 2048 if (musb->dma_controller)
2049 dma_controller_destroy(musb->dma_controller);
48054147 2050fail2_5:
c04352a5
GI		 2051 pm_runtime_put_sync(musb->controller);
2052
2053fail2:
34e2beb2
SS		 2054 if (musb->irq_wake)
2055 device_init_wakeup(dev, 0);
550a7375 2056 musb_platform_exit(musb);
28c2c51c 2057
34e2beb2 2058fail1:
681d1e87 2059 pm_runtime_disable(musb->controller);
34e2beb2
SS		 2060 dev_err(musb->controller,
2061 "musb_init_controller failed with status %d\n", status);
2062
28c2c51c
FB		 2063 musb_free(musb);
2064
34e2beb2
SS		 2065fail0:
2066
28c2c51c
FB		 2067 return status;
2068
550a7375
FB		 2069}
2070
2071/*-------------------------------------------------------------------------*/
2072
2073/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2074 * bridge to a platform device; this driver then suffices.
2075 */
41ac7b3a 2076static int musb_probe(struct platform_device *pdev)
550a7375
FB		 2077{
2078 struct device *dev = &pdev->dev;
fcf173e4 2079 int irq = platform_get_irq_byname(pdev, "mc");
550a7375
FB		 2080 struct resource *iomem;
2081 void __iomem *base;
2082
2083 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
541079de 2084 if (!iomem || irq <= 0)
550a7375
FB		 2085 return -ENODEV;
2086
b42f7f30
FB		 2087 base = devm_ioremap_resource(dev, iomem);
2088 if (IS_ERR(base))
2089 return PTR_ERR(base);
550a7375 2090
b42f7f30 2091 return musb_init_controller(dev, irq, base);
550a7375
FB		 2092}
2093
fb4e98ab 2094static int musb_remove(struct platform_device *pdev)
550a7375 2095{
8d2421e6
AKG		 2096 struct device *dev = &pdev->dev;
2097 struct musb *musb = dev_to_musb(dev);
550a7375
FB		 2098
2099 /* this gets called on rmmod.
2100 * - Host mode: host may still be active
2101 * - Peripheral mode: peripheral is deactivated (or never-activated)
2102 * - OTG mode: both roles are deactivated (or never-activated)
2103 */
7f7f9e2a 2104 musb_exit_debugfs(musb);
550a7375 2105 musb_shutdown(pdev);
461972d8 2106
8d1aad74
SAS		 2107 if (musb->dma_controller)
2108 dma_controller_destroy(musb->dma_controller);
2109
66fadea5 2110 cancel_work_sync(&musb->irq_work);
675ae763 2111 cancel_delayed_work_sync(&musb->recover_work);
8ed1fb79
DM		 2112 cancel_delayed_work_sync(&musb->finish_resume_work);
2113 cancel_delayed_work_sync(&musb->deassert_reset_work);
550a7375 2114 musb_free(musb);
8d2421e6 2115 device_init_wakeup(dev, 0);
550a7375
FB		 2116 return 0;
2117}
2118
2119#ifdef CONFIG_PM
2120
3c8a5fcc 2121static void musb_save_context(struct musb *musb)
4f712e01
AKG		 2122{
2123 int i;
2124 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2125 void __iomem *epio;
4f712e01 2126
032ec49f
FB		 2127 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2128 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2129 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
7421107b 2130 musb->context.power = musb_readb(musb_base, MUSB_POWER);
7421107b
FB		 2131 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2132 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2133 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
4f712e01 2134
ae9b2ad2 2135 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2136 struct musb_hw_ep *hw_ep;
2137
2138 hw_ep = &musb->endpoints[i];
2139 if (!hw_ep)
2140 continue;
2141
2142 epio = hw_ep->regs;
2143 if (!epio)
2144 continue;
2145
ea737554 2146 musb_writeb(musb_base, MUSB_INDEX, i);
7421107b 2147 musb->context.index_regs[i].txmaxp =
ae9b2ad2 2148 musb_readw(epio, MUSB_TXMAXP);
7421107b 2149 musb->context.index_regs[i].txcsr =
ae9b2ad2 2150 musb_readw(epio, MUSB_TXCSR);
7421107b 2151 musb->context.index_regs[i].rxmaxp =
ae9b2ad2 2152 musb_readw(epio, MUSB_RXMAXP);
7421107b 2153 musb->context.index_regs[i].rxcsr =
ae9b2ad2 2154 musb_readw(epio, MUSB_RXCSR);
4f712e01
AKG		 2155
2156 if (musb->dyn_fifo) {
7421107b 2157 musb->context.index_regs[i].txfifoadd =
4f712e01 2158 musb_read_txfifoadd(musb_base);
7421107b 2159 musb->context.index_regs[i].rxfifoadd =
4f712e01 2160 musb_read_rxfifoadd(musb_base);
7421107b 2161 musb->context.index_regs[i].txfifosz =
4f712e01 2162 musb_read_txfifosz(musb_base);
7421107b 2163 musb->context.index_regs[i].rxfifosz =
4f712e01
AKG		 2164 musb_read_rxfifosz(musb_base);
2165 }
032ec49f
FB		 2166
2167 musb->context.index_regs[i].txtype =
2168 musb_readb(epio, MUSB_TXTYPE);
2169 musb->context.index_regs[i].txinterval =
2170 musb_readb(epio, MUSB_TXINTERVAL);
2171 musb->context.index_regs[i].rxtype =
2172 musb_readb(epio, MUSB_RXTYPE);
2173 musb->context.index_regs[i].rxinterval =
2174 musb_readb(epio, MUSB_RXINTERVAL);
2175
2176 musb->context.index_regs[i].txfunaddr =
2177 musb_read_txfunaddr(musb_base, i);
2178 musb->context.index_regs[i].txhubaddr =
2179 musb_read_txhubaddr(musb_base, i);
2180 musb->context.index_regs[i].txhubport =
2181 musb_read_txhubport(musb_base, i);
2182
2183 musb->context.index_regs[i].rxfunaddr =
2184 musb_read_rxfunaddr(musb_base, i);
2185 musb->context.index_regs[i].rxhubaddr =
2186 musb_read_rxhubaddr(musb_base, i);
2187 musb->context.index_regs[i].rxhubport =
2188 musb_read_rxhubport(musb_base, i);
4f712e01 2189 }
4f712e01
AKG		 2190}
2191
3c8a5fcc 2192static void musb_restore_context(struct musb *musb)
4f712e01
AKG		 2193{
2194 int i;
2195 void __iomem *musb_base = musb->mregs;
2196 void __iomem *ep_target_regs;
ae9b2ad2 2197 void __iomem *epio;
33f8d75f 2198 u8 power;
4f712e01 2199
032ec49f
FB		 2200 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2201 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2202 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
33f8d75f
RQ		 2203
2204 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2205 power = musb_readb(musb_base, MUSB_POWER);
2206 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2207 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2208 power |= musb->context.power;
2209 musb_writeb(musb_base, MUSB_POWER, power);
2210
b18d26f6 2211 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
af5ec14d 2212 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
7421107b
FB		 2213 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2214 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
4f712e01 2215
ae9b2ad2 2216 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2217 struct musb_hw_ep *hw_ep;
2218
2219 hw_ep = &musb->endpoints[i];
2220 if (!hw_ep)
2221 continue;
2222
2223 epio = hw_ep->regs;
2224 if (!epio)
2225 continue;
2226
ea737554 2227 musb_writeb(musb_base, MUSB_INDEX, i);
ae9b2ad2 2228 musb_writew(epio, MUSB_TXMAXP,
7421107b 2229 musb->context.index_regs[i].txmaxp);
ae9b2ad2 2230 musb_writew(epio, MUSB_TXCSR,
7421107b 2231 musb->context.index_regs[i].txcsr);
ae9b2ad2 2232 musb_writew(epio, MUSB_RXMAXP,
7421107b 2233 musb->context.index_regs[i].rxmaxp);
ae9b2ad2 2234 musb_writew(epio, MUSB_RXCSR,
7421107b 2235 musb->context.index_regs[i].rxcsr);
4f712e01
AKG		 2236
2237 if (musb->dyn_fifo) {
2238 musb_write_txfifosz(musb_base,
7421107b 2239 musb->context.index_regs[i].txfifosz);
4f712e01 2240 musb_write_rxfifosz(musb_base,
7421107b 2241 musb->context.index_regs[i].rxfifosz);
4f712e01 2242 musb_write_txfifoadd(musb_base,
7421107b 2243 musb->context.index_regs[i].txfifoadd);
4f712e01 2244 musb_write_rxfifoadd(musb_base,
7421107b 2245 musb->context.index_regs[i].rxfifoadd);
4f712e01
AKG		 2246 }
2247
032ec49f 2248 musb_writeb(epio, MUSB_TXTYPE,
7421107b 2249 musb->context.index_regs[i].txtype);
032ec49f 2250 musb_writeb(epio, MUSB_TXINTERVAL,
7421107b 2251 musb->context.index_regs[i].txinterval);
032ec49f 2252 musb_writeb(epio, MUSB_RXTYPE,
7421107b 2253 musb->context.index_regs[i].rxtype);
032ec49f 2254 musb_writeb(epio, MUSB_RXINTERVAL,
4f712e01 2255
032ec49f
FB		 2256 musb->context.index_regs[i].rxinterval);
2257 musb_write_txfunaddr(musb_base, i,
7421107b 2258 musb->context.index_regs[i].txfunaddr);
032ec49f 2259 musb_write_txhubaddr(musb_base, i,
7421107b 2260 musb->context.index_regs[i].txhubaddr);
032ec49f 2261 musb_write_txhubport(musb_base, i,
7421107b 2262 musb->context.index_regs[i].txhubport);
4f712e01 2263
032ec49f
FB		 2264 ep_target_regs =
2265 musb_read_target_reg_base(i, musb_base);
4f712e01 2266
032ec49f 2267 musb_write_rxfunaddr(ep_target_regs,
7421107b 2268 musb->context.index_regs[i].rxfunaddr);
032ec49f 2269 musb_write_rxhubaddr(ep_target_regs,
7421107b 2270 musb->context.index_regs[i].rxhubaddr);
032ec49f 2271 musb_write_rxhubport(ep_target_regs,
7421107b 2272 musb->context.index_regs[i].rxhubport);
4f712e01 2273 }
3c5fec75 2274 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
4f712e01
AKG		 2275}
2276
48fea965 2277static int musb_suspend(struct device *dev)
550a7375 2278{
8220796d 2279 struct musb *musb = dev_to_musb(dev);
550a7375 2280 unsigned long flags;
550a7375 2281
550a7375
FB		 2282 spin_lock_irqsave(&musb->lock, flags);
2283
2284 if (is_peripheral_active(musb)) {
2285 /* FIXME force disconnect unless we know USB will wake
2286 * the system up quickly enough to respond ...
2287 */
2288 } else if (is_host_active(musb)) {
2289 /* we know all the children are suspended; sometimes
2290 * they will even be wakeup-enabled.
2291 */
2292 }
2293
c338412b
DM		 2294 musb_save_context(musb);
2295
550a7375
FB		 2296 spin_unlock_irqrestore(&musb->lock, flags);
2297 return 0;
2298}
2299
48fea965 2300static int musb_resume_noirq(struct device *dev)
550a7375 2301{
c338412b
DM		 2302 struct musb *musb = dev_to_musb(dev);
2303
2304 /*
2305 * For static cmos like DaVinci, register values were preserved
0ec8fd70
KK		 2306 * unless for some reason the whole soc powered down or the USB
2307 * module got reset through the PSC (vs just being disabled).
c338412b
DM		 2308 *
2309 * For the DSPS glue layer though, a full register restore has to
2310 * be done. As it shouldn't harm other platforms, we do it
2311 * unconditionally.
550a7375 2312 */
c338412b
DM		 2313
2314 musb_restore_context(musb);
2315
550a7375
FB		 2316 return 0;
2317}
2318
7acc6197
HH		 2319static int musb_runtime_suspend(struct device *dev)
2320{
2321 struct musb *musb = dev_to_musb(dev);
2322
2323 musb_save_context(musb);
2324
2325 return 0;
2326}
2327
2328static int musb_runtime_resume(struct device *dev)
2329{
2330 struct musb *musb = dev_to_musb(dev);
2331 static int first = 1;
2332
2333 /*
2334 * When pm_runtime_get_sync called for the first time in driver
2335 * init, some of the structure is still not initialized which is
2336 * used in restore function. But clock needs to be
2337 * enabled before any register access, so
2338 * pm_runtime_get_sync has to be called.
2339 * Also context restore without save does not make
2340 * any sense
2341 */
2342 if (!first)
2343 musb_restore_context(musb);
2344 first = 0;
2345
2346 return 0;
2347}
2348
47145210 2349static const struct dev_pm_ops musb_dev_pm_ops = {
48fea965
MD		 2350 .suspend = musb_suspend,
2351 .resume_noirq = musb_resume_noirq,
7acc6197
HH		 2352 .runtime_suspend = musb_runtime_suspend,
2353 .runtime_resume = musb_runtime_resume,
48fea965
MD		 2354};
2355
2356#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
550a7375 2357#else
48fea965 2358#define MUSB_DEV_PM_OPS NULL
550a7375
FB		 2359#endif
2360
2361static struct platform_driver musb_driver = {
2362 .driver = {
2363 .name = (char *)musb_driver_name,
2364 .bus = &platform_bus_type,
2365 .owner = THIS_MODULE,
48fea965 2366 .pm = MUSB_DEV_PM_OPS,
550a7375 2367 },
e9e8c85e 2368 .probe = musb_probe,
7690417d 2369 .remove = musb_remove,
550a7375 2370 .shutdown = musb_shutdown,
550a7375
FB		 2371};
2372
89f836a8 2373module_platform_driver(musb_driver);
Linux kernel - Deliverables
This page took 0.60264 seconds and 5 git commands to generate.