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usb: remove code associated with !CONFIG_PPC_MERGE
[deliverable/linux.git] / drivers / usb / musb / musb_core.c
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550a7375
FB		 1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - <asm/arch/hdrc_cnf.h> for SOC or family details
86 * - platform_device for addressing, irq, and platform_data
87 * - platform_data is mostly for board-specific informarion
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
96#include <linux/init.h>
97#include <linux/list.h>
98#include <linux/kobject.h>
99#include <linux/platform_device.h>
100#include <linux/io.h>
101
102#ifdef CONFIG_ARM
0590d587
FB		 103#include <mach/hardware.h>
104#include <mach/memory.h>
550a7375
FB		 105#include <asm/mach-types.h>
106#endif
107
108#include "musb_core.h"
109
110
111#ifdef CONFIG_ARCH_DAVINCI
112#include "davinci.h"
113#endif
114
115
116
e8164f64
FB		 117unsigned debug;
118module_param(debug, uint, S_IRUGO | S_IWUSR);
119MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
550a7375
FB		 120
121#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
122#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
123
e8164f64 124#define MUSB_VERSION "6.0"
550a7375
FB		 125
126#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
127
128#define MUSB_DRIVER_NAME "musb_hdrc"
129const char musb_driver_name[] = MUSB_DRIVER_NAME;
130
131MODULE_DESCRIPTION(DRIVER_INFO);
132MODULE_AUTHOR(DRIVER_AUTHOR);
133MODULE_LICENSE("GPL");
134MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
135
136
137/*-------------------------------------------------------------------------*/
138
139static inline struct musb *dev_to_musb(struct device *dev)
140{
141#ifdef CONFIG_USB_MUSB_HDRC_HCD
142 /* usbcore insists dev->driver_data is a "struct hcd *" */
143 return hcd_to_musb(dev_get_drvdata(dev));
144#else
145 return dev_get_drvdata(dev);
146#endif
147}
148
149/*-------------------------------------------------------------------------*/
150
151#ifndef CONFIG_USB_TUSB6010
152/*
153 * Load an endpoint's FIFO
154 */
155void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
156{
157 void __iomem *fifo = hw_ep->fifo;
158
159 prefetch((u8 *)src);
160
161 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
162 'T', hw_ep->epnum, fifo, len, src);
163
164 /* we can't assume unaligned reads work */
165 if (likely((0x01 & (unsigned long) src) == 0)) {
166 u16 index = 0;
167
168 /* best case is 32bit-aligned source address */
169 if ((0x02 & (unsigned long) src) == 0) {
170 if (len >= 4) {
171 writesl(fifo, src + index, len >> 2);
172 index += len & ~0x03;
173 }
174 if (len & 0x02) {
175 musb_writew(fifo, 0, *(u16 *)&src[index]);
176 index += 2;
177 }
178 } else {
179 if (len >= 2) {
180 writesw(fifo, src + index, len >> 1);
181 index += len & ~0x01;
182 }
183 }
184 if (len & 0x01)
185 musb_writeb(fifo, 0, src[index]);
186 } else {
187 /* byte aligned */
188 writesb(fifo, src, len);
189 }
190}
191
192/*
193 * Unload an endpoint's FIFO
194 */
195void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
196{
197 void __iomem *fifo = hw_ep->fifo;
198
199 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
200 'R', hw_ep->epnum, fifo, len, dst);
201
202 /* we can't assume unaligned writes work */
203 if (likely((0x01 & (unsigned long) dst) == 0)) {
204 u16 index = 0;
205
206 /* best case is 32bit-aligned destination address */
207 if ((0x02 & (unsigned long) dst) == 0) {
208 if (len >= 4) {
209 readsl(fifo, dst, len >> 2);
210 index = len & ~0x03;
211 }
212 if (len & 0x02) {
213 *(u16 *)&dst[index] = musb_readw(fifo, 0);
214 index += 2;
215 }
216 } else {
217 if (len >= 2) {
218 readsw(fifo, dst, len >> 1);
219 index = len & ~0x01;
220 }
221 }
222 if (len & 0x01)
223 dst[index] = musb_readb(fifo, 0);
224 } else {
225 /* byte aligned */
226 readsb(fifo, dst, len);
227 }
228}
229
230#endif /* normal PIO */
231
232
233/*-------------------------------------------------------------------------*/
234
235/* for high speed test mode; see USB 2.0 spec 7.1.20 */
236static const u8 musb_test_packet[53] = {
237 /* implicit SYNC then DATA0 to start */
238
239 /* JKJKJKJK x9 */
240 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
241 /* JJKKJJKK x8 */
242 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
243 /* JJJJKKKK x8 */
244 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
245 /* JJJJJJJKKKKKKK x8 */
246 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
247 /* JJJJJJJK x8 */
248 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
249 /* JKKKKKKK x10, JK */
250 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
251
252 /* implicit CRC16 then EOP to end */
253};
254
255void musb_load_testpacket(struct musb *musb)
256{
257 void __iomem *regs = musb->endpoints[0].regs;
258
259 musb_ep_select(musb->mregs, 0);
260 musb_write_fifo(musb->control_ep,
261 sizeof(musb_test_packet), musb_test_packet);
262 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
263}
264
265/*-------------------------------------------------------------------------*/
266
267const char *otg_state_string(struct musb *musb)
268{
269 switch (musb->xceiv.state) {
270 case OTG_STATE_A_IDLE: return "a_idle";
271 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
272 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
273 case OTG_STATE_A_HOST: return "a_host";
274 case OTG_STATE_A_SUSPEND: return "a_suspend";
275 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
276 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
277 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
278 case OTG_STATE_B_IDLE: return "b_idle";
279 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
280 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
281 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
282 case OTG_STATE_B_HOST: return "b_host";
283 default: return "UNDEFINED";
284 }
285}
286
287#ifdef CONFIG_USB_MUSB_OTG
288
289/*
290 * See also USB_OTG_1-3.pdf 6.6.5 Timers
291 * REVISIT: Are the other timers done in the hardware?
292 */
293#define TB_ASE0_BRST 100 /* Min 3.125 ms */
294
295/*
296 * Handles OTG hnp timeouts, such as b_ase0_brst
297 */
298void musb_otg_timer_func(unsigned long data)
299{
300 struct musb *musb = (struct musb *)data;
301 unsigned long flags;
302
303 spin_lock_irqsave(&musb->lock, flags);
304 switch (musb->xceiv.state) {
305 case OTG_STATE_B_WAIT_ACON:
306 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
307 musb_g_disconnect(musb);
308 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
309 musb->is_active = 0;
310 break;
311 case OTG_STATE_A_WAIT_BCON:
312 DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n");
313 musb_hnp_stop(musb);
314 break;
315 default:
316 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
317 }
318 musb->ignore_disconnect = 0;
319 spin_unlock_irqrestore(&musb->lock, flags);
320}
321
322static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
323
324/*
325 * Stops the B-device HNP state. Caller must take care of locking.
326 */
327void musb_hnp_stop(struct musb *musb)
328{
329 struct usb_hcd *hcd = musb_to_hcd(musb);
330 void __iomem *mbase = musb->mregs;
331 u8 reg;
332
333 switch (musb->xceiv.state) {
334 case OTG_STATE_A_PERIPHERAL:
335 case OTG_STATE_A_WAIT_VFALL:
336 case OTG_STATE_A_WAIT_BCON:
337 DBG(1, "HNP: Switching back to A-host\n");
338 musb_g_disconnect(musb);
339 musb->xceiv.state = OTG_STATE_A_IDLE;
340 MUSB_HST_MODE(musb);
341 musb->is_active = 0;
342 break;
343 case OTG_STATE_B_HOST:
344 DBG(1, "HNP: Disabling HR\n");
345 hcd->self.is_b_host = 0;
346 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
347 MUSB_DEV_MODE(musb);
348 reg = musb_readb(mbase, MUSB_POWER);
349 reg |= MUSB_POWER_SUSPENDM;
350 musb_writeb(mbase, MUSB_POWER, reg);
351 /* REVISIT: Start SESSION_REQUEST here? */
352 break;
353 default:
354 DBG(1, "HNP: Stopping in unknown state %s\n",
355 otg_state_string(musb));
356 }
357
358 /*
359 * When returning to A state after HNP, avoid hub_port_rebounce(),
360 * which cause occasional OPT A "Did not receive reset after connect"
361 * errors.
362 */
363 musb->port1_status &=
364 ~(1 << USB_PORT_FEAT_C_CONNECTION);
365}
366
367#endif
368
369/*
370 * Interrupt Service Routine to record USB "global" interrupts.
371 * Since these do not happen often and signify things of
372 * paramount importance, it seems OK to check them individually;
373 * the order of the tests is specified in the manual
374 *
375 * @param musb instance pointer
376 * @param int_usb register contents
377 * @param devctl
378 * @param power
379 */
380
381#define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
382 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
383 | MUSB_INTR_RESET)
384
385static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
386 u8 devctl, u8 power)
387{
388 irqreturn_t handled = IRQ_NONE;
389 void __iomem *mbase = musb->mregs;
390
391 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
392 int_usb);
393
394 /* in host mode, the peripheral may issue remote wakeup.
395 * in peripheral mode, the host may resume the link.
396 * spurious RESUME irqs happen too, paired with SUSPEND.
397 */
398 if (int_usb & MUSB_INTR_RESUME) {
399 handled = IRQ_HANDLED;
400 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
401
402 if (devctl & MUSB_DEVCTL_HM) {
403#ifdef CONFIG_USB_MUSB_HDRC_HCD
404 switch (musb->xceiv.state) {
405 case OTG_STATE_A_SUSPEND:
406 /* remote wakeup? later, GetPortStatus
407 * will stop RESUME signaling
408 */
409
410 if (power & MUSB_POWER_SUSPENDM) {
411 /* spurious */
412 musb->int_usb &= ~MUSB_INTR_SUSPEND;
413 DBG(2, "Spurious SUSPENDM\n");
414 break;
415 }
416
417 power &= ~MUSB_POWER_SUSPENDM;
418 musb_writeb(mbase, MUSB_POWER,
419 power | MUSB_POWER_RESUME);
420
421 musb->port1_status |=
422 (USB_PORT_STAT_C_SUSPEND << 16)
423 | MUSB_PORT_STAT_RESUME;
424 musb->rh_timer = jiffies
425 + msecs_to_jiffies(20);
426
427 musb->xceiv.state = OTG_STATE_A_HOST;
428 musb->is_active = 1;
429 usb_hcd_resume_root_hub(musb_to_hcd(musb));
430 break;
431 case OTG_STATE_B_WAIT_ACON:
432 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
433 musb->is_active = 1;
434 MUSB_DEV_MODE(musb);
435 break;
436 default:
437 WARNING("bogus %s RESUME (%s)\n",
438 "host",
439 otg_state_string(musb));
440 }
441#endif
442 } else {
443 switch (musb->xceiv.state) {
444#ifdef CONFIG_USB_MUSB_HDRC_HCD
445 case OTG_STATE_A_SUSPEND:
446 /* possibly DISCONNECT is upcoming */
447 musb->xceiv.state = OTG_STATE_A_HOST;
448 usb_hcd_resume_root_hub(musb_to_hcd(musb));
449 break;
450#endif
451#ifdef CONFIG_USB_GADGET_MUSB_HDRC
452 case OTG_STATE_B_WAIT_ACON:
453 case OTG_STATE_B_PERIPHERAL:
454 /* disconnect while suspended? we may
455 * not get a disconnect irq...
456 */
457 if ((devctl & MUSB_DEVCTL_VBUS)
458 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
459 ) {
460 musb->int_usb |= MUSB_INTR_DISCONNECT;
461 musb->int_usb &= ~MUSB_INTR_SUSPEND;
462 break;
463 }
464 musb_g_resume(musb);
465 break;
466 case OTG_STATE_B_IDLE:
467 musb->int_usb &= ~MUSB_INTR_SUSPEND;
468 break;
469#endif
470 default:
471 WARNING("bogus %s RESUME (%s)\n",
472 "peripheral",
473 otg_state_string(musb));
474 }
475 }
476 }
477
478#ifdef CONFIG_USB_MUSB_HDRC_HCD
479 /* see manual for the order of the tests */
480 if (int_usb & MUSB_INTR_SESSREQ) {
481 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
482
483 /* IRQ arrives from ID pin sense or (later, if VBUS power
484 * is removed) SRP. responses are time critical:
485 * - turn on VBUS (with silicon-specific mechanism)
486 * - go through A_WAIT_VRISE
487 * - ... to A_WAIT_BCON.
488 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
489 */
490 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
491 musb->ep0_stage = MUSB_EP0_START;
492 musb->xceiv.state = OTG_STATE_A_IDLE;
493 MUSB_HST_MODE(musb);
494 musb_set_vbus(musb, 1);
495
496 handled = IRQ_HANDLED;
497 }
498
499 if (int_usb & MUSB_INTR_VBUSERROR) {
500 int ignore = 0;
501
502 /* During connection as an A-Device, we may see a short
503 * current spikes causing voltage drop, because of cable
504 * and peripheral capacitance combined with vbus draw.
505 * (So: less common with truly self-powered devices, where
506 * vbus doesn't act like a power supply.)
507 *
508 * Such spikes are short; usually less than ~500 usec, max
509 * of ~2 msec. That is, they're not sustained overcurrent
510 * errors, though they're reported using VBUSERROR irqs.
511 *
512 * Workarounds: (a) hardware: use self powered devices.
513 * (b) software: ignore non-repeated VBUS errors.
514 *
515 * REVISIT: do delays from lots of DEBUG_KERNEL checks
516 * make trouble here, keeping VBUS < 4.4V ?
517 */
518 switch (musb->xceiv.state) {
519 case OTG_STATE_A_HOST:
520 /* recovery is dicey once we've gotten past the
521 * initial stages of enumeration, but if VBUS
522 * stayed ok at the other end of the link, and
523 * another reset is due (at least for high speed,
524 * to redo the chirp etc), it might work OK...
525 */
526 case OTG_STATE_A_WAIT_BCON:
527 case OTG_STATE_A_WAIT_VRISE:
528 if (musb->vbuserr_retry) {
529 musb->vbuserr_retry--;
530 ignore = 1;
531 devctl |= MUSB_DEVCTL_SESSION;
532 musb_writeb(mbase, MUSB_DEVCTL, devctl);
533 } else {
534 musb->port1_status |=
535 (1 << USB_PORT_FEAT_OVER_CURRENT)
536 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
537 }
538 break;
539 default:
540 break;
541 }
542
543 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
544 otg_state_string(musb),
545 devctl,
546 ({ char *s;
547 switch (devctl & MUSB_DEVCTL_VBUS) {
548 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
549 s = "<SessEnd"; break;
550 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
551 s = "<AValid"; break;
552 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
553 s = "<VBusValid"; break;
554 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
555 default:
556 s = "VALID"; break;
557 }; s; }),
558 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
559 musb->port1_status);
560
561 /* go through A_WAIT_VFALL then start a new session */
562 if (!ignore)
563 musb_set_vbus(musb, 0);
564 handled = IRQ_HANDLED;
565 }
566
567 if (int_usb & MUSB_INTR_CONNECT) {
568 struct usb_hcd *hcd = musb_to_hcd(musb);
569
570 handled = IRQ_HANDLED;
571 musb->is_active = 1;
572 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
573
574 musb->ep0_stage = MUSB_EP0_START;
575
576#ifdef CONFIG_USB_MUSB_OTG
577 /* flush endpoints when transitioning from Device Mode */
578 if (is_peripheral_active(musb)) {
579 /* REVISIT HNP; just force disconnect */
580 }
581 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
582 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
583 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
584#endif
585 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
586 |USB_PORT_STAT_HIGH_SPEED
587 |USB_PORT_STAT_ENABLE
588 );
589 musb->port1_status |= USB_PORT_STAT_CONNECTION
590 |(USB_PORT_STAT_C_CONNECTION << 16);
591
592 /* high vs full speed is just a guess until after reset */
593 if (devctl & MUSB_DEVCTL_LSDEV)
594 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
595
596 if (hcd->status_urb)
597 usb_hcd_poll_rh_status(hcd);
598 else
599 usb_hcd_resume_root_hub(hcd);
600
601 MUSB_HST_MODE(musb);
602
603 /* indicate new connection to OTG machine */
604 switch (musb->xceiv.state) {
605 case OTG_STATE_B_PERIPHERAL:
606 if (int_usb & MUSB_INTR_SUSPEND) {
607 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
608 musb->xceiv.state = OTG_STATE_B_HOST;
609 hcd->self.is_b_host = 1;
610 int_usb &= ~MUSB_INTR_SUSPEND;
611 } else
612 DBG(1, "CONNECT as b_peripheral???\n");
613 break;
614 case OTG_STATE_B_WAIT_ACON:
615 DBG(1, "HNP: Waiting to switch to b_host state\n");
616 musb->xceiv.state = OTG_STATE_B_HOST;
617 hcd->self.is_b_host = 1;
618 break;
619 default:
620 if ((devctl & MUSB_DEVCTL_VBUS)
621 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
622 musb->xceiv.state = OTG_STATE_A_HOST;
623 hcd->self.is_b_host = 0;
624 }
625 break;
626 }
627 DBG(1, "CONNECT (%s) devctl %02x\n",
628 otg_state_string(musb), devctl);
629 }
630#endif /* CONFIG_USB_MUSB_HDRC_HCD */
631
632 /* mentor saves a bit: bus reset and babble share the same irq.
633 * only host sees babble; only peripheral sees bus reset.
634 */
635 if (int_usb & MUSB_INTR_RESET) {
636 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
637 /*
638 * Looks like non-HS BABBLE can be ignored, but
639 * HS BABBLE is an error condition. For HS the solution
640 * is to avoid babble in the first place and fix what
641 * caused BABBLE. When HS BABBLE happens we can only
642 * stop the session.
643 */
644 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
645 DBG(1, "BABBLE devctl: %02x\n", devctl);
646 else {
647 ERR("Stopping host session -- babble\n");
648 musb_writeb(mbase, MUSB_DEVCTL, 0);
649 }
650 } else if (is_peripheral_capable()) {
651 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
652 switch (musb->xceiv.state) {
653#ifdef CONFIG_USB_OTG
654 case OTG_STATE_A_SUSPEND:
655 /* We need to ignore disconnect on suspend
656 * otherwise tusb 2.0 won't reconnect after a
657 * power cycle, which breaks otg compliance.
658 */
659 musb->ignore_disconnect = 1;
660 musb_g_reset(musb);
661 /* FALLTHROUGH */
662 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
663 DBG(1, "HNP: Setting timer as %s\n",
664 otg_state_string(musb));
665 musb_otg_timer.data = (unsigned long)musb;
666 mod_timer(&musb_otg_timer, jiffies
667 + msecs_to_jiffies(100));
668 break;
669 case OTG_STATE_A_PERIPHERAL:
670 musb_hnp_stop(musb);
671 break;
672 case OTG_STATE_B_WAIT_ACON:
673 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
674 otg_state_string(musb));
675 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
676 musb_g_reset(musb);
677 break;
678#endif
679 case OTG_STATE_B_IDLE:
680 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
681 /* FALLTHROUGH */
682 case OTG_STATE_B_PERIPHERAL:
683 musb_g_reset(musb);
684 break;
685 default:
686 DBG(1, "Unhandled BUS RESET as %s\n",
687 otg_state_string(musb));
688 }
689 }
690
691 handled = IRQ_HANDLED;
692 }
693 schedule_work(&musb->irq_work);
694
695 return handled;
696}
697
698/*
699 * Interrupt Service Routine to record USB "global" interrupts.
700 * Since these do not happen often and signify things of
701 * paramount importance, it seems OK to check them individually;
702 * the order of the tests is specified in the manual
703 *
704 * @param musb instance pointer
705 * @param int_usb register contents
706 * @param devctl
707 * @param power
708 */
709static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
710 u8 devctl, u8 power)
711{
712 irqreturn_t handled = IRQ_NONE;
713
714#if 0
715/* REVISIT ... this would be for multiplexing periodic endpoints, or
716 * supporting transfer phasing to prevent exceeding ISO bandwidth
717 * limits of a given frame or microframe.
718 *
719 * It's not needed for peripheral side, which dedicates endpoints;
720 * though it _might_ use SOF irqs for other purposes.
721 *
722 * And it's not currently needed for host side, which also dedicates
723 * endpoints, relies on TX/RX interval registers, and isn't claimed
724 * to support ISO transfers yet.
725 */
726 if (int_usb & MUSB_INTR_SOF) {
727 void __iomem *mbase = musb->mregs;
728 struct musb_hw_ep *ep;
729 u8 epnum;
730 u16 frame;
731
732 DBG(6, "START_OF_FRAME\n");
733 handled = IRQ_HANDLED;
734
735 /* start any periodic Tx transfers waiting for current frame */
736 frame = musb_readw(mbase, MUSB_FRAME);
737 ep = musb->endpoints;
738 for (epnum = 1; (epnum < musb->nr_endpoints)
739 && (musb->epmask >= (1 << epnum));
740 epnum++, ep++) {
741 /*
742 * FIXME handle framecounter wraps (12 bits)
743 * eliminate duplicated StartUrb logic
744 */
745 if (ep->dwWaitFrame >= frame) {
746 ep->dwWaitFrame = 0;
747 pr_debug("SOF --> periodic TX%s on %d\n",
748 ep->tx_channel ? " DMA" : "",
749 epnum);
750 if (!ep->tx_channel)
751 musb_h_tx_start(musb, epnum);
752 else
753 cppi_hostdma_start(musb, epnum);
754 }
755 } /* end of for loop */
756 }
757#endif
758
759 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
760 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
761 otg_state_string(musb),
762 MUSB_MODE(musb), devctl);
763 handled = IRQ_HANDLED;
764
765 switch (musb->xceiv.state) {
766#ifdef CONFIG_USB_MUSB_HDRC_HCD
767 case OTG_STATE_A_HOST:
768 case OTG_STATE_A_SUSPEND:
769 musb_root_disconnect(musb);
770 if (musb->a_wait_bcon != 0)
771 musb_platform_try_idle(musb, jiffies
772 + msecs_to_jiffies(musb->a_wait_bcon));
773 break;
774#endif /* HOST */
775#ifdef CONFIG_USB_MUSB_OTG
776 case OTG_STATE_B_HOST:
777 musb_hnp_stop(musb);
778 break;
779 case OTG_STATE_A_PERIPHERAL:
780 musb_hnp_stop(musb);
781 musb_root_disconnect(musb);
782 /* FALLTHROUGH */
783 case OTG_STATE_B_WAIT_ACON:
784 /* FALLTHROUGH */
785#endif /* OTG */
786#ifdef CONFIG_USB_GADGET_MUSB_HDRC
787 case OTG_STATE_B_PERIPHERAL:
788 case OTG_STATE_B_IDLE:
789 musb_g_disconnect(musb);
790 break;
791#endif /* GADGET */
792 default:
793 WARNING("unhandled DISCONNECT transition (%s)\n",
794 otg_state_string(musb));
795 break;
796 }
797
798 schedule_work(&musb->irq_work);
799 }
800
801 if (int_usb & MUSB_INTR_SUSPEND) {
802 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
803 otg_state_string(musb), devctl, power);
804 handled = IRQ_HANDLED;
805
806 switch (musb->xceiv.state) {
807#ifdef CONFIG_USB_MUSB_OTG
808 case OTG_STATE_A_PERIPHERAL:
809 /*
810 * We cannot stop HNP here, devctl BDEVICE might be
811 * still set.
812 */
813 break;
814#endif
815 case OTG_STATE_B_PERIPHERAL:
816 musb_g_suspend(musb);
817 musb->is_active = is_otg_enabled(musb)
818 && musb->xceiv.gadget->b_hnp_enable;
819 if (musb->is_active) {
820#ifdef CONFIG_USB_MUSB_OTG
821 musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
822 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
823 musb_otg_timer.data = (unsigned long)musb;
824 mod_timer(&musb_otg_timer, jiffies
825 + msecs_to_jiffies(TB_ASE0_BRST));
826#endif
827 }
828 break;
829 case OTG_STATE_A_WAIT_BCON:
830 if (musb->a_wait_bcon != 0)
831 musb_platform_try_idle(musb, jiffies
832 + msecs_to_jiffies(musb->a_wait_bcon));
833 break;
834 case OTG_STATE_A_HOST:
835 musb->xceiv.state = OTG_STATE_A_SUSPEND;
836 musb->is_active = is_otg_enabled(musb)
837 && musb->xceiv.host->b_hnp_enable;
838 break;
839 case OTG_STATE_B_HOST:
840 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
841 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
842 break;
843 default:
844 /* "should not happen" */
845 musb->is_active = 0;
846 break;
847 }
848 schedule_work(&musb->irq_work);
849 }
850
851
852 return handled;
853}
854
855/*-------------------------------------------------------------------------*/
856
857/*
858* Program the HDRC to start (enable interrupts, dma, etc.).
859*/
860void musb_start(struct musb *musb)
861{
862 void __iomem *regs = musb->mregs;
863 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
864
865 DBG(2, "<== devctl %02x\n", devctl);
866
867 /* Set INT enable registers, enable interrupts */
868 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
869 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
870 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
871
872 musb_writeb(regs, MUSB_TESTMODE, 0);
873
874 /* put into basic highspeed mode and start session */
875 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
876 | MUSB_POWER_SOFTCONN
877 | MUSB_POWER_HSENAB
878 /* ENSUSPEND wedges tusb */
879 /* | MUSB_POWER_ENSUSPEND */
880 );
881
882 musb->is_active = 0;
883 devctl = musb_readb(regs, MUSB_DEVCTL);
884 devctl &= ~MUSB_DEVCTL_SESSION;
885
886 if (is_otg_enabled(musb)) {
887 /* session started after:
888 * (a) ID-grounded irq, host mode;
889 * (b) vbus present/connect IRQ, peripheral mode;
890 * (c) peripheral initiates, using SRP
891 */
892 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
893 musb->is_active = 1;
894 else
895 devctl |= MUSB_DEVCTL_SESSION;
896
897 } else if (is_host_enabled(musb)) {
898 /* assume ID pin is hard-wired to ground */
899 devctl |= MUSB_DEVCTL_SESSION;
900
901 } else /* peripheral is enabled */ {
902 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
903 musb->is_active = 1;
904 }
905 musb_platform_enable(musb);
906 musb_writeb(regs, MUSB_DEVCTL, devctl);
907}
908
909
910static void musb_generic_disable(struct musb *musb)
911{
912 void __iomem *mbase = musb->mregs;
913 u16 temp;
914
915 /* disable interrupts */
916 musb_writeb(mbase, MUSB_INTRUSBE, 0);
917 musb_writew(mbase, MUSB_INTRTXE, 0);
918 musb_writew(mbase, MUSB_INTRRXE, 0);
919
920 /* off */
921 musb_writeb(mbase, MUSB_DEVCTL, 0);
922
923 /* flush pending interrupts */
924 temp = musb_readb(mbase, MUSB_INTRUSB);
925 temp = musb_readw(mbase, MUSB_INTRTX);
926 temp = musb_readw(mbase, MUSB_INTRRX);
927
928}
929
930/*
931 * Make the HDRC stop (disable interrupts, etc.);
932 * reversible by musb_start
933 * called on gadget driver unregister
934 * with controller locked, irqs blocked
935 * acts as a NOP unless some role activated the hardware
936 */
937void musb_stop(struct musb *musb)
938{
939 /* stop IRQs, timers, ... */
940 musb_platform_disable(musb);
941 musb_generic_disable(musb);
942 DBG(3, "HDRC disabled\n");
943
944 /* FIXME
945 * - mark host and/or peripheral drivers unusable/inactive
946 * - disable DMA (and enable it in HdrcStart)
947 * - make sure we can musb_start() after musb_stop(); with
948 * OTG mode, gadget driver module rmmod/modprobe cycles that
949 * - ...
950 */
951 musb_platform_try_idle(musb, 0);
952}
953
954static void musb_shutdown(struct platform_device *pdev)
955{
956 struct musb *musb = dev_to_musb(&pdev->dev);
957 unsigned long flags;
958
959 spin_lock_irqsave(&musb->lock, flags);
960 musb_platform_disable(musb);
961 musb_generic_disable(musb);
962 if (musb->clock) {
963 clk_put(musb->clock);
964 musb->clock = NULL;
965 }
966 spin_unlock_irqrestore(&musb->lock, flags);
967
968 /* FIXME power down */
969}
970
971
972/*-------------------------------------------------------------------------*/
973
974/*
975 * The silicon either has hard-wired endpoint configurations, or else
976 * "dynamic fifo" sizing. The driver has support for both, though at this
977 * writing only the dynamic sizing is very well tested. We use normal
978 * idioms to so both modes are compile-tested, but dead code elimination
979 * leaves only the relevant one in the object file.
980 *
981 * We don't currently use dynamic fifo setup capability to do anything
982 * more than selecting one of a bunch of predefined configurations.
983 */
550a7375
FB		 984#if defined(CONFIG_USB_TUSB6010) || \
985 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
986static ushort __initdata fifo_mode = 4;
987#else
988static ushort __initdata fifo_mode = 2;
989#endif
990
991/* "modprobe ... fifo_mode=1" etc */
992module_param(fifo_mode, ushort, 0);
993MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
994
995
550a7375
FB		 996enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
997enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
998
999struct fifo_cfg {
1000 u8 hw_ep_num;
1001 enum fifo_style style;
1002 enum buf_mode mode;
1003 u16 maxpacket;
1004};
1005
1006/*
1007 * tables defining fifo_mode values. define more if you like.
1008 * for host side, make sure both halves of ep1 are set up.
1009 */
1010
1011/* mode 0 - fits in 2KB */
1012static struct fifo_cfg __initdata mode_0_cfg[] = {
1013{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1014{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1015{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1016{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1017{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1018};
1019
1020/* mode 1 - fits in 4KB */
1021static struct fifo_cfg __initdata mode_1_cfg[] = {
1022{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1023{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1024{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1025{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1026{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1027};
1028
1029/* mode 2 - fits in 4KB */
1030static struct fifo_cfg __initdata mode_2_cfg[] = {
1031{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1032{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1033{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1034{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1035{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1036{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1037};
1038
1039/* mode 3 - fits in 4KB */
1040static struct fifo_cfg __initdata mode_3_cfg[] = {
1041{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1042{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1043{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1044{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1045{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1046{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1047};
1048
1049/* mode 4 - fits in 16KB */
1050static struct fifo_cfg __initdata mode_4_cfg[] = {
1051{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1052{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1053{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1054{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1055{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1056{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1057{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1058{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1059{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1060{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1061{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1062{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1063{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1064{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1065{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1066{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1067{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1068{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1069{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1070{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
1071{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
1072{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
1073{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
1074{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
1075{ .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
1076{ .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
1077{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1078{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1079};
1080
1081
1082/*
1083 * configure a fifo; for non-shared endpoints, this may be called
1084 * once for a tx fifo and once for an rx fifo.
1085 *
1086 * returns negative errno or offset for next fifo.
1087 */
1088static int __init
1089fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1090 const struct fifo_cfg *cfg, u16 offset)
1091{
1092 void __iomem *mbase = musb->mregs;
1093 int size = 0;
1094 u16 maxpacket = cfg->maxpacket;
1095 u16 c_off = offset >> 3;
1096 u8 c_size;
1097
1098 /* expect hw_ep has already been zero-initialized */
1099
1100 size = ffs(max(maxpacket, (u16) 8)) - 1;
1101 maxpacket = 1 << size;
1102
1103 c_size = size - 3;
1104 if (cfg->mode == BUF_DOUBLE) {
ca6d1b13
FB		 1105 if ((offset + (maxpacket << 1)) >
1106 (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1107 return -EMSGSIZE;
1108 c_size |= MUSB_FIFOSZ_DPB;
1109 } else {
ca6d1b13 1110 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1111 return -EMSGSIZE;
1112 }
1113
1114 /* configure the FIFO */
1115 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1116
1117#ifdef CONFIG_USB_MUSB_HDRC_HCD
1118 /* EP0 reserved endpoint for control, bidirectional;
1119 * EP1 reserved for bulk, two unidirection halves.
1120 */
1121 if (hw_ep->epnum == 1)
1122 musb->bulk_ep = hw_ep;
1123 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1124#endif
1125 switch (cfg->style) {
1126 case FIFO_TX:
1127 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1128 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1129 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1130 hw_ep->max_packet_sz_tx = maxpacket;
1131 break;
1132 case FIFO_RX:
1133 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1134 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1135 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1136 hw_ep->max_packet_sz_rx = maxpacket;
1137 break;
1138 case FIFO_RXTX:
1139 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1140 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1141 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1142 hw_ep->max_packet_sz_rx = maxpacket;
1143
1144 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1145 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1146 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1147 hw_ep->max_packet_sz_tx = maxpacket;
1148
1149 hw_ep->is_shared_fifo = true;
1150 break;
1151 }
1152
1153 /* NOTE rx and tx endpoint irqs aren't managed separately,
1154 * which happens to be ok
1155 */
1156 musb->epmask |= (1 << hw_ep->epnum);
1157
1158 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1159}
1160
1161static struct fifo_cfg __initdata ep0_cfg = {
1162 .style = FIFO_RXTX, .maxpacket = 64,
1163};
1164
1165static int __init ep_config_from_table(struct musb *musb)
1166{
1167 const struct fifo_cfg *cfg;
1168 unsigned i, n;
1169 int offset;
1170 struct musb_hw_ep *hw_ep = musb->endpoints;
1171
1172 switch (fifo_mode) {
1173 default:
1174 fifo_mode = 0;
1175 /* FALLTHROUGH */
1176 case 0:
1177 cfg = mode_0_cfg;
1178 n = ARRAY_SIZE(mode_0_cfg);
1179 break;
1180 case 1:
1181 cfg = mode_1_cfg;
1182 n = ARRAY_SIZE(mode_1_cfg);
1183 break;
1184 case 2:
1185 cfg = mode_2_cfg;
1186 n = ARRAY_SIZE(mode_2_cfg);
1187 break;
1188 case 3:
1189 cfg = mode_3_cfg;
1190 n = ARRAY_SIZE(mode_3_cfg);
1191 break;
1192 case 4:
1193 cfg = mode_4_cfg;
1194 n = ARRAY_SIZE(mode_4_cfg);
1195 break;
1196 }
1197
1198 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1199 musb_driver_name, fifo_mode);
1200
1201
1202 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1203 /* assert(offset > 0) */
1204
1205 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
ca6d1b13 1206 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
550a7375
FB		 1207 */
1208
1209 for (i = 0; i < n; i++) {
1210 u8 epn = cfg->hw_ep_num;
1211
ca6d1b13 1212 if (epn >= musb->config->num_eps) {
550a7375
FB		 1213 pr_debug("%s: invalid ep %d\n",
1214 musb_driver_name, epn);
1215 continue;
1216 }
1217 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1218 if (offset < 0) {
1219 pr_debug("%s: mem overrun, ep %d\n",
1220 musb_driver_name, epn);
1221 return -EINVAL;
1222 }
1223 epn++;
1224 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1225 }
1226
1227 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1228 musb_driver_name,
ca6d1b13
FB		 1229 n + 1, musb->config->num_eps * 2 - 1,
1230 offset, (1 << (musb->config->ram_bits + 2)));
550a7375
FB		 1231
1232#ifdef CONFIG_USB_MUSB_HDRC_HCD
1233 if (!musb->bulk_ep) {
1234 pr_debug("%s: missing bulk\n", musb_driver_name);
1235 return -EINVAL;
1236 }
1237#endif
1238
1239 return 0;
1240}
1241
1242
1243/*
1244 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1245 * @param musb the controller
1246 */
1247static int __init ep_config_from_hw(struct musb *musb)
1248{
1249 u8 epnum = 0, reg;
1250 struct musb_hw_ep *hw_ep;
1251 void *mbase = musb->mregs;
1252
1253 DBG(2, "<== static silicon ep config\n");
1254
1255 /* FIXME pick up ep0 maxpacket size */
1256
ca6d1b13 1257 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
550a7375
FB		 1258 musb_ep_select(mbase, epnum);
1259 hw_ep = musb->endpoints + epnum;
1260
1261 /* read from core using indexed model */
1262 reg = musb_readb(hw_ep->regs, 0x10 + MUSB_FIFOSIZE);
1263 if (!reg) {
1264 /* 0's returned when no more endpoints */
1265 break;
1266 }
1267 musb->nr_endpoints++;
1268 musb->epmask |= (1 << epnum);
1269
1270 hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f);
1271
1272 /* shared TX/RX FIFO? */
1273 if ((reg & 0xf0) == 0xf0) {
1274 hw_ep->max_packet_sz_rx = hw_ep->max_packet_sz_tx;
1275 hw_ep->is_shared_fifo = true;
1276 continue;
1277 } else {
1278 hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4);
1279 hw_ep->is_shared_fifo = false;
1280 }
1281
1282 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1283
1284#ifdef CONFIG_USB_MUSB_HDRC_HCD
1285 /* pick an RX/TX endpoint for bulk */
1286 if (hw_ep->max_packet_sz_tx < 512
1287 || hw_ep->max_packet_sz_rx < 512)
1288 continue;
1289
1290 /* REVISIT: this algorithm is lazy, we should at least
1291 * try to pick a double buffered endpoint.
1292 */
1293 if (musb->bulk_ep)
1294 continue;
1295 musb->bulk_ep = hw_ep;
1296#endif
1297 }
1298
1299#ifdef CONFIG_USB_MUSB_HDRC_HCD
1300 if (!musb->bulk_ep) {
1301 pr_debug("%s: missing bulk\n", musb_driver_name);
1302 return -EINVAL;
1303 }
1304#endif
1305
1306 return 0;
1307}
1308
1309enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1310
1311/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1312 * configure endpoints, or take their config from silicon
1313 */
1314static int __init musb_core_init(u16 musb_type, struct musb *musb)
1315{
1316#ifdef MUSB_AHB_ID
1317 u32 data;
1318#endif
1319 u8 reg;
1320 char *type;
1321 u16 hwvers, rev_major, rev_minor;
1322 char aInfo[78], aRevision[32], aDate[12];
1323 void __iomem *mbase = musb->mregs;
1324 int status = 0;
1325 int i;
1326
1327 /* log core options (read using indexed model) */
1328 musb_ep_select(mbase, 0);
1329 reg = musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
1330
1331 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1332 if (reg & MUSB_CONFIGDATA_DYNFIFO)
1333 strcat(aInfo, ", dyn FIFOs");
1334 if (reg & MUSB_CONFIGDATA_MPRXE) {
1335 strcat(aInfo, ", bulk combine");
1336#ifdef C_MP_RX
1337 musb->bulk_combine = true;
1338#else
1339 strcat(aInfo, " (X)"); /* no driver support */
1340#endif
1341 }
1342 if (reg & MUSB_CONFIGDATA_MPTXE) {
1343 strcat(aInfo, ", bulk split");
1344#ifdef C_MP_TX
1345 musb->bulk_split = true;
1346#else
1347 strcat(aInfo, " (X)"); /* no driver support */
1348#endif
1349 }
1350 if (reg & MUSB_CONFIGDATA_HBRXE) {
1351 strcat(aInfo, ", HB-ISO Rx");
1352 strcat(aInfo, " (X)"); /* no driver support */
1353 }
1354 if (reg & MUSB_CONFIGDATA_HBTXE) {
1355 strcat(aInfo, ", HB-ISO Tx");
1356 strcat(aInfo, " (X)"); /* no driver support */
1357 }
1358 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1359 strcat(aInfo, ", SoftConn");
1360
1361 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1362 musb_driver_name, reg, aInfo);
1363
1364#ifdef MUSB_AHB_ID
1365 data = musb_readl(mbase, 0x404);
1366 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1367 (data >> 16) & 0xff, (data >> 24) & 0xff);
1368 /* FIXME ID2 and ID3 are unused */
1369 data = musb_readl(mbase, 0x408);
1370 printk(KERN_DEBUG "ID2=%lx\n", (long unsigned)data);
1371 data = musb_readl(mbase, 0x40c);
1372 printk(KERN_DEBUG "ID3=%lx\n", (long unsigned)data);
1373 reg = musb_readb(mbase, 0x400);
1374 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1375#else
1376 aDate[0] = 0;
1377#endif
1378 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1379 musb->is_multipoint = 1;
1380 type = "M";
1381 } else {
1382 musb->is_multipoint = 0;
1383 type = "";
1384#ifdef CONFIG_USB_MUSB_HDRC_HCD
1385#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1386 printk(KERN_ERR
1387 "%s: kernel must blacklist external hubs\n",
1388 musb_driver_name);
1389#endif
1390#endif
1391 }
1392
1393 /* log release info */
1394 hwvers = musb_readw(mbase, MUSB_HWVERS);
1395 rev_major = (hwvers >> 10) & 0x1f;
1396 rev_minor = hwvers & 0x3ff;
1397 snprintf(aRevision, 32, "%d.%d%s", rev_major,
1398 rev_minor, (hwvers & 0x8000) ? "RC" : "");
1399 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1400 musb_driver_name, type, aRevision, aDate);
1401
1402 /* configure ep0 */
1403 musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
1404 musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
1405
1406 /* discover endpoint configuration */
1407 musb->nr_endpoints = 1;
1408 musb->epmask = 1;
1409
1410 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
ca6d1b13 1411 if (musb->config->dyn_fifo)
550a7375
FB		 1412 status = ep_config_from_table(musb);
1413 else {
1414 ERR("reconfigure software for Dynamic FIFOs\n");
1415 status = -ENODEV;
1416 }
1417 } else {
ca6d1b13 1418 if (!musb->config->dyn_fifo)
550a7375
FB		 1419 status = ep_config_from_hw(musb);
1420 else {
1421 ERR("reconfigure software for static FIFOs\n");
1422 return -ENODEV;
1423 }
1424 }
1425
1426 if (status < 0)
1427 return status;
1428
1429 /* finish init, and print endpoint config */
1430 for (i = 0; i < musb->nr_endpoints; i++) {
1431 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1432
1433 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1434#ifdef CONFIG_USB_TUSB6010
1435 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1436 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1437 hw_ep->fifo_sync_va =
1438 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1439
1440 if (i == 0)
1441 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1442 else
1443 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1444#endif
1445
1446 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1447#ifdef CONFIG_USB_MUSB_HDRC_HCD
1448 hw_ep->target_regs = MUSB_BUSCTL_OFFSET(i, 0) + mbase;
1449 hw_ep->rx_reinit = 1;
1450 hw_ep->tx_reinit = 1;
1451#endif
1452
1453 if (hw_ep->max_packet_sz_tx) {
1454 printk(KERN_DEBUG
1455 "%s: hw_ep %d%s, %smax %d\n",
1456 musb_driver_name, i,
1457 hw_ep->is_shared_fifo ? "shared" : "tx",
1458 hw_ep->tx_double_buffered
1459 ? "doublebuffer, " : "",
1460 hw_ep->max_packet_sz_tx);
1461 }
1462 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1463 printk(KERN_DEBUG
1464 "%s: hw_ep %d%s, %smax %d\n",
1465 musb_driver_name, i,
1466 "rx",
1467 hw_ep->rx_double_buffered
1468 ? "doublebuffer, " : "",
1469 hw_ep->max_packet_sz_rx);
1470 }
1471 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1472 DBG(1, "hw_ep %d not configured\n", i);
1473 }
1474
1475 return 0;
1476}
1477
1478/*-------------------------------------------------------------------------*/
1479
1480#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1481
1482static irqreturn_t generic_interrupt(int irq, void *__hci)
1483{
1484 unsigned long flags;
1485 irqreturn_t retval = IRQ_NONE;
1486 struct musb *musb = __hci;
1487
1488 spin_lock_irqsave(&musb->lock, flags);
1489
1490 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1491 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1492 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1493
1494 if (musb->int_usb || musb->int_tx || musb->int_rx)
1495 retval = musb_interrupt(musb);
1496
1497 spin_unlock_irqrestore(&musb->lock, flags);
1498
1499 /* REVISIT we sometimes get spurious IRQs on g_ep0
1500 * not clear why...
1501 */
1502 if (retval != IRQ_HANDLED)
1503 DBG(5, "spurious?\n");
1504
1505 return IRQ_HANDLED;
1506}
1507
1508#else
1509#define generic_interrupt NULL
1510#endif
1511
1512/*
1513 * handle all the irqs defined by the HDRC core. for now we expect: other
1514 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1515 * will be assigned, and the irq will already have been acked.
1516 *
1517 * called in irq context with spinlock held, irqs blocked
1518 */
1519irqreturn_t musb_interrupt(struct musb *musb)
1520{
1521 irqreturn_t retval = IRQ_NONE;
1522 u8 devctl, power;
1523 int ep_num;
1524 u32 reg;
1525
1526 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1527 power = musb_readb(musb->mregs, MUSB_POWER);
1528
1529 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1530 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1531 musb->int_usb, musb->int_tx, musb->int_rx);
1532
1533 /* the core can interrupt us for multiple reasons; docs have
1534 * a generic interrupt flowchart to follow
1535 */
1536 if (musb->int_usb & STAGE0_MASK)
1537 retval |= musb_stage0_irq(musb, musb->int_usb,
1538 devctl, power);
1539
1540 /* "stage 1" is handling endpoint irqs */
1541
1542 /* handle endpoint 0 first */
1543 if (musb->int_tx & 1) {
1544 if (devctl & MUSB_DEVCTL_HM)
1545 retval |= musb_h_ep0_irq(musb);
1546 else
1547 retval |= musb_g_ep0_irq(musb);
1548 }
1549
1550 /* RX on endpoints 1-15 */
1551 reg = musb->int_rx >> 1;
1552 ep_num = 1;
1553 while (reg) {
1554 if (reg & 1) {
1555 /* musb_ep_select(musb->mregs, ep_num); */
1556 /* REVISIT just retval = ep->rx_irq(...) */
1557 retval = IRQ_HANDLED;
1558 if (devctl & MUSB_DEVCTL_HM) {
1559 if (is_host_capable())
1560 musb_host_rx(musb, ep_num);
1561 } else {
1562 if (is_peripheral_capable())
1563 musb_g_rx(musb, ep_num);
1564 }
1565 }
1566
1567 reg >>= 1;
1568 ep_num++;
1569 }
1570
1571 /* TX on endpoints 1-15 */
1572 reg = musb->int_tx >> 1;
1573 ep_num = 1;
1574 while (reg) {
1575 if (reg & 1) {
1576 /* musb_ep_select(musb->mregs, ep_num); */
1577 /* REVISIT just retval |= ep->tx_irq(...) */
1578 retval = IRQ_HANDLED;
1579 if (devctl & MUSB_DEVCTL_HM) {
1580 if (is_host_capable())
1581 musb_host_tx(musb, ep_num);
1582 } else {
1583 if (is_peripheral_capable())
1584 musb_g_tx(musb, ep_num);
1585 }
1586 }
1587 reg >>= 1;
1588 ep_num++;
1589 }
1590
1591 /* finish handling "global" interrupts after handling fifos */
1592 if (musb->int_usb)
1593 retval |= musb_stage2_irq(musb,
1594 musb->int_usb, devctl, power);
1595
1596 return retval;
1597}
1598
1599
1600#ifndef CONFIG_MUSB_PIO_ONLY
1601static int __initdata use_dma = 1;
1602
1603/* "modprobe ... use_dma=0" etc */
1604module_param(use_dma, bool, 0);
1605MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1606
1607void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1608{
1609 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1610
1611 /* called with controller lock already held */
1612
1613 if (!epnum) {
1614#ifndef CONFIG_USB_TUSB_OMAP_DMA
1615 if (!is_cppi_enabled()) {
1616 /* endpoint 0 */
1617 if (devctl & MUSB_DEVCTL_HM)
1618 musb_h_ep0_irq(musb);
1619 else
1620 musb_g_ep0_irq(musb);
1621 }
1622#endif
1623 } else {
1624 /* endpoints 1..15 */
1625 if (transmit) {
1626 if (devctl & MUSB_DEVCTL_HM) {
1627 if (is_host_capable())
1628 musb_host_tx(musb, epnum);
1629 } else {
1630 if (is_peripheral_capable())
1631 musb_g_tx(musb, epnum);
1632 }
1633 } else {
1634 /* receive */
1635 if (devctl & MUSB_DEVCTL_HM) {
1636 if (is_host_capable())
1637 musb_host_rx(musb, epnum);
1638 } else {
1639 if (is_peripheral_capable())
1640 musb_g_rx(musb, epnum);
1641 }
1642 }
1643 }
1644}
1645
1646#else
1647#define use_dma 0
1648#endif
1649
1650/*-------------------------------------------------------------------------*/
1651
1652#ifdef CONFIG_SYSFS
1653
1654static ssize_t
1655musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1656{
1657 struct musb *musb = dev_to_musb(dev);
1658 unsigned long flags;
1659 int ret = -EINVAL;
1660
1661 spin_lock_irqsave(&musb->lock, flags);
1662 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1663 spin_unlock_irqrestore(&musb->lock, flags);
1664
1665 return ret;
1666}
1667
1668static ssize_t
1669musb_mode_store(struct device *dev, struct device_attribute *attr,
1670 const char *buf, size_t n)
1671{
1672 struct musb *musb = dev_to_musb(dev);
1673 unsigned long flags;
1674
1675 spin_lock_irqsave(&musb->lock, flags);
1676 if (!strncmp(buf, "host", 4))
1677 musb_platform_set_mode(musb, MUSB_HOST);
1678 if (!strncmp(buf, "peripheral", 10))
1679 musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1680 if (!strncmp(buf, "otg", 3))
1681 musb_platform_set_mode(musb, MUSB_OTG);
1682 spin_unlock_irqrestore(&musb->lock, flags);
1683
1684 return n;
1685}
1686static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1687
1688static ssize_t
1689musb_vbus_store(struct device *dev, struct device_attribute *attr,
1690 const char *buf, size_t n)
1691{
1692 struct musb *musb = dev_to_musb(dev);
1693 unsigned long flags;
1694 unsigned long val;
1695
1696 if (sscanf(buf, "%lu", &val) < 1) {
1697 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
1698 return -EINVAL;
1699 }
1700
1701 spin_lock_irqsave(&musb->lock, flags);
1702 musb->a_wait_bcon = val;
1703 if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON)
1704 musb->is_active = 0;
1705 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1706 spin_unlock_irqrestore(&musb->lock, flags);
1707
1708 return n;
1709}
1710
1711static ssize_t
1712musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1713{
1714 struct musb *musb = dev_to_musb(dev);
1715 unsigned long flags;
1716 unsigned long val;
1717 int vbus;
1718
1719 spin_lock_irqsave(&musb->lock, flags);
1720 val = musb->a_wait_bcon;
1721 vbus = musb_platform_get_vbus_status(musb);
1722 spin_unlock_irqrestore(&musb->lock, flags);
1723
1724 return sprintf(buf, "Vbus %s, timeout %lu\n",
1725 vbus ? "on" : "off", val);
1726}
1727static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1728
1729#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1730
1731/* Gadget drivers can't know that a host is connected so they might want
1732 * to start SRP, but users can. This allows userspace to trigger SRP.
1733 */
1734static ssize_t
1735musb_srp_store(struct device *dev, struct device_attribute *attr,
1736 const char *buf, size_t n)
1737{
1738 struct musb *musb = dev_to_musb(dev);
1739 unsigned short srp;
1740
1741 if (sscanf(buf, "%hu", &srp) != 1
1742 || (srp != 1)) {
1743 printk(KERN_ERR "SRP: Value must be 1\n");
1744 return -EINVAL;
1745 }
1746
1747 if (srp == 1)
1748 musb_g_wakeup(musb);
1749
1750 return n;
1751}
1752static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1753
1754#endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1755
1756#endif /* sysfs */
1757
1758/* Only used to provide driver mode change events */
1759static void musb_irq_work(struct work_struct *data)
1760{
1761 struct musb *musb = container_of(data, struct musb, irq_work);
1762 static int old_state;
1763
1764 if (musb->xceiv.state != old_state) {
1765 old_state = musb->xceiv.state;
1766 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1767 }
1768}
1769
1770/* --------------------------------------------------------------------------
1771 * Init support
1772 */
1773
1774static struct musb *__init
ca6d1b13
FB		 1775allocate_instance(struct device *dev,
1776 struct musb_hdrc_config *config, void __iomem *mbase)
550a7375
FB		 1777{
1778 struct musb *musb;
1779 struct musb_hw_ep *ep;
1780 int epnum;
1781#ifdef CONFIG_USB_MUSB_HDRC_HCD
1782 struct usb_hcd *hcd;
1783
1784 hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id);
1785 if (!hcd)
1786 return NULL;
1787 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1788
1789 musb = hcd_to_musb(hcd);
1790 INIT_LIST_HEAD(&musb->control);
1791 INIT_LIST_HEAD(&musb->in_bulk);
1792 INIT_LIST_HEAD(&musb->out_bulk);
1793
1794 hcd->uses_new_polling = 1;
1795
1796 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1797#else
1798 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1799 if (!musb)
1800 return NULL;
1801 dev_set_drvdata(dev, musb);
1802
1803#endif
1804
1805 musb->mregs = mbase;
1806 musb->ctrl_base = mbase;
1807 musb->nIrq = -ENODEV;
ca6d1b13 1808 musb->config = config;
550a7375 1809 for (epnum = 0, ep = musb->endpoints;
ca6d1b13 1810 epnum < musb->config->num_eps;
550a7375
FB		 1811 epnum++, ep++) {
1812
1813 ep->musb = musb;
1814 ep->epnum = epnum;
1815 }
1816
1817 musb->controller = dev;
1818 return musb;
1819}
1820
1821static void musb_free(struct musb *musb)
1822{
1823 /* this has multiple entry modes. it handles fault cleanup after
1824 * probe(), where things may be partially set up, as well as rmmod
1825 * cleanup after everything's been de-activated.
1826 */
1827
1828#ifdef CONFIG_SYSFS
1829 device_remove_file(musb->controller, &dev_attr_mode);
1830 device_remove_file(musb->controller, &dev_attr_vbus);
1831#ifdef CONFIG_USB_MUSB_OTG
1832 device_remove_file(musb->controller, &dev_attr_srp);
1833#endif
1834#endif
1835
1836#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1837 musb_gadget_cleanup(musb);
1838#endif
1839
1840 if (musb->nIrq >= 0) {
1841 disable_irq_wake(musb->nIrq);
1842 free_irq(musb->nIrq, musb);
1843 }
1844 if (is_dma_capable() && musb->dma_controller) {
1845 struct dma_controller *c = musb->dma_controller;
1846
1847 (void) c->stop(c);
1848 dma_controller_destroy(c);
1849 }
1850
1851 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1852 musb_platform_exit(musb);
1853 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1854
1855 if (musb->clock) {
1856 clk_disable(musb->clock);
1857 clk_put(musb->clock);
1858 }
1859
1860#ifdef CONFIG_USB_MUSB_OTG
1861 put_device(musb->xceiv.dev);
1862#endif
1863
1864#ifdef CONFIG_USB_MUSB_HDRC_HCD
1865 usb_put_hcd(musb_to_hcd(musb));
1866#else
1867 kfree(musb);
1868#endif
1869}
1870
1871/*
1872 * Perform generic per-controller initialization.
1873 *
1874 * @pDevice: the controller (already clocked, etc)
1875 * @nIrq: irq
1876 * @mregs: virtual address of controller registers,
1877 * not yet corrected for platform-specific offsets
1878 */
1879static int __init
1880musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1881{
1882 int status;
1883 struct musb *musb;
1884 struct musb_hdrc_platform_data *plat = dev->platform_data;
1885
1886 /* The driver might handle more features than the board; OK.
1887 * Fail when the board needs a feature that's not enabled.
1888 */
1889 if (!plat) {
1890 dev_dbg(dev, "no platform_data?\n");
1891 return -ENODEV;
1892 }
1893 switch (plat->mode) {
1894 case MUSB_HOST:
1895#ifdef CONFIG_USB_MUSB_HDRC_HCD
1896 break;
1897#else
1898 goto bad_config;
1899#endif
1900 case MUSB_PERIPHERAL:
1901#ifdef CONFIG_USB_GADGET_MUSB_HDRC
1902 break;
1903#else
1904 goto bad_config;
1905#endif
1906 case MUSB_OTG:
1907#ifdef CONFIG_USB_MUSB_OTG
1908 break;
1909#else
1910bad_config:
1911#endif
1912 default:
1913 dev_err(dev, "incompatible Kconfig role setting\n");
1914 return -EINVAL;
1915 }
1916
1917 /* allocate */
ca6d1b13 1918 musb = allocate_instance(dev, plat->config, ctrl);
550a7375
FB		 1919 if (!musb)
1920 return -ENOMEM;
1921
1922 spin_lock_init(&musb->lock);
1923 musb->board_mode = plat->mode;
1924 musb->board_set_power = plat->set_power;
1925 musb->set_clock = plat->set_clock;
1926 musb->min_power = plat->min_power;
1927
1928 /* Clock usage is chip-specific ... functional clock (DaVinci,
1929 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1930 * code does is make sure a clock handle is available; platform
1931 * code manages it during start/stop and suspend/resume.
1932 */
1933 if (plat->clock) {
1934 musb->clock = clk_get(dev, plat->clock);
1935 if (IS_ERR(musb->clock)) {
1936 status = PTR_ERR(musb->clock);
1937 musb->clock = NULL;
1938 goto fail;
1939 }
1940 }
1941
1942 /* assume vbus is off */
1943
1944 /* platform adjusts musb->mregs and musb->isr if needed,
1945 * and activates clocks
1946 */
1947 musb->isr = generic_interrupt;
1948 status = musb_platform_init(musb);
1949
1950 if (status < 0)
1951 goto fail;
1952 if (!musb->isr) {
1953 status = -ENODEV;
1954 goto fail2;
1955 }
1956
1957#ifndef CONFIG_MUSB_PIO_ONLY
1958 if (use_dma && dev->dma_mask) {
1959 struct dma_controller *c;
1960
1961 c = dma_controller_create(musb, musb->mregs);
1962 musb->dma_controller = c;
1963 if (c)
1964 (void) c->start(c);
1965 }
1966#endif
1967 /* ideally this would be abstracted in platform setup */
1968 if (!is_dma_capable() || !musb->dma_controller)
1969 dev->dma_mask = NULL;
1970
1971 /* be sure interrupts are disabled before connecting ISR */
1972 musb_platform_disable(musb);
1973 musb_generic_disable(musb);
1974
1975 /* setup musb parts of the core (especially endpoints) */
ca6d1b13 1976 status = musb_core_init(plat->config->multipoint
550a7375
FB		 1977 ? MUSB_CONTROLLER_MHDRC
1978 : MUSB_CONTROLLER_HDRC, musb);
1979 if (status < 0)
1980 goto fail2;
1981
1982 /* Init IRQ workqueue before request_irq */
1983 INIT_WORK(&musb->irq_work, musb_irq_work);
1984
1985 /* attach to the IRQ */
1986 if (request_irq(nIrq, musb->isr, 0, dev->bus_id, musb)) {
1987 dev_err(dev, "request_irq %d failed!\n", nIrq);
1988 status = -ENODEV;
1989 goto fail2;
1990 }
1991 musb->nIrq = nIrq;
1992/* FIXME this handles wakeup irqs wrong */
1993 if (enable_irq_wake(nIrq) == 0)
1994 device_init_wakeup(dev, 1);
1995
1996 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
1997 musb_driver_name,
1998 ({char *s;
1999 switch (musb->board_mode) {
2000 case MUSB_HOST: s = "Host"; break;
2001 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2002 default: s = "OTG"; break;
2003 }; s; }),
2004 ctrl,
2005 (is_dma_capable() && musb->dma_controller)
2006 ? "DMA" : "PIO",
2007 musb->nIrq);
2008
2009#ifdef CONFIG_USB_MUSB_HDRC_HCD
2010 /* host side needs more setup, except for no-host modes */
2011 if (musb->board_mode != MUSB_PERIPHERAL) {
2012 struct usb_hcd *hcd = musb_to_hcd(musb);
2013
2014 if (musb->board_mode == MUSB_OTG)
2015 hcd->self.otg_port = 1;
2016 musb->xceiv.host = &hcd->self;
2017 hcd->power_budget = 2 * (plat->power ? : 250);
2018 }
2019#endif /* CONFIG_USB_MUSB_HDRC_HCD */
2020
2021 /* For the host-only role, we can activate right away.
2022 * (We expect the ID pin to be forcibly grounded!!)
2023 * Otherwise, wait till the gadget driver hooks up.
2024 */
2025 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2026 MUSB_HST_MODE(musb);
2027 musb->xceiv.default_a = 1;
2028 musb->xceiv.state = OTG_STATE_A_IDLE;
2029
2030 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
746cdd0b
FB		 2031 if (status)
2032 goto fail;
550a7375
FB		 2033
2034 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2035 "HOST", status,
2036 musb_readb(musb->mregs, MUSB_DEVCTL),
2037 (musb_readb(musb->mregs, MUSB_DEVCTL)
2038 & MUSB_DEVCTL_BDEVICE
2039 ? 'B' : 'A'));
2040
2041 } else /* peripheral is enabled */ {
2042 MUSB_DEV_MODE(musb);
2043 musb->xceiv.default_a = 0;
2044 musb->xceiv.state = OTG_STATE_B_IDLE;
2045
2046 status = musb_gadget_setup(musb);
746cdd0b
FB		 2047 if (status)
2048 goto fail;
550a7375
FB		 2049
2050 DBG(1, "%s mode, status %d, dev%02x\n",
2051 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2052 status,
2053 musb_readb(musb->mregs, MUSB_DEVCTL));
2054
2055 }
2056
746cdd0b
FB		 2057 return 0;
2058
550a7375 2059fail:
746cdd0b
FB		 2060 if (musb->clock)
2061 clk_put(musb->clock);
2062 device_init_wakeup(dev, 0);
2063 musb_free(musb);
2064 return status;
550a7375
FB		 2065
2066#ifdef CONFIG_SYSFS
2067 status = device_create_file(dev, &dev_attr_mode);
2068 status = device_create_file(dev, &dev_attr_vbus);
2069#ifdef CONFIG_USB_GADGET_MUSB_HDRC
2070 status = device_create_file(dev, &dev_attr_srp);
2071#endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2072 status = 0;
2073#endif
2074
2075 return status;
2076
2077fail2:
2078 musb_platform_exit(musb);
2079 goto fail;
2080}
2081
2082/*-------------------------------------------------------------------------*/
2083
2084/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2085 * bridge to a platform device; this driver then suffices.
2086 */
2087
2088#ifndef CONFIG_MUSB_PIO_ONLY
2089static u64 *orig_dma_mask;
2090#endif
2091
2092static int __init musb_probe(struct platform_device *pdev)
2093{
2094 struct device *dev = &pdev->dev;
2095 int irq = platform_get_irq(pdev, 0);
2096 struct resource *iomem;
2097 void __iomem *base;
2098
2099 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2100 if (!iomem || irq == 0)
2101 return -ENODEV;
2102
2103 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2104 if (!base) {
2105 dev_err(dev, "ioremap failed\n");
2106 return -ENOMEM;
2107 }
2108
2109#ifndef CONFIG_MUSB_PIO_ONLY
2110 /* clobbered by use_dma=n */
2111 orig_dma_mask = dev->dma_mask;
2112#endif
2113 return musb_init_controller(dev, irq, base);
2114}
2115
2116static int __devexit musb_remove(struct platform_device *pdev)
2117{
2118 struct musb *musb = dev_to_musb(&pdev->dev);
2119 void __iomem *ctrl_base = musb->ctrl_base;
2120
2121 /* this gets called on rmmod.
2122 * - Host mode: host may still be active
2123 * - Peripheral mode: peripheral is deactivated (or never-activated)
2124 * - OTG mode: both roles are deactivated (or never-activated)
2125 */
2126 musb_shutdown(pdev);
550a7375
FB		 2127#ifdef CONFIG_USB_MUSB_HDRC_HCD
2128 if (musb->board_mode == MUSB_HOST)
2129 usb_remove_hcd(musb_to_hcd(musb));
2130#endif
2131 musb_free(musb);
2132 iounmap(ctrl_base);
2133 device_init_wakeup(&pdev->dev, 0);
2134#ifndef CONFIG_MUSB_PIO_ONLY
2135 pdev->dev.dma_mask = orig_dma_mask;
2136#endif
2137 return 0;
2138}
2139
2140#ifdef CONFIG_PM
2141
2142static int musb_suspend(struct platform_device *pdev, pm_message_t message)
2143{
2144 unsigned long flags;
2145 struct musb *musb = dev_to_musb(&pdev->dev);
2146
2147 if (!musb->clock)
2148 return 0;
2149
2150 spin_lock_irqsave(&musb->lock, flags);
2151
2152 if (is_peripheral_active(musb)) {
2153 /* FIXME force disconnect unless we know USB will wake
2154 * the system up quickly enough to respond ...
2155 */
2156 } else if (is_host_active(musb)) {
2157 /* we know all the children are suspended; sometimes
2158 * they will even be wakeup-enabled.
2159 */
2160 }
2161
2162 if (musb->set_clock)
2163 musb->set_clock(musb->clock, 0);
2164 else
2165 clk_disable(musb->clock);
2166 spin_unlock_irqrestore(&musb->lock, flags);
2167 return 0;
2168}
2169
2170static int musb_resume(struct platform_device *pdev)
2171{
2172 unsigned long flags;
2173 struct musb *musb = dev_to_musb(&pdev->dev);
2174
2175 if (!musb->clock)
2176 return 0;
2177
2178 spin_lock_irqsave(&musb->lock, flags);
2179
2180 if (musb->set_clock)
2181 musb->set_clock(musb->clock, 1);
2182 else
2183 clk_enable(musb->clock);
2184
2185 /* for static cmos like DaVinci, register values were preserved
2186 * unless for some reason the whole soc powered down and we're
2187 * not treating that as a whole-system restart (e.g. swsusp)
2188 */
2189 spin_unlock_irqrestore(&musb->lock, flags);
2190 return 0;
2191}
2192
2193#else
2194#define musb_suspend NULL
2195#define musb_resume NULL
2196#endif
2197
2198static struct platform_driver musb_driver = {
2199 .driver = {
2200 .name = (char *)musb_driver_name,
2201 .bus = &platform_bus_type,
2202 .owner = THIS_MODULE,
2203 },
2204 .remove = __devexit_p(musb_remove),
2205 .shutdown = musb_shutdown,
2206 .suspend = musb_suspend,
2207 .resume = musb_resume,
2208};
2209
2210/*-------------------------------------------------------------------------*/
2211
2212static int __init musb_init(void)
2213{
2214#ifdef CONFIG_USB_MUSB_HDRC_HCD
2215 if (usb_disabled())
2216 return 0;
2217#endif
2218
2219 pr_info("%s: version " MUSB_VERSION ", "
2220#ifdef CONFIG_MUSB_PIO_ONLY
2221 "pio"
2222#elif defined(CONFIG_USB_TI_CPPI_DMA)
2223 "cppi-dma"
2224#elif defined(CONFIG_USB_INVENTRA_DMA)
2225 "musb-dma"
2226#elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2227 "tusb-omap-dma"
2228#else
2229 "?dma?"
2230#endif
2231 ", "
2232#ifdef CONFIG_USB_MUSB_OTG
2233 "otg (peripheral+host)"
2234#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2235 "peripheral"
2236#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2237 "host"
2238#endif
2239 ", debug=%d\n",
2240 musb_driver_name, debug);
2241 return platform_driver_probe(&musb_driver, musb_probe);
2242}
2243
2244/* make us init after usbcore and before usb
2245 * gadget and host-side drivers start to register
2246 */
2247subsys_initcall(musb_init);
2248
2249static void __exit musb_cleanup(void)
2250{
2251 platform_driver_unregister(&musb_driver);
2252}
2253module_exit(musb_cleanup);
Linux kernel - Deliverables
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