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usb: musb: core: add missing curly braces
[deliverable/linux.git] / drivers / usb / musb / musb_core.c
CommitLineData
550a7375
FB		 1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
550a7375 85 * - platform_device for addressing, irq, and platform_data
5ae477b0 86 * - platform_data is mostly for board-specific information
c767c1c6 87 * (plus recentrly, SOC or family details)
550a7375
FB		 88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
550a7375
FB		 96#include <linux/list.h>
97#include <linux/kobject.h>
9303961f 98#include <linux/prefetch.h>
550a7375
FB		 99#include <linux/platform_device.h>
100#include <linux/io.h>
8d2421e6 101#include <linux/dma-mapping.h>
550a7375 102
550a7375
FB		 103#include "musb_core.h"
104
f7f9d63e 105#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
550a7375
FB		 106
107
550a7375
FB		 108#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110
e8164f64 111#define MUSB_VERSION "6.0"
550a7375
FB		 112
113#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114
05ac10dd 115#define MUSB_DRIVER_NAME "musb-hdrc"
550a7375
FB		 116const char musb_driver_name[] = MUSB_DRIVER_NAME;
117
118MODULE_DESCRIPTION(DRIVER_INFO);
119MODULE_AUTHOR(DRIVER_AUTHOR);
120MODULE_LICENSE("GPL");
121MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122
123
124/*-------------------------------------------------------------------------*/
125
126static inline struct musb *dev_to_musb(struct device *dev)
127{
550a7375 128 return dev_get_drvdata(dev);
550a7375
FB		 129}
130
131/*-------------------------------------------------------------------------*/
132
ffb865b1 133#ifndef CONFIG_BLACKFIN
b96d3b08 134static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
ffb865b1 135{
b96d3b08 136 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 137 int i = 0;
138 u8 r;
139 u8 power;
bf070bc1
GI		 140 int ret;
141
142 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 143
144 /* Make sure the transceiver is not in low power mode */
145 power = musb_readb(addr, MUSB_POWER);
146 power &= ~MUSB_POWER_SUSPENDM;
147 musb_writeb(addr, MUSB_POWER, power);
148
149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
151 */
152
153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
156
157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158 & MUSB_ULPI_REG_CMPLT)) {
159 i++;
bf070bc1
GI		 160 if (i == 10000) {
161 ret = -ETIMEDOUT;
162 goto out;
163 }
ffb865b1
HK		 164
165 }
166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167 r &= ~MUSB_ULPI_REG_CMPLT;
168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
169
bf070bc1
GI		 170 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
171
172out:
173 pm_runtime_put(phy->io_dev);
174
175 return ret;
ffb865b1
HK		 176}
177
b96d3b08 178static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
ffb865b1 179{
b96d3b08 180 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 181 int i = 0;
182 u8 r = 0;
183 u8 power;
bf070bc1
GI		 184 int ret = 0;
185
186 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 187
188 /* Make sure the transceiver is not in low power mode */
189 power = musb_readb(addr, MUSB_POWER);
190 power &= ~MUSB_POWER_SUSPENDM;
191 musb_writeb(addr, MUSB_POWER, power);
192
193 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
194 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
195 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
196
197 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
198 & MUSB_ULPI_REG_CMPLT)) {
199 i++;
bf070bc1
GI		 200 if (i == 10000) {
201 ret = -ETIMEDOUT;
202 goto out;
203 }
ffb865b1
HK		 204 }
205
206 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
207 r &= ~MUSB_ULPI_REG_CMPLT;
208 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
209
bf070bc1
GI		 210out:
211 pm_runtime_put(phy->io_dev);
212
213 return ret;
ffb865b1
HK		 214}
215#else
f2263db7
MF		 216#define musb_ulpi_read NULL
217#define musb_ulpi_write NULL
ffb865b1
HK		 218#endif
219
b96d3b08 220static struct usb_phy_io_ops musb_ulpi_access = {
ffb865b1
HK		 221 .read = musb_ulpi_read,
222 .write = musb_ulpi_write,
223};
224
225/*-------------------------------------------------------------------------*/
226
1b40fc57
TL		 227static u32 musb_default_fifo_offset(u8 epnum)
228{
229 return 0x20 + (epnum * 4);
230}
231
d026e9c7
TL		 232/* "flat" mapping: each endpoint has its own i/o address */
233static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
234{
235}
236
237static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
238{
239 return 0x100 + (0x10 * epnum) + offset;
240}
241
242/* "indexed" mapping: INDEX register controls register bank select */
243static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
244{
245 musb_writeb(mbase, MUSB_INDEX, epnum);
246}
247
248static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
249{
250 return 0x10 + offset;
251}
252
1b40fc57
TL		 253static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
254{
255 return __raw_readb(addr + offset);
256}
257
258static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
259{
260 __raw_writeb(data, addr + offset);
261}
262
263static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
264{
265 return __raw_readw(addr + offset);
266}
267
268static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
269{
270 __raw_writew(data, addr + offset);
271}
272
273static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
274{
275 return __raw_readl(addr + offset);
276}
277
278static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
279{
280 __raw_writel(data, addr + offset);
281}
c6cf8b00 282
550a7375
FB		 283/*
284 * Load an endpoint's FIFO
285 */
1b40fc57
TL		 286static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
287 const u8 *src)
550a7375 288{
5c8a86e1 289 struct musb *musb = hw_ep->musb;
550a7375
FB		 290 void __iomem *fifo = hw_ep->fifo;
291
603fe2b2
AKG		 292 if (unlikely(len == 0))
293 return;
294
550a7375
FB		 295 prefetch((u8 *)src);
296
5c8a86e1 297 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 298 'T', hw_ep->epnum, fifo, len, src);
299
300 /* we can't assume unaligned reads work */
301 if (likely((0x01 & (unsigned long) src) == 0)) {
302 u16 index = 0;
303
304 /* best case is 32bit-aligned source address */
305 if ((0x02 & (unsigned long) src) == 0) {
306 if (len >= 4) {
2bf0a8f6 307 iowrite32_rep(fifo, src + index, len >> 2);
550a7375
FB		 308 index += len & ~0x03;
309 }
310 if (len & 0x02) {
311 musb_writew(fifo, 0, *(u16 *)&src[index]);
312 index += 2;
313 }
314 } else {
315 if (len >= 2) {
2bf0a8f6 316 iowrite16_rep(fifo, src + index, len >> 1);
550a7375
FB		 317 index += len & ~0x01;
318 }
319 }
320 if (len & 0x01)
321 musb_writeb(fifo, 0, src[index]);
322 } else {
323 /* byte aligned */
2bf0a8f6 324 iowrite8_rep(fifo, src, len);
550a7375
FB		 325 }
326}
327
328/*
329 * Unload an endpoint's FIFO
330 */
1b40fc57 331static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
550a7375 332{
5c8a86e1 333 struct musb *musb = hw_ep->musb;
550a7375
FB		 334 void __iomem *fifo = hw_ep->fifo;
335
603fe2b2
AKG		 336 if (unlikely(len == 0))
337 return;
338
5c8a86e1 339 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 340 'R', hw_ep->epnum, fifo, len, dst);
341
342 /* we can't assume unaligned writes work */
343 if (likely((0x01 & (unsigned long) dst) == 0)) {
344 u16 index = 0;
345
346 /* best case is 32bit-aligned destination address */
347 if ((0x02 & (unsigned long) dst) == 0) {
348 if (len >= 4) {
2bf0a8f6 349 ioread32_rep(fifo, dst, len >> 2);
550a7375
FB		 350 index = len & ~0x03;
351 }
352 if (len & 0x02) {
353 *(u16 *)&dst[index] = musb_readw(fifo, 0);
354 index += 2;
355 }
356 } else {
357 if (len >= 2) {
2bf0a8f6 358 ioread16_rep(fifo, dst, len >> 1);
550a7375
FB		 359 index = len & ~0x01;
360 }
361 }
362 if (len & 0x01)
363 dst[index] = musb_readb(fifo, 0);
364 } else {
365 /* byte aligned */
2bf0a8f6 366 ioread8_rep(fifo, dst, len);
550a7375
FB		 367 }
368}
369
1b40fc57
TL		 370/*
371 * Old style IO functions
372 */
373u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
374EXPORT_SYMBOL_GPL(musb_readb);
375
376void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
377EXPORT_SYMBOL_GPL(musb_writeb);
550a7375 378
1b40fc57
TL		 379u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
380EXPORT_SYMBOL_GPL(musb_readw);
381
382void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
383EXPORT_SYMBOL_GPL(musb_writew);
384
385u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
386EXPORT_SYMBOL_GPL(musb_readl);
387
388void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
389EXPORT_SYMBOL_GPL(musb_writel);
390
391/*
392 * New style IO functions
393 */
394void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
395{
396 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
397}
398
399void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
400{
401 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
402}
550a7375
FB		 403
404/*-------------------------------------------------------------------------*/
405
406/* for high speed test mode; see USB 2.0 spec 7.1.20 */
407static const u8 musb_test_packet[53] = {
408 /* implicit SYNC then DATA0 to start */
409
410 /* JKJKJKJK x9 */
411 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
412 /* JJKKJJKK x8 */
413 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
414 /* JJJJKKKK x8 */
415 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
416 /* JJJJJJJKKKKKKK x8 */
417 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
418 /* JJJJJJJK x8 */
419 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
420 /* JKKKKKKK x10, JK */
421 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
422
423 /* implicit CRC16 then EOP to end */
424};
425
426void musb_load_testpacket(struct musb *musb)
427{
428 void __iomem *regs = musb->endpoints[0].regs;
429
430 musb_ep_select(musb->mregs, 0);
431 musb_write_fifo(musb->control_ep,
432 sizeof(musb_test_packet), musb_test_packet);
433 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
434}
435
436/*-------------------------------------------------------------------------*/
437
550a7375
FB		 438/*
439 * Handles OTG hnp timeouts, such as b_ase0_brst
440 */
a156544b 441static void musb_otg_timer_func(unsigned long data)
550a7375
FB		 442{
443 struct musb *musb = (struct musb *)data;
444 unsigned long flags;
445
446 spin_lock_irqsave(&musb->lock, flags);
e47d9254 447 switch (musb->xceiv->otg->state) {
550a7375 448 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 449 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
550a7375 450 musb_g_disconnect(musb);
e47d9254 451 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 452 musb->is_active = 0;
453 break;
ab983f2a 454 case OTG_STATE_A_SUSPEND:
550a7375 455 case OTG_STATE_A_WAIT_BCON:
5c8a86e1 456 dev_dbg(musb->controller, "HNP: %s timeout\n",
e47d9254 457 usb_otg_state_string(musb->xceiv->otg->state));
743411b3 458 musb_platform_set_vbus(musb, 0);
e47d9254 459 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
550a7375
FB		 460 break;
461 default:
5c8a86e1 462 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
e47d9254 463 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 464 }
550a7375
FB		 465 spin_unlock_irqrestore(&musb->lock, flags);
466}
467
550a7375 468/*
f7f9d63e 469 * Stops the HNP transition. Caller must take care of locking.
550a7375
FB		 470 */
471void musb_hnp_stop(struct musb *musb)
472{
8b125df5 473 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 474 void __iomem *mbase = musb->mregs;
475 u8 reg;
476
42c0bf1c 477 dev_dbg(musb->controller, "HNP: stop from %s\n",
e47d9254 478 usb_otg_state_string(musb->xceiv->otg->state));
ab983f2a 479
e47d9254 480 switch (musb->xceiv->otg->state) {
550a7375 481 case OTG_STATE_A_PERIPHERAL:
550a7375 482 musb_g_disconnect(musb);
5c8a86e1 483 dev_dbg(musb->controller, "HNP: back to %s\n",
e47d9254 484 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 485 break;
486 case OTG_STATE_B_HOST:
5c8a86e1 487 dev_dbg(musb->controller, "HNP: Disabling HR\n");
74c2e936
DM		 488 if (hcd)
489 hcd->self.is_b_host = 0;
e47d9254 490 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 491 MUSB_DEV_MODE(musb);
492 reg = musb_readb(mbase, MUSB_POWER);
493 reg |= MUSB_POWER_SUSPENDM;
494 musb_writeb(mbase, MUSB_POWER, reg);
495 /* REVISIT: Start SESSION_REQUEST here? */
496 break;
497 default:
5c8a86e1 498 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
e47d9254 499 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 500 }
501
502 /*
503 * When returning to A state after HNP, avoid hub_port_rebounce(),
504 * which cause occasional OPT A "Did not receive reset after connect"
505 * errors.
506 */
749da5f8 507 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
550a7375
FB		 508}
509
f905bc68 510static void musb_generic_disable(struct musb *musb);
550a7375
FB		 511/*
512 * Interrupt Service Routine to record USB "global" interrupts.
513 * Since these do not happen often and signify things of
514 * paramount importance, it seems OK to check them individually;
515 * the order of the tests is specified in the manual
516 *
517 * @param musb instance pointer
518 * @param int_usb register contents
519 * @param devctl
520 * @param power
521 */
522
550a7375 523static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
b11e94d0 524 u8 devctl)
550a7375
FB		 525{
526 irqreturn_t handled = IRQ_NONE;
550a7375 527
b11e94d0 528 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
550a7375
FB		 529 int_usb);
530
531 /* in host mode, the peripheral may issue remote wakeup.
532 * in peripheral mode, the host may resume the link.
533 * spurious RESUME irqs happen too, paired with SUSPEND.
534 */
535 if (int_usb & MUSB_INTR_RESUME) {
536 handled = IRQ_HANDLED;
e47d9254 537 dev_dbg(musb->controller, "RESUME (%s)\n", usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 538
539 if (devctl & MUSB_DEVCTL_HM) {
aa471456 540 void __iomem *mbase = musb->mregs;
b11e94d0 541 u8 power;
aa471456 542
e47d9254 543 switch (musb->xceiv->otg->state) {
550a7375
FB		 544 case OTG_STATE_A_SUSPEND:
545 /* remote wakeup? later, GetPortStatus
546 * will stop RESUME signaling
547 */
548
b11e94d0 549 power = musb_readb(musb->mregs, MUSB_POWER);
550a7375
FB		 550 if (power & MUSB_POWER_SUSPENDM) {
551 /* spurious */
552 musb->int_usb &= ~MUSB_INTR_SUSPEND;
5c8a86e1 553 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
550a7375
FB		 554 break;
555 }
556
557 power &= ~MUSB_POWER_SUSPENDM;
558 musb_writeb(mbase, MUSB_POWER,
559 power | MUSB_POWER_RESUME);
560
561 musb->port1_status |=
562 (USB_PORT_STAT_C_SUSPEND << 16)
563 | MUSB_PORT_STAT_RESUME;
30d361bf
DM		 564 musb->rh_timer = jiffies
565 + msecs_to_jiffies(20);
baadd52f 566 musb->need_finish_resume = 1;
550a7375 567
e47d9254 568 musb->xceiv->otg->state = OTG_STATE_A_HOST;
550a7375 569 musb->is_active = 1;
9298b4aa 570 musb_host_resume_root_hub(musb);
550a7375
FB		 571 break;
572 case OTG_STATE_B_WAIT_ACON:
e47d9254 573 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 574 musb->is_active = 1;
575 MUSB_DEV_MODE(musb);
576 break;
577 default:
578 WARNING("bogus %s RESUME (%s)\n",
579 "host",
e47d9254 580 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 581 }
550a7375 582 } else {
e47d9254 583 switch (musb->xceiv->otg->state) {
550a7375
FB		 584 case OTG_STATE_A_SUSPEND:
585 /* possibly DISCONNECT is upcoming */
e47d9254 586 musb->xceiv->otg->state = OTG_STATE_A_HOST;
0b3eba44 587 musb_host_resume_root_hub(musb);
550a7375 588 break;
550a7375
FB		 589 case OTG_STATE_B_WAIT_ACON:
590 case OTG_STATE_B_PERIPHERAL:
591 /* disconnect while suspended? we may
592 * not get a disconnect irq...
593 */
594 if ((devctl & MUSB_DEVCTL_VBUS)
595 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
596 ) {
597 musb->int_usb |= MUSB_INTR_DISCONNECT;
598 musb->int_usb &= ~MUSB_INTR_SUSPEND;
599 break;
600 }
601 musb_g_resume(musb);
602 break;
603 case OTG_STATE_B_IDLE:
604 musb->int_usb &= ~MUSB_INTR_SUSPEND;
605 break;
550a7375
FB		 606 default:
607 WARNING("bogus %s RESUME (%s)\n",
608 "peripheral",
e47d9254 609 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 610 }
611 }
612 }
613
550a7375
FB		 614 /* see manual for the order of the tests */
615 if (int_usb & MUSB_INTR_SESSREQ) {
aa471456
FB		 616 void __iomem *mbase = musb->mregs;
617
19aab56c
HK		 618 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
619 && (devctl & MUSB_DEVCTL_BDEVICE)) {
5c8a86e1 620 dev_dbg(musb->controller, "SessReq while on B state\n");
a6038ee7
HK		 621 return IRQ_HANDLED;
622 }
623
5c8a86e1 624 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
e47d9254 625 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 626
627 /* IRQ arrives from ID pin sense or (later, if VBUS power
628 * is removed) SRP. responses are time critical:
629 * - turn on VBUS (with silicon-specific mechanism)
630 * - go through A_WAIT_VRISE
631 * - ... to A_WAIT_BCON.
632 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
633 */
634 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
635 musb->ep0_stage = MUSB_EP0_START;
e47d9254 636 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
550a7375 637 MUSB_HST_MODE(musb);
743411b3 638 musb_platform_set_vbus(musb, 1);
550a7375
FB		 639
640 handled = IRQ_HANDLED;
641 }
642
643 if (int_usb & MUSB_INTR_VBUSERROR) {
644 int ignore = 0;
645
646 /* During connection as an A-Device, we may see a short
647 * current spikes causing voltage drop, because of cable
648 * and peripheral capacitance combined with vbus draw.
649 * (So: less common with truly self-powered devices, where
650 * vbus doesn't act like a power supply.)
651 *
652 * Such spikes are short; usually less than ~500 usec, max
653 * of ~2 msec. That is, they're not sustained overcurrent
654 * errors, though they're reported using VBUSERROR irqs.
655 *
656 * Workarounds: (a) hardware: use self powered devices.
657 * (b) software: ignore non-repeated VBUS errors.
658 *
659 * REVISIT: do delays from lots of DEBUG_KERNEL checks
660 * make trouble here, keeping VBUS < 4.4V ?
661 */
e47d9254 662 switch (musb->xceiv->otg->state) {
550a7375
FB		 663 case OTG_STATE_A_HOST:
664 /* recovery is dicey once we've gotten past the
665 * initial stages of enumeration, but if VBUS
666 * stayed ok at the other end of the link, and
667 * another reset is due (at least for high speed,
668 * to redo the chirp etc), it might work OK...
669 */
670 case OTG_STATE_A_WAIT_BCON:
671 case OTG_STATE_A_WAIT_VRISE:
672 if (musb->vbuserr_retry) {
aa471456
FB		 673 void __iomem *mbase = musb->mregs;
674
550a7375
FB		 675 musb->vbuserr_retry--;
676 ignore = 1;
677 devctl |= MUSB_DEVCTL_SESSION;
678 musb_writeb(mbase, MUSB_DEVCTL, devctl);
679 } else {
680 musb->port1_status |=
749da5f8
AS		 681 USB_PORT_STAT_OVERCURRENT
682 | (USB_PORT_STAT_C_OVERCURRENT << 16);
550a7375
FB		 683 }
684 break;
685 default:
686 break;
687 }
688
54485116
GI		 689 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
690 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
e47d9254 691 usb_otg_state_string(musb->xceiv->otg->state),
550a7375
FB		 692 devctl,
693 ({ char *s;
694 switch (devctl & MUSB_DEVCTL_VBUS) {
695 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
696 s = "<SessEnd"; break;
697 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
698 s = "<AValid"; break;
699 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
700 s = "<VBusValid"; break;
701 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
702 default:
703 s = "VALID"; break;
2b84f92b 704 } s; }),
550a7375
FB		 705 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
706 musb->port1_status);
707
708 /* go through A_WAIT_VFALL then start a new session */
709 if (!ignore)
743411b3 710 musb_platform_set_vbus(musb, 0);
550a7375
FB		 711 handled = IRQ_HANDLED;
712 }
713
1c25fda4 714 if (int_usb & MUSB_INTR_SUSPEND) {
b11e94d0 715 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
e47d9254 716 usb_otg_state_string(musb->xceiv->otg->state), devctl);
1c25fda4
AM		 717 handled = IRQ_HANDLED;
718
e47d9254 719 switch (musb->xceiv->otg->state) {
1c25fda4
AM		 720 case OTG_STATE_A_PERIPHERAL:
721 /* We also come here if the cable is removed, since
722 * this silicon doesn't report ID-no-longer-grounded.
723 *
724 * We depend on T(a_wait_bcon) to shut us down, and
725 * hope users don't do anything dicey during this
726 * undesired detour through A_WAIT_BCON.
727 */
728 musb_hnp_stop(musb);
0b3eba44 729 musb_host_resume_root_hub(musb);
1c25fda4
AM		 730 musb_root_disconnect(musb);
731 musb_platform_try_idle(musb, jiffies
732 + msecs_to_jiffies(musb->a_wait_bcon
733 ? : OTG_TIME_A_WAIT_BCON));
734
735 break;
1c25fda4
AM		 736 case OTG_STATE_B_IDLE:
737 if (!musb->is_active)
738 break;
739 case OTG_STATE_B_PERIPHERAL:
740 musb_g_suspend(musb);
eee3f15d 741 musb->is_active = musb->g.b_hnp_enable;
1c25fda4 742 if (musb->is_active) {
e47d9254 743 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
5c8a86e1 744 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
1c25fda4
AM		 745 mod_timer(&musb->otg_timer, jiffies
746 + msecs_to_jiffies(
747 OTG_TIME_B_ASE0_BRST));
1c25fda4
AM		 748 }
749 break;
750 case OTG_STATE_A_WAIT_BCON:
751 if (musb->a_wait_bcon != 0)
752 musb_platform_try_idle(musb, jiffies
753 + msecs_to_jiffies(musb->a_wait_bcon));
754 break;
755 case OTG_STATE_A_HOST:
e47d9254 756 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
eee3f15d 757 musb->is_active = musb->hcd->self.b_hnp_enable;
1c25fda4
AM		 758 break;
759 case OTG_STATE_B_HOST:
760 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
5c8a86e1 761 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
1c25fda4
AM		 762 break;
763 default:
764 /* "should not happen" */
765 musb->is_active = 0;
766 break;
767 }
768 }
769
550a7375 770 if (int_usb & MUSB_INTR_CONNECT) {
8b125df5 771 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 772
773 handled = IRQ_HANDLED;
774 musb->is_active = 1;
550a7375
FB		 775
776 musb->ep0_stage = MUSB_EP0_START;
777
550a7375
FB		 778 /* flush endpoints when transitioning from Device Mode */
779 if (is_peripheral_active(musb)) {
780 /* REVISIT HNP; just force disconnect */
781 }
b18d26f6
SAS		 782 musb->intrtxe = musb->epmask;
783 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
af5ec14d
SAS		 784 musb->intrrxe = musb->epmask & 0xfffe;
785 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
d709d22e 786 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 787 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
788 |USB_PORT_STAT_HIGH_SPEED
789 |USB_PORT_STAT_ENABLE
790 );
791 musb->port1_status |= USB_PORT_STAT_CONNECTION
792 |(USB_PORT_STAT_C_CONNECTION << 16);
793
794 /* high vs full speed is just a guess until after reset */
795 if (devctl & MUSB_DEVCTL_LSDEV)
796 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
797
550a7375 798 /* indicate new connection to OTG machine */
e47d9254 799 switch (musb->xceiv->otg->state) {
550a7375
FB		 800 case OTG_STATE_B_PERIPHERAL:
801 if (int_usb & MUSB_INTR_SUSPEND) {
5c8a86e1 802 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
550a7375 803 int_usb &= ~MUSB_INTR_SUSPEND;
1de00dae 804 goto b_host;
550a7375 805 } else
5c8a86e1 806 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
550a7375
FB		 807 break;
808 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 809 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
1de00dae 810b_host:
e47d9254 811 musb->xceiv->otg->state = OTG_STATE_B_HOST;
74c2e936
DM		 812 if (musb->hcd)
813 musb->hcd->self.is_b_host = 1;
1de00dae 814 del_timer(&musb->otg_timer);
550a7375
FB		 815 break;
816 default:
817 if ((devctl & MUSB_DEVCTL_VBUS)
818 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
e47d9254 819 musb->xceiv->otg->state = OTG_STATE_A_HOST;
0b3eba44
DM		 820 if (hcd)
821 hcd->self.is_b_host = 0;
550a7375
FB		 822 }
823 break;
824 }
1de00dae 825
0b3eba44 826 musb_host_poke_root_hub(musb);
1de00dae 827
5c8a86e1 828 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
e47d9254 829 usb_otg_state_string(musb->xceiv->otg->state), devctl);
550a7375 830 }
550a7375 831
6d349671 832 if (int_usb & MUSB_INTR_DISCONNECT) {
5c8a86e1 833 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
e47d9254 834 usb_otg_state_string(musb->xceiv->otg->state),
1c25fda4
AM		 835 MUSB_MODE(musb), devctl);
836 handled = IRQ_HANDLED;
837
e47d9254 838 switch (musb->xceiv->otg->state) {
1c25fda4
AM		 839 case OTG_STATE_A_HOST:
840 case OTG_STATE_A_SUSPEND:
0b3eba44 841 musb_host_resume_root_hub(musb);
1c25fda4 842 musb_root_disconnect(musb);
032ec49f 843 if (musb->a_wait_bcon != 0)
1c25fda4
AM		 844 musb_platform_try_idle(musb, jiffies
845 + msecs_to_jiffies(musb->a_wait_bcon));
846 break;
1c25fda4
AM		 847 case OTG_STATE_B_HOST:
848 /* REVISIT this behaves for "real disconnect"
849 * cases; make sure the other transitions from
850 * from B_HOST act right too. The B_HOST code
851 * in hnp_stop() is currently not used...
852 */
853 musb_root_disconnect(musb);
74c2e936
DM		 854 if (musb->hcd)
855 musb->hcd->self.is_b_host = 0;
e47d9254 856 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
1c25fda4
AM		 857 MUSB_DEV_MODE(musb);
858 musb_g_disconnect(musb);
859 break;
860 case OTG_STATE_A_PERIPHERAL:
861 musb_hnp_stop(musb);
862 musb_root_disconnect(musb);
863 /* FALLTHROUGH */
864 case OTG_STATE_B_WAIT_ACON:
865 /* FALLTHROUGH */
1c25fda4
AM		 866 case OTG_STATE_B_PERIPHERAL:
867 case OTG_STATE_B_IDLE:
868 musb_g_disconnect(musb);
869 break;
1c25fda4
AM		 870 default:
871 WARNING("unhandled DISCONNECT transition (%s)\n",
e47d9254 872 usb_otg_state_string(musb->xceiv->otg->state));
1c25fda4
AM		 873 break;
874 }
875 }
876
550a7375
FB		 877 /* mentor saves a bit: bus reset and babble share the same irq.
878 * only host sees babble; only peripheral sees bus reset.
879 */
880 if (int_usb & MUSB_INTR_RESET) {
1c25fda4 881 handled = IRQ_HANDLED;
896f7ea3 882 if (devctl & MUSB_DEVCTL_HM) {
550a7375
FB		 883 /*
884 * Looks like non-HS BABBLE can be ignored, but
885 * HS BABBLE is an error condition. For HS the solution
886 * is to avoid babble in the first place and fix what
887 * caused BABBLE. When HS BABBLE happens we can only
888 * stop the session.
889 */
d57a2771 890 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) {
5c8a86e1 891 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
d57a2771 892 } else {
550a7375 893 ERR("Stopping host session -- babble\n");
1c25fda4 894 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
550a7375 895 }
a04d46d0 896 } else {
5c8a86e1 897 dev_dbg(musb->controller, "BUS RESET as %s\n",
e47d9254
AT		 898 usb_otg_state_string(musb->xceiv->otg->state));
899 switch (musb->xceiv->otg->state) {
550a7375 900 case OTG_STATE_A_SUSPEND:
550a7375
FB		 901 musb_g_reset(musb);
902 /* FALLTHROUGH */
903 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
f7f9d63e 904 /* never use invalid T(a_wait_bcon) */
5c8a86e1 905 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
e47d9254 906 usb_otg_state_string(musb->xceiv->otg->state),
3df00453 907 TA_WAIT_BCON(musb));
f7f9d63e
DB		 908 mod_timer(&musb->otg_timer, jiffies
909 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
550a7375
FB		 910 break;
911 case OTG_STATE_A_PERIPHERAL:
1de00dae
DB		 912 del_timer(&musb->otg_timer);
913 musb_g_reset(musb);
550a7375
FB		 914 break;
915 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 916 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
e47d9254
AT		 917 usb_otg_state_string(musb->xceiv->otg->state));
918 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 919 musb_g_reset(musb);
920 break;
550a7375 921 case OTG_STATE_B_IDLE:
e47d9254 922 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 923 /* FALLTHROUGH */
924 case OTG_STATE_B_PERIPHERAL:
925 musb_g_reset(musb);
926 break;
927 default:
5c8a86e1 928 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
e47d9254 929 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 930 }
931 }
550a7375 932 }
550a7375 933
ca88fc2e 934 /* handle babble condition */
f905bc68
GC		 935 if (int_usb & MUSB_INTR_BABBLE && is_host_active(musb)) {
936 musb_generic_disable(musb);
675ae763
GC		 937 schedule_delayed_work(&musb->recover_work,
938 msecs_to_jiffies(100));
f905bc68 939 }
ca88fc2e 940
550a7375
FB		 941#if 0
942/* REVISIT ... this would be for multiplexing periodic endpoints, or
943 * supporting transfer phasing to prevent exceeding ISO bandwidth
944 * limits of a given frame or microframe.
945 *
946 * It's not needed for peripheral side, which dedicates endpoints;
947 * though it _might_ use SOF irqs for other purposes.
948 *
949 * And it's not currently needed for host side, which also dedicates
950 * endpoints, relies on TX/RX interval registers, and isn't claimed
951 * to support ISO transfers yet.
952 */
953 if (int_usb & MUSB_INTR_SOF) {
954 void __iomem *mbase = musb->mregs;
955 struct musb_hw_ep *ep;
956 u8 epnum;
957 u16 frame;
958
5c8a86e1 959 dev_dbg(musb->controller, "START_OF_FRAME\n");
550a7375
FB		 960 handled = IRQ_HANDLED;
961
962 /* start any periodic Tx transfers waiting for current frame */
963 frame = musb_readw(mbase, MUSB_FRAME);
964 ep = musb->endpoints;
965 for (epnum = 1; (epnum < musb->nr_endpoints)
966 && (musb->epmask >= (1 << epnum));
967 epnum++, ep++) {
968 /*
969 * FIXME handle framecounter wraps (12 bits)
970 * eliminate duplicated StartUrb logic
971 */
972 if (ep->dwWaitFrame >= frame) {
973 ep->dwWaitFrame = 0;
974 pr_debug("SOF --> periodic TX%s on %d\n",
975 ep->tx_channel ? " DMA" : "",
976 epnum);
977 if (!ep->tx_channel)
978 musb_h_tx_start(musb, epnum);
979 else
980 cppi_hostdma_start(musb, epnum);
981 }
982 } /* end of for loop */
983 }
984#endif
985
1c25fda4 986 schedule_work(&musb->irq_work);
550a7375
FB		 987
988 return handled;
989}
990
991/*-------------------------------------------------------------------------*/
992
550a7375
FB		 993static void musb_generic_disable(struct musb *musb)
994{
995 void __iomem *mbase = musb->mregs;
996 u16 temp;
997
998 /* disable interrupts */
999 musb_writeb(mbase, MUSB_INTRUSBE, 0);
b18d26f6 1000 musb->intrtxe = 0;
550a7375 1001 musb_writew(mbase, MUSB_INTRTXE, 0);
af5ec14d 1002 musb->intrrxe = 0;
550a7375
FB		 1003 musb_writew(mbase, MUSB_INTRRXE, 0);
1004
1005 /* off */
1006 musb_writeb(mbase, MUSB_DEVCTL, 0);
1007
1008 /* flush pending interrupts */
1009 temp = musb_readb(mbase, MUSB_INTRUSB);
1010 temp = musb_readw(mbase, MUSB_INTRTX);
1011 temp = musb_readw(mbase, MUSB_INTRRX);
1012
1013}
1014
001dd84a
SAS		 1015/*
1016 * Program the HDRC to start (enable interrupts, dma, etc.).
1017 */
1018void musb_start(struct musb *musb)
1019{
1020 void __iomem *regs = musb->mregs;
1021 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1022
1023 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1024
1025 /* Set INT enable registers, enable interrupts */
1026 musb->intrtxe = musb->epmask;
1027 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1028 musb->intrrxe = musb->epmask & 0xfffe;
1029 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1030 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1031
1032 musb_writeb(regs, MUSB_TESTMODE, 0);
1033
1034 /* put into basic highspeed mode and start session */
1035 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
1036 | MUSB_POWER_HSENAB
1037 /* ENSUSPEND wedges tusb */
1038 /* | MUSB_POWER_ENSUSPEND */
1039 );
1040
1041 musb->is_active = 0;
1042 devctl = musb_readb(regs, MUSB_DEVCTL);
1043 devctl &= ~MUSB_DEVCTL_SESSION;
1044
1045 /* session started after:
1046 * (a) ID-grounded irq, host mode;
1047 * (b) vbus present/connect IRQ, peripheral mode;
1048 * (c) peripheral initiates, using SRP
1049 */
1050 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1051 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1052 musb->is_active = 1;
1053 } else {
1054 devctl |= MUSB_DEVCTL_SESSION;
1055 }
1056
1057 musb_platform_enable(musb);
1058 musb_writeb(regs, MUSB_DEVCTL, devctl);
1059}
1060
550a7375
FB		 1061/*
1062 * Make the HDRC stop (disable interrupts, etc.);
1063 * reversible by musb_start
1064 * called on gadget driver unregister
1065 * with controller locked, irqs blocked
1066 * acts as a NOP unless some role activated the hardware
1067 */
1068void musb_stop(struct musb *musb)
1069{
1070 /* stop IRQs, timers, ... */
1071 musb_platform_disable(musb);
1072 musb_generic_disable(musb);
5c8a86e1 1073 dev_dbg(musb->controller, "HDRC disabled\n");
550a7375
FB		 1074
1075 /* FIXME
1076 * - mark host and/or peripheral drivers unusable/inactive
1077 * - disable DMA (and enable it in HdrcStart)
1078 * - make sure we can musb_start() after musb_stop(); with
1079 * OTG mode, gadget driver module rmmod/modprobe cycles that
1080 * - ...
1081 */
1082 musb_platform_try_idle(musb, 0);
1083}
1084
1085static void musb_shutdown(struct platform_device *pdev)
1086{
1087 struct musb *musb = dev_to_musb(&pdev->dev);
1088 unsigned long flags;
1089
4f9edd2d 1090 pm_runtime_get_sync(musb->controller);
24307cae 1091
2cc65fea 1092 musb_host_cleanup(musb);
24307cae
GI		 1093 musb_gadget_cleanup(musb);
1094
550a7375
FB		 1095 spin_lock_irqsave(&musb->lock, flags);
1096 musb_platform_disable(musb);
1097 musb_generic_disable(musb);
550a7375
FB		 1098 spin_unlock_irqrestore(&musb->lock, flags);
1099
120d074c
GI		 1100 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1101 musb_platform_exit(musb);
120d074c 1102
4f9edd2d 1103 pm_runtime_put(musb->controller);
550a7375
FB		 1104 /* FIXME power down */
1105}
1106
1107
1108/*-------------------------------------------------------------------------*/
1109
1110/*
1111 * The silicon either has hard-wired endpoint configurations, or else
1112 * "dynamic fifo" sizing. The driver has support for both, though at this
c767c1c6
DB		 1113 * writing only the dynamic sizing is very well tested. Since we switched
1114 * away from compile-time hardware parameters, we can no longer rely on
1115 * dead code elimination to leave only the relevant one in the object file.
550a7375
FB		 1116 *
1117 * We don't currently use dynamic fifo setup capability to do anything
1118 * more than selecting one of a bunch of predefined configurations.
1119 */
8a77f05a 1120static ushort fifo_mode;
550a7375
FB		 1121
1122/* "modprobe ... fifo_mode=1" etc */
1123module_param(fifo_mode, ushort, 0);
1124MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1125
550a7375
FB		 1126/*
1127 * tables defining fifo_mode values. define more if you like.
1128 * for host side, make sure both halves of ep1 are set up.
1129 */
1130
1131/* mode 0 - fits in 2KB */
d3608b6d 1132static struct musb_fifo_cfg mode_0_cfg[] = {
550a7375
FB		 1133{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1134{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1135{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1136{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1137{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1138};
1139
1140/* mode 1 - fits in 4KB */
d3608b6d 1141static struct musb_fifo_cfg mode_1_cfg[] = {
550a7375
FB		 1142{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1143{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1144{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1145{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1146{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1147};
1148
1149/* mode 2 - fits in 4KB */
d3608b6d 1150static struct musb_fifo_cfg mode_2_cfg[] = {
550a7375
FB		 1151{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1152{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1153{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1154{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1155{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1156{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1157};
1158
1159/* mode 3 - fits in 4KB */
d3608b6d 1160static struct musb_fifo_cfg mode_3_cfg[] = {
550a7375
FB		 1161{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1162{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1163{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1164{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1165{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1166{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1167};
1168
1169/* mode 4 - fits in 16KB */
d3608b6d 1170static struct musb_fifo_cfg mode_4_cfg[] = {
550a7375
FB		 1171{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1172{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1173{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1174{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1175{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1176{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1177{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1178{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1179{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1180{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1181{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1182{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1183{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1184{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1185{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1186{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1187{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1188{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
a483d706
AKG		 1189{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1190{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1191{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1192{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1193{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1194{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1195{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
550a7375
FB		 1196{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1197{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1198};
1199
3b151526 1200/* mode 5 - fits in 8KB */
d3608b6d 1201static struct musb_fifo_cfg mode_5_cfg[] = {
3b151526
AKG		 1202{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1203{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1204{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1205{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1206{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1207{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1208{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1209{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1210{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1211{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1212{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1213{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1214{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1215{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1216{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1217{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1218{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1219{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1220{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1221{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1222{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1223{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1224{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1225{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1226{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1227{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1228{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1229};
550a7375
FB		 1230
1231/*
1232 * configure a fifo; for non-shared endpoints, this may be called
1233 * once for a tx fifo and once for an rx fifo.
1234 *
1235 * returns negative errno or offset for next fifo.
1236 */
41ac7b3a 1237static int
550a7375 1238fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
e6c213b2 1239 const struct musb_fifo_cfg *cfg, u16 offset)
550a7375
FB		 1240{
1241 void __iomem *mbase = musb->mregs;
1242 int size = 0;
1243 u16 maxpacket = cfg->maxpacket;
1244 u16 c_off = offset >> 3;
1245 u8 c_size;
1246
1247 /* expect hw_ep has already been zero-initialized */
1248
1249 size = ffs(max(maxpacket, (u16) 8)) - 1;
1250 maxpacket = 1 << size;
1251
1252 c_size = size - 3;
1253 if (cfg->mode == BUF_DOUBLE) {
ca6d1b13
FB		 1254 if ((offset + (maxpacket << 1)) >
1255 (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1256 return -EMSGSIZE;
1257 c_size |= MUSB_FIFOSZ_DPB;
1258 } else {
ca6d1b13 1259 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1260 return -EMSGSIZE;
1261 }
1262
1263 /* configure the FIFO */
1264 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1265
550a7375 1266 /* EP0 reserved endpoint for control, bidirectional;
5ae477b0 1267 * EP1 reserved for bulk, two unidirectional halves.
550a7375
FB		 1268 */
1269 if (hw_ep->epnum == 1)
1270 musb->bulk_ep = hw_ep;
1271 /* REVISIT error check: be sure ep0 can both rx and tx ... */
550a7375
FB		 1272 switch (cfg->style) {
1273 case FIFO_TX:
c6cf8b00
BW		 1274 musb_write_txfifosz(mbase, c_size);
1275 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1276 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1277 hw_ep->max_packet_sz_tx = maxpacket;
1278 break;
1279 case FIFO_RX:
c6cf8b00
BW		 1280 musb_write_rxfifosz(mbase, c_size);
1281 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1282 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1283 hw_ep->max_packet_sz_rx = maxpacket;
1284 break;
1285 case FIFO_RXTX:
c6cf8b00
BW		 1286 musb_write_txfifosz(mbase, c_size);
1287 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1288 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1289 hw_ep->max_packet_sz_rx = maxpacket;
1290
c6cf8b00
BW		 1291 musb_write_rxfifosz(mbase, c_size);
1292 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1293 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1294 hw_ep->max_packet_sz_tx = maxpacket;
1295
1296 hw_ep->is_shared_fifo = true;
1297 break;
1298 }
1299
1300 /* NOTE rx and tx endpoint irqs aren't managed separately,
1301 * which happens to be ok
1302 */
1303 musb->epmask |= (1 << hw_ep->epnum);
1304
1305 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1306}
1307
d3608b6d 1308static struct musb_fifo_cfg ep0_cfg = {
550a7375
FB		 1309 .style = FIFO_RXTX, .maxpacket = 64,
1310};
1311
41ac7b3a 1312static int ep_config_from_table(struct musb *musb)
550a7375 1313{
e6c213b2 1314 const struct musb_fifo_cfg *cfg;
550a7375
FB		 1315 unsigned i, n;
1316 int offset;
1317 struct musb_hw_ep *hw_ep = musb->endpoints;
1318
e6c213b2
FB		 1319 if (musb->config->fifo_cfg) {
1320 cfg = musb->config->fifo_cfg;
1321 n = musb->config->fifo_cfg_size;
1322 goto done;
1323 }
1324
550a7375
FB		 1325 switch (fifo_mode) {
1326 default:
1327 fifo_mode = 0;
1328 /* FALLTHROUGH */
1329 case 0:
1330 cfg = mode_0_cfg;
1331 n = ARRAY_SIZE(mode_0_cfg);
1332 break;
1333 case 1:
1334 cfg = mode_1_cfg;
1335 n = ARRAY_SIZE(mode_1_cfg);
1336 break;
1337 case 2:
1338 cfg = mode_2_cfg;
1339 n = ARRAY_SIZE(mode_2_cfg);
1340 break;
1341 case 3:
1342 cfg = mode_3_cfg;
1343 n = ARRAY_SIZE(mode_3_cfg);
1344 break;
1345 case 4:
1346 cfg = mode_4_cfg;
1347 n = ARRAY_SIZE(mode_4_cfg);
1348 break;
3b151526
AKG		 1349 case 5:
1350 cfg = mode_5_cfg;
1351 n = ARRAY_SIZE(mode_5_cfg);
1352 break;
550a7375
FB		 1353 }
1354
1355 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1356 musb_driver_name, fifo_mode);
1357
1358
e6c213b2 1359done:
550a7375
FB		 1360 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1361 /* assert(offset > 0) */
1362
1363 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
ca6d1b13 1364 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
550a7375
FB		 1365 */
1366
1367 for (i = 0; i < n; i++) {
1368 u8 epn = cfg->hw_ep_num;
1369
ca6d1b13 1370 if (epn >= musb->config->num_eps) {
550a7375
FB		 1371 pr_debug("%s: invalid ep %d\n",
1372 musb_driver_name, epn);
bb1c9ef1 1373 return -EINVAL;
550a7375
FB		 1374 }
1375 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1376 if (offset < 0) {
1377 pr_debug("%s: mem overrun, ep %d\n",
1378 musb_driver_name, epn);
f69dfa1f 1379 return offset;
550a7375
FB		 1380 }
1381 epn++;
1382 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1383 }
1384
1385 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1386 musb_driver_name,
ca6d1b13
FB		 1387 n + 1, musb->config->num_eps * 2 - 1,
1388 offset, (1 << (musb->config->ram_bits + 2)));
550a7375 1389
550a7375
FB		 1390 if (!musb->bulk_ep) {
1391 pr_debug("%s: missing bulk\n", musb_driver_name);
1392 return -EINVAL;
1393 }
550a7375
FB		 1394
1395 return 0;
1396}
1397
1398
1399/*
1400 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1401 * @param musb the controller
1402 */
41ac7b3a 1403static int ep_config_from_hw(struct musb *musb)
550a7375 1404{
c6cf8b00 1405 u8 epnum = 0;
550a7375 1406 struct musb_hw_ep *hw_ep;
a156544b 1407 void __iomem *mbase = musb->mregs;
c6cf8b00 1408 int ret = 0;
550a7375 1409
5c8a86e1 1410 dev_dbg(musb->controller, "<== static silicon ep config\n");
550a7375
FB		 1411
1412 /* FIXME pick up ep0 maxpacket size */
1413
ca6d1b13 1414 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
550a7375
FB		 1415 musb_ep_select(mbase, epnum);
1416 hw_ep = musb->endpoints + epnum;
1417
c6cf8b00
BW		 1418 ret = musb_read_fifosize(musb, hw_ep, epnum);
1419 if (ret < 0)
550a7375 1420 break;
550a7375
FB		 1421
1422 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1423
550a7375
FB		 1424 /* pick an RX/TX endpoint for bulk */
1425 if (hw_ep->max_packet_sz_tx < 512
1426 || hw_ep->max_packet_sz_rx < 512)
1427 continue;
1428
1429 /* REVISIT: this algorithm is lazy, we should at least
1430 * try to pick a double buffered endpoint.
1431 */
1432 if (musb->bulk_ep)
1433 continue;
1434 musb->bulk_ep = hw_ep;
550a7375
FB		 1435 }
1436
550a7375
FB		 1437 if (!musb->bulk_ep) {
1438 pr_debug("%s: missing bulk\n", musb_driver_name);
1439 return -EINVAL;
1440 }
550a7375
FB		 1441
1442 return 0;
1443}
1444
1445enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1446
1447/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1448 * configure endpoints, or take their config from silicon
1449 */
41ac7b3a 1450static int musb_core_init(u16 musb_type, struct musb *musb)
550a7375 1451{
550a7375
FB		 1452 u8 reg;
1453 char *type;
0ea52ff4 1454 char aInfo[90], aRevision[32], aDate[12];
550a7375
FB		 1455 void __iomem *mbase = musb->mregs;
1456 int status = 0;
1457 int i;
1458
1459 /* log core options (read using indexed model) */
c6cf8b00 1460 reg = musb_read_configdata(mbase);
550a7375
FB		 1461
1462 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
51bf0d0e 1463 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
550a7375 1464 strcat(aInfo, ", dyn FIFOs");
51bf0d0e
AKG		 1465 musb->dyn_fifo = true;
1466 }
550a7375
FB		 1467 if (reg & MUSB_CONFIGDATA_MPRXE) {
1468 strcat(aInfo, ", bulk combine");
550a7375 1469 musb->bulk_combine = true;
550a7375
FB		 1470 }
1471 if (reg & MUSB_CONFIGDATA_MPTXE) {
1472 strcat(aInfo, ", bulk split");
550a7375 1473 musb->bulk_split = true;
550a7375
FB		 1474 }
1475 if (reg & MUSB_CONFIGDATA_HBRXE) {
1476 strcat(aInfo, ", HB-ISO Rx");
a483d706 1477 musb->hb_iso_rx = true;
550a7375
FB		 1478 }
1479 if (reg & MUSB_CONFIGDATA_HBTXE) {
1480 strcat(aInfo, ", HB-ISO Tx");
a483d706 1481 musb->hb_iso_tx = true;
550a7375
FB		 1482 }
1483 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1484 strcat(aInfo, ", SoftConn");
1485
1486 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1487 musb_driver_name, reg, aInfo);
1488
550a7375 1489 aDate[0] = 0;
550a7375
FB		 1490 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1491 musb->is_multipoint = 1;
1492 type = "M";
1493 } else {
1494 musb->is_multipoint = 0;
1495 type = "";
550a7375
FB		 1496#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1497 printk(KERN_ERR
1498 "%s: kernel must blacklist external hubs\n",
1499 musb_driver_name);
550a7375
FB		 1500#endif
1501 }
1502
1503 /* log release info */
32c3b94e
AG		 1504 musb->hwvers = musb_read_hwvers(mbase);
1505 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1506 MUSB_HWVERS_MINOR(musb->hwvers),
1507 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
550a7375
FB		 1508 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1509 musb_driver_name, type, aRevision, aDate);
1510
1511 /* configure ep0 */
c6cf8b00 1512 musb_configure_ep0(musb);
550a7375
FB		 1513
1514 /* discover endpoint configuration */
1515 musb->nr_endpoints = 1;
1516 musb->epmask = 1;
1517
ad517e9e
FB		 1518 if (musb->dyn_fifo)
1519 status = ep_config_from_table(musb);
1520 else
1521 status = ep_config_from_hw(musb);
550a7375
FB		 1522
1523 if (status < 0)
1524 return status;
1525
1526 /* finish init, and print endpoint config */
1527 for (i = 0; i < musb->nr_endpoints; i++) {
1528 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1529
1b40fc57 1530 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
ebf39920 1531#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1b40fc57
TL		 1532 if (musb->io.quirks & MUSB_IN_TUSB) {
1533 hw_ep->fifo_async = musb->async + 0x400 +
1534 musb->io.fifo_offset(i);
1535 hw_ep->fifo_sync = musb->sync + 0x400 +
1536 musb->io.fifo_offset(i);
1537 hw_ep->fifo_sync_va =
1538 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1539
1540 if (i == 0)
1541 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1542 else
1543 hw_ep->conf = mbase + 0x400 +
1544 (((i - 1) & 0xf) << 2);
1545 }
550a7375
FB		 1546#endif
1547
d026e9c7 1548 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
c6cf8b00 1549 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
550a7375
FB		 1550 hw_ep->rx_reinit = 1;
1551 hw_ep->tx_reinit = 1;
550a7375
FB		 1552
1553 if (hw_ep->max_packet_sz_tx) {
5c8a86e1 1554 dev_dbg(musb->controller,
550a7375
FB		 1555 "%s: hw_ep %d%s, %smax %d\n",
1556 musb_driver_name, i,
1557 hw_ep->is_shared_fifo ? "shared" : "tx",
1558 hw_ep->tx_double_buffered
1559 ? "doublebuffer, " : "",
1560 hw_ep->max_packet_sz_tx);
1561 }
1562 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
5c8a86e1 1563 dev_dbg(musb->controller,
550a7375
FB		 1564 "%s: hw_ep %d%s, %smax %d\n",
1565 musb_driver_name, i,
1566 "rx",
1567 hw_ep->rx_double_buffered
1568 ? "doublebuffer, " : "",
1569 hw_ep->max_packet_sz_rx);
1570 }
1571 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
5c8a86e1 1572 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
550a7375
FB		 1573 }
1574
1575 return 0;
1576}
1577
1578/*-------------------------------------------------------------------------*/
1579
550a7375
FB		 1580/*
1581 * handle all the irqs defined by the HDRC core. for now we expect: other
1582 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1583 * will be assigned, and the irq will already have been acked.
1584 *
1585 * called in irq context with spinlock held, irqs blocked
1586 */
1587irqreturn_t musb_interrupt(struct musb *musb)
1588{
1589 irqreturn_t retval = IRQ_NONE;
31a0ede0
FB		 1590 unsigned long status;
1591 unsigned long epnum;
b11e94d0 1592 u8 devctl;
31a0ede0
FB		 1593
1594 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1595 return IRQ_NONE;
550a7375
FB		 1596
1597 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
550a7375 1598
5c8a86e1 1599 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
c03da38d 1600 is_host_active(musb) ? "host" : "peripheral",
550a7375
FB		 1601 musb->int_usb, musb->int_tx, musb->int_rx);
1602
e3c93e1a
FB		 1603 /**
1604 * According to Mentor Graphics' documentation, flowchart on page 98,
1605 * IRQ should be handled as follows:
1606 *
1607 * . Resume IRQ
1608 * . Session Request IRQ
1609 * . VBUS Error IRQ
1610 * . Suspend IRQ
1611 * . Connect IRQ
1612 * . Disconnect IRQ
1613 * . Reset/Babble IRQ
1614 * . SOF IRQ (we're not using this one)
1615 * . Endpoint 0 IRQ
1616 * . TX Endpoints
1617 * . RX Endpoints
1618 *
1619 * We will be following that flowchart in order to avoid any problems
1620 * that might arise with internal Finite State Machine.
550a7375 1621 */
e3c93e1a 1622
7d9645fd 1623 if (musb->int_usb)
31a0ede0 1624 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
550a7375 1625
550a7375 1626 if (musb->int_tx & 1) {
c03da38d 1627 if (is_host_active(musb))
550a7375
FB		 1628 retval |= musb_h_ep0_irq(musb);
1629 else
1630 retval |= musb_g_ep0_irq(musb);
31a0ede0
FB		 1631
1632 /* we have just handled endpoint 0 IRQ, clear it */
1633 musb->int_tx &= ~BIT(0);
550a7375
FB		 1634 }
1635
31a0ede0
FB		 1636 status = musb->int_tx;
1637
1638 for_each_set_bit(epnum, &status, 16) {
1639 retval = IRQ_HANDLED;
1640 if (is_host_active(musb))
1641 musb_host_tx(musb, epnum);
1642 else
1643 musb_g_tx(musb, epnum);
550a7375
FB		 1644 }
1645
31a0ede0 1646 status = musb->int_rx;
e3c93e1a 1647
31a0ede0
FB		 1648 for_each_set_bit(epnum, &status, 16) {
1649 retval = IRQ_HANDLED;
1650 if (is_host_active(musb))
1651 musb_host_rx(musb, epnum);
1652 else
1653 musb_g_rx(musb, epnum);
550a7375
FB		 1654 }
1655
550a7375
FB		 1656 return retval;
1657}
981430a1 1658EXPORT_SYMBOL_GPL(musb_interrupt);
550a7375
FB		 1659
1660#ifndef CONFIG_MUSB_PIO_ONLY
d3608b6d 1661static bool use_dma = 1;
550a7375
FB		 1662
1663/* "modprobe ... use_dma=0" etc */
1664module_param(use_dma, bool, 0);
1665MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1666
1667void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1668{
550a7375
FB		 1669 /* called with controller lock already held */
1670
1671 if (!epnum) {
1672#ifndef CONFIG_USB_TUSB_OMAP_DMA
1673 if (!is_cppi_enabled()) {
1674 /* endpoint 0 */
c03da38d 1675 if (is_host_active(musb))
550a7375
FB		 1676 musb_h_ep0_irq(musb);
1677 else
1678 musb_g_ep0_irq(musb);
1679 }
1680#endif
1681 } else {
1682 /* endpoints 1..15 */
1683 if (transmit) {
c03da38d 1684 if (is_host_active(musb))
a04d46d0
FB		 1685 musb_host_tx(musb, epnum);
1686 else
1687 musb_g_tx(musb, epnum);
550a7375
FB		 1688 } else {
1689 /* receive */
c03da38d 1690 if (is_host_active(musb))
a04d46d0
FB		 1691 musb_host_rx(musb, epnum);
1692 else
1693 musb_g_rx(musb, epnum);
550a7375
FB		 1694 }
1695 }
1696}
9a35f876 1697EXPORT_SYMBOL_GPL(musb_dma_completion);
550a7375
FB		 1698
1699#else
1700#define use_dma 0
1701#endif
1702
1703/*-------------------------------------------------------------------------*/
1704
550a7375
FB		 1705static ssize_t
1706musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1707{
1708 struct musb *musb = dev_to_musb(dev);
1709 unsigned long flags;
1710 int ret = -EINVAL;
1711
1712 spin_lock_irqsave(&musb->lock, flags);
e47d9254 1713 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 1714 spin_unlock_irqrestore(&musb->lock, flags);
1715
1716 return ret;
1717}
1718
1719static ssize_t
1720musb_mode_store(struct device *dev, struct device_attribute *attr,
1721 const char *buf, size_t n)
1722{
1723 struct musb *musb = dev_to_musb(dev);
1724 unsigned long flags;
96a274d1 1725 int status;
550a7375
FB		 1726
1727 spin_lock_irqsave(&musb->lock, flags);
96a274d1
DB		 1728 if (sysfs_streq(buf, "host"))
1729 status = musb_platform_set_mode(musb, MUSB_HOST);
1730 else if (sysfs_streq(buf, "peripheral"))
1731 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1732 else if (sysfs_streq(buf, "otg"))
1733 status = musb_platform_set_mode(musb, MUSB_OTG);
1734 else
1735 status = -EINVAL;
550a7375
FB		 1736 spin_unlock_irqrestore(&musb->lock, flags);
1737
96a274d1 1738 return (status == 0) ? n : status;
550a7375
FB		 1739}
1740static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1741
1742static ssize_t
1743musb_vbus_store(struct device *dev, struct device_attribute *attr,
1744 const char *buf, size_t n)
1745{
1746 struct musb *musb = dev_to_musb(dev);
1747 unsigned long flags;
1748 unsigned long val;
1749
1750 if (sscanf(buf, "%lu", &val) < 1) {
b3b1cc3b 1751 dev_err(dev, "Invalid VBUS timeout ms value\n");
550a7375
FB		 1752 return -EINVAL;
1753 }
1754
1755 spin_lock_irqsave(&musb->lock, flags);
f7f9d63e
DB		 1756 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1757 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
e47d9254 1758 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
550a7375
FB		 1759 musb->is_active = 0;
1760 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1761 spin_unlock_irqrestore(&musb->lock, flags);
1762
1763 return n;
1764}
1765
1766static ssize_t
1767musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1768{
1769 struct musb *musb = dev_to_musb(dev);
1770 unsigned long flags;
1771 unsigned long val;
1772 int vbus;
1773
1774 spin_lock_irqsave(&musb->lock, flags);
1775 val = musb->a_wait_bcon;
f7f9d63e
DB		 1776 /* FIXME get_vbus_status() is normally #defined as false...
1777 * and is effectively TUSB-specific.
1778 */
550a7375
FB		 1779 vbus = musb_platform_get_vbus_status(musb);
1780 spin_unlock_irqrestore(&musb->lock, flags);
1781
f7f9d63e 1782 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
550a7375
FB		 1783 vbus ? "on" : "off", val);
1784}
1785static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1786
550a7375
FB		 1787/* Gadget drivers can't know that a host is connected so they might want
1788 * to start SRP, but users can. This allows userspace to trigger SRP.
1789 */
1790static ssize_t
1791musb_srp_store(struct device *dev, struct device_attribute *attr,
1792 const char *buf, size_t n)
1793{
1794 struct musb *musb = dev_to_musb(dev);
1795 unsigned short srp;
1796
1797 if (sscanf(buf, "%hu", &srp) != 1
1798 || (srp != 1)) {
b3b1cc3b 1799 dev_err(dev, "SRP: Value must be 1\n");
550a7375
FB		 1800 return -EINVAL;
1801 }
1802
1803 if (srp == 1)
1804 musb_g_wakeup(musb);
1805
1806 return n;
1807}
1808static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1809
94375751
FB		 1810static struct attribute *musb_attributes[] = {
1811 &dev_attr_mode.attr,
1812 &dev_attr_vbus.attr,
94375751 1813 &dev_attr_srp.attr,
94375751
FB		 1814 NULL
1815};
1816
1817static const struct attribute_group musb_attr_group = {
1818 .attrs = musb_attributes,
1819};
1820
550a7375
FB		 1821/* Only used to provide driver mode change events */
1822static void musb_irq_work(struct work_struct *data)
1823{
1824 struct musb *musb = container_of(data, struct musb, irq_work);
550a7375 1825
e47d9254
AT		 1826 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1827 musb->xceiv_old_state = musb->xceiv->otg->state;
550a7375
FB		 1828 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1829 }
1830}
1831
ca88fc2e
DM		 1832/* Recover from babble interrupt conditions */
1833static void musb_recover_work(struct work_struct *data)
1834{
675ae763 1835 struct musb *musb = container_of(data, struct musb, recover_work.work);
d871c622 1836 int status, ret;
ca88fc2e 1837
d871c622
GC		 1838 ret = musb_platform_reset(musb);
1839 if (ret)
1840 return;
ca88fc2e
DM		 1841
1842 usb_phy_vbus_off(musb->xceiv);
675ae763 1843 usleep_range(100, 200);
ca88fc2e
DM		 1844
1845 usb_phy_vbus_on(musb->xceiv);
675ae763 1846 usleep_range(100, 200);
ca88fc2e
DM		 1847
1848 /*
d871c622
GC		 1849 * When a babble condition occurs, the musb controller
1850 * removes the session bit and the endpoint config is lost.
ca88fc2e
DM		 1851 */
1852 if (musb->dyn_fifo)
1853 status = ep_config_from_table(musb);
1854 else
1855 status = ep_config_from_hw(musb);
1856
1857 /* start the session again */
1858 if (status == 0)
1859 musb_start(musb);
1860}
1861
550a7375
FB		 1862/* --------------------------------------------------------------------------
1863 * Init support
1864 */
1865
41ac7b3a 1866static struct musb *allocate_instance(struct device *dev,
ca6d1b13 1867 struct musb_hdrc_config *config, void __iomem *mbase)
550a7375
FB		 1868{
1869 struct musb *musb;
1870 struct musb_hw_ep *ep;
1871 int epnum;
74c2e936 1872 int ret;
550a7375 1873
74c2e936
DM		 1874 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1875 if (!musb)
550a7375 1876 return NULL;
550a7375 1877
550a7375
FB		 1878 INIT_LIST_HEAD(&musb->control);
1879 INIT_LIST_HEAD(&musb->in_bulk);
1880 INIT_LIST_HEAD(&musb->out_bulk);
1881
550a7375 1882 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
f7f9d63e 1883 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
550a7375
FB		 1884 musb->mregs = mbase;
1885 musb->ctrl_base = mbase;
1886 musb->nIrq = -ENODEV;
ca6d1b13 1887 musb->config = config;
02582b92 1888 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
550a7375 1889 for (epnum = 0, ep = musb->endpoints;
ca6d1b13 1890 epnum < musb->config->num_eps;
550a7375 1891 epnum++, ep++) {
550a7375
FB		 1892 ep->musb = musb;
1893 ep->epnum = epnum;
1894 }
1895
1896 musb->controller = dev;
743411b3 1897
74c2e936
DM		 1898 ret = musb_host_alloc(musb);
1899 if (ret < 0)
1900 goto err_free;
1901
1902 dev_set_drvdata(dev, musb);
1903
550a7375 1904 return musb;
74c2e936
DM		 1905
1906err_free:
1907 return NULL;
550a7375
FB		 1908}
1909
1910static void musb_free(struct musb *musb)
1911{
1912 /* this has multiple entry modes. it handles fault cleanup after
1913 * probe(), where things may be partially set up, as well as rmmod
1914 * cleanup after everything's been de-activated.
1915 */
1916
1917#ifdef CONFIG_SYSFS
94375751 1918 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
550a7375
FB		 1919#endif
1920
97a39896
AKG		 1921 if (musb->nIrq >= 0) {
1922 if (musb->irq_wake)
1923 disable_irq_wake(musb->nIrq);
550a7375
FB		 1924 free_irq(musb->nIrq, musb);
1925 }
550a7375 1926
74c2e936 1927 musb_host_free(musb);
550a7375
FB		 1928}
1929
8ed1fb79
DM		 1930static void musb_deassert_reset(struct work_struct *work)
1931{
1932 struct musb *musb;
1933 unsigned long flags;
1934
1935 musb = container_of(work, struct musb, deassert_reset_work.work);
1936
1937 spin_lock_irqsave(&musb->lock, flags);
1938
1939 if (musb->port1_status & USB_PORT_STAT_RESET)
1940 musb_port_reset(musb, false);
1941
1942 spin_unlock_irqrestore(&musb->lock, flags);
1943}
1944
550a7375
FB		 1945/*
1946 * Perform generic per-controller initialization.
1947 *
28dd924a
SS		 1948 * @dev: the controller (already clocked, etc)
1949 * @nIrq: IRQ number
1950 * @ctrl: virtual address of controller registers,
550a7375
FB		 1951 * not yet corrected for platform-specific offsets
1952 */
41ac7b3a 1953static int
550a7375
FB		 1954musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1955{
1956 int status;
1957 struct musb *musb;
c1a7d67c 1958 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
550a7375
FB		 1959
1960 /* The driver might handle more features than the board; OK.
1961 * Fail when the board needs a feature that's not enabled.
1962 */
1963 if (!plat) {
1964 dev_dbg(dev, "no platform_data?\n");
34e2beb2
SS		 1965 status = -ENODEV;
1966 goto fail0;
550a7375 1967 }
34e2beb2 1968
550a7375 1969 /* allocate */
ca6d1b13 1970 musb = allocate_instance(dev, plat->config, ctrl);
34e2beb2
SS		 1971 if (!musb) {
1972 status = -ENOMEM;
1973 goto fail0;
1974 }
550a7375
FB		 1975
1976 spin_lock_init(&musb->lock);
550a7375 1977 musb->board_set_power = plat->set_power;
550a7375 1978 musb->min_power = plat->min_power;
f7ec9437 1979 musb->ops = plat->platform_ops;
9ad96e69 1980 musb->port_mode = plat->mode;
550a7375 1981
1b40fc57
TL		 1982 /*
1983 * Initialize the default IO functions. At least omap2430 needs
1984 * these early. We initialize the platform specific IO functions
1985 * later on.
1986 */
1987 musb_readb = musb_default_readb;
1988 musb_writeb = musb_default_writeb;
1989 musb_readw = musb_default_readw;
1990 musb_writew = musb_default_writew;
1991 musb_readl = musb_default_readl;
1992 musb_writel = musb_default_writel;
1993
3e43a072
FB		 1994 /* We need musb_read/write functions initialized for PM */
1995 pm_runtime_use_autosuspend(musb->controller);
1996 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1997 pm_runtime_irq_safe(musb->controller);
1998 pm_runtime_enable(musb->controller);
1999
84e250ff 2000 /* The musb_platform_init() call:
baef653a
PDS		 2001 * - adjusts musb->mregs
2002 * - sets the musb->isr
5ae477b0 2003 * - may initialize an integrated transceiver
721002ec 2004 * - initializes musb->xceiv, usually by otg_get_phy()
84e250ff 2005 * - stops powering VBUS
84e250ff 2006 *
7c9d440e 2007 * There are various transceiver configurations. Blackfin,
84e250ff
DB		 2008 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2009 * external/discrete ones in various flavors (twl4030 family,
2010 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
550a7375 2011 */
ea65df57 2012 status = musb_platform_init(musb);
550a7375 2013 if (status < 0)
03491761 2014 goto fail1;
34e2beb2 2015
550a7375
FB		 2016 if (!musb->isr) {
2017 status = -ENODEV;
c04352a5 2018 goto fail2;
550a7375
FB		 2019 }
2020
1b40fc57
TL		 2021 if (musb->ops->quirks)
2022 musb->io.quirks = musb->ops->quirks;
2023
d026e9c7
TL		 2024 /* At least tusb6010 has it's own offsets.. */
2025 if (musb->ops->ep_offset)
2026 musb->io.ep_offset = musb->ops->ep_offset;
2027 if (musb->ops->ep_select)
2028 musb->io.ep_select = musb->ops->ep_select;
2029
2030 /* ..and some devices use indexed offset or flat offset */
2031 if (musb->io.quirks & MUSB_INDEXED_EP) {
2032 musb->io.ep_offset = musb_indexed_ep_offset;
2033 musb->io.ep_select = musb_indexed_ep_select;
2034 } else {
2035 musb->io.ep_offset = musb_flat_ep_offset;
2036 musb->io.ep_select = musb_flat_ep_select;
2037 }
2038
8a77f05a
TL		 2039 if (musb->ops->fifo_mode)
2040 fifo_mode = musb->ops->fifo_mode;
2041 else
2042 fifo_mode = 4;
2043
1b40fc57
TL		 2044 if (musb->ops->fifo_offset)
2045 musb->io.fifo_offset = musb->ops->fifo_offset;
2046 else
2047 musb->io.fifo_offset = musb_default_fifo_offset;
2048
2049 if (musb->ops->readb)
2050 musb_readb = musb->ops->readb;
2051 if (musb->ops->writeb)
2052 musb_writeb = musb->ops->writeb;
2053 if (musb->ops->readw)
2054 musb_readw = musb->ops->readw;
2055 if (musb->ops->writew)
2056 musb_writew = musb->ops->writew;
2057 if (musb->ops->readl)
2058 musb_readl = musb->ops->readl;
2059 if (musb->ops->writel)
2060 musb_writel = musb->ops->writel;
2061
2062 if (musb->ops->read_fifo)
2063 musb->io.read_fifo = musb->ops->read_fifo;
2064 else
2065 musb->io.read_fifo = musb_default_read_fifo;
2066
2067 if (musb->ops->write_fifo)
2068 musb->io.write_fifo = musb->ops->write_fifo;
2069 else
2070 musb->io.write_fifo = musb_default_write_fifo;
2071
ffb865b1 2072 if (!musb->xceiv->io_ops) {
bf070bc1 2073 musb->xceiv->io_dev = musb->controller;
ffb865b1
HK		 2074 musb->xceiv->io_priv = musb->mregs;
2075 musb->xceiv->io_ops = &musb_ulpi_access;
2076 }
2077
c04352a5
GI		 2078 pm_runtime_get_sync(musb->controller);
2079
48054147 2080 if (use_dma && dev->dma_mask) {
66c01883 2081 musb->dma_controller = dma_controller_create(musb, musb->mregs);
48054147
SAS		 2082 if (IS_ERR(musb->dma_controller)) {
2083 status = PTR_ERR(musb->dma_controller);
2084 goto fail2_5;
2085 }
2086 }
550a7375
FB		 2087
2088 /* be sure interrupts are disabled before connecting ISR */
2089 musb_platform_disable(musb);
2090 musb_generic_disable(musb);
2091
66fadea5
SAS		 2092 /* Init IRQ workqueue before request_irq */
2093 INIT_WORK(&musb->irq_work, musb_irq_work);
675ae763 2094 INIT_DELAYED_WORK(&musb->recover_work, musb_recover_work);
8ed1fb79
DM		 2095 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2096 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
66fadea5 2097
550a7375 2098 /* setup musb parts of the core (especially endpoints) */
ca6d1b13 2099 status = musb_core_init(plat->config->multipoint
550a7375
FB		 2100 ? MUSB_CONTROLLER_MHDRC
2101 : MUSB_CONTROLLER_HDRC, musb);
2102 if (status < 0)
34e2beb2 2103 goto fail3;
550a7375 2104
f7f9d63e 2105 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
f7f9d63e 2106
550a7375 2107 /* attach to the IRQ */
427c4f33 2108 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
550a7375
FB		 2109 dev_err(dev, "request_irq %d failed!\n", nIrq);
2110 status = -ENODEV;
34e2beb2 2111 goto fail3;
550a7375
FB		 2112 }
2113 musb->nIrq = nIrq;
032ec49f 2114 /* FIXME this handles wakeup irqs wrong */
c48a5155
FB		 2115 if (enable_irq_wake(nIrq) == 0) {
2116 musb->irq_wake = 1;
550a7375 2117 device_init_wakeup(dev, 1);
c48a5155
FB		 2118 } else {
2119 musb->irq_wake = 0;
2120 }
550a7375 2121
032ec49f
FB		 2122 /* program PHY to use external vBus if required */
2123 if (plat->extvbus) {
2124 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2125 busctl |= MUSB_ULPI_USE_EXTVBUS;
2126 musb_write_ulpi_buscontrol(musb->mregs, busctl);
550a7375 2127 }
550a7375 2128
e5615112
GI		 2129 if (musb->xceiv->otg->default_a) {
2130 MUSB_HST_MODE(musb);
e47d9254 2131 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
e5615112
GI		 2132 } else {
2133 MUSB_DEV_MODE(musb);
e47d9254 2134 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
e5615112 2135 }
550a7375 2136
6c5f6a6f
DM		 2137 switch (musb->port_mode) {
2138 case MUSB_PORT_MODE_HOST:
2139 status = musb_host_setup(musb, plat->power);
2df6761e
FB		 2140 if (status < 0)
2141 goto fail3;
2142 status = musb_platform_set_mode(musb, MUSB_HOST);
6c5f6a6f
DM		 2143 break;
2144 case MUSB_PORT_MODE_GADGET:
2145 status = musb_gadget_setup(musb);
2df6761e
FB		 2146 if (status < 0)
2147 goto fail3;
2148 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
6c5f6a6f
DM		 2149 break;
2150 case MUSB_PORT_MODE_DUAL_ROLE:
2151 status = musb_host_setup(musb, plat->power);
2152 if (status < 0)
2153 goto fail3;
2154 status = musb_gadget_setup(musb);
2df6761e 2155 if (status) {
0d2dd7ea 2156 musb_host_cleanup(musb);
2df6761e
FB		 2157 goto fail3;
2158 }
2159 status = musb_platform_set_mode(musb, MUSB_OTG);
6c5f6a6f
DM		 2160 break;
2161 default:
2162 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2163 break;
2164 }
550a7375 2165
461972d8 2166 if (status < 0)
34e2beb2 2167 goto fail3;
550a7375 2168
7f7f9e2a
FB		 2169 status = musb_init_debugfs(musb);
2170 if (status < 0)
b0f9da7e 2171 goto fail4;
7f7f9e2a 2172
94375751 2173 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
28c2c51c 2174 if (status)
b0f9da7e 2175 goto fail5;
550a7375 2176
c04352a5
GI		 2177 pm_runtime_put(musb->controller);
2178
28c2c51c 2179 return 0;
550a7375 2180
b0f9da7e
FB		 2181fail5:
2182 musb_exit_debugfs(musb);
2183
34e2beb2 2184fail4:
032ec49f 2185 musb_gadget_cleanup(musb);
0d2dd7ea 2186 musb_host_cleanup(musb);
34e2beb2
SS		 2187
2188fail3:
66fadea5 2189 cancel_work_sync(&musb->irq_work);
675ae763 2190 cancel_delayed_work_sync(&musb->recover_work);
8ed1fb79
DM		 2191 cancel_delayed_work_sync(&musb->finish_resume_work);
2192 cancel_delayed_work_sync(&musb->deassert_reset_work);
f3ce4d5b
SAS		 2193 if (musb->dma_controller)
2194 dma_controller_destroy(musb->dma_controller);
48054147 2195fail2_5:
c04352a5
GI		 2196 pm_runtime_put_sync(musb->controller);
2197
2198fail2:
34e2beb2
SS		 2199 if (musb->irq_wake)
2200 device_init_wakeup(dev, 0);
550a7375 2201 musb_platform_exit(musb);
28c2c51c 2202
34e2beb2 2203fail1:
681d1e87 2204 pm_runtime_disable(musb->controller);
34e2beb2
SS		 2205 dev_err(musb->controller,
2206 "musb_init_controller failed with status %d\n", status);
2207
28c2c51c
FB		 2208 musb_free(musb);
2209
34e2beb2
SS		 2210fail0:
2211
28c2c51c
FB		 2212 return status;
2213
550a7375
FB		 2214}
2215
2216/*-------------------------------------------------------------------------*/
2217
2218/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2219 * bridge to a platform device; this driver then suffices.
2220 */
41ac7b3a 2221static int musb_probe(struct platform_device *pdev)
550a7375
FB		 2222{
2223 struct device *dev = &pdev->dev;
fcf173e4 2224 int irq = platform_get_irq_byname(pdev, "mc");
550a7375
FB		 2225 struct resource *iomem;
2226 void __iomem *base;
2227
1f79b26c 2228 if (irq <= 0)
550a7375
FB		 2229 return -ENODEV;
2230
1f79b26c 2231 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b42f7f30
FB		 2232 base = devm_ioremap_resource(dev, iomem);
2233 if (IS_ERR(base))
2234 return PTR_ERR(base);
550a7375 2235
b42f7f30 2236 return musb_init_controller(dev, irq, base);
550a7375
FB		 2237}
2238
fb4e98ab 2239static int musb_remove(struct platform_device *pdev)
550a7375 2240{
8d2421e6
AKG		 2241 struct device *dev = &pdev->dev;
2242 struct musb *musb = dev_to_musb(dev);
550a7375
FB		 2243
2244 /* this gets called on rmmod.
2245 * - Host mode: host may still be active
2246 * - Peripheral mode: peripheral is deactivated (or never-activated)
2247 * - OTG mode: both roles are deactivated (or never-activated)
2248 */
7f7f9e2a 2249 musb_exit_debugfs(musb);
550a7375 2250 musb_shutdown(pdev);
461972d8 2251
8d1aad74
SAS		 2252 if (musb->dma_controller)
2253 dma_controller_destroy(musb->dma_controller);
2254
66fadea5 2255 cancel_work_sync(&musb->irq_work);
675ae763 2256 cancel_delayed_work_sync(&musb->recover_work);
8ed1fb79
DM		 2257 cancel_delayed_work_sync(&musb->finish_resume_work);
2258 cancel_delayed_work_sync(&musb->deassert_reset_work);
550a7375 2259 musb_free(musb);
8d2421e6 2260 device_init_wakeup(dev, 0);
550a7375
FB		 2261 return 0;
2262}
2263
2264#ifdef CONFIG_PM
2265
3c8a5fcc 2266static void musb_save_context(struct musb *musb)
4f712e01
AKG		 2267{
2268 int i;
2269 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2270 void __iomem *epio;
4f712e01 2271
032ec49f
FB		 2272 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2273 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2274 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
7421107b 2275 musb->context.power = musb_readb(musb_base, MUSB_POWER);
7421107b
FB		 2276 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2277 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2278 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
4f712e01 2279
ae9b2ad2 2280 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2281 struct musb_hw_ep *hw_ep;
2282
2283 hw_ep = &musb->endpoints[i];
2284 if (!hw_ep)
2285 continue;
2286
2287 epio = hw_ep->regs;
2288 if (!epio)
2289 continue;
2290
ea737554 2291 musb_writeb(musb_base, MUSB_INDEX, i);
7421107b 2292 musb->context.index_regs[i].txmaxp =
ae9b2ad2 2293 musb_readw(epio, MUSB_TXMAXP);
7421107b 2294 musb->context.index_regs[i].txcsr =
ae9b2ad2 2295 musb_readw(epio, MUSB_TXCSR);
7421107b 2296 musb->context.index_regs[i].rxmaxp =
ae9b2ad2 2297 musb_readw(epio, MUSB_RXMAXP);
7421107b 2298 musb->context.index_regs[i].rxcsr =
ae9b2ad2 2299 musb_readw(epio, MUSB_RXCSR);
4f712e01
AKG		 2300
2301 if (musb->dyn_fifo) {
7421107b 2302 musb->context.index_regs[i].txfifoadd =
4f712e01 2303 musb_read_txfifoadd(musb_base);
7421107b 2304 musb->context.index_regs[i].rxfifoadd =
4f712e01 2305 musb_read_rxfifoadd(musb_base);
7421107b 2306 musb->context.index_regs[i].txfifosz =
4f712e01 2307 musb_read_txfifosz(musb_base);
7421107b 2308 musb->context.index_regs[i].rxfifosz =
4f712e01
AKG		 2309 musb_read_rxfifosz(musb_base);
2310 }
032ec49f
FB		 2311
2312 musb->context.index_regs[i].txtype =
2313 musb_readb(epio, MUSB_TXTYPE);
2314 musb->context.index_regs[i].txinterval =
2315 musb_readb(epio, MUSB_TXINTERVAL);
2316 musb->context.index_regs[i].rxtype =
2317 musb_readb(epio, MUSB_RXTYPE);
2318 musb->context.index_regs[i].rxinterval =
2319 musb_readb(epio, MUSB_RXINTERVAL);
2320
2321 musb->context.index_regs[i].txfunaddr =
2322 musb_read_txfunaddr(musb_base, i);
2323 musb->context.index_regs[i].txhubaddr =
2324 musb_read_txhubaddr(musb_base, i);
2325 musb->context.index_regs[i].txhubport =
2326 musb_read_txhubport(musb_base, i);
2327
2328 musb->context.index_regs[i].rxfunaddr =
2329 musb_read_rxfunaddr(musb_base, i);
2330 musb->context.index_regs[i].rxhubaddr =
2331 musb_read_rxhubaddr(musb_base, i);
2332 musb->context.index_regs[i].rxhubport =
2333 musb_read_rxhubport(musb_base, i);
4f712e01 2334 }
4f712e01
AKG		 2335}
2336
3c8a5fcc 2337static void musb_restore_context(struct musb *musb)
4f712e01
AKG		 2338{
2339 int i;
2340 void __iomem *musb_base = musb->mregs;
2341 void __iomem *ep_target_regs;
ae9b2ad2 2342 void __iomem *epio;
33f8d75f 2343 u8 power;
4f712e01 2344
032ec49f
FB		 2345 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2346 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2347 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
33f8d75f
RQ		 2348
2349 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2350 power = musb_readb(musb_base, MUSB_POWER);
2351 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2352 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2353 power |= musb->context.power;
2354 musb_writeb(musb_base, MUSB_POWER, power);
2355
b18d26f6 2356 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
af5ec14d 2357 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
7421107b
FB		 2358 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2359 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
4f712e01 2360
ae9b2ad2 2361 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2362 struct musb_hw_ep *hw_ep;
2363
2364 hw_ep = &musb->endpoints[i];
2365 if (!hw_ep)
2366 continue;
2367
2368 epio = hw_ep->regs;
2369 if (!epio)
2370 continue;
2371
ea737554 2372 musb_writeb(musb_base, MUSB_INDEX, i);
ae9b2ad2 2373 musb_writew(epio, MUSB_TXMAXP,
7421107b 2374 musb->context.index_regs[i].txmaxp);
ae9b2ad2 2375 musb_writew(epio, MUSB_TXCSR,
7421107b 2376 musb->context.index_regs[i].txcsr);
ae9b2ad2 2377 musb_writew(epio, MUSB_RXMAXP,
7421107b 2378 musb->context.index_regs[i].rxmaxp);
ae9b2ad2 2379 musb_writew(epio, MUSB_RXCSR,
7421107b 2380 musb->context.index_regs[i].rxcsr);
4f712e01
AKG		 2381
2382 if (musb->dyn_fifo) {
2383 musb_write_txfifosz(musb_base,
7421107b 2384 musb->context.index_regs[i].txfifosz);
4f712e01 2385 musb_write_rxfifosz(musb_base,
7421107b 2386 musb->context.index_regs[i].rxfifosz);
4f712e01 2387 musb_write_txfifoadd(musb_base,
7421107b 2388 musb->context.index_regs[i].txfifoadd);
4f712e01 2389 musb_write_rxfifoadd(musb_base,
7421107b 2390 musb->context.index_regs[i].rxfifoadd);
4f712e01
AKG		 2391 }
2392
032ec49f 2393 musb_writeb(epio, MUSB_TXTYPE,
7421107b 2394 musb->context.index_regs[i].txtype);
032ec49f 2395 musb_writeb(epio, MUSB_TXINTERVAL,
7421107b 2396 musb->context.index_regs[i].txinterval);
032ec49f 2397 musb_writeb(epio, MUSB_RXTYPE,
7421107b 2398 musb->context.index_regs[i].rxtype);
032ec49f 2399 musb_writeb(epio, MUSB_RXINTERVAL,
4f712e01 2400
032ec49f
FB		 2401 musb->context.index_regs[i].rxinterval);
2402 musb_write_txfunaddr(musb_base, i,
7421107b 2403 musb->context.index_regs[i].txfunaddr);
032ec49f 2404 musb_write_txhubaddr(musb_base, i,
7421107b 2405 musb->context.index_regs[i].txhubaddr);
032ec49f 2406 musb_write_txhubport(musb_base, i,
7421107b 2407 musb->context.index_regs[i].txhubport);
4f712e01 2408
032ec49f
FB		 2409 ep_target_regs =
2410 musb_read_target_reg_base(i, musb_base);
4f712e01 2411
032ec49f 2412 musb_write_rxfunaddr(ep_target_regs,
7421107b 2413 musb->context.index_regs[i].rxfunaddr);
032ec49f 2414 musb_write_rxhubaddr(ep_target_regs,
7421107b 2415 musb->context.index_regs[i].rxhubaddr);
032ec49f 2416 musb_write_rxhubport(ep_target_regs,
7421107b 2417 musb->context.index_regs[i].rxhubport);
4f712e01 2418 }
3c5fec75 2419 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
4f712e01
AKG		 2420}
2421
48fea965 2422static int musb_suspend(struct device *dev)
550a7375 2423{
8220796d 2424 struct musb *musb = dev_to_musb(dev);
550a7375 2425 unsigned long flags;
550a7375 2426
550a7375
FB		 2427 spin_lock_irqsave(&musb->lock, flags);
2428
2429 if (is_peripheral_active(musb)) {
2430 /* FIXME force disconnect unless we know USB will wake
2431 * the system up quickly enough to respond ...
2432 */
2433 } else if (is_host_active(musb)) {
2434 /* we know all the children are suspended; sometimes
2435 * they will even be wakeup-enabled.
2436 */
2437 }
2438
c338412b
DM		 2439 musb_save_context(musb);
2440
550a7375
FB		 2441 spin_unlock_irqrestore(&musb->lock, flags);
2442 return 0;
2443}
2444
3e87d9a3 2445static int musb_resume(struct device *dev)
550a7375 2446{
c338412b 2447 struct musb *musb = dev_to_musb(dev);
b87fd2f7
SAS		 2448 u8 devctl;
2449 u8 mask;
c338412b
DM		 2450
2451 /*
2452 * For static cmos like DaVinci, register values were preserved
0ec8fd70
KK		 2453 * unless for some reason the whole soc powered down or the USB
2454 * module got reset through the PSC (vs just being disabled).
c338412b
DM		 2455 *
2456 * For the DSPS glue layer though, a full register restore has to
2457 * be done. As it shouldn't harm other platforms, we do it
2458 * unconditionally.
550a7375 2459 */
c338412b
DM		 2460
2461 musb_restore_context(musb);
2462
b87fd2f7
SAS		 2463 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2464 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2465 if ((devctl & mask) != (musb->context.devctl & mask))
2466 musb->port1_status = 0;
baadd52f
SAS		 2467 if (musb->need_finish_resume) {
2468 musb->need_finish_resume = 0;
2469 schedule_delayed_work(&musb->finish_resume_work,
2470 msecs_to_jiffies(20));
2471 }
a1fc1920
SAS		 2472
2473 /*
2474 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2475 * out of suspend
2476 */
2477 pm_runtime_disable(dev);
2478 pm_runtime_set_active(dev);
2479 pm_runtime_enable(dev);
550a7375
FB		 2480 return 0;
2481}
2482
7acc6197
HH		 2483static int musb_runtime_suspend(struct device *dev)
2484{
2485 struct musb *musb = dev_to_musb(dev);
2486
2487 musb_save_context(musb);
2488
2489 return 0;
2490}
2491
2492static int musb_runtime_resume(struct device *dev)
2493{
2494 struct musb *musb = dev_to_musb(dev);
2495 static int first = 1;
2496
2497 /*
2498 * When pm_runtime_get_sync called for the first time in driver
2499 * init, some of the structure is still not initialized which is
2500 * used in restore function. But clock needs to be
2501 * enabled before any register access, so
2502 * pm_runtime_get_sync has to be called.
2503 * Also context restore without save does not make
2504 * any sense
2505 */
2506 if (!first)
2507 musb_restore_context(musb);
2508 first = 0;
2509
9298b4aa
BL		 2510 if (musb->need_finish_resume) {
2511 musb->need_finish_resume = 0;
2512 schedule_delayed_work(&musb->finish_resume_work,
2513 msecs_to_jiffies(20));
2514 }
2515
7acc6197
HH		 2516 return 0;
2517}
2518
47145210 2519static const struct dev_pm_ops musb_dev_pm_ops = {
48fea965 2520 .suspend = musb_suspend,
3e87d9a3 2521 .resume = musb_resume,
7acc6197
HH		 2522 .runtime_suspend = musb_runtime_suspend,
2523 .runtime_resume = musb_runtime_resume,
48fea965
MD		 2524};
2525
2526#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
550a7375 2527#else
48fea965 2528#define MUSB_DEV_PM_OPS NULL
550a7375
FB		 2529#endif
2530
2531static struct platform_driver musb_driver = {
2532 .driver = {
2533 .name = (char *)musb_driver_name,
2534 .bus = &platform_bus_type,
48fea965 2535 .pm = MUSB_DEV_PM_OPS,
550a7375 2536 },
e9e8c85e 2537 .probe = musb_probe,
7690417d 2538 .remove = musb_remove,
550a7375 2539 .shutdown = musb_shutdown,
550a7375
FB		 2540};
2541
89f836a8 2542module_platform_driver(musb_driver);
Linux kernel - Deliverables
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