[deliverable/linux.git] / drivers / usb / musb / musb_cppi41.c

#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/sizes.h>
#include <linux/platform_device.h>
#include <linux/of.h>

#include "musb_core.h"

#define RNDIS_REG(x) (0x80 + ((x - 1) * 4))

#define EP_MODE_AUTOREG_NONE		0
#define EP_MODE_AUTOREG_ALL_NEOP	1
#define EP_MODE_AUTOREG_ALWAYS		3

#define EP_MODE_DMA_TRANSPARENT		0
#define EP_MODE_DMA_RNDIS		1
#define EP_MODE_DMA_GEN_RNDIS		3

#define USB_CTRL_TX_MODE	0x70
#define USB_CTRL_RX_MODE	0x74
#define USB_CTRL_AUTOREQ	0xd0
#define USB_TDOWN		0xd8

struct cppi41_dma_channel {
	struct dma_channel channel;
	struct cppi41_dma_controller *controller;
	struct musb_hw_ep *hw_ep;
	struct dma_chan *dc;
	dma_cookie_t cookie;
	u8 port_num;
	u8 is_tx;
	u8 is_allocated;
	u8 usb_toggle;

	dma_addr_t buf_addr;
	u32 total_len;
	u32 prog_len;
	u32 transferred;
	u32 packet_sz;
};

#define MUSB_DMA_NUM_CHANNELS 15

struct cppi41_dma_controller {
	struct dma_controller controller;
	struct cppi41_dma_channel rx_channel[MUSB_DMA_NUM_CHANNELS];
	struct cppi41_dma_channel tx_channel[MUSB_DMA_NUM_CHANNELS];
	struct musb *musb;
	u32 rx_mode;
	u32 tx_mode;
	u32 auto_req;
};

static void save_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
{
	u16 csr;
	u8 toggle;

	if (cppi41_channel->is_tx)
		return;
	if (!is_host_active(cppi41_channel->controller->musb))
		return;

	csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
	toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;

	cppi41_channel->usb_toggle = toggle;
}

static void update_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
{
	u16 csr;
	u8 toggle;

	if (cppi41_channel->is_tx)
		return;
	if (!is_host_active(cppi41_channel->controller->musb))
		return;

	csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
	toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;

	/*
	 * AM335x Advisory 1.0.13: Due to internal synchronisation error the
	 * data toggle may reset from DATA1 to DATA0 during receiving data from
	 * more than one endpoint.
	 */
	if (!toggle && toggle == cppi41_channel->usb_toggle) {
		csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE;
		musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr);
		dev_dbg(cppi41_channel->controller->musb->controller,
				"Restoring DATA1 toggle.\n");
	}

	cppi41_channel->usb_toggle = toggle;
}

static void cppi41_dma_callback(void *private_data)
{
	struct dma_channel *channel = private_data;
	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
	struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
	struct musb *musb = hw_ep->musb;
	unsigned long flags;
	struct dma_tx_state txstate;
	u32 transferred;

	spin_lock_irqsave(&musb->lock, flags);

	dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie,
			&txstate);
	transferred = cppi41_channel->prog_len - txstate.residue;
	cppi41_channel->transferred += transferred;

	dev_dbg(musb->controller, "DMA transfer done on hw_ep=%d bytes=%d/%d\n",
		hw_ep->epnum, cppi41_channel->transferred,
		cppi41_channel->total_len);

	update_rx_toggle(cppi41_channel);

	if (cppi41_channel->transferred == cppi41_channel->total_len ||
			transferred < cppi41_channel->packet_sz) {

		/* done, complete */
		cppi41_channel->channel.actual_len =
			cppi41_channel->transferred;
		cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
		musb_dma_completion(musb, hw_ep->epnum, cppi41_channel->is_tx);
	} else {
		/* next iteration, reload */
		struct dma_chan *dc = cppi41_channel->dc;
		struct dma_async_tx_descriptor *dma_desc;
		enum dma_transfer_direction direction;
		u16 csr;
		u32 remain_bytes;
		void __iomem *epio = cppi41_channel->hw_ep->regs;

		cppi41_channel->buf_addr += cppi41_channel->packet_sz;

		remain_bytes = cppi41_channel->total_len;
		remain_bytes -= cppi41_channel->transferred;
		remain_bytes = min(remain_bytes, cppi41_channel->packet_sz);
		cppi41_channel->prog_len = remain_bytes;

		direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV
			: DMA_DEV_TO_MEM;
		dma_desc = dmaengine_prep_slave_single(dc,
				cppi41_channel->buf_addr,
				remain_bytes,
				direction,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
		if (WARN_ON(!dma_desc))
			return;

		dma_desc->callback = cppi41_dma_callback;
		dma_desc->callback_param = channel;
		cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
		dma_async_issue_pending(dc);

		if (!cppi41_channel->is_tx) {
			csr = musb_readw(epio, MUSB_RXCSR);
			csr |= MUSB_RXCSR_H_REQPKT;
			musb_writew(epio, MUSB_RXCSR, csr);
		}
	}
	spin_unlock_irqrestore(&musb->lock, flags);
}

static u32 update_ep_mode(unsigned ep, unsigned mode, u32 old)
{
	unsigned shift;

	shift = (ep - 1) * 2;
	old &= ~(3 << shift);
	old |= mode << shift;
	return old;
}

static void cppi41_set_dma_mode(struct cppi41_dma_channel *cppi41_channel,
		unsigned mode)
{
	struct cppi41_dma_controller *controller = cppi41_channel->controller;
	u32 port;
	u32 new_mode;
	u32 old_mode;

	if (cppi41_channel->is_tx)
		old_mode = controller->tx_mode;
	else
		old_mode = controller->rx_mode;
	port = cppi41_channel->port_num;
	new_mode = update_ep_mode(port, mode, old_mode);

	if (new_mode == old_mode)
		return;
	if (cppi41_channel->is_tx) {
		controller->tx_mode = new_mode;
		musb_writel(controller->musb->ctrl_base, USB_CTRL_TX_MODE,
				new_mode);
	} else {
		controller->rx_mode = new_mode;
		musb_writel(controller->musb->ctrl_base, USB_CTRL_RX_MODE,
				new_mode);
	}
}

static void cppi41_set_autoreq_mode(struct cppi41_dma_channel *cppi41_channel,
		unsigned mode)
{
	struct cppi41_dma_controller *controller = cppi41_channel->controller;
	u32 port;
	u32 new_mode;
	u32 old_mode;

	old_mode = controller->auto_req;
	port = cppi41_channel->port_num;
	new_mode = update_ep_mode(port, mode, old_mode);

	if (new_mode == old_mode)
		return;
	controller->auto_req = new_mode;
	musb_writel(controller->musb->ctrl_base, USB_CTRL_AUTOREQ, new_mode);
}

static bool cppi41_configure_channel(struct dma_channel *channel,
				u16 packet_sz, u8 mode,
				dma_addr_t dma_addr, u32 len)
{
	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
	struct dma_chan *dc = cppi41_channel->dc;
	struct dma_async_tx_descriptor *dma_desc;
	enum dma_transfer_direction direction;
	struct musb *musb = cppi41_channel->controller->musb;
	unsigned use_gen_rndis = 0;

	dev_dbg(musb->controller,
		"configure ep%d/%x packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
		cppi41_channel->port_num, RNDIS_REG(cppi41_channel->port_num),
		packet_sz, mode, (unsigned long long) dma_addr,
		len, cppi41_channel->is_tx);

	cppi41_channel->buf_addr = dma_addr;
	cppi41_channel->total_len = len;
	cppi41_channel->transferred = 0;
	cppi41_channel->packet_sz = packet_sz;

	/*
	 * Due to AM335x' Advisory 1.0.13 we are not allowed to transfer more
	 * than max packet size at a time.
	 */
	if (cppi41_channel->is_tx)
		use_gen_rndis = 1;

	if (use_gen_rndis) {
		/* RNDIS mode */
		if (len > packet_sz) {
			musb_writel(musb->ctrl_base,
				RNDIS_REG(cppi41_channel->port_num), len);
			/* gen rndis */
			cppi41_set_dma_mode(cppi41_channel,
					EP_MODE_DMA_GEN_RNDIS);

			/* auto req */
			cppi41_set_autoreq_mode(cppi41_channel,
					EP_MODE_AUTOREG_ALL_NEOP);
		} else {
			musb_writel(musb->ctrl_base,
					RNDIS_REG(cppi41_channel->port_num), 0);
			cppi41_set_dma_mode(cppi41_channel,
					EP_MODE_DMA_TRANSPARENT);
			cppi41_set_autoreq_mode(cppi41_channel,
					EP_MODE_AUTOREG_NONE);
		}
	} else {
		/* fallback mode */
		cppi41_set_dma_mode(cppi41_channel, EP_MODE_DMA_TRANSPARENT);
		cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREG_NONE);
		len = min_t(u32, packet_sz, len);
	}
	cppi41_channel->prog_len = len;
	direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
	dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction,
			DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	if (!dma_desc)
		return false;

	dma_desc->callback = cppi41_dma_callback;
	dma_desc->callback_param = channel;
	cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);

	save_rx_toggle(cppi41_channel);
	dma_async_issue_pending(dc);
	return true;
}

static struct dma_channel *cppi41_dma_channel_allocate(struct dma_controller *c,
				struct musb_hw_ep *hw_ep, u8 is_tx)
{
	struct cppi41_dma_controller *controller = container_of(c,
			struct cppi41_dma_controller, controller);
	struct cppi41_dma_channel *cppi41_channel = NULL;
	u8 ch_num = hw_ep->epnum - 1;

	if (ch_num >= MUSB_DMA_NUM_CHANNELS)
		return NULL;

	if (is_tx)
		cppi41_channel = &controller->tx_channel[ch_num];
	else
		cppi41_channel = &controller->rx_channel[ch_num];

	if (!cppi41_channel->dc)
		return NULL;

	if (cppi41_channel->is_allocated)
		return NULL;

	cppi41_channel->hw_ep = hw_ep;
	cppi41_channel->is_allocated = 1;

	return &cppi41_channel->channel;
}

static void cppi41_dma_channel_release(struct dma_channel *channel)
{
	struct cppi41_dma_channel *cppi41_channel = channel->private_data;

	if (cppi41_channel->is_allocated) {
		cppi41_channel->is_allocated = 0;
		channel->status = MUSB_DMA_STATUS_FREE;
		channel->actual_len = 0;
	}
}

static int cppi41_dma_channel_program(struct dma_channel *channel,
				u16 packet_sz, u8 mode,
				dma_addr_t dma_addr, u32 len)
{
	int ret;

	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
		channel->status == MUSB_DMA_STATUS_BUSY);

	channel->status = MUSB_DMA_STATUS_BUSY;
	channel->actual_len = 0;
	ret = cppi41_configure_channel(channel, packet_sz, mode, dma_addr, len);
	if (!ret)
		channel->status = MUSB_DMA_STATUS_FREE;

	return ret;
}

static int cppi41_is_compatible(struct dma_channel *channel, u16 maxpacket,
		void *buf, u32 length)
{
	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
	struct cppi41_dma_controller *controller = cppi41_channel->controller;
	struct musb *musb = controller->musb;

	if (is_host_active(musb)) {
		WARN_ON(1);
		return 1;
	}
	return 0;
}

static int cppi41_dma_channel_abort(struct dma_channel *channel)
{
	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
	struct cppi41_dma_controller *controller = cppi41_channel->controller;
	struct musb *musb = controller->musb;
	void __iomem *epio = cppi41_channel->hw_ep->regs;
	int tdbit;
	int ret;
	unsigned is_tx;
	u16 csr;

	is_tx = cppi41_channel->is_tx;
	dev_dbg(musb->controller, "abort channel=%d, is_tx=%d\n",
			cppi41_channel->port_num, is_tx);

	if (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)
		return 0;

	if (is_tx) {
		csr = musb_readw(epio, MUSB_TXCSR);
		csr &= ~MUSB_TXCSR_DMAENAB;
		musb_writew(epio, MUSB_TXCSR, csr);
	} else {
		csr = musb_readw(epio, MUSB_RXCSR);
		csr &= ~(MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_DMAENAB);
		musb_writew(epio, MUSB_RXCSR, csr);

		csr = musb_readw(epio, MUSB_RXCSR);
		if (csr & MUSB_RXCSR_RXPKTRDY) {
			csr |= MUSB_RXCSR_FLUSHFIFO;
			musb_writew(epio, MUSB_RXCSR, csr);
			musb_writew(epio, MUSB_RXCSR, csr);
		}
	}

	tdbit = 1 << cppi41_channel->port_num;
	if (is_tx)
		tdbit <<= 16;

	do {
		musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
		ret = dmaengine_terminate_all(cppi41_channel->dc);
	} while (ret == -EAGAIN);

	musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);

	if (is_tx) {
		csr = musb_readw(epio, MUSB_TXCSR);
		if (csr & MUSB_TXCSR_TXPKTRDY) {
			csr |= MUSB_TXCSR_FLUSHFIFO;
			musb_writew(epio, MUSB_TXCSR, csr);
		}
	}

	cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
	return 0;
}

static void cppi41_release_all_dma_chans(struct cppi41_dma_controller *ctrl)
{
	struct dma_chan *dc;
	int i;

	for (i = 0; i < MUSB_DMA_NUM_CHANNELS; i++) {
		dc = ctrl->tx_channel[i].dc;
		if (dc)
			dma_release_channel(dc);
		dc = ctrl->rx_channel[i].dc;
		if (dc)
			dma_release_channel(dc);
	}
}

static void cppi41_dma_controller_stop(struct cppi41_dma_controller *controller)
{
	cppi41_release_all_dma_chans(controller);
}

static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
{
	struct musb *musb = controller->musb;
	struct device *dev = musb->controller;
	struct device_node *np = dev->of_node;
	struct cppi41_dma_channel *cppi41_channel;
	int count;
	int i;
	int ret;

	count = of_property_count_strings(np, "dma-names");
	if (count < 0)
		return count;

	for (i = 0; i < count; i++) {
		struct dma_chan *dc;
		struct dma_channel *musb_dma;
		const char *str;
		unsigned is_tx;
		unsigned int port;

		ret = of_property_read_string_index(np, "dma-names", i, &str);
		if (ret)
			goto err;
		if (!strncmp(str, "tx", 2))
			is_tx = 1;
		else if (!strncmp(str, "rx", 2))
			is_tx = 0;
		else {
			dev_err(dev, "Wrong dmatype %s\n", str);
			goto err;
		}
		ret = kstrtouint(str + 2, 0, &port);
		if (ret)
			goto err;

		if (port > MUSB_DMA_NUM_CHANNELS || !port)
			goto err;
		if (is_tx)
			cppi41_channel = &controller->tx_channel[port - 1];
		else
			cppi41_channel = &controller->rx_channel[port - 1];

		cppi41_channel->controller = controller;
		cppi41_channel->port_num = port;
		cppi41_channel->is_tx = is_tx;

		musb_dma = &cppi41_channel->channel;
		musb_dma->private_data = cppi41_channel;
		musb_dma->status = MUSB_DMA_STATUS_FREE;
		musb_dma->max_len = SZ_4M;

		dc = dma_request_slave_channel(dev, str);
		if (!dc) {
			dev_err(dev, "Falied to request %s.\n", str);
			goto err;
		}
		cppi41_channel->dc = dc;
	}
	return 0;
err:
	cppi41_release_all_dma_chans(controller);
	return -EINVAL;
}

void dma_controller_destroy(struct dma_controller *c)
{
	struct cppi41_dma_controller *controller = container_of(c,
			struct cppi41_dma_controller, controller);

	cppi41_dma_controller_stop(controller);
	kfree(controller);
}

struct dma_controller *dma_controller_create(struct musb *musb,
					void __iomem *base)
{
	struct cppi41_dma_controller *controller;
	int ret;

	if (!musb->controller->of_node) {
		dev_err(musb->controller, "Need DT for the DMA engine.\n");
		return NULL;
	}

	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
	if (!controller)
		goto kzalloc_fail;

	controller->musb = musb;

	controller->controller.channel_alloc = cppi41_dma_channel_allocate;
	controller->controller.channel_release = cppi41_dma_channel_release;
	controller->controller.channel_program = cppi41_dma_channel_program;
	controller->controller.channel_abort = cppi41_dma_channel_abort;
	controller->controller.is_compatible = cppi41_is_compatible;

	ret = cppi41_dma_controller_start(controller);
	if (ret)
		goto plat_get_fail;
	return &controller->controller;

plat_get_fail:
	kfree(controller);
kzalloc_fail:
	return NULL;
}
Commit	Line	Data
9b3452d1 SAS	1	#include <linux/device.h>
	2	#include <linux/dma-mapping.h>
	3	#include <linux/dmaengine.h>
	4	#include <linux/sizes.h>
	5	#include <linux/platform_device.h>
	6	#include <linux/of.h>
	7
	8	#include "musb_core.h"
	9
	10	#define RNDIS_REG(x) (0x80 + ((x - 1) * 4))
	11
	12	#define EP_MODE_AUTOREG_NONE 0
	13	#define EP_MODE_AUTOREG_ALL_NEOP 1
	14	#define EP_MODE_AUTOREG_ALWAYS 3
	15
	16	#define EP_MODE_DMA_TRANSPARENT 0
	17	#define EP_MODE_DMA_RNDIS 1
	18	#define EP_MODE_DMA_GEN_RNDIS 3
	19
	20	#define USB_CTRL_TX_MODE 0x70
	21	#define USB_CTRL_RX_MODE 0x74
	22	#define USB_CTRL_AUTOREQ 0xd0
	23	#define USB_TDOWN 0xd8
	24
	25	struct cppi41_dma_channel {
	26	struct dma_channel channel;
	27	struct cppi41_dma_controller *controller;
	28	struct musb_hw_ep *hw_ep;
	29	struct dma_chan *dc;
	30	dma_cookie_t cookie;
	31	u8 port_num;
	32	u8 is_tx;
	33	u8 is_allocated;
	34	u8 usb_toggle;
	35
	36	dma_addr_t buf_addr;
	37	u32 total_len;
	38	u32 prog_len;
	39	u32 transferred;
	40	u32 packet_sz;
	41	};
	42
	43	#define MUSB_DMA_NUM_CHANNELS 15
	44
	45	struct cppi41_dma_controller {
	46	struct dma_controller controller;
	47	struct cppi41_dma_channel rx_channel[MUSB_DMA_NUM_CHANNELS];
	48	struct cppi41_dma_channel tx_channel[MUSB_DMA_NUM_CHANNELS];
	49	struct musb *musb;
	50	u32 rx_mode;
	51	u32 tx_mode;
	52	u32 auto_req;
	53	};
	54
	55	static void save_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
	56	{
	57	u16 csr;
	58	u8 toggle;
	59
	60	if (cppi41_channel->is_tx)
	61	return;
	62	if (!is_host_active(cppi41_channel->controller->musb))
	63	return;
	64
65	csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
66	toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
67
68	cppi41_channel->usb_toggle = toggle;
69	}
70
71	static void update_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
72	{
73	u16 csr;
74	u8 toggle;
75
76	if (cppi41_channel->is_tx)
77	return;
78	if (!is_host_active(cppi41_channel->controller->musb))
79	return;
80
81	csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
82	toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
83
84	/*
85	* AM335x Advisory 1.0.13: Due to internal synchronisation error the
86	* data toggle may reset from DATA1 to DATA0 during receiving data from
87	* more than one endpoint.
88	*/
89	if (!toggle && toggle == cppi41_channel->usb_toggle) {
90	csr \|= MUSB_RXCSR_H_DATATOGGLE \| MUSB_RXCSR_H_WR_DATATOGGLE;
91	musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr);
92	dev_dbg(cppi41_channel->controller->musb->controller,
93	"Restoring DATA1 toggle.\n");
94	}
95
96	cppi41_channel->usb_toggle = toggle;
97	}
98
99	static void cppi41_dma_callback(void *private_data)
100	{
101	struct dma_channel *channel = private_data;
102	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
103	struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
104	struct musb *musb = hw_ep->musb;
105	unsigned long flags;
106	struct dma_tx_state txstate;
107	u32 transferred;
108
109	spin_lock_irqsave(&musb->lock, flags);
110
111	dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie,
112	&txstate);
113	transferred = cppi41_channel->prog_len - txstate.residue;
114	cppi41_channel->transferred += transferred;
115
116	dev_dbg(musb->controller, "DMA transfer done on hw_ep=%d bytes=%d/%d\n",
117	hw_ep->epnum, cppi41_channel->transferred,
118	cppi41_channel->total_len);
119
120	update_rx_toggle(cppi41_channel);
121
122	if (cppi41_channel->transferred == cppi41_channel->total_len \|\|
123	transferred < cppi41_channel->packet_sz) {
124
125	/* done, complete */
126	cppi41_channel->channel.actual_len =
127	cppi41_channel->transferred;
128	cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
129	musb_dma_completion(musb, hw_ep->epnum, cppi41_channel->is_tx);
130	} else {
131	/* next iteration, reload */
132	struct dma_chan *dc = cppi41_channel->dc;
133	struct dma_async_tx_descriptor *dma_desc;
134	enum dma_transfer_direction direction;
135	u16 csr;
136	u32 remain_bytes;
137	void __iomem *epio = cppi41_channel->hw_ep->regs;
138
139	cppi41_channel->buf_addr += cppi41_channel->packet_sz;
140
141	remain_bytes = cppi41_channel->total_len;
142	remain_bytes -= cppi41_channel->transferred;
143	remain_bytes = min(remain_bytes, cppi41_channel->packet_sz);
144	cppi41_channel->prog_len = remain_bytes;
145
146	direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV
147	: DMA_DEV_TO_MEM;
148	dma_desc = dmaengine_prep_slave_single(dc,
149	cppi41_channel->buf_addr,
150	remain_bytes,
151	direction,
152	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
153	if (WARN_ON(!dma_desc))
154	return;
155
156	dma_desc->callback = cppi41_dma_callback;
157	dma_desc->callback_param = channel;
158	cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
159	dma_async_issue_pending(dc);
160
161	if (!cppi41_channel->is_tx) {
162	csr = musb_readw(epio, MUSB_RXCSR);
163	csr \|= MUSB_RXCSR_H_REQPKT;
164	musb_writew(epio, MUSB_RXCSR, csr);
165	}
166	}
167	spin_unlock_irqrestore(&musb->lock, flags);
168	}
169
170	static u32 update_ep_mode(unsigned ep, unsigned mode, u32 old)
171	{
172	unsigned shift;
173
174	shift = (ep - 1) * 2;
175	old &= ~(3 << shift);
176	old \|= mode << shift;
177	return old;
178	}
179
180	static void cppi41_set_dma_mode(struct cppi41_dma_channel *cppi41_channel,
181	unsigned mode)
182	{
183	struct cppi41_dma_controller *controller = cppi41_channel->controller;
184	u32 port;
185	u32 new_mode;
186	u32 old_mode;
187
188	if (cppi41_channel->is_tx)
189	old_mode = controller->tx_mode;
190	else
191	old_mode = controller->rx_mode;
192	port = cppi41_channel->port_num;
193	new_mode = update_ep_mode(port, mode, old_mode);
194
195	if (new_mode == old_mode)
196	return;
197	if (cppi41_channel->is_tx) {
198	controller->tx_mode = new_mode;
199	musb_writel(controller->musb->ctrl_base, USB_CTRL_TX_MODE,
200	new_mode);
201	} else {
202	controller->rx_mode = new_mode;
203	musb_writel(controller->musb->ctrl_base, USB_CTRL_RX_MODE,
204	new_mode);
205	}
206	}
207
208	static void cppi41_set_autoreq_mode(struct cppi41_dma_channel *cppi41_channel,
209	unsigned mode)
210	{
211	struct cppi41_dma_controller *controller = cppi41_channel->controller;
212	u32 port;
213	u32 new_mode;
214	u32 old_mode;
215
216	old_mode = controller->auto_req;
217	port = cppi41_channel->port_num;
218	new_mode = update_ep_mode(port, mode, old_mode);
219
220	if (new_mode == old_mode)
221	return;
222	controller->auto_req = new_mode;
223	musb_writel(controller->musb->ctrl_base, USB_CTRL_AUTOREQ, new_mode);
224	}
225
226	static bool cppi41_configure_channel(struct dma_channel *channel,
227	u16 packet_sz, u8 mode,
228	dma_addr_t dma_addr, u32 len)
229	{
230	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
231	struct dma_chan *dc = cppi41_channel->dc;
232	struct dma_async_tx_descriptor *dma_desc;
233	enum dma_transfer_direction direction;
234	struct musb *musb = cppi41_channel->controller->musb;
235	unsigned use_gen_rndis = 0;
236
237	dev_dbg(musb->controller,
238	"configure ep%d/%x packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
239	cppi41_channel->port_num, RNDIS_REG(cppi41_channel->port_num),
240	packet_sz, mode, (unsigned long long) dma_addr,
241	len, cppi41_channel->is_tx);
242
243	cppi41_channel->buf_addr = dma_addr;
244	cppi41_channel->total_len = len;
245	cppi41_channel->transferred = 0;
246	cppi41_channel->packet_sz = packet_sz;
247
248	/*
249	* Due to AM335x' Advisory 1.0.13 we are not allowed to transfer more
250	* than max packet size at a time.
251	*/
252	if (cppi41_channel->is_tx)
253	use_gen_rndis = 1;
254
255	if (use_gen_rndis) {
256	/* RNDIS mode */
257	if (len > packet_sz) {
258	musb_writel(musb->ctrl_base,
259	RNDIS_REG(cppi41_channel->port_num), len);
260	/* gen rndis */
261	cppi41_set_dma_mode(cppi41_channel,
262	EP_MODE_DMA_GEN_RNDIS);
263
264	/* auto req */
265	cppi41_set_autoreq_mode(cppi41_channel,
266	EP_MODE_AUTOREG_ALL_NEOP);
267	} else {
268	musb_writel(musb->ctrl_base,
269	RNDIS_REG(cppi41_channel->port_num), 0);
270	cppi41_set_dma_mode(cppi41_channel,
271	EP_MODE_DMA_TRANSPARENT);
272	cppi41_set_autoreq_mode(cppi41_channel,
273	EP_MODE_AUTOREG_NONE);
274	}
275	} else {
276	/* fallback mode */
277	cppi41_set_dma_mode(cppi41_channel, EP_MODE_DMA_TRANSPARENT);
278	cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREG_NONE);
279	len = min_t(u32, packet_sz, len);
280	}
281	cppi41_channel->prog_len = len;
282	direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
283	dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction,
284	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
285	if (!dma_desc)
286	return false;
287
288	dma_desc->callback = cppi41_dma_callback;
289	dma_desc->callback_param = channel;
290	cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
291
292	save_rx_toggle(cppi41_channel);
293	dma_async_issue_pending(dc);
294	return true;
295	}
296
297	static struct dma_channel cppi41_dma_channel_allocate(struct dma_controller c,
298	struct musb_hw_ep *hw_ep, u8 is_tx)
299	{
300	struct cppi41_dma_controller *controller = container_of(c,
301	struct cppi41_dma_controller, controller);
302	struct cppi41_dma_channel *cppi41_channel = NULL;
303	u8 ch_num = hw_ep->epnum - 1;
304
305	if (ch_num >= MUSB_DMA_NUM_CHANNELS)
306	return NULL;
307
308	if (is_tx)
309	cppi41_channel = &controller->tx_channel[ch_num];
310	else
311	cppi41_channel = &controller->rx_channel[ch_num];
312
313	if (!cppi41_channel->dc)
314	return NULL;
315
316	if (cppi41_channel->is_allocated)
317	return NULL;
318
319	cppi41_channel->hw_ep = hw_ep;
320	cppi41_channel->is_allocated = 1;
321
322	return &cppi41_channel->channel;
323	}
324
325	static void cppi41_dma_channel_release(struct dma_channel *channel)
326	{
327	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
328
329	if (cppi41_channel->is_allocated) {
330	cppi41_channel->is_allocated = 0;
331	channel->status = MUSB_DMA_STATUS_FREE;
332	channel->actual_len = 0;
333	}
334	}
335
336	static int cppi41_dma_channel_program(struct dma_channel *channel,
337	u16 packet_sz, u8 mode,
338	dma_addr_t dma_addr, u32 len)
339	{
340	int ret;
341
342	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN \|\|
343	channel->status == MUSB_DMA_STATUS_BUSY);
344
345	channel->status = MUSB_DMA_STATUS_BUSY;
346	channel->actual_len = 0;
347	ret = cppi41_configure_channel(channel, packet_sz, mode, dma_addr, len);
348	if (!ret)
349	channel->status = MUSB_DMA_STATUS_FREE;
350
351	return ret;
352	}
353
354	static int cppi41_is_compatible(struct dma_channel *channel, u16 maxpacket,
355	void *buf, u32 length)
356	{
357	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
358	struct cppi41_dma_controller *controller = cppi41_channel->controller;
359	struct musb *musb = controller->musb;
360
361	if (is_host_active(musb)) {
362	WARN_ON(1);
363	return 1;
364	}
365	return 0;
366	}
367
368	static int cppi41_dma_channel_abort(struct dma_channel *channel)
369	{
370	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
371	struct cppi41_dma_controller *controller = cppi41_channel->controller;
372	struct musb *musb = controller->musb;
373	void __iomem *epio = cppi41_channel->hw_ep->regs;
374	int tdbit;
375	int ret;
376	unsigned is_tx;
377	u16 csr;
378
379	is_tx = cppi41_channel->is_tx;
380	dev_dbg(musb->controller, "abort channel=%d, is_tx=%d\n",
381	cppi41_channel->port_num, is_tx);
382
383	if (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)
384	return 0;
385
386	if (is_tx) {
387	csr = musb_readw(epio, MUSB_TXCSR);
388	csr &= ~MUSB_TXCSR_DMAENAB;
389	musb_writew(epio, MUSB_TXCSR, csr);
390	} else {
391	csr = musb_readw(epio, MUSB_RXCSR);
392	csr &= ~(MUSB_RXCSR_H_REQPKT \| MUSB_RXCSR_DMAENAB);
393	musb_writew(epio, MUSB_RXCSR, csr);
394
395	csr = musb_readw(epio, MUSB_RXCSR);
396	if (csr & MUSB_RXCSR_RXPKTRDY) {
397	csr \|= MUSB_RXCSR_FLUSHFIFO;
398	musb_writew(epio, MUSB_RXCSR, csr);
399	musb_writew(epio, MUSB_RXCSR, csr);
400	}
401	}
402
403	tdbit = 1 << cppi41_channel->port_num;
404	if (is_tx)
405	tdbit <<= 16;
406
407	do {
408	musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
409	ret = dmaengine_terminate_all(cppi41_channel->dc);
410	} while (ret == -EAGAIN);
411
412	musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
413
414	if (is_tx) {
415	csr = musb_readw(epio, MUSB_TXCSR);
416	if (csr & MUSB_TXCSR_TXPKTRDY) {
417	csr \|= MUSB_TXCSR_FLUSHFIFO;
418	musb_writew(epio, MUSB_TXCSR, csr);
419	}
420	}
421
422	cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
423	return 0;
424	}
425
426	static void cppi41_release_all_dma_chans(struct cppi41_dma_controller *ctrl)
427	{
428	struct dma_chan *dc;
429	int i;
430
431	for (i = 0; i < MUSB_DMA_NUM_CHANNELS; i++) {
432	dc = ctrl->tx_channel[i].dc;
433	if (dc)
434	dma_release_channel(dc);
435	dc = ctrl->rx_channel[i].dc;
436	if (dc)
437	dma_release_channel(dc);
438	}
439	}
440
441	static void cppi41_dma_controller_stop(struct cppi41_dma_controller *controller)
442	{
443	cppi41_release_all_dma_chans(controller);
444	}
445
446	static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
447	{
448	struct musb *musb = controller->musb;
449	struct device *dev = musb->controller;
450	struct device_node *np = dev->of_node;
451	struct cppi41_dma_channel *cppi41_channel;
452	int count;
453	int i;
454	int ret;
455
456	count = of_property_count_strings(np, "dma-names");
457	if (count < 0)
458	return count;
459
460	for (i = 0; i < count; i++) {
461	struct dma_chan *dc;
462	struct dma_channel *musb_dma;
463	const char *str;
464	unsigned is_tx;
465	unsigned int port;
466
467	ret = of_property_read_string_index(np, "dma-names", i, &str);
468	if (ret)
469	goto err;
470	if (!strncmp(str, "tx", 2))
471	is_tx = 1;
472	else if (!strncmp(str, "rx", 2))
473	is_tx = 0;
474	else {
475	dev_err(dev, "Wrong dmatype %s\n", str);
476	goto err;
477	}
478	ret = kstrtouint(str + 2, 0, &port);
479	if (ret)
480	goto err;
481
482	if (port > MUSB_DMA_NUM_CHANNELS \|\| !port)
483	goto err;
484	if (is_tx)
485	cppi41_channel = &controller->tx_channel[port - 1];
486	else
487	cppi41_channel = &controller->rx_channel[port - 1];
488
489	cppi41_channel->controller = controller;
490	cppi41_channel->port_num = port;
491	cppi41_channel->is_tx = is_tx;
492
493	musb_dma = &cppi41_channel->channel;
494	musb_dma->private_data = cppi41_channel;
495	musb_dma->status = MUSB_DMA_STATUS_FREE;
496	musb_dma->max_len = SZ_4M;
497
498	dc = dma_request_slave_channel(dev, str);
499	if (!dc) {
500	dev_err(dev, "Falied to request %s.\n", str);
501	goto err;
502	}
503	cppi41_channel->dc = dc;
504	}
505	return 0;
506	err:
507	cppi41_release_all_dma_chans(controller);
508	return -EINVAL;
509	}
510
511	void dma_controller_destroy(struct dma_controller *c)
512	{
513	struct cppi41_dma_controller *controller = container_of(c,
514	struct cppi41_dma_controller, controller);
515
516	cppi41_dma_controller_stop(controller);
517	kfree(controller);
518	}
519
520	struct dma_controller dma_controller_create(struct musb musb,
521	void __iomem *base)
522	{
523	struct cppi41_dma_controller *controller;
524	int ret;
525
526	if (!musb->controller->of_node) {
527	dev_err(musb->controller, "Need DT for the DMA engine.\n");
528	return NULL;
529	}
530
531	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
532	if (!controller)
533	goto kzalloc_fail;
534
535	controller->musb = musb;
536
537	controller->controller.channel_alloc = cppi41_dma_channel_allocate;
538	controller->controller.channel_release = cppi41_dma_channel_release;
539	controller->controller.channel_program = cppi41_dma_channel_program;
540	controller->controller.channel_abort = cppi41_dma_channel_abort;
541	controller->controller.is_compatible = cppi41_is_compatible;
542
543	ret = cppi41_dma_controller_start(controller);
544	if (ret)
545	goto plat_get_fail;
546	return &controller->controller;
547
548	plat_get_fail:
549	kfree(controller);
550	kzalloc_fail:
551	return NULL;
552	}