Commit | Line | Data |
---|---|---|
550a7375 FB |
1 | /* |
2 | * MUSB OTG driver peripheral support | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
cea83241 | 7 | * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com> |
550a7375 FB |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
24 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
25 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
26 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
27 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
28 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
29 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
30 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
32 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
33 | * | |
34 | */ | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/list.h> | |
38 | #include <linux/timer.h> | |
39 | #include <linux/module.h> | |
40 | #include <linux/smp.h> | |
41 | #include <linux/spinlock.h> | |
42 | #include <linux/delay.h> | |
550a7375 | 43 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 44 | #include <linux/slab.h> |
550a7375 FB |
45 | |
46 | #include "musb_core.h" | |
47 | ||
48 | ||
550a7375 FB |
49 | /* ----------------------------------------------------------------------- */ |
50 | ||
c65bfa62 MYK |
51 | #define is_buffer_mapped(req) (is_dma_capable() && \ |
52 | (req->map_state != UN_MAPPED)) | |
53 | ||
92d2711f HK |
54 | /* Maps the buffer to dma */ |
55 | ||
56 | static inline void map_dma_buffer(struct musb_request *request, | |
c65bfa62 | 57 | struct musb *musb, struct musb_ep *musb_ep) |
92d2711f | 58 | { |
5f5761cb MYK |
59 | int compatible = true; |
60 | struct dma_controller *dma = musb->dma_controller; | |
61 | ||
c65bfa62 MYK |
62 | request->map_state = UN_MAPPED; |
63 | ||
64 | if (!is_dma_capable() || !musb_ep->dma) | |
65 | return; | |
66 | ||
5f5761cb MYK |
67 | /* Check if DMA engine can handle this request. |
68 | * DMA code must reject the USB request explicitly. | |
69 | * Default behaviour is to map the request. | |
70 | */ | |
71 | if (dma->is_compatible) | |
72 | compatible = dma->is_compatible(musb_ep->dma, | |
73 | musb_ep->packet_sz, request->request.buf, | |
74 | request->request.length); | |
75 | if (!compatible) | |
76 | return; | |
77 | ||
92d2711f HK |
78 | if (request->request.dma == DMA_ADDR_INVALID) { |
79 | request->request.dma = dma_map_single( | |
80 | musb->controller, | |
81 | request->request.buf, | |
82 | request->request.length, | |
83 | request->tx | |
84 | ? DMA_TO_DEVICE | |
85 | : DMA_FROM_DEVICE); | |
c65bfa62 | 86 | request->map_state = MUSB_MAPPED; |
92d2711f HK |
87 | } else { |
88 | dma_sync_single_for_device(musb->controller, | |
89 | request->request.dma, | |
90 | request->request.length, | |
91 | request->tx | |
92 | ? DMA_TO_DEVICE | |
93 | : DMA_FROM_DEVICE); | |
c65bfa62 | 94 | request->map_state = PRE_MAPPED; |
92d2711f HK |
95 | } |
96 | } | |
97 | ||
98 | /* Unmap the buffer from dma and maps it back to cpu */ | |
99 | static inline void unmap_dma_buffer(struct musb_request *request, | |
100 | struct musb *musb) | |
101 | { | |
06d9db72 KVA |
102 | struct musb_ep *musb_ep = request->ep; |
103 | ||
104 | if (!is_buffer_mapped(request) || !musb_ep->dma) | |
c65bfa62 MYK |
105 | return; |
106 | ||
92d2711f | 107 | if (request->request.dma == DMA_ADDR_INVALID) { |
5c8a86e1 FB |
108 | dev_vdbg(musb->controller, |
109 | "not unmapping a never mapped buffer\n"); | |
92d2711f HK |
110 | return; |
111 | } | |
c65bfa62 | 112 | if (request->map_state == MUSB_MAPPED) { |
92d2711f HK |
113 | dma_unmap_single(musb->controller, |
114 | request->request.dma, | |
115 | request->request.length, | |
116 | request->tx | |
117 | ? DMA_TO_DEVICE | |
118 | : DMA_FROM_DEVICE); | |
119 | request->request.dma = DMA_ADDR_INVALID; | |
c65bfa62 | 120 | } else { /* PRE_MAPPED */ |
92d2711f HK |
121 | dma_sync_single_for_cpu(musb->controller, |
122 | request->request.dma, | |
123 | request->request.length, | |
124 | request->tx | |
125 | ? DMA_TO_DEVICE | |
126 | : DMA_FROM_DEVICE); | |
92d2711f | 127 | } |
c65bfa62 | 128 | request->map_state = UN_MAPPED; |
92d2711f HK |
129 | } |
130 | ||
550a7375 FB |
131 | /* |
132 | * Immediately complete a request. | |
133 | * | |
134 | * @param request the request to complete | |
135 | * @param status the status to complete the request with | |
136 | * Context: controller locked, IRQs blocked. | |
137 | */ | |
138 | void musb_g_giveback( | |
139 | struct musb_ep *ep, | |
140 | struct usb_request *request, | |
141 | int status) | |
142 | __releases(ep->musb->lock) | |
143 | __acquires(ep->musb->lock) | |
144 | { | |
145 | struct musb_request *req; | |
146 | struct musb *musb; | |
147 | int busy = ep->busy; | |
148 | ||
149 | req = to_musb_request(request); | |
150 | ||
ad1adb89 | 151 | list_del(&req->list); |
550a7375 FB |
152 | if (req->request.status == -EINPROGRESS) |
153 | req->request.status = status; | |
154 | musb = req->musb; | |
155 | ||
156 | ep->busy = 1; | |
157 | spin_unlock(&musb->lock); | |
06d9db72 KVA |
158 | |
159 | if (!dma_mapping_error(&musb->g.dev, request->dma)) | |
160 | unmap_dma_buffer(req, musb); | |
161 | ||
550a7375 | 162 | if (request->status == 0) |
5c8a86e1 | 163 | dev_dbg(musb->controller, "%s done request %p, %d/%d\n", |
550a7375 FB |
164 | ep->end_point.name, request, |
165 | req->request.actual, req->request.length); | |
166 | else | |
5c8a86e1 | 167 | dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n", |
550a7375 FB |
168 | ep->end_point.name, request, |
169 | req->request.actual, req->request.length, | |
170 | request->status); | |
171 | req->request.complete(&req->ep->end_point, &req->request); | |
172 | spin_lock(&musb->lock); | |
173 | ep->busy = busy; | |
174 | } | |
175 | ||
176 | /* ----------------------------------------------------------------------- */ | |
177 | ||
178 | /* | |
179 | * Abort requests queued to an endpoint using the status. Synchronous. | |
180 | * caller locked controller and blocked irqs, and selected this ep. | |
181 | */ | |
182 | static void nuke(struct musb_ep *ep, const int status) | |
183 | { | |
5c8a86e1 | 184 | struct musb *musb = ep->musb; |
550a7375 FB |
185 | struct musb_request *req = NULL; |
186 | void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs; | |
187 | ||
188 | ep->busy = 1; | |
189 | ||
190 | if (is_dma_capable() && ep->dma) { | |
191 | struct dma_controller *c = ep->musb->dma_controller; | |
192 | int value; | |
b6e434a5 | 193 | |
550a7375 | 194 | if (ep->is_in) { |
b6e434a5 SS |
195 | /* |
196 | * The programming guide says that we must not clear | |
197 | * the DMAMODE bit before DMAENAB, so we only | |
198 | * clear it in the second write... | |
199 | */ | |
550a7375 | 200 | musb_writew(epio, MUSB_TXCSR, |
b6e434a5 | 201 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO); |
550a7375 FB |
202 | musb_writew(epio, MUSB_TXCSR, |
203 | 0 | MUSB_TXCSR_FLUSHFIFO); | |
204 | } else { | |
205 | musb_writew(epio, MUSB_RXCSR, | |
206 | 0 | MUSB_RXCSR_FLUSHFIFO); | |
207 | musb_writew(epio, MUSB_RXCSR, | |
208 | 0 | MUSB_RXCSR_FLUSHFIFO); | |
209 | } | |
210 | ||
211 | value = c->channel_abort(ep->dma); | |
5c8a86e1 FB |
212 | dev_dbg(musb->controller, "%s: abort DMA --> %d\n", |
213 | ep->name, value); | |
550a7375 FB |
214 | c->channel_release(ep->dma); |
215 | ep->dma = NULL; | |
216 | } | |
217 | ||
ad1adb89 FB |
218 | while (!list_empty(&ep->req_list)) { |
219 | req = list_first_entry(&ep->req_list, struct musb_request, list); | |
550a7375 FB |
220 | musb_g_giveback(ep, &req->request, status); |
221 | } | |
222 | } | |
223 | ||
224 | /* ----------------------------------------------------------------------- */ | |
225 | ||
226 | /* Data transfers - pure PIO, pure DMA, or mixed mode */ | |
227 | ||
228 | /* | |
229 | * This assumes the separate CPPI engine is responding to DMA requests | |
230 | * from the usb core ... sequenced a bit differently from mentor dma. | |
231 | */ | |
232 | ||
233 | static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep) | |
234 | { | |
235 | if (can_bulk_split(musb, ep->type)) | |
236 | return ep->hw_ep->max_packet_sz_tx; | |
237 | else | |
238 | return ep->packet_sz; | |
239 | } | |
240 | ||
550a7375 FB |
241 | /* |
242 | * An endpoint is transmitting data. This can be called either from | |
243 | * the IRQ routine or from ep.queue() to kickstart a request on an | |
244 | * endpoint. | |
245 | * | |
246 | * Context: controller locked, IRQs blocked, endpoint selected | |
247 | */ | |
248 | static void txstate(struct musb *musb, struct musb_request *req) | |
249 | { | |
250 | u8 epnum = req->epnum; | |
251 | struct musb_ep *musb_ep; | |
252 | void __iomem *epio = musb->endpoints[epnum].regs; | |
253 | struct usb_request *request; | |
254 | u16 fifo_count = 0, csr; | |
255 | int use_dma = 0; | |
256 | ||
257 | musb_ep = req->ep; | |
258 | ||
abf710e6 VP |
259 | /* Check if EP is disabled */ |
260 | if (!musb_ep->desc) { | |
261 | dev_dbg(musb->controller, "ep:%s disabled - ignore request\n", | |
262 | musb_ep->end_point.name); | |
263 | return; | |
264 | } | |
265 | ||
550a7375 FB |
266 | /* we shouldn't get here while DMA is active ... but we do ... */ |
267 | if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { | |
5c8a86e1 | 268 | dev_dbg(musb->controller, "dma pending...\n"); |
550a7375 FB |
269 | return; |
270 | } | |
271 | ||
272 | /* read TXCSR before */ | |
273 | csr = musb_readw(epio, MUSB_TXCSR); | |
274 | ||
275 | request = &req->request; | |
276 | fifo_count = min(max_ep_writesize(musb, musb_ep), | |
277 | (int)(request->length - request->actual)); | |
278 | ||
279 | if (csr & MUSB_TXCSR_TXPKTRDY) { | |
5c8a86e1 | 280 | dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n", |
550a7375 FB |
281 | musb_ep->end_point.name, csr); |
282 | return; | |
283 | } | |
284 | ||
285 | if (csr & MUSB_TXCSR_P_SENDSTALL) { | |
5c8a86e1 | 286 | dev_dbg(musb->controller, "%s stalling, txcsr %03x\n", |
550a7375 FB |
287 | musb_ep->end_point.name, csr); |
288 | return; | |
289 | } | |
290 | ||
5c8a86e1 | 291 | dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n", |
550a7375 FB |
292 | epnum, musb_ep->packet_sz, fifo_count, |
293 | csr); | |
294 | ||
295 | #ifndef CONFIG_MUSB_PIO_ONLY | |
c65bfa62 | 296 | if (is_buffer_mapped(req)) { |
550a7375 | 297 | struct dma_controller *c = musb->dma_controller; |
66af83dd ML |
298 | size_t request_size; |
299 | ||
300 | /* setup DMA, then program endpoint CSR */ | |
301 | request_size = min_t(size_t, request->length - request->actual, | |
302 | musb_ep->dma->max_len); | |
550a7375 | 303 | |
d17d535f | 304 | use_dma = (request->dma != DMA_ADDR_INVALID && request_size); |
550a7375 FB |
305 | |
306 | /* MUSB_TXCSR_P_ISO is still set correctly */ | |
307 | ||
a48ff906 | 308 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) |
550a7375 | 309 | { |
d1043a26 | 310 | if (request_size < musb_ep->packet_sz) |
550a7375 FB |
311 | musb_ep->dma->desired_mode = 0; |
312 | else | |
313 | musb_ep->dma->desired_mode = 1; | |
314 | ||
315 | use_dma = use_dma && c->channel_program( | |
316 | musb_ep->dma, musb_ep->packet_sz, | |
317 | musb_ep->dma->desired_mode, | |
796a83fa | 318 | request->dma + request->actual, request_size); |
550a7375 FB |
319 | if (use_dma) { |
320 | if (musb_ep->dma->desired_mode == 0) { | |
b6e434a5 SS |
321 | /* |
322 | * We must not clear the DMAMODE bit | |
323 | * before the DMAENAB bit -- and the | |
324 | * latter doesn't always get cleared | |
325 | * before we get here... | |
326 | */ | |
327 | csr &= ~(MUSB_TXCSR_AUTOSET | |
328 | | MUSB_TXCSR_DMAENAB); | |
329 | musb_writew(epio, MUSB_TXCSR, csr | |
330 | | MUSB_TXCSR_P_WZC_BITS); | |
331 | csr &= ~MUSB_TXCSR_DMAMODE; | |
550a7375 FB |
332 | csr |= (MUSB_TXCSR_DMAENAB | |
333 | MUSB_TXCSR_MODE); | |
334 | /* against programming guide */ | |
f11d893d ML |
335 | } else { |
336 | csr |= (MUSB_TXCSR_DMAENAB | |
550a7375 FB |
337 | | MUSB_TXCSR_DMAMODE |
338 | | MUSB_TXCSR_MODE); | |
bb3a2ef2 | 339 | /* |
340 | * Enable Autoset according to table | |
341 | * below | |
342 | * bulk_split hb_mult Autoset_Enable | |
343 | * 0 0 Yes(Normal) | |
344 | * 0 >0 No(High BW ISO) | |
345 | * 1 0 Yes(HS bulk) | |
346 | * 1 >0 Yes(FS bulk) | |
347 | */ | |
348 | if (!musb_ep->hb_mult || | |
349 | (musb_ep->hb_mult && | |
350 | can_bulk_split(musb, | |
351 | musb_ep->type))) | |
f11d893d ML |
352 | csr |= MUSB_TXCSR_AUTOSET; |
353 | } | |
550a7375 | 354 | csr &= ~MUSB_TXCSR_P_UNDERRUN; |
f11d893d | 355 | |
550a7375 FB |
356 | musb_writew(epio, MUSB_TXCSR, csr); |
357 | } | |
358 | } | |
359 | ||
550a7375 | 360 | #endif |
fc525751 SAS |
361 | if (is_cppi_enabled()) { |
362 | /* program endpoint CSR first, then setup DMA */ | |
363 | csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); | |
364 | csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE | | |
365 | MUSB_TXCSR_MODE; | |
366 | musb_writew(epio, MUSB_TXCSR, (MUSB_TXCSR_P_WZC_BITS & | |
367 | ~MUSB_TXCSR_P_UNDERRUN) | csr); | |
368 | ||
369 | /* ensure writebuffer is empty */ | |
370 | csr = musb_readw(epio, MUSB_TXCSR); | |
371 | ||
372 | /* | |
373 | * NOTE host side sets DMAENAB later than this; both are | |
374 | * OK since the transfer dma glue (between CPPI and | |
375 | * Mentor fifos) just tells CPPI it could start. Data | |
376 | * only moves to the USB TX fifo when both fifos are | |
377 | * ready. | |
378 | */ | |
379 | /* | |
380 | * "mode" is irrelevant here; handle terminating ZLPs | |
381 | * like PIO does, since the hardware RNDIS mode seems | |
382 | * unreliable except for the | |
383 | * last-packet-is-already-short case. | |
384 | */ | |
385 | use_dma = use_dma && c->channel_program( | |
386 | musb_ep->dma, musb_ep->packet_sz, | |
387 | 0, | |
388 | request->dma + request->actual, | |
389 | request_size); | |
390 | if (!use_dma) { | |
391 | c->channel_release(musb_ep->dma); | |
392 | musb_ep->dma = NULL; | |
393 | csr &= ~MUSB_TXCSR_DMAENAB; | |
394 | musb_writew(epio, MUSB_TXCSR, csr); | |
395 | /* invariant: prequest->buf is non-null */ | |
396 | } | |
397 | } else if (tusb_dma_omap()) | |
398 | use_dma = use_dma && c->channel_program( | |
399 | musb_ep->dma, musb_ep->packet_sz, | |
400 | request->zero, | |
401 | request->dma + request->actual, | |
402 | request_size); | |
550a7375 FB |
403 | } |
404 | #endif | |
405 | ||
406 | if (!use_dma) { | |
92d2711f HK |
407 | /* |
408 | * Unmap the dma buffer back to cpu if dma channel | |
409 | * programming fails | |
410 | */ | |
c65bfa62 | 411 | unmap_dma_buffer(req, musb); |
92d2711f | 412 | |
550a7375 FB |
413 | musb_write_fifo(musb_ep->hw_ep, fifo_count, |
414 | (u8 *) (request->buf + request->actual)); | |
415 | request->actual += fifo_count; | |
416 | csr |= MUSB_TXCSR_TXPKTRDY; | |
417 | csr &= ~MUSB_TXCSR_P_UNDERRUN; | |
418 | musb_writew(epio, MUSB_TXCSR, csr); | |
419 | } | |
420 | ||
421 | /* host may already have the data when this message shows... */ | |
5c8a86e1 | 422 | dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n", |
550a7375 FB |
423 | musb_ep->end_point.name, use_dma ? "dma" : "pio", |
424 | request->actual, request->length, | |
425 | musb_readw(epio, MUSB_TXCSR), | |
426 | fifo_count, | |
427 | musb_readw(epio, MUSB_TXMAXP)); | |
428 | } | |
429 | ||
430 | /* | |
431 | * FIFO state update (e.g. data ready). | |
432 | * Called from IRQ, with controller locked. | |
433 | */ | |
434 | void musb_g_tx(struct musb *musb, u8 epnum) | |
435 | { | |
436 | u16 csr; | |
ad1adb89 | 437 | struct musb_request *req; |
550a7375 FB |
438 | struct usb_request *request; |
439 | u8 __iomem *mbase = musb->mregs; | |
440 | struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in; | |
441 | void __iomem *epio = musb->endpoints[epnum].regs; | |
442 | struct dma_channel *dma; | |
443 | ||
444 | musb_ep_select(mbase, epnum); | |
ad1adb89 FB |
445 | req = next_request(musb_ep); |
446 | request = &req->request; | |
550a7375 FB |
447 | |
448 | csr = musb_readw(epio, MUSB_TXCSR); | |
5c8a86e1 | 449 | dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr); |
550a7375 FB |
450 | |
451 | dma = is_dma_capable() ? musb_ep->dma : NULL; | |
7723de7e SS |
452 | |
453 | /* | |
454 | * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX | |
455 | * probably rates reporting as a host error. | |
456 | */ | |
457 | if (csr & MUSB_TXCSR_P_SENTSTALL) { | |
458 | csr |= MUSB_TXCSR_P_WZC_BITS; | |
459 | csr &= ~MUSB_TXCSR_P_SENTSTALL; | |
460 | musb_writew(epio, MUSB_TXCSR, csr); | |
461 | return; | |
462 | } | |
463 | ||
464 | if (csr & MUSB_TXCSR_P_UNDERRUN) { | |
465 | /* We NAKed, no big deal... little reason to care. */ | |
466 | csr |= MUSB_TXCSR_P_WZC_BITS; | |
467 | csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); | |
468 | musb_writew(epio, MUSB_TXCSR, csr); | |
5c8a86e1 FB |
469 | dev_vdbg(musb->controller, "underrun on ep%d, req %p\n", |
470 | epnum, request); | |
7723de7e SS |
471 | } |
472 | ||
473 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
474 | /* | |
475 | * SHOULD NOT HAPPEN... has with CPPI though, after | |
476 | * changing SENDSTALL (and other cases); harmless? | |
550a7375 | 477 | */ |
5c8a86e1 | 478 | dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name); |
7723de7e SS |
479 | return; |
480 | } | |
550a7375 | 481 | |
7723de7e SS |
482 | if (request) { |
483 | u8 is_dma = 0; | |
484 | ||
485 | if (dma && (csr & MUSB_TXCSR_DMAENAB)) { | |
486 | is_dma = 1; | |
550a7375 | 487 | csr |= MUSB_TXCSR_P_WZC_BITS; |
7723de7e | 488 | csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN | |
100d4a9d | 489 | MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET); |
550a7375 | 490 | musb_writew(epio, MUSB_TXCSR, csr); |
7723de7e SS |
491 | /* Ensure writebuffer is empty. */ |
492 | csr = musb_readw(epio, MUSB_TXCSR); | |
493 | request->actual += musb_ep->dma->actual_len; | |
5c8a86e1 | 494 | dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n", |
7723de7e | 495 | epnum, csr, musb_ep->dma->actual_len, request); |
550a7375 FB |
496 | } |
497 | ||
e7379aaa ML |
498 | /* |
499 | * First, maybe a terminating short packet. Some DMA | |
500 | * engines might handle this by themselves. | |
501 | */ | |
502 | if ((request->zero && request->length | |
503 | && (request->length % musb_ep->packet_sz == 0) | |
504 | && (request->actual == request->length)) | |
a48ff906 | 505 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) |
e7379aaa ML |
506 | || (is_dma && (!dma->desired_mode || |
507 | (request->actual & | |
508 | (musb_ep->packet_sz - 1)))) | |
550a7375 | 509 | #endif |
e7379aaa ML |
510 | ) { |
511 | /* | |
512 | * On DMA completion, FIFO may not be | |
513 | * available yet... | |
514 | */ | |
515 | if (csr & MUSB_TXCSR_TXPKTRDY) | |
516 | return; | |
550a7375 | 517 | |
5c8a86e1 | 518 | dev_dbg(musb->controller, "sending zero pkt\n"); |
e7379aaa ML |
519 | musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE |
520 | | MUSB_TXCSR_TXPKTRDY); | |
521 | request->zero = 0; | |
522 | } | |
523 | ||
524 | if (request->actual == request->length) { | |
525 | musb_g_giveback(musb_ep, request, 0); | |
39287076 SK |
526 | /* |
527 | * In the giveback function the MUSB lock is | |
528 | * released and acquired after sometime. During | |
529 | * this time period the INDEX register could get | |
530 | * changed by the gadget_queue function especially | |
531 | * on SMP systems. Reselect the INDEX to be sure | |
532 | * we are reading/modifying the right registers | |
533 | */ | |
534 | musb_ep_select(mbase, epnum); | |
ad1adb89 FB |
535 | req = musb_ep->desc ? next_request(musb_ep) : NULL; |
536 | if (!req) { | |
5c8a86e1 | 537 | dev_dbg(musb->controller, "%s idle now\n", |
e7379aaa ML |
538 | musb_ep->end_point.name); |
539 | return; | |
95962a77 | 540 | } |
550a7375 FB |
541 | } |
542 | ||
ad1adb89 | 543 | txstate(musb, req); |
7723de7e | 544 | } |
550a7375 FB |
545 | } |
546 | ||
547 | /* ------------------------------------------------------------ */ | |
548 | ||
550a7375 FB |
549 | /* |
550 | * Context: controller locked, IRQs blocked, endpoint selected | |
551 | */ | |
552 | static void rxstate(struct musb *musb, struct musb_request *req) | |
553 | { | |
550a7375 FB |
554 | const u8 epnum = req->epnum; |
555 | struct usb_request *request = &req->request; | |
bd2e74d6 | 556 | struct musb_ep *musb_ep; |
550a7375 | 557 | void __iomem *epio = musb->endpoints[epnum].regs; |
f0443afd SS |
558 | unsigned len = 0; |
559 | u16 fifo_count; | |
cea83241 | 560 | u16 csr = musb_readw(epio, MUSB_RXCSR); |
bd2e74d6 | 561 | struct musb_hw_ep *hw_ep = &musb->endpoints[epnum]; |
0ae52d54 | 562 | u8 use_mode_1; |
bd2e74d6 ML |
563 | |
564 | if (hw_ep->is_shared_fifo) | |
565 | musb_ep = &hw_ep->ep_in; | |
566 | else | |
567 | musb_ep = &hw_ep->ep_out; | |
568 | ||
f0443afd | 569 | fifo_count = musb_ep->packet_sz; |
550a7375 | 570 | |
abf710e6 VP |
571 | /* Check if EP is disabled */ |
572 | if (!musb_ep->desc) { | |
573 | dev_dbg(musb->controller, "ep:%s disabled - ignore request\n", | |
574 | musb_ep->end_point.name); | |
575 | return; | |
576 | } | |
577 | ||
cea83241 SS |
578 | /* We shouldn't get here while DMA is active, but we do... */ |
579 | if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { | |
5c8a86e1 | 580 | dev_dbg(musb->controller, "DMA pending...\n"); |
cea83241 SS |
581 | return; |
582 | } | |
583 | ||
584 | if (csr & MUSB_RXCSR_P_SENDSTALL) { | |
5c8a86e1 | 585 | dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n", |
cea83241 SS |
586 | musb_ep->end_point.name, csr); |
587 | return; | |
588 | } | |
550a7375 | 589 | |
c65bfa62 | 590 | if (is_cppi_enabled() && is_buffer_mapped(req)) { |
550a7375 FB |
591 | struct dma_controller *c = musb->dma_controller; |
592 | struct dma_channel *channel = musb_ep->dma; | |
593 | ||
594 | /* NOTE: CPPI won't actually stop advancing the DMA | |
595 | * queue after short packet transfers, so this is almost | |
596 | * always going to run as IRQ-per-packet DMA so that | |
597 | * faults will be handled correctly. | |
598 | */ | |
599 | if (c->channel_program(channel, | |
600 | musb_ep->packet_sz, | |
601 | !request->short_not_ok, | |
602 | request->dma + request->actual, | |
603 | request->length - request->actual)) { | |
604 | ||
605 | /* make sure that if an rxpkt arrived after the irq, | |
606 | * the cppi engine will be ready to take it as soon | |
607 | * as DMA is enabled | |
608 | */ | |
609 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | |
610 | | MUSB_RXCSR_DMAMODE); | |
611 | csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS; | |
612 | musb_writew(epio, MUSB_RXCSR, csr); | |
613 | return; | |
614 | } | |
615 | } | |
616 | ||
617 | if (csr & MUSB_RXCSR_RXPKTRDY) { | |
f0443afd | 618 | fifo_count = musb_readw(epio, MUSB_RXCOUNT); |
0ae52d54 AG |
619 | |
620 | /* | |
00a89180 FB |
621 | * Enable Mode 1 on RX transfers only when short_not_ok flag |
622 | * is set. Currently short_not_ok flag is set only from | |
623 | * file_storage and f_mass_storage drivers | |
0ae52d54 | 624 | */ |
00a89180 FB |
625 | |
626 | if (request->short_not_ok && fifo_count == musb_ep->packet_sz) | |
0ae52d54 AG |
627 | use_mode_1 = 1; |
628 | else | |
629 | use_mode_1 = 0; | |
630 | ||
550a7375 FB |
631 | if (request->actual < request->length) { |
632 | #ifdef CONFIG_USB_INVENTRA_DMA | |
c65bfa62 | 633 | if (is_buffer_mapped(req)) { |
550a7375 FB |
634 | struct dma_controller *c; |
635 | struct dma_channel *channel; | |
636 | int use_dma = 0; | |
37730ecc | 637 | unsigned int transfer_size; |
550a7375 FB |
638 | |
639 | c = musb->dma_controller; | |
640 | channel = musb_ep->dma; | |
641 | ||
00a89180 FB |
642 | /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in |
643 | * mode 0 only. So we do not get endpoint interrupts due to DMA | |
644 | * completion. We only get interrupts from DMA controller. | |
645 | * | |
646 | * We could operate in DMA mode 1 if we knew the size of the tranfer | |
647 | * in advance. For mass storage class, request->length = what the host | |
648 | * sends, so that'd work. But for pretty much everything else, | |
649 | * request->length is routinely more than what the host sends. For | |
650 | * most these gadgets, end of is signified either by a short packet, | |
651 | * or filling the last byte of the buffer. (Sending extra data in | |
652 | * that last pckate should trigger an overflow fault.) But in mode 1, | |
653 | * we don't get DMA completion interrupt for short packets. | |
654 | * | |
655 | * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1), | |
656 | * to get endpoint interrupt on every DMA req, but that didn't seem | |
657 | * to work reliably. | |
658 | * | |
659 | * REVISIT an updated g_file_storage can set req->short_not_ok, which | |
660 | * then becomes usable as a runtime "use mode 1" hint... | |
661 | */ | |
662 | ||
0ae52d54 AG |
663 | /* Experimental: Mode1 works with mass storage use cases */ |
664 | if (use_mode_1) { | |
9001d80d | 665 | csr |= MUSB_RXCSR_AUTOCLEAR; |
0ae52d54 AG |
666 | musb_writew(epio, MUSB_RXCSR, csr); |
667 | csr |= MUSB_RXCSR_DMAENAB; | |
668 | musb_writew(epio, MUSB_RXCSR, csr); | |
669 | ||
670 | /* | |
671 | * this special sequence (enabling and then | |
672 | * disabling MUSB_RXCSR_DMAMODE) is required | |
673 | * to get DMAReq to activate | |
674 | */ | |
675 | musb_writew(epio, MUSB_RXCSR, | |
676 | csr | MUSB_RXCSR_DMAMODE); | |
677 | musb_writew(epio, MUSB_RXCSR, csr); | |
678 | ||
37730ecc FB |
679 | transfer_size = min_t(unsigned int, |
680 | request->length - | |
681 | request->actual, | |
660fa886 RQ |
682 | channel->max_len); |
683 | musb_ep->dma->desired_mode = 1; | |
0ae52d54 AG |
684 | } else { |
685 | if (!musb_ep->hb_mult && | |
686 | musb_ep->hw_ep->rx_double_buffered) | |
687 | csr |= MUSB_RXCSR_AUTOCLEAR; | |
688 | csr |= MUSB_RXCSR_DMAENAB; | |
689 | musb_writew(epio, MUSB_RXCSR, csr); | |
550a7375 | 690 | |
660fa886 | 691 | transfer_size = min(request->length - request->actual, |
f0443afd | 692 | (unsigned)fifo_count); |
660fa886 | 693 | musb_ep->dma->desired_mode = 0; |
550a7375 FB |
694 | } |
695 | ||
660fa886 RQ |
696 | use_dma = c->channel_program( |
697 | channel, | |
698 | musb_ep->packet_sz, | |
699 | channel->desired_mode, | |
700 | request->dma | |
701 | + request->actual, | |
702 | transfer_size); | |
703 | ||
550a7375 | 704 | if (use_dma) |
a48ff906 MYK |
705 | return; |
706 | } | |
707 | #elif defined(CONFIG_USB_UX500_DMA) | |
708 | if ((is_buffer_mapped(req)) && | |
709 | (request->actual < request->length)) { | |
710 | ||
711 | struct dma_controller *c; | |
712 | struct dma_channel *channel; | |
37730ecc | 713 | unsigned int transfer_size = 0; |
a48ff906 MYK |
714 | |
715 | c = musb->dma_controller; | |
716 | channel = musb_ep->dma; | |
717 | ||
718 | /* In case first packet is short */ | |
f0443afd SS |
719 | if (fifo_count < musb_ep->packet_sz) |
720 | transfer_size = fifo_count; | |
a48ff906 | 721 | else if (request->short_not_ok) |
37730ecc FB |
722 | transfer_size = min_t(unsigned int, |
723 | request->length - | |
a48ff906 MYK |
724 | request->actual, |
725 | channel->max_len); | |
726 | else | |
37730ecc FB |
727 | transfer_size = min_t(unsigned int, |
728 | request->length - | |
a48ff906 | 729 | request->actual, |
f0443afd | 730 | (unsigned)fifo_count); |
a48ff906 MYK |
731 | |
732 | csr &= ~MUSB_RXCSR_DMAMODE; | |
733 | csr |= (MUSB_RXCSR_DMAENAB | | |
734 | MUSB_RXCSR_AUTOCLEAR); | |
735 | ||
736 | musb_writew(epio, MUSB_RXCSR, csr); | |
737 | ||
738 | if (transfer_size <= musb_ep->packet_sz) { | |
739 | musb_ep->dma->desired_mode = 0; | |
740 | } else { | |
741 | musb_ep->dma->desired_mode = 1; | |
742 | /* Mode must be set after DMAENAB */ | |
743 | csr |= MUSB_RXCSR_DMAMODE; | |
744 | musb_writew(epio, MUSB_RXCSR, csr); | |
745 | } | |
746 | ||
747 | if (c->channel_program(channel, | |
748 | musb_ep->packet_sz, | |
749 | channel->desired_mode, | |
750 | request->dma | |
751 | + request->actual, | |
752 | transfer_size)) | |
753 | ||
550a7375 FB |
754 | return; |
755 | } | |
756 | #endif /* Mentor's DMA */ | |
757 | ||
f0443afd | 758 | len = request->length - request->actual; |
5c8a86e1 | 759 | dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n", |
550a7375 | 760 | musb_ep->end_point.name, |
f0443afd | 761 | fifo_count, len, |
550a7375 FB |
762 | musb_ep->packet_sz); |
763 | ||
c2c96321 | 764 | fifo_count = min_t(unsigned, len, fifo_count); |
550a7375 FB |
765 | |
766 | #ifdef CONFIG_USB_TUSB_OMAP_DMA | |
c65bfa62 | 767 | if (tusb_dma_omap() && is_buffer_mapped(req)) { |
550a7375 FB |
768 | struct dma_controller *c = musb->dma_controller; |
769 | struct dma_channel *channel = musb_ep->dma; | |
770 | u32 dma_addr = request->dma + request->actual; | |
771 | int ret; | |
772 | ||
773 | ret = c->channel_program(channel, | |
774 | musb_ep->packet_sz, | |
775 | channel->desired_mode, | |
776 | dma_addr, | |
777 | fifo_count); | |
778 | if (ret) | |
779 | return; | |
780 | } | |
781 | #endif | |
92d2711f HK |
782 | /* |
783 | * Unmap the dma buffer back to cpu if dma channel | |
784 | * programming fails. This buffer is mapped if the | |
785 | * channel allocation is successful | |
786 | */ | |
c65bfa62 | 787 | if (is_buffer_mapped(req)) { |
92d2711f HK |
788 | unmap_dma_buffer(req, musb); |
789 | ||
e75df371 ML |
790 | /* |
791 | * Clear DMAENAB and AUTOCLEAR for the | |
92d2711f HK |
792 | * PIO mode transfer |
793 | */ | |
e75df371 | 794 | csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR); |
92d2711f HK |
795 | musb_writew(epio, MUSB_RXCSR, csr); |
796 | } | |
550a7375 FB |
797 | |
798 | musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *) | |
799 | (request->buf + request->actual)); | |
800 | request->actual += fifo_count; | |
801 | ||
802 | /* REVISIT if we left anything in the fifo, flush | |
803 | * it and report -EOVERFLOW | |
804 | */ | |
805 | ||
806 | /* ack the read! */ | |
807 | csr |= MUSB_RXCSR_P_WZC_BITS; | |
808 | csr &= ~MUSB_RXCSR_RXPKTRDY; | |
809 | musb_writew(epio, MUSB_RXCSR, csr); | |
810 | } | |
811 | } | |
812 | ||
813 | /* reach the end or short packet detected */ | |
f0443afd SS |
814 | if (request->actual == request->length || |
815 | fifo_count < musb_ep->packet_sz) | |
550a7375 FB |
816 | musb_g_giveback(musb_ep, request, 0); |
817 | } | |
818 | ||
819 | /* | |
820 | * Data ready for a request; called from IRQ | |
821 | */ | |
822 | void musb_g_rx(struct musb *musb, u8 epnum) | |
823 | { | |
824 | u16 csr; | |
ad1adb89 | 825 | struct musb_request *req; |
550a7375 FB |
826 | struct usb_request *request; |
827 | void __iomem *mbase = musb->mregs; | |
bd2e74d6 | 828 | struct musb_ep *musb_ep; |
550a7375 FB |
829 | void __iomem *epio = musb->endpoints[epnum].regs; |
830 | struct dma_channel *dma; | |
bd2e74d6 ML |
831 | struct musb_hw_ep *hw_ep = &musb->endpoints[epnum]; |
832 | ||
833 | if (hw_ep->is_shared_fifo) | |
834 | musb_ep = &hw_ep->ep_in; | |
835 | else | |
836 | musb_ep = &hw_ep->ep_out; | |
550a7375 FB |
837 | |
838 | musb_ep_select(mbase, epnum); | |
839 | ||
ad1adb89 FB |
840 | req = next_request(musb_ep); |
841 | if (!req) | |
0abdc36f | 842 | return; |
550a7375 | 843 | |
ad1adb89 FB |
844 | request = &req->request; |
845 | ||
550a7375 FB |
846 | csr = musb_readw(epio, MUSB_RXCSR); |
847 | dma = is_dma_capable() ? musb_ep->dma : NULL; | |
848 | ||
5c8a86e1 | 849 | dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name, |
550a7375 FB |
850 | csr, dma ? " (dma)" : "", request); |
851 | ||
852 | if (csr & MUSB_RXCSR_P_SENTSTALL) { | |
550a7375 FB |
853 | csr |= MUSB_RXCSR_P_WZC_BITS; |
854 | csr &= ~MUSB_RXCSR_P_SENTSTALL; | |
855 | musb_writew(epio, MUSB_RXCSR, csr); | |
cea83241 | 856 | return; |
550a7375 FB |
857 | } |
858 | ||
859 | if (csr & MUSB_RXCSR_P_OVERRUN) { | |
860 | /* csr |= MUSB_RXCSR_P_WZC_BITS; */ | |
861 | csr &= ~MUSB_RXCSR_P_OVERRUN; | |
862 | musb_writew(epio, MUSB_RXCSR, csr); | |
863 | ||
5c8a86e1 | 864 | dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request); |
43467868 | 865 | if (request->status == -EINPROGRESS) |
550a7375 FB |
866 | request->status = -EOVERFLOW; |
867 | } | |
868 | if (csr & MUSB_RXCSR_INCOMPRX) { | |
869 | /* REVISIT not necessarily an error */ | |
5c8a86e1 | 870 | dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name); |
550a7375 FB |
871 | } |
872 | ||
873 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
874 | /* "should not happen"; likely RXPKTRDY pending for DMA */ | |
5c8a86e1 | 875 | dev_dbg(musb->controller, "%s busy, csr %04x\n", |
550a7375 | 876 | musb_ep->end_point.name, csr); |
cea83241 | 877 | return; |
550a7375 FB |
878 | } |
879 | ||
880 | if (dma && (csr & MUSB_RXCSR_DMAENAB)) { | |
881 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | |
882 | | MUSB_RXCSR_DMAENAB | |
883 | | MUSB_RXCSR_DMAMODE); | |
884 | musb_writew(epio, MUSB_RXCSR, | |
885 | MUSB_RXCSR_P_WZC_BITS | csr); | |
886 | ||
887 | request->actual += musb_ep->dma->actual_len; | |
888 | ||
5c8a86e1 | 889 | dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n", |
550a7375 FB |
890 | epnum, csr, |
891 | musb_readw(epio, MUSB_RXCSR), | |
892 | musb_ep->dma->actual_len, request); | |
893 | ||
a48ff906 MYK |
894 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \ |
895 | defined(CONFIG_USB_UX500_DMA) | |
550a7375 | 896 | /* Autoclear doesn't clear RxPktRdy for short packets */ |
9001d80d | 897 | if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered) |
550a7375 FB |
898 | || (dma->actual_len |
899 | & (musb_ep->packet_sz - 1))) { | |
900 | /* ack the read! */ | |
901 | csr &= ~MUSB_RXCSR_RXPKTRDY; | |
902 | musb_writew(epio, MUSB_RXCSR, csr); | |
903 | } | |
904 | ||
905 | /* incomplete, and not short? wait for next IN packet */ | |
906 | if ((request->actual < request->length) | |
907 | && (musb_ep->dma->actual_len | |
9001d80d ML |
908 | == musb_ep->packet_sz)) { |
909 | /* In double buffer case, continue to unload fifo if | |
910 | * there is Rx packet in FIFO. | |
911 | **/ | |
912 | csr = musb_readw(epio, MUSB_RXCSR); | |
913 | if ((csr & MUSB_RXCSR_RXPKTRDY) && | |
914 | hw_ep->rx_double_buffered) | |
915 | goto exit; | |
cea83241 | 916 | return; |
9001d80d | 917 | } |
550a7375 FB |
918 | #endif |
919 | musb_g_giveback(musb_ep, request, 0); | |
39287076 SK |
920 | /* |
921 | * In the giveback function the MUSB lock is | |
922 | * released and acquired after sometime. During | |
923 | * this time period the INDEX register could get | |
924 | * changed by the gadget_queue function especially | |
925 | * on SMP systems. Reselect the INDEX to be sure | |
926 | * we are reading/modifying the right registers | |
927 | */ | |
928 | musb_ep_select(mbase, epnum); | |
550a7375 | 929 | |
ad1adb89 FB |
930 | req = next_request(musb_ep); |
931 | if (!req) | |
cea83241 | 932 | return; |
550a7375 | 933 | } |
a48ff906 MYK |
934 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \ |
935 | defined(CONFIG_USB_UX500_DMA) | |
9001d80d | 936 | exit: |
bb324b08 | 937 | #endif |
43467868 | 938 | /* Analyze request */ |
ad1adb89 | 939 | rxstate(musb, req); |
550a7375 FB |
940 | } |
941 | ||
942 | /* ------------------------------------------------------------ */ | |
943 | ||
944 | static int musb_gadget_enable(struct usb_ep *ep, | |
945 | const struct usb_endpoint_descriptor *desc) | |
946 | { | |
947 | unsigned long flags; | |
948 | struct musb_ep *musb_ep; | |
949 | struct musb_hw_ep *hw_ep; | |
950 | void __iomem *regs; | |
951 | struct musb *musb; | |
952 | void __iomem *mbase; | |
953 | u8 epnum; | |
954 | u16 csr; | |
955 | unsigned tmp; | |
956 | int status = -EINVAL; | |
957 | ||
958 | if (!ep || !desc) | |
959 | return -EINVAL; | |
960 | ||
961 | musb_ep = to_musb_ep(ep); | |
962 | hw_ep = musb_ep->hw_ep; | |
963 | regs = hw_ep->regs; | |
964 | musb = musb_ep->musb; | |
965 | mbase = musb->mregs; | |
966 | epnum = musb_ep->current_epnum; | |
967 | ||
968 | spin_lock_irqsave(&musb->lock, flags); | |
969 | ||
970 | if (musb_ep->desc) { | |
971 | status = -EBUSY; | |
972 | goto fail; | |
973 | } | |
96bcd090 | 974 | musb_ep->type = usb_endpoint_type(desc); |
550a7375 FB |
975 | |
976 | /* check direction and (later) maxpacket size against endpoint */ | |
96bcd090 | 977 | if (usb_endpoint_num(desc) != epnum) |
550a7375 FB |
978 | goto fail; |
979 | ||
980 | /* REVISIT this rules out high bandwidth periodic transfers */ | |
29cc8897 | 981 | tmp = usb_endpoint_maxp(desc); |
f11d893d ML |
982 | if (tmp & ~0x07ff) { |
983 | int ok; | |
984 | ||
985 | if (usb_endpoint_dir_in(desc)) | |
986 | ok = musb->hb_iso_tx; | |
987 | else | |
988 | ok = musb->hb_iso_rx; | |
989 | ||
990 | if (!ok) { | |
5c8a86e1 | 991 | dev_dbg(musb->controller, "no support for high bandwidth ISO\n"); |
f11d893d ML |
992 | goto fail; |
993 | } | |
994 | musb_ep->hb_mult = (tmp >> 11) & 3; | |
995 | } else { | |
996 | musb_ep->hb_mult = 0; | |
997 | } | |
998 | ||
999 | musb_ep->packet_sz = tmp & 0x7ff; | |
1000 | tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1); | |
550a7375 FB |
1001 | |
1002 | /* enable the interrupts for the endpoint, set the endpoint | |
1003 | * packet size (or fail), set the mode, clear the fifo | |
1004 | */ | |
1005 | musb_ep_select(mbase, epnum); | |
96bcd090 | 1006 | if (usb_endpoint_dir_in(desc)) { |
550a7375 FB |
1007 | |
1008 | if (hw_ep->is_shared_fifo) | |
1009 | musb_ep->is_in = 1; | |
1010 | if (!musb_ep->is_in) | |
1011 | goto fail; | |
f11d893d ML |
1012 | |
1013 | if (tmp > hw_ep->max_packet_sz_tx) { | |
5c8a86e1 | 1014 | dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n"); |
550a7375 | 1015 | goto fail; |
f11d893d | 1016 | } |
550a7375 | 1017 | |
b18d26f6 SAS |
1018 | musb->intrtxe |= (1 << epnum); |
1019 | musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe); | |
550a7375 FB |
1020 | |
1021 | /* REVISIT if can_bulk_split(), use by updating "tmp"; | |
1022 | * likewise high bandwidth periodic tx | |
1023 | */ | |
9f445cb2 | 1024 | /* Set TXMAXP with the FIFO size of the endpoint |
31c9909b | 1025 | * to disable double buffering mode. |
9f445cb2 | 1026 | */ |
bb3a2ef2 | 1027 | if (musb->double_buffer_not_ok) { |
06624818 | 1028 | musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx); |
bb3a2ef2 | 1029 | } else { |
1030 | if (can_bulk_split(musb, musb_ep->type)) | |
1031 | musb_ep->hb_mult = (hw_ep->max_packet_sz_tx / | |
1032 | musb_ep->packet_sz) - 1; | |
06624818 FB |
1033 | musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz |
1034 | | (musb_ep->hb_mult << 11)); | |
bb3a2ef2 | 1035 | } |
550a7375 FB |
1036 | |
1037 | csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; | |
1038 | if (musb_readw(regs, MUSB_TXCSR) | |
1039 | & MUSB_TXCSR_FIFONOTEMPTY) | |
1040 | csr |= MUSB_TXCSR_FLUSHFIFO; | |
1041 | if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) | |
1042 | csr |= MUSB_TXCSR_P_ISO; | |
1043 | ||
1044 | /* set twice in case of double buffering */ | |
1045 | musb_writew(regs, MUSB_TXCSR, csr); | |
1046 | /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ | |
1047 | musb_writew(regs, MUSB_TXCSR, csr); | |
1048 | ||
1049 | } else { | |
550a7375 FB |
1050 | |
1051 | if (hw_ep->is_shared_fifo) | |
1052 | musb_ep->is_in = 0; | |
1053 | if (musb_ep->is_in) | |
1054 | goto fail; | |
f11d893d ML |
1055 | |
1056 | if (tmp > hw_ep->max_packet_sz_rx) { | |
5c8a86e1 | 1057 | dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n"); |
550a7375 | 1058 | goto fail; |
f11d893d | 1059 | } |
550a7375 | 1060 | |
af5ec14d SAS |
1061 | musb->intrrxe |= (1 << epnum); |
1062 | musb_writew(mbase, MUSB_INTRRXE, musb->intrrxe); | |
550a7375 FB |
1063 | |
1064 | /* REVISIT if can_bulk_combine() use by updating "tmp" | |
1065 | * likewise high bandwidth periodic rx | |
1066 | */ | |
9f445cb2 CC |
1067 | /* Set RXMAXP with the FIFO size of the endpoint |
1068 | * to disable double buffering mode. | |
1069 | */ | |
06624818 FB |
1070 | if (musb->double_buffer_not_ok) |
1071 | musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx); | |
1072 | else | |
1073 | musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz | |
1074 | | (musb_ep->hb_mult << 11)); | |
550a7375 FB |
1075 | |
1076 | /* force shared fifo to OUT-only mode */ | |
1077 | if (hw_ep->is_shared_fifo) { | |
1078 | csr = musb_readw(regs, MUSB_TXCSR); | |
1079 | csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY); | |
1080 | musb_writew(regs, MUSB_TXCSR, csr); | |
1081 | } | |
1082 | ||
1083 | csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG; | |
1084 | if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) | |
1085 | csr |= MUSB_RXCSR_P_ISO; | |
1086 | else if (musb_ep->type == USB_ENDPOINT_XFER_INT) | |
1087 | csr |= MUSB_RXCSR_DISNYET; | |
1088 | ||
1089 | /* set twice in case of double buffering */ | |
1090 | musb_writew(regs, MUSB_RXCSR, csr); | |
1091 | musb_writew(regs, MUSB_RXCSR, csr); | |
1092 | } | |
1093 | ||
1094 | /* NOTE: all the I/O code _should_ work fine without DMA, in case | |
1095 | * for some reason you run out of channels here. | |
1096 | */ | |
1097 | if (is_dma_capable() && musb->dma_controller) { | |
1098 | struct dma_controller *c = musb->dma_controller; | |
1099 | ||
1100 | musb_ep->dma = c->channel_alloc(c, hw_ep, | |
1101 | (desc->bEndpointAddress & USB_DIR_IN)); | |
1102 | } else | |
1103 | musb_ep->dma = NULL; | |
1104 | ||
1105 | musb_ep->desc = desc; | |
1106 | musb_ep->busy = 0; | |
47e97605 | 1107 | musb_ep->wedged = 0; |
550a7375 FB |
1108 | status = 0; |
1109 | ||
1110 | pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n", | |
1111 | musb_driver_name, musb_ep->end_point.name, | |
1112 | ({ char *s; switch (musb_ep->type) { | |
1113 | case USB_ENDPOINT_XFER_BULK: s = "bulk"; break; | |
1114 | case USB_ENDPOINT_XFER_INT: s = "int"; break; | |
1115 | default: s = "iso"; break; | |
1116 | }; s; }), | |
1117 | musb_ep->is_in ? "IN" : "OUT", | |
1118 | musb_ep->dma ? "dma, " : "", | |
1119 | musb_ep->packet_sz); | |
1120 | ||
1121 | schedule_work(&musb->irq_work); | |
1122 | ||
1123 | fail: | |
1124 | spin_unlock_irqrestore(&musb->lock, flags); | |
1125 | return status; | |
1126 | } | |
1127 | ||
1128 | /* | |
1129 | * Disable an endpoint flushing all requests queued. | |
1130 | */ | |
1131 | static int musb_gadget_disable(struct usb_ep *ep) | |
1132 | { | |
1133 | unsigned long flags; | |
1134 | struct musb *musb; | |
1135 | u8 epnum; | |
1136 | struct musb_ep *musb_ep; | |
1137 | void __iomem *epio; | |
1138 | int status = 0; | |
1139 | ||
1140 | musb_ep = to_musb_ep(ep); | |
1141 | musb = musb_ep->musb; | |
1142 | epnum = musb_ep->current_epnum; | |
1143 | epio = musb->endpoints[epnum].regs; | |
1144 | ||
1145 | spin_lock_irqsave(&musb->lock, flags); | |
1146 | musb_ep_select(musb->mregs, epnum); | |
1147 | ||
1148 | /* zero the endpoint sizes */ | |
1149 | if (musb_ep->is_in) { | |
b18d26f6 SAS |
1150 | musb->intrtxe &= ~(1 << epnum); |
1151 | musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe); | |
550a7375 FB |
1152 | musb_writew(epio, MUSB_TXMAXP, 0); |
1153 | } else { | |
af5ec14d SAS |
1154 | musb->intrrxe &= ~(1 << epnum); |
1155 | musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe); | |
550a7375 FB |
1156 | musb_writew(epio, MUSB_RXMAXP, 0); |
1157 | } | |
1158 | ||
1159 | musb_ep->desc = NULL; | |
08f75bf1 | 1160 | musb_ep->end_point.desc = NULL; |
550a7375 FB |
1161 | |
1162 | /* abort all pending DMA and requests */ | |
1163 | nuke(musb_ep, -ESHUTDOWN); | |
1164 | ||
1165 | schedule_work(&musb->irq_work); | |
1166 | ||
1167 | spin_unlock_irqrestore(&(musb->lock), flags); | |
1168 | ||
5c8a86e1 | 1169 | dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name); |
550a7375 FB |
1170 | |
1171 | return status; | |
1172 | } | |
1173 | ||
1174 | /* | |
1175 | * Allocate a request for an endpoint. | |
1176 | * Reused by ep0 code. | |
1177 | */ | |
1178 | struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) | |
1179 | { | |
1180 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
5c8a86e1 | 1181 | struct musb *musb = musb_ep->musb; |
550a7375 FB |
1182 | struct musb_request *request = NULL; |
1183 | ||
1184 | request = kzalloc(sizeof *request, gfp_flags); | |
0607f862 | 1185 | if (!request) { |
5c8a86e1 | 1186 | dev_dbg(musb->controller, "not enough memory\n"); |
0607f862 | 1187 | return NULL; |
550a7375 FB |
1188 | } |
1189 | ||
0607f862 FB |
1190 | request->request.dma = DMA_ADDR_INVALID; |
1191 | request->epnum = musb_ep->current_epnum; | |
1192 | request->ep = musb_ep; | |
1193 | ||
550a7375 FB |
1194 | return &request->request; |
1195 | } | |
1196 | ||
1197 | /* | |
1198 | * Free a request | |
1199 | * Reused by ep0 code. | |
1200 | */ | |
1201 | void musb_free_request(struct usb_ep *ep, struct usb_request *req) | |
1202 | { | |
1203 | kfree(to_musb_request(req)); | |
1204 | } | |
1205 | ||
1206 | static LIST_HEAD(buffers); | |
1207 | ||
1208 | struct free_record { | |
1209 | struct list_head list; | |
1210 | struct device *dev; | |
1211 | unsigned bytes; | |
1212 | dma_addr_t dma; | |
1213 | }; | |
1214 | ||
1215 | /* | |
1216 | * Context: controller locked, IRQs blocked. | |
1217 | */ | |
a666e3e6 | 1218 | void musb_ep_restart(struct musb *musb, struct musb_request *req) |
550a7375 | 1219 | { |
5c8a86e1 | 1220 | dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n", |
550a7375 FB |
1221 | req->tx ? "TX/IN" : "RX/OUT", |
1222 | &req->request, req->request.length, req->epnum); | |
1223 | ||
1224 | musb_ep_select(musb->mregs, req->epnum); | |
1225 | if (req->tx) | |
1226 | txstate(musb, req); | |
1227 | else | |
1228 | rxstate(musb, req); | |
1229 | } | |
1230 | ||
1231 | static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req, | |
1232 | gfp_t gfp_flags) | |
1233 | { | |
1234 | struct musb_ep *musb_ep; | |
1235 | struct musb_request *request; | |
1236 | struct musb *musb; | |
1237 | int status = 0; | |
1238 | unsigned long lockflags; | |
1239 | ||
1240 | if (!ep || !req) | |
1241 | return -EINVAL; | |
1242 | if (!req->buf) | |
1243 | return -ENODATA; | |
1244 | ||
1245 | musb_ep = to_musb_ep(ep); | |
1246 | musb = musb_ep->musb; | |
1247 | ||
1248 | request = to_musb_request(req); | |
1249 | request->musb = musb; | |
1250 | ||
1251 | if (request->ep != musb_ep) | |
1252 | return -EINVAL; | |
1253 | ||
5c8a86e1 | 1254 | dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req); |
550a7375 FB |
1255 | |
1256 | /* request is mine now... */ | |
1257 | request->request.actual = 0; | |
1258 | request->request.status = -EINPROGRESS; | |
1259 | request->epnum = musb_ep->current_epnum; | |
1260 | request->tx = musb_ep->is_in; | |
1261 | ||
c65bfa62 | 1262 | map_dma_buffer(request, musb, musb_ep); |
550a7375 FB |
1263 | |
1264 | spin_lock_irqsave(&musb->lock, lockflags); | |
1265 | ||
1266 | /* don't queue if the ep is down */ | |
1267 | if (!musb_ep->desc) { | |
5c8a86e1 | 1268 | dev_dbg(musb->controller, "req %p queued to %s while ep %s\n", |
550a7375 FB |
1269 | req, ep->name, "disabled"); |
1270 | status = -ESHUTDOWN; | |
23a53d90 SAS |
1271 | unmap_dma_buffer(request, musb); |
1272 | goto unlock; | |
550a7375 FB |
1273 | } |
1274 | ||
1275 | /* add request to the list */ | |
ad1adb89 | 1276 | list_add_tail(&request->list, &musb_ep->req_list); |
550a7375 FB |
1277 | |
1278 | /* it this is the head of the queue, start i/o ... */ | |
ad1adb89 | 1279 | if (!musb_ep->busy && &request->list == musb_ep->req_list.next) |
550a7375 FB |
1280 | musb_ep_restart(musb, request); |
1281 | ||
23a53d90 | 1282 | unlock: |
550a7375 FB |
1283 | spin_unlock_irqrestore(&musb->lock, lockflags); |
1284 | return status; | |
1285 | } | |
1286 | ||
1287 | static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request) | |
1288 | { | |
1289 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
4cbbf084 FB |
1290 | struct musb_request *req = to_musb_request(request); |
1291 | struct musb_request *r; | |
550a7375 FB |
1292 | unsigned long flags; |
1293 | int status = 0; | |
1294 | struct musb *musb = musb_ep->musb; | |
1295 | ||
1296 | if (!ep || !request || to_musb_request(request)->ep != musb_ep) | |
1297 | return -EINVAL; | |
1298 | ||
1299 | spin_lock_irqsave(&musb->lock, flags); | |
1300 | ||
1301 | list_for_each_entry(r, &musb_ep->req_list, list) { | |
4cbbf084 | 1302 | if (r == req) |
550a7375 FB |
1303 | break; |
1304 | } | |
4cbbf084 | 1305 | if (r != req) { |
5c8a86e1 | 1306 | dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name); |
550a7375 FB |
1307 | status = -EINVAL; |
1308 | goto done; | |
1309 | } | |
1310 | ||
1311 | /* if the hardware doesn't have the request, easy ... */ | |
3d5ad13e | 1312 | if (musb_ep->req_list.next != &req->list || musb_ep->busy) |
550a7375 FB |
1313 | musb_g_giveback(musb_ep, request, -ECONNRESET); |
1314 | ||
1315 | /* ... else abort the dma transfer ... */ | |
1316 | else if (is_dma_capable() && musb_ep->dma) { | |
1317 | struct dma_controller *c = musb->dma_controller; | |
1318 | ||
1319 | musb_ep_select(musb->mregs, musb_ep->current_epnum); | |
1320 | if (c->channel_abort) | |
1321 | status = c->channel_abort(musb_ep->dma); | |
1322 | else | |
1323 | status = -EBUSY; | |
1324 | if (status == 0) | |
1325 | musb_g_giveback(musb_ep, request, -ECONNRESET); | |
1326 | } else { | |
1327 | /* NOTE: by sticking to easily tested hardware/driver states, | |
1328 | * we leave counting of in-flight packets imprecise. | |
1329 | */ | |
1330 | musb_g_giveback(musb_ep, request, -ECONNRESET); | |
1331 | } | |
1332 | ||
1333 | done: | |
1334 | spin_unlock_irqrestore(&musb->lock, flags); | |
1335 | return status; | |
1336 | } | |
1337 | ||
1338 | /* | |
1339 | * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any | |
1340 | * data but will queue requests. | |
1341 | * | |
1342 | * exported to ep0 code | |
1343 | */ | |
1b6c3b0f | 1344 | static int musb_gadget_set_halt(struct usb_ep *ep, int value) |
550a7375 FB |
1345 | { |
1346 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1347 | u8 epnum = musb_ep->current_epnum; | |
1348 | struct musb *musb = musb_ep->musb; | |
1349 | void __iomem *epio = musb->endpoints[epnum].regs; | |
1350 | void __iomem *mbase; | |
1351 | unsigned long flags; | |
1352 | u16 csr; | |
cea83241 | 1353 | struct musb_request *request; |
550a7375 FB |
1354 | int status = 0; |
1355 | ||
1356 | if (!ep) | |
1357 | return -EINVAL; | |
1358 | mbase = musb->mregs; | |
1359 | ||
1360 | spin_lock_irqsave(&musb->lock, flags); | |
1361 | ||
1362 | if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) { | |
1363 | status = -EINVAL; | |
1364 | goto done; | |
1365 | } | |
1366 | ||
1367 | musb_ep_select(mbase, epnum); | |
1368 | ||
ad1adb89 | 1369 | request = next_request(musb_ep); |
cea83241 SS |
1370 | if (value) { |
1371 | if (request) { | |
5c8a86e1 | 1372 | dev_dbg(musb->controller, "request in progress, cannot halt %s\n", |
cea83241 SS |
1373 | ep->name); |
1374 | status = -EAGAIN; | |
1375 | goto done; | |
1376 | } | |
1377 | /* Cannot portably stall with non-empty FIFO */ | |
1378 | if (musb_ep->is_in) { | |
1379 | csr = musb_readw(epio, MUSB_TXCSR); | |
1380 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) { | |
5c8a86e1 | 1381 | dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name); |
cea83241 SS |
1382 | status = -EAGAIN; |
1383 | goto done; | |
1384 | } | |
550a7375 | 1385 | } |
47e97605 SS |
1386 | } else |
1387 | musb_ep->wedged = 0; | |
550a7375 FB |
1388 | |
1389 | /* set/clear the stall and toggle bits */ | |
5c8a86e1 | 1390 | dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear"); |
550a7375 FB |
1391 | if (musb_ep->is_in) { |
1392 | csr = musb_readw(epio, MUSB_TXCSR); | |
550a7375 FB |
1393 | csr |= MUSB_TXCSR_P_WZC_BITS |
1394 | | MUSB_TXCSR_CLRDATATOG; | |
1395 | if (value) | |
1396 | csr |= MUSB_TXCSR_P_SENDSTALL; | |
1397 | else | |
1398 | csr &= ~(MUSB_TXCSR_P_SENDSTALL | |
1399 | | MUSB_TXCSR_P_SENTSTALL); | |
1400 | csr &= ~MUSB_TXCSR_TXPKTRDY; | |
1401 | musb_writew(epio, MUSB_TXCSR, csr); | |
1402 | } else { | |
1403 | csr = musb_readw(epio, MUSB_RXCSR); | |
1404 | csr |= MUSB_RXCSR_P_WZC_BITS | |
1405 | | MUSB_RXCSR_FLUSHFIFO | |
1406 | | MUSB_RXCSR_CLRDATATOG; | |
1407 | if (value) | |
1408 | csr |= MUSB_RXCSR_P_SENDSTALL; | |
1409 | else | |
1410 | csr &= ~(MUSB_RXCSR_P_SENDSTALL | |
1411 | | MUSB_RXCSR_P_SENTSTALL); | |
1412 | musb_writew(epio, MUSB_RXCSR, csr); | |
1413 | } | |
1414 | ||
550a7375 FB |
1415 | /* maybe start the first request in the queue */ |
1416 | if (!musb_ep->busy && !value && request) { | |
5c8a86e1 | 1417 | dev_dbg(musb->controller, "restarting the request\n"); |
550a7375 FB |
1418 | musb_ep_restart(musb, request); |
1419 | } | |
1420 | ||
cea83241 | 1421 | done: |
550a7375 FB |
1422 | spin_unlock_irqrestore(&musb->lock, flags); |
1423 | return status; | |
1424 | } | |
1425 | ||
47e97605 SS |
1426 | /* |
1427 | * Sets the halt feature with the clear requests ignored | |
1428 | */ | |
1b6c3b0f | 1429 | static int musb_gadget_set_wedge(struct usb_ep *ep) |
47e97605 SS |
1430 | { |
1431 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1432 | ||
1433 | if (!ep) | |
1434 | return -EINVAL; | |
1435 | ||
1436 | musb_ep->wedged = 1; | |
1437 | ||
1438 | return usb_ep_set_halt(ep); | |
1439 | } | |
1440 | ||
550a7375 FB |
1441 | static int musb_gadget_fifo_status(struct usb_ep *ep) |
1442 | { | |
1443 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1444 | void __iomem *epio = musb_ep->hw_ep->regs; | |
1445 | int retval = -EINVAL; | |
1446 | ||
1447 | if (musb_ep->desc && !musb_ep->is_in) { | |
1448 | struct musb *musb = musb_ep->musb; | |
1449 | int epnum = musb_ep->current_epnum; | |
1450 | void __iomem *mbase = musb->mregs; | |
1451 | unsigned long flags; | |
1452 | ||
1453 | spin_lock_irqsave(&musb->lock, flags); | |
1454 | ||
1455 | musb_ep_select(mbase, epnum); | |
1456 | /* FIXME return zero unless RXPKTRDY is set */ | |
1457 | retval = musb_readw(epio, MUSB_RXCOUNT); | |
1458 | ||
1459 | spin_unlock_irqrestore(&musb->lock, flags); | |
1460 | } | |
1461 | return retval; | |
1462 | } | |
1463 | ||
1464 | static void musb_gadget_fifo_flush(struct usb_ep *ep) | |
1465 | { | |
1466 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1467 | struct musb *musb = musb_ep->musb; | |
1468 | u8 epnum = musb_ep->current_epnum; | |
1469 | void __iomem *epio = musb->endpoints[epnum].regs; | |
1470 | void __iomem *mbase; | |
1471 | unsigned long flags; | |
b18d26f6 | 1472 | u16 csr; |
550a7375 FB |
1473 | |
1474 | mbase = musb->mregs; | |
1475 | ||
1476 | spin_lock_irqsave(&musb->lock, flags); | |
1477 | musb_ep_select(mbase, (u8) epnum); | |
1478 | ||
1479 | /* disable interrupts */ | |
b18d26f6 | 1480 | musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe & ~(1 << epnum)); |
550a7375 FB |
1481 | |
1482 | if (musb_ep->is_in) { | |
1483 | csr = musb_readw(epio, MUSB_TXCSR); | |
1484 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) { | |
1485 | csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS; | |
4858f06e YK |
1486 | /* |
1487 | * Setting both TXPKTRDY and FLUSHFIFO makes controller | |
1488 | * to interrupt current FIFO loading, but not flushing | |
1489 | * the already loaded ones. | |
1490 | */ | |
1491 | csr &= ~MUSB_TXCSR_TXPKTRDY; | |
550a7375 FB |
1492 | musb_writew(epio, MUSB_TXCSR, csr); |
1493 | /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ | |
1494 | musb_writew(epio, MUSB_TXCSR, csr); | |
1495 | } | |
1496 | } else { | |
1497 | csr = musb_readw(epio, MUSB_RXCSR); | |
1498 | csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS; | |
1499 | musb_writew(epio, MUSB_RXCSR, csr); | |
1500 | musb_writew(epio, MUSB_RXCSR, csr); | |
1501 | } | |
1502 | ||
1503 | /* re-enable interrupt */ | |
b18d26f6 | 1504 | musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe); |
550a7375 FB |
1505 | spin_unlock_irqrestore(&musb->lock, flags); |
1506 | } | |
1507 | ||
1508 | static const struct usb_ep_ops musb_ep_ops = { | |
1509 | .enable = musb_gadget_enable, | |
1510 | .disable = musb_gadget_disable, | |
1511 | .alloc_request = musb_alloc_request, | |
1512 | .free_request = musb_free_request, | |
1513 | .queue = musb_gadget_queue, | |
1514 | .dequeue = musb_gadget_dequeue, | |
1515 | .set_halt = musb_gadget_set_halt, | |
47e97605 | 1516 | .set_wedge = musb_gadget_set_wedge, |
550a7375 FB |
1517 | .fifo_status = musb_gadget_fifo_status, |
1518 | .fifo_flush = musb_gadget_fifo_flush | |
1519 | }; | |
1520 | ||
1521 | /* ----------------------------------------------------------------------- */ | |
1522 | ||
1523 | static int musb_gadget_get_frame(struct usb_gadget *gadget) | |
1524 | { | |
1525 | struct musb *musb = gadget_to_musb(gadget); | |
1526 | ||
1527 | return (int)musb_readw(musb->mregs, MUSB_FRAME); | |
1528 | } | |
1529 | ||
1530 | static int musb_gadget_wakeup(struct usb_gadget *gadget) | |
1531 | { | |
1532 | struct musb *musb = gadget_to_musb(gadget); | |
1533 | void __iomem *mregs = musb->mregs; | |
1534 | unsigned long flags; | |
1535 | int status = -EINVAL; | |
1536 | u8 power, devctl; | |
1537 | int retries; | |
1538 | ||
1539 | spin_lock_irqsave(&musb->lock, flags); | |
1540 | ||
84e250ff | 1541 | switch (musb->xceiv->state) { |
550a7375 FB |
1542 | case OTG_STATE_B_PERIPHERAL: |
1543 | /* NOTE: OTG state machine doesn't include B_SUSPENDED; | |
1544 | * that's part of the standard usb 1.1 state machine, and | |
1545 | * doesn't affect OTG transitions. | |
1546 | */ | |
1547 | if (musb->may_wakeup && musb->is_suspended) | |
1548 | break; | |
1549 | goto done; | |
1550 | case OTG_STATE_B_IDLE: | |
1551 | /* Start SRP ... OTG not required. */ | |
1552 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
5c8a86e1 | 1553 | dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl); |
550a7375 FB |
1554 | devctl |= MUSB_DEVCTL_SESSION; |
1555 | musb_writeb(mregs, MUSB_DEVCTL, devctl); | |
1556 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1557 | retries = 100; | |
1558 | while (!(devctl & MUSB_DEVCTL_SESSION)) { | |
1559 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1560 | if (retries-- < 1) | |
1561 | break; | |
1562 | } | |
1563 | retries = 10000; | |
1564 | while (devctl & MUSB_DEVCTL_SESSION) { | |
1565 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1566 | if (retries-- < 1) | |
1567 | break; | |
1568 | } | |
1569 | ||
8620543e | 1570 | spin_unlock_irqrestore(&musb->lock, flags); |
6e13c650 | 1571 | otg_start_srp(musb->xceiv->otg); |
8620543e HH |
1572 | spin_lock_irqsave(&musb->lock, flags); |
1573 | ||
550a7375 FB |
1574 | /* Block idling for at least 1s */ |
1575 | musb_platform_try_idle(musb, | |
1576 | jiffies + msecs_to_jiffies(1 * HZ)); | |
1577 | ||
1578 | status = 0; | |
1579 | goto done; | |
1580 | default: | |
5c8a86e1 | 1581 | dev_dbg(musb->controller, "Unhandled wake: %s\n", |
42c0bf1c | 1582 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
1583 | goto done; |
1584 | } | |
1585 | ||
1586 | status = 0; | |
1587 | ||
1588 | power = musb_readb(mregs, MUSB_POWER); | |
1589 | power |= MUSB_POWER_RESUME; | |
1590 | musb_writeb(mregs, MUSB_POWER, power); | |
5c8a86e1 | 1591 | dev_dbg(musb->controller, "issue wakeup\n"); |
550a7375 FB |
1592 | |
1593 | /* FIXME do this next chunk in a timer callback, no udelay */ | |
1594 | mdelay(2); | |
1595 | ||
1596 | power = musb_readb(mregs, MUSB_POWER); | |
1597 | power &= ~MUSB_POWER_RESUME; | |
1598 | musb_writeb(mregs, MUSB_POWER, power); | |
1599 | done: | |
1600 | spin_unlock_irqrestore(&musb->lock, flags); | |
1601 | return status; | |
1602 | } | |
1603 | ||
1604 | static int | |
1605 | musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered) | |
1606 | { | |
1607 | struct musb *musb = gadget_to_musb(gadget); | |
1608 | ||
1609 | musb->is_self_powered = !!is_selfpowered; | |
1610 | return 0; | |
1611 | } | |
1612 | ||
1613 | static void musb_pullup(struct musb *musb, int is_on) | |
1614 | { | |
1615 | u8 power; | |
1616 | ||
1617 | power = musb_readb(musb->mregs, MUSB_POWER); | |
1618 | if (is_on) | |
1619 | power |= MUSB_POWER_SOFTCONN; | |
1620 | else | |
1621 | power &= ~MUSB_POWER_SOFTCONN; | |
1622 | ||
1623 | /* FIXME if on, HdrcStart; if off, HdrcStop */ | |
1624 | ||
e71eb392 SAS |
1625 | dev_dbg(musb->controller, "gadget D+ pullup %s\n", |
1626 | is_on ? "on" : "off"); | |
550a7375 FB |
1627 | musb_writeb(musb->mregs, MUSB_POWER, power); |
1628 | } | |
1629 | ||
1630 | #if 0 | |
1631 | static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active) | |
1632 | { | |
5c8a86e1 | 1633 | dev_dbg(musb->controller, "<= %s =>\n", __func__); |
550a7375 FB |
1634 | |
1635 | /* | |
1636 | * FIXME iff driver's softconnect flag is set (as it is during probe, | |
1637 | * though that can clear it), just musb_pullup(). | |
1638 | */ | |
1639 | ||
1640 | return -EINVAL; | |
1641 | } | |
1642 | #endif | |
1643 | ||
1644 | static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA) | |
1645 | { | |
1646 | struct musb *musb = gadget_to_musb(gadget); | |
1647 | ||
84e250ff | 1648 | if (!musb->xceiv->set_power) |
550a7375 | 1649 | return -EOPNOTSUPP; |
b96d3b08 | 1650 | return usb_phy_set_power(musb->xceiv, mA); |
550a7375 FB |
1651 | } |
1652 | ||
1653 | static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on) | |
1654 | { | |
1655 | struct musb *musb = gadget_to_musb(gadget); | |
1656 | unsigned long flags; | |
1657 | ||
1658 | is_on = !!is_on; | |
1659 | ||
93e098a8 JS |
1660 | pm_runtime_get_sync(musb->controller); |
1661 | ||
550a7375 FB |
1662 | /* NOTE: this assumes we are sensing vbus; we'd rather |
1663 | * not pullup unless the B-session is active. | |
1664 | */ | |
1665 | spin_lock_irqsave(&musb->lock, flags); | |
1666 | if (is_on != musb->softconnect) { | |
1667 | musb->softconnect = is_on; | |
1668 | musb_pullup(musb, is_on); | |
1669 | } | |
1670 | spin_unlock_irqrestore(&musb->lock, flags); | |
93e098a8 JS |
1671 | |
1672 | pm_runtime_put(musb->controller); | |
1673 | ||
550a7375 FB |
1674 | return 0; |
1675 | } | |
1676 | ||
e71eb392 SAS |
1677 | static int musb_gadget_start(struct usb_gadget *g, |
1678 | struct usb_gadget_driver *driver); | |
1679 | static int musb_gadget_stop(struct usb_gadget *g, | |
1680 | struct usb_gadget_driver *driver); | |
0f91349b | 1681 | |
550a7375 FB |
1682 | static const struct usb_gadget_ops musb_gadget_operations = { |
1683 | .get_frame = musb_gadget_get_frame, | |
1684 | .wakeup = musb_gadget_wakeup, | |
1685 | .set_selfpowered = musb_gadget_set_self_powered, | |
1686 | /* .vbus_session = musb_gadget_vbus_session, */ | |
1687 | .vbus_draw = musb_gadget_vbus_draw, | |
1688 | .pullup = musb_gadget_pullup, | |
e71eb392 SAS |
1689 | .udc_start = musb_gadget_start, |
1690 | .udc_stop = musb_gadget_stop, | |
550a7375 FB |
1691 | }; |
1692 | ||
1693 | /* ----------------------------------------------------------------------- */ | |
1694 | ||
1695 | /* Registration */ | |
1696 | ||
1697 | /* Only this registration code "knows" the rule (from USB standards) | |
1698 | * about there being only one external upstream port. It assumes | |
1699 | * all peripheral ports are external... | |
1700 | */ | |
550a7375 | 1701 | |
41ac7b3a | 1702 | static void |
550a7375 FB |
1703 | init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in) |
1704 | { | |
1705 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; | |
1706 | ||
1707 | memset(ep, 0, sizeof *ep); | |
1708 | ||
1709 | ep->current_epnum = epnum; | |
1710 | ep->musb = musb; | |
1711 | ep->hw_ep = hw_ep; | |
1712 | ep->is_in = is_in; | |
1713 | ||
1714 | INIT_LIST_HEAD(&ep->req_list); | |
1715 | ||
1716 | sprintf(ep->name, "ep%d%s", epnum, | |
1717 | (!epnum || hw_ep->is_shared_fifo) ? "" : ( | |
1718 | is_in ? "in" : "out")); | |
1719 | ep->end_point.name = ep->name; | |
1720 | INIT_LIST_HEAD(&ep->end_point.ep_list); | |
1721 | if (!epnum) { | |
1722 | ep->end_point.maxpacket = 64; | |
1723 | ep->end_point.ops = &musb_g_ep0_ops; | |
1724 | musb->g.ep0 = &ep->end_point; | |
1725 | } else { | |
1726 | if (is_in) | |
1727 | ep->end_point.maxpacket = hw_ep->max_packet_sz_tx; | |
1728 | else | |
1729 | ep->end_point.maxpacket = hw_ep->max_packet_sz_rx; | |
1730 | ep->end_point.ops = &musb_ep_ops; | |
1731 | list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list); | |
1732 | } | |
1733 | } | |
1734 | ||
1735 | /* | |
1736 | * Initialize the endpoints exposed to peripheral drivers, with backlinks | |
1737 | * to the rest of the driver state. | |
1738 | */ | |
41ac7b3a | 1739 | static inline void musb_g_init_endpoints(struct musb *musb) |
550a7375 FB |
1740 | { |
1741 | u8 epnum; | |
1742 | struct musb_hw_ep *hw_ep; | |
1743 | unsigned count = 0; | |
1744 | ||
b595076a | 1745 | /* initialize endpoint list just once */ |
550a7375 FB |
1746 | INIT_LIST_HEAD(&(musb->g.ep_list)); |
1747 | ||
1748 | for (epnum = 0, hw_ep = musb->endpoints; | |
1749 | epnum < musb->nr_endpoints; | |
1750 | epnum++, hw_ep++) { | |
1751 | if (hw_ep->is_shared_fifo /* || !epnum */) { | |
1752 | init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0); | |
1753 | count++; | |
1754 | } else { | |
1755 | if (hw_ep->max_packet_sz_tx) { | |
1756 | init_peripheral_ep(musb, &hw_ep->ep_in, | |
1757 | epnum, 1); | |
1758 | count++; | |
1759 | } | |
1760 | if (hw_ep->max_packet_sz_rx) { | |
1761 | init_peripheral_ep(musb, &hw_ep->ep_out, | |
1762 | epnum, 0); | |
1763 | count++; | |
1764 | } | |
1765 | } | |
1766 | } | |
1767 | } | |
1768 | ||
1769 | /* called once during driver setup to initialize and link into | |
1770 | * the driver model; memory is zeroed. | |
1771 | */ | |
41ac7b3a | 1772 | int musb_gadget_setup(struct musb *musb) |
550a7375 FB |
1773 | { |
1774 | int status; | |
1775 | ||
1776 | /* REVISIT minor race: if (erroneously) setting up two | |
1777 | * musb peripherals at the same time, only the bus lock | |
1778 | * is probably held. | |
1779 | */ | |
550a7375 FB |
1780 | |
1781 | musb->g.ops = &musb_gadget_operations; | |
d327ab5b | 1782 | musb->g.max_speed = USB_SPEED_HIGH; |
550a7375 FB |
1783 | musb->g.speed = USB_SPEED_UNKNOWN; |
1784 | ||
1785 | /* this "gadget" abstracts/virtualizes the controller */ | |
550a7375 | 1786 | musb->g.name = musb_driver_name; |
032ec49f | 1787 | musb->g.is_otg = 1; |
550a7375 FB |
1788 | |
1789 | musb_g_init_endpoints(musb); | |
1790 | ||
1791 | musb->is_active = 0; | |
1792 | musb_platform_try_idle(musb, 0); | |
1793 | ||
0f91349b SAS |
1794 | status = usb_add_gadget_udc(musb->controller, &musb->g); |
1795 | if (status) | |
1796 | goto err; | |
1797 | ||
1798 | return 0; | |
1799 | err: | |
6193d699 | 1800 | musb->g.dev.parent = NULL; |
0f91349b | 1801 | device_unregister(&musb->g.dev); |
550a7375 FB |
1802 | return status; |
1803 | } | |
1804 | ||
1805 | void musb_gadget_cleanup(struct musb *musb) | |
1806 | { | |
0f91349b | 1807 | usb_del_gadget_udc(&musb->g); |
550a7375 FB |
1808 | } |
1809 | ||
1810 | /* | |
1811 | * Register the gadget driver. Used by gadget drivers when | |
1812 | * registering themselves with the controller. | |
1813 | * | |
1814 | * -EINVAL something went wrong (not driver) | |
1815 | * -EBUSY another gadget is already using the controller | |
b595076a | 1816 | * -ENOMEM no memory to perform the operation |
550a7375 FB |
1817 | * |
1818 | * @param driver the gadget driver | |
1819 | * @return <0 if error, 0 if everything is fine | |
1820 | */ | |
e71eb392 SAS |
1821 | static int musb_gadget_start(struct usb_gadget *g, |
1822 | struct usb_gadget_driver *driver) | |
550a7375 | 1823 | { |
e71eb392 | 1824 | struct musb *musb = gadget_to_musb(g); |
d445b6da | 1825 | struct usb_otg *otg = musb->xceiv->otg; |
63eed2b5 | 1826 | unsigned long flags; |
032ec49f | 1827 | int retval = 0; |
550a7375 | 1828 | |
032ec49f FB |
1829 | if (driver->max_speed < USB_SPEED_HIGH) { |
1830 | retval = -EINVAL; | |
1831 | goto err; | |
1832 | } | |
550a7375 | 1833 | |
7acc6197 HH |
1834 | pm_runtime_get_sync(musb->controller); |
1835 | ||
5c8a86e1 | 1836 | dev_dbg(musb->controller, "registering driver %s\n", driver->function); |
550a7375 | 1837 | |
e71eb392 | 1838 | musb->softconnect = 0; |
63eed2b5 | 1839 | musb->gadget_driver = driver; |
550a7375 | 1840 | |
63eed2b5 | 1841 | spin_lock_irqsave(&musb->lock, flags); |
e71eb392 | 1842 | musb->is_active = 1; |
550a7375 | 1843 | |
6e13c650 | 1844 | otg_set_peripheral(otg, &musb->g); |
63eed2b5 | 1845 | musb->xceiv->state = OTG_STATE_B_IDLE; |
63eed2b5 | 1846 | spin_unlock_irqrestore(&musb->lock, flags); |
550a7375 | 1847 | |
032ec49f FB |
1848 | /* REVISIT: funcall to other code, which also |
1849 | * handles power budgeting ... this way also | |
1850 | * ensures HdrcStart is indirectly called. | |
1851 | */ | |
b65ae0f1 GI |
1852 | if (musb->xceiv->last_event == USB_EVENT_ID) |
1853 | musb_platform_set_vbus(musb, 1); | |
63eed2b5 | 1854 | |
cdefce16 JN |
1855 | if (musb->xceiv->last_event == USB_EVENT_NONE) |
1856 | pm_runtime_put(musb->controller); | |
550a7375 | 1857 | |
63eed2b5 FB |
1858 | return 0; |
1859 | ||
032ec49f | 1860 | err: |
550a7375 FB |
1861 | return retval; |
1862 | } | |
550a7375 FB |
1863 | |
1864 | static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver) | |
1865 | { | |
1866 | int i; | |
1867 | struct musb_hw_ep *hw_ep; | |
1868 | ||
1869 | /* don't disconnect if it's not connected */ | |
1870 | if (musb->g.speed == USB_SPEED_UNKNOWN) | |
1871 | driver = NULL; | |
1872 | else | |
1873 | musb->g.speed = USB_SPEED_UNKNOWN; | |
1874 | ||
1875 | /* deactivate the hardware */ | |
1876 | if (musb->softconnect) { | |
1877 | musb->softconnect = 0; | |
1878 | musb_pullup(musb, 0); | |
1879 | } | |
1880 | musb_stop(musb); | |
1881 | ||
1882 | /* killing any outstanding requests will quiesce the driver; | |
1883 | * then report disconnect | |
1884 | */ | |
1885 | if (driver) { | |
1886 | for (i = 0, hw_ep = musb->endpoints; | |
1887 | i < musb->nr_endpoints; | |
1888 | i++, hw_ep++) { | |
1889 | musb_ep_select(musb->mregs, i); | |
1890 | if (hw_ep->is_shared_fifo /* || !epnum */) { | |
1891 | nuke(&hw_ep->ep_in, -ESHUTDOWN); | |
1892 | } else { | |
1893 | if (hw_ep->max_packet_sz_tx) | |
1894 | nuke(&hw_ep->ep_in, -ESHUTDOWN); | |
1895 | if (hw_ep->max_packet_sz_rx) | |
1896 | nuke(&hw_ep->ep_out, -ESHUTDOWN); | |
1897 | } | |
1898 | } | |
550a7375 FB |
1899 | } |
1900 | } | |
1901 | ||
1902 | /* | |
1903 | * Unregister the gadget driver. Used by gadget drivers when | |
1904 | * unregistering themselves from the controller. | |
1905 | * | |
1906 | * @param driver the gadget driver to unregister | |
1907 | */ | |
e71eb392 SAS |
1908 | static int musb_gadget_stop(struct usb_gadget *g, |
1909 | struct usb_gadget_driver *driver) | |
550a7375 | 1910 | { |
e71eb392 | 1911 | struct musb *musb = gadget_to_musb(g); |
63eed2b5 | 1912 | unsigned long flags; |
550a7375 | 1913 | |
7acc6197 HH |
1914 | if (musb->xceiv->last_event == USB_EVENT_NONE) |
1915 | pm_runtime_get_sync(musb->controller); | |
1916 | ||
63eed2b5 FB |
1917 | /* |
1918 | * REVISIT always use otg_set_peripheral() here too; | |
550a7375 FB |
1919 | * this needs to shut down the OTG engine. |
1920 | */ | |
1921 | ||
1922 | spin_lock_irqsave(&musb->lock, flags); | |
1923 | ||
550a7375 | 1924 | musb_hnp_stop(musb); |
550a7375 | 1925 | |
63eed2b5 | 1926 | (void) musb_gadget_vbus_draw(&musb->g, 0); |
550a7375 | 1927 | |
63eed2b5 FB |
1928 | musb->xceiv->state = OTG_STATE_UNDEFINED; |
1929 | stop_activity(musb, driver); | |
6e13c650 | 1930 | otg_set_peripheral(musb->xceiv->otg, NULL); |
550a7375 | 1931 | |
5c8a86e1 | 1932 | dev_dbg(musb->controller, "unregistering driver %s\n", driver->function); |
550a7375 | 1933 | |
63eed2b5 | 1934 | musb->is_active = 0; |
e21de10c | 1935 | musb->gadget_driver = NULL; |
63eed2b5 | 1936 | musb_platform_try_idle(musb, 0); |
550a7375 FB |
1937 | spin_unlock_irqrestore(&musb->lock, flags); |
1938 | ||
032ec49f FB |
1939 | /* |
1940 | * FIXME we need to be able to register another | |
1941 | * gadget driver here and have everything work; | |
1942 | * that currently misbehaves. | |
1943 | */ | |
63eed2b5 | 1944 | |
7acc6197 HH |
1945 | pm_runtime_put(musb->controller); |
1946 | ||
63eed2b5 | 1947 | return 0; |
550a7375 | 1948 | } |
550a7375 FB |
1949 | |
1950 | /* ----------------------------------------------------------------------- */ | |
1951 | ||
1952 | /* lifecycle operations called through plat_uds.c */ | |
1953 | ||
1954 | void musb_g_resume(struct musb *musb) | |
1955 | { | |
1956 | musb->is_suspended = 0; | |
84e250ff | 1957 | switch (musb->xceiv->state) { |
550a7375 FB |
1958 | case OTG_STATE_B_IDLE: |
1959 | break; | |
1960 | case OTG_STATE_B_WAIT_ACON: | |
1961 | case OTG_STATE_B_PERIPHERAL: | |
1962 | musb->is_active = 1; | |
1963 | if (musb->gadget_driver && musb->gadget_driver->resume) { | |
1964 | spin_unlock(&musb->lock); | |
1965 | musb->gadget_driver->resume(&musb->g); | |
1966 | spin_lock(&musb->lock); | |
1967 | } | |
1968 | break; | |
1969 | default: | |
1970 | WARNING("unhandled RESUME transition (%s)\n", | |
42c0bf1c | 1971 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
1972 | } |
1973 | } | |
1974 | ||
1975 | /* called when SOF packets stop for 3+ msec */ | |
1976 | void musb_g_suspend(struct musb *musb) | |
1977 | { | |
1978 | u8 devctl; | |
1979 | ||
1980 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
5c8a86e1 | 1981 | dev_dbg(musb->controller, "devctl %02x\n", devctl); |
550a7375 | 1982 | |
84e250ff | 1983 | switch (musb->xceiv->state) { |
550a7375 FB |
1984 | case OTG_STATE_B_IDLE: |
1985 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
84e250ff | 1986 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
1987 | break; |
1988 | case OTG_STATE_B_PERIPHERAL: | |
1989 | musb->is_suspended = 1; | |
1990 | if (musb->gadget_driver && musb->gadget_driver->suspend) { | |
1991 | spin_unlock(&musb->lock); | |
1992 | musb->gadget_driver->suspend(&musb->g); | |
1993 | spin_lock(&musb->lock); | |
1994 | } | |
1995 | break; | |
1996 | default: | |
1997 | /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ; | |
1998 | * A_PERIPHERAL may need care too | |
1999 | */ | |
2000 | WARNING("unhandled SUSPEND transition (%s)\n", | |
42c0bf1c | 2001 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
2002 | } |
2003 | } | |
2004 | ||
2005 | /* Called during SRP */ | |
2006 | void musb_g_wakeup(struct musb *musb) | |
2007 | { | |
2008 | musb_gadget_wakeup(&musb->g); | |
2009 | } | |
2010 | ||
2011 | /* called when VBUS drops below session threshold, and in other cases */ | |
2012 | void musb_g_disconnect(struct musb *musb) | |
2013 | { | |
2014 | void __iomem *mregs = musb->mregs; | |
2015 | u8 devctl = musb_readb(mregs, MUSB_DEVCTL); | |
2016 | ||
5c8a86e1 | 2017 | dev_dbg(musb->controller, "devctl %02x\n", devctl); |
550a7375 FB |
2018 | |
2019 | /* clear HR */ | |
2020 | musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION); | |
2021 | ||
2022 | /* don't draw vbus until new b-default session */ | |
2023 | (void) musb_gadget_vbus_draw(&musb->g, 0); | |
2024 | ||
2025 | musb->g.speed = USB_SPEED_UNKNOWN; | |
2026 | if (musb->gadget_driver && musb->gadget_driver->disconnect) { | |
2027 | spin_unlock(&musb->lock); | |
2028 | musb->gadget_driver->disconnect(&musb->g); | |
2029 | spin_lock(&musb->lock); | |
2030 | } | |
2031 | ||
84e250ff | 2032 | switch (musb->xceiv->state) { |
550a7375 | 2033 | default: |
5c8a86e1 | 2034 | dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n", |
42c0bf1c | 2035 | usb_otg_state_string(musb->xceiv->state)); |
84e250ff | 2036 | musb->xceiv->state = OTG_STATE_A_IDLE; |
ab983f2a | 2037 | MUSB_HST_MODE(musb); |
550a7375 FB |
2038 | break; |
2039 | case OTG_STATE_A_PERIPHERAL: | |
1de00dae | 2040 | musb->xceiv->state = OTG_STATE_A_WAIT_BCON; |
ab983f2a | 2041 | MUSB_HST_MODE(musb); |
550a7375 FB |
2042 | break; |
2043 | case OTG_STATE_B_WAIT_ACON: | |
2044 | case OTG_STATE_B_HOST: | |
550a7375 FB |
2045 | case OTG_STATE_B_PERIPHERAL: |
2046 | case OTG_STATE_B_IDLE: | |
84e250ff | 2047 | musb->xceiv->state = OTG_STATE_B_IDLE; |
550a7375 FB |
2048 | break; |
2049 | case OTG_STATE_B_SRP_INIT: | |
2050 | break; | |
2051 | } | |
2052 | ||
2053 | musb->is_active = 0; | |
2054 | } | |
2055 | ||
2056 | void musb_g_reset(struct musb *musb) | |
2057 | __releases(musb->lock) | |
2058 | __acquires(musb->lock) | |
2059 | { | |
2060 | void __iomem *mbase = musb->mregs; | |
2061 | u8 devctl = musb_readb(mbase, MUSB_DEVCTL); | |
2062 | u8 power; | |
2063 | ||
515ba29c | 2064 | dev_dbg(musb->controller, "<== %s driver '%s'\n", |
550a7375 FB |
2065 | (devctl & MUSB_DEVCTL_BDEVICE) |
2066 | ? "B-Device" : "A-Device", | |
550a7375 FB |
2067 | musb->gadget_driver |
2068 | ? musb->gadget_driver->driver.name | |
2069 | : NULL | |
2070 | ); | |
2071 | ||
2072 | /* report disconnect, if we didn't already (flushing EP state) */ | |
2073 | if (musb->g.speed != USB_SPEED_UNKNOWN) | |
2074 | musb_g_disconnect(musb); | |
2075 | ||
2076 | /* clear HR */ | |
2077 | else if (devctl & MUSB_DEVCTL_HR) | |
2078 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
2079 | ||
2080 | ||
2081 | /* what speed did we negotiate? */ | |
2082 | power = musb_readb(mbase, MUSB_POWER); | |
2083 | musb->g.speed = (power & MUSB_POWER_HSMODE) | |
2084 | ? USB_SPEED_HIGH : USB_SPEED_FULL; | |
2085 | ||
2086 | /* start in USB_STATE_DEFAULT */ | |
2087 | musb->is_active = 1; | |
2088 | musb->is_suspended = 0; | |
2089 | MUSB_DEV_MODE(musb); | |
2090 | musb->address = 0; | |
2091 | musb->ep0_state = MUSB_EP0_STAGE_SETUP; | |
2092 | ||
2093 | musb->may_wakeup = 0; | |
2094 | musb->g.b_hnp_enable = 0; | |
2095 | musb->g.a_alt_hnp_support = 0; | |
2096 | musb->g.a_hnp_support = 0; | |
2097 | ||
2098 | /* Normal reset, as B-Device; | |
2099 | * or else after HNP, as A-Device | |
2100 | */ | |
2101 | if (devctl & MUSB_DEVCTL_BDEVICE) { | |
84e250ff | 2102 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 | 2103 | musb->g.is_a_peripheral = 0; |
032ec49f | 2104 | } else { |
84e250ff | 2105 | musb->xceiv->state = OTG_STATE_A_PERIPHERAL; |
550a7375 | 2106 | musb->g.is_a_peripheral = 1; |
032ec49f | 2107 | } |
550a7375 FB |
2108 | |
2109 | /* start with default limits on VBUS power draw */ | |
032ec49f | 2110 | (void) musb_gadget_vbus_draw(&musb->g, 8); |
550a7375 | 2111 | } |