[deliverable/linux.git] / drivers / usb / musb / musb_regs.h

/*
 * MUSB OTG driver register defines
 *
 * Copyright 2005 Mentor Graphics Corporation
 * Copyright (C) 2005-2006 by Texas Instruments
 * Copyright (C) 2006-2007 Nokia Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#ifndef __MUSB_REGS_H__
#define __MUSB_REGS_H__

#define MUSB_EP0_FIFOSIZE	64	/* This is non-configurable */

/*
 * MUSB Register bits
 */

/* POWER */
#define MUSB_POWER_ISOUPDATE	0x80
#define MUSB_POWER_SOFTCONN	0x40
#define MUSB_POWER_HSENAB	0x20
#define MUSB_POWER_HSMODE	0x10
#define MUSB_POWER_RESET	0x08
#define MUSB_POWER_RESUME	0x04
#define MUSB_POWER_SUSPENDM	0x02
#define MUSB_POWER_ENSUSPEND	0x01

/* INTRUSB */
#define MUSB_INTR_SUSPEND	0x01
#define MUSB_INTR_RESUME	0x02
#define MUSB_INTR_RESET		0x04
#define MUSB_INTR_BABBLE	0x04
#define MUSB_INTR_SOF		0x08
#define MUSB_INTR_CONNECT	0x10
#define MUSB_INTR_DISCONNECT	0x20
#define MUSB_INTR_SESSREQ	0x40
#define MUSB_INTR_VBUSERROR	0x80	/* For SESSION end */

/* DEVCTL */
#define MUSB_DEVCTL_BDEVICE	0x80
#define MUSB_DEVCTL_FSDEV	0x40
#define MUSB_DEVCTL_LSDEV	0x20
#define MUSB_DEVCTL_VBUS	0x18
#define MUSB_DEVCTL_VBUS_SHIFT	3
#define MUSB_DEVCTL_HM		0x04
#define MUSB_DEVCTL_HR		0x02
#define MUSB_DEVCTL_SESSION	0x01

/* TESTMODE */
#define MUSB_TEST_FORCE_HOST	0x80
#define MUSB_TEST_FIFO_ACCESS	0x40
#define MUSB_TEST_FORCE_FS	0x20
#define MUSB_TEST_FORCE_HS	0x10
#define MUSB_TEST_PACKET	0x08
#define MUSB_TEST_K		0x04
#define MUSB_TEST_J		0x02
#define MUSB_TEST_SE0_NAK	0x01

/* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
#define MUSB_FIFOSZ_DPB	0x10
/* Allocation size (8, 16, 32, ... 4096) */
#define MUSB_FIFOSZ_SIZE	0x0f

/* CSR0 */
#define MUSB_CSR0_FLUSHFIFO	0x0100
#define MUSB_CSR0_TXPKTRDY	0x0002
#define MUSB_CSR0_RXPKTRDY	0x0001

/* CSR0 in Peripheral mode */
#define MUSB_CSR0_P_SVDSETUPEND	0x0080
#define MUSB_CSR0_P_SVDRXPKTRDY	0x0040
#define MUSB_CSR0_P_SENDSTALL	0x0020
#define MUSB_CSR0_P_SETUPEND	0x0010
#define MUSB_CSR0_P_DATAEND	0x0008
#define MUSB_CSR0_P_SENTSTALL	0x0004

/* CSR0 in Host mode */
#define MUSB_CSR0_H_DIS_PING		0x0800
#define MUSB_CSR0_H_WR_DATATOGGLE	0x0400	/* Set to allow setting: */
#define MUSB_CSR0_H_DATATOGGLE		0x0200	/* Data toggle control */
#define MUSB_CSR0_H_NAKTIMEOUT		0x0080
#define MUSB_CSR0_H_STATUSPKT		0x0040
#define MUSB_CSR0_H_REQPKT		0x0020
#define MUSB_CSR0_H_ERROR		0x0010
#define MUSB_CSR0_H_SETUPPKT		0x0008
#define MUSB_CSR0_H_RXSTALL		0x0004

/* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
#define MUSB_CSR0_P_WZC_BITS	\
	(MUSB_CSR0_P_SENTSTALL)
#define MUSB_CSR0_H_WZC_BITS	\
	(MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
	| MUSB_CSR0_RXPKTRDY)

/* TxType/RxType */
#define MUSB_TYPE_SPEED		0xc0
#define MUSB_TYPE_SPEED_SHIFT	6
#define MUSB_TYPE_PROTO		0x30	/* Implicitly zero for ep0 */
#define MUSB_TYPE_PROTO_SHIFT	4
#define MUSB_TYPE_REMOTE_END	0xf	/* Implicitly zero for ep0 */

/* CONFIGDATA */
#define MUSB_CONFIGDATA_MPRXE		0x80	/* Auto bulk pkt combining */
#define MUSB_CONFIGDATA_MPTXE		0x40	/* Auto bulk pkt splitting */
#define MUSB_CONFIGDATA_BIGENDIAN	0x20
#define MUSB_CONFIGDATA_HBRXE		0x10	/* HB-ISO for RX */
#define MUSB_CONFIGDATA_HBTXE		0x08	/* HB-ISO for TX */
#define MUSB_CONFIGDATA_DYNFIFO		0x04	/* Dynamic FIFO sizing */
#define MUSB_CONFIGDATA_SOFTCONE	0x02	/* SoftConnect */
#define MUSB_CONFIGDATA_UTMIDW		0x01	/* Data width 0/1 => 8/16bits */

/* TXCSR in Peripheral and Host mode */
#define MUSB_TXCSR_AUTOSET		0x8000
#define MUSB_TXCSR_DMAENAB		0x1000
#define MUSB_TXCSR_FRCDATATOG		0x0800
#define MUSB_TXCSR_DMAMODE		0x0400
#define MUSB_TXCSR_CLRDATATOG		0x0040
#define MUSB_TXCSR_FLUSHFIFO		0x0008
#define MUSB_TXCSR_FIFONOTEMPTY		0x0002
#define MUSB_TXCSR_TXPKTRDY		0x0001

/* TXCSR in Peripheral mode */
#define MUSB_TXCSR_P_ISO		0x4000
#define MUSB_TXCSR_P_INCOMPTX		0x0080
#define MUSB_TXCSR_P_SENTSTALL		0x0020
#define MUSB_TXCSR_P_SENDSTALL		0x0010
#define MUSB_TXCSR_P_UNDERRUN		0x0004

/* TXCSR in Host mode */
#define MUSB_TXCSR_H_WR_DATATOGGLE	0x0200
#define MUSB_TXCSR_H_DATATOGGLE		0x0100
#define MUSB_TXCSR_H_NAKTIMEOUT		0x0080
#define MUSB_TXCSR_H_RXSTALL		0x0020
#define MUSB_TXCSR_H_ERROR		0x0004

/* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
#define MUSB_TXCSR_P_WZC_BITS	\
	(MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
	| MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
#define MUSB_TXCSR_H_WZC_BITS	\
	(MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
	| MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)

/* RXCSR in Peripheral and Host mode */
#define MUSB_RXCSR_AUTOCLEAR		0x8000
#define MUSB_RXCSR_DMAENAB		0x2000
#define MUSB_RXCSR_DISNYET		0x1000
#define MUSB_RXCSR_PID_ERR		0x1000
#define MUSB_RXCSR_DMAMODE		0x0800
#define MUSB_RXCSR_INCOMPRX		0x0100
#define MUSB_RXCSR_CLRDATATOG		0x0080
#define MUSB_RXCSR_FLUSHFIFO		0x0010
#define MUSB_RXCSR_DATAERROR		0x0008
#define MUSB_RXCSR_FIFOFULL		0x0002
#define MUSB_RXCSR_RXPKTRDY		0x0001

/* RXCSR in Peripheral mode */
#define MUSB_RXCSR_P_ISO		0x4000
#define MUSB_RXCSR_P_SENTSTALL		0x0040
#define MUSB_RXCSR_P_SENDSTALL		0x0020
#define MUSB_RXCSR_P_OVERRUN		0x0004

/* RXCSR in Host mode */
#define MUSB_RXCSR_H_AUTOREQ		0x4000
#define MUSB_RXCSR_H_WR_DATATOGGLE	0x0400
#define MUSB_RXCSR_H_DATATOGGLE		0x0200
#define MUSB_RXCSR_H_RXSTALL		0x0040
#define MUSB_RXCSR_H_REQPKT		0x0020
#define MUSB_RXCSR_H_ERROR		0x0004

/* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
#define MUSB_RXCSR_P_WZC_BITS	\
	(MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
	| MUSB_RXCSR_RXPKTRDY)
#define MUSB_RXCSR_H_WZC_BITS	\
	(MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
	| MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)

/* HUBADDR */
#define MUSB_HUBADDR_MULTI_TT		0x80


#ifndef CONFIG_BLACKFIN

/*
 * Common USB registers
 */

#define MUSB_FADDR		0x00	/* 8-bit */
#define MUSB_POWER		0x01	/* 8-bit */

#define MUSB_INTRTX		0x02	/* 16-bit */
#define MUSB_INTRRX		0x04
#define MUSB_INTRTXE		0x06
#define MUSB_INTRRXE		0x08
#define MUSB_INTRUSB		0x0A	/* 8 bit */
#define MUSB_INTRUSBE		0x0B	/* 8 bit */
#define MUSB_FRAME		0x0C
#define MUSB_INDEX		0x0E	/* 8 bit */
#define MUSB_TESTMODE		0x0F	/* 8 bit */

/* Get offset for a given FIFO from musb->mregs */
#ifdef	CONFIG_USB_TUSB6010
#define MUSB_FIFO_OFFSET(epnum)	(0x200 + ((epnum) * 0x20))
#else
#define MUSB_FIFO_OFFSET(epnum)	(0x20 + ((epnum) * 4))
#endif

/*
 * Additional Control Registers
 */

#define MUSB_DEVCTL		0x60	/* 8 bit */

/* These are always controlled through the INDEX register */
#define MUSB_TXFIFOSZ		0x62	/* 8-bit (see masks) */
#define MUSB_RXFIFOSZ		0x63	/* 8-bit (see masks) */
#define MUSB_TXFIFOADD		0x64	/* 16-bit offset shifted right 3 */
#define MUSB_RXFIFOADD		0x66	/* 16-bit offset shifted right 3 */

/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
#define MUSB_HWVERS		0x6C	/* 8 bit */

#define MUSB_EPINFO		0x78	/* 8 bit */
#define MUSB_RAMINFO		0x79	/* 8 bit */
#define MUSB_LINKINFO		0x7a	/* 8 bit */
#define MUSB_VPLEN		0x7b	/* 8 bit */
#define MUSB_HS_EOF1		0x7c	/* 8 bit */
#define MUSB_FS_EOF1		0x7d	/* 8 bit */
#define MUSB_LS_EOF1		0x7e	/* 8 bit */

/* Offsets to endpoint registers */
#define MUSB_TXMAXP		0x00
#define MUSB_TXCSR		0x02
#define MUSB_CSR0		MUSB_TXCSR	/* Re-used for EP0 */
#define MUSB_RXMAXP		0x04
#define MUSB_RXCSR		0x06
#define MUSB_RXCOUNT		0x08
#define MUSB_COUNT0		MUSB_RXCOUNT	/* Re-used for EP0 */
#define MUSB_TXTYPE		0x0A
#define MUSB_TYPE0		MUSB_TXTYPE	/* Re-used for EP0 */
#define MUSB_TXINTERVAL		0x0B
#define MUSB_NAKLIMIT0		MUSB_TXINTERVAL	/* Re-used for EP0 */
#define MUSB_RXTYPE		0x0C
#define MUSB_RXINTERVAL		0x0D
#define MUSB_FIFOSIZE		0x0F
#define MUSB_CONFIGDATA		MUSB_FIFOSIZE	/* Re-used for EP0 */

/* Offsets to endpoint registers in indexed model (using INDEX register) */
#define MUSB_INDEXED_OFFSET(_epnum, _offset)	\
	(0x10 + (_offset))

/* Offsets to endpoint registers in flat models */
#define MUSB_FLAT_OFFSET(_epnum, _offset)	\
	(0x100 + (0x10*(_epnum)) + (_offset))

#ifdef CONFIG_USB_TUSB6010
/* TUSB6010 EP0 configuration register is special */
#define MUSB_TUSB_OFFSET(_epnum, _offset)	\
	(0x10 + _offset)
#include "tusb6010.h"		/* Needed "only" for TUSB_EP0_CONF */
#endif

#define MUSB_TXCSR_MODE			0x2000

/* "bus control"/target registers, for host side multipoint (external hubs) */
#define MUSB_TXFUNCADDR		0x00
#define MUSB_TXHUBADDR		0x02
#define MUSB_TXHUBPORT		0x03

#define MUSB_RXFUNCADDR		0x04
#define MUSB_RXHUBADDR		0x06
#define MUSB_RXHUBPORT		0x07

#define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
	(0x80 + (8*(_epnum)) + (_offset))

static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
{
	musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
}

static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
{
	musb_writew(mbase, MUSB_TXFIFOADD, c_off);
}

static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
{
	musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
}

static inline void  musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
{
	musb_writew(mbase, MUSB_RXFIFOADD, c_off);
}

static inline u8 musb_read_configdata(void __iomem *mbase)
{
	musb_writeb(mbase, MUSB_INDEX, 0);
	return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
}

static inline u16 musb_read_hwvers(void __iomem *mbase)
{
	return musb_readw(mbase, MUSB_HWVERS);
}

static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
{
	return (MUSB_BUSCTL_OFFSET(i, 0) + mbase);
}

static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
		u8 qh_addr_reg)
{
	musb_writeb(ep_target_regs, MUSB_RXFUNCADDR, qh_addr_reg);
}

static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
		u8 qh_h_addr_reg)
{
	musb_writeb(ep_target_regs, MUSB_RXHUBADDR, qh_h_addr_reg);
}

static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
		u8 qh_h_port_reg)
{
	musb_writeb(ep_target_regs, MUSB_RXHUBPORT, qh_h_port_reg);
}

static inline void  musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
		u8 qh_addr_reg)
{
	musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR),
			qh_addr_reg);
}

static inline void  musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
		u8 qh_addr_reg)
{
	musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR),
			qh_addr_reg);
}

static inline void  musb_write_txhubport(void __iomem *mbase, u8 epnum,
		u8 qh_h_port_reg)
{
	musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT),
			qh_h_port_reg);
}

#else /* CONFIG_BLACKFIN */

#define USB_BASE		USB_FADDR
#define USB_OFFSET(reg)		(reg - USB_BASE)

/*
 * Common USB registers
 */
#define MUSB_FADDR		USB_OFFSET(USB_FADDR)	/* 8-bit */
#define MUSB_POWER		USB_OFFSET(USB_POWER)	/* 8-bit */
#define MUSB_INTRTX		USB_OFFSET(USB_INTRTX)	/* 16-bit */
#define MUSB_INTRRX		USB_OFFSET(USB_INTRRX)
#define MUSB_INTRTXE		USB_OFFSET(USB_INTRTXE)
#define MUSB_INTRRXE		USB_OFFSET(USB_INTRRXE)
#define MUSB_INTRUSB		USB_OFFSET(USB_INTRUSB)	/* 8 bit */
#define MUSB_INTRUSBE		USB_OFFSET(USB_INTRUSBE)/* 8 bit */
#define MUSB_FRAME		USB_OFFSET(USB_FRAME)
#define MUSB_INDEX		USB_OFFSET(USB_INDEX)	/* 8 bit */
#define MUSB_TESTMODE		USB_OFFSET(USB_TESTMODE)/* 8 bit */

/* Get offset for a given FIFO from musb->mregs */
#define MUSB_FIFO_OFFSET(epnum)	\
	(USB_OFFSET(USB_EP0_FIFO) + ((epnum) * 8))

/*
 * Additional Control Registers
 */

#define MUSB_DEVCTL		USB_OFFSET(USB_OTG_DEV_CTL)	/* 8 bit */

#define MUSB_LINKINFO		USB_OFFSET(USB_LINKINFO)/* 8 bit */
#define MUSB_VPLEN		USB_OFFSET(USB_VPLEN)	/* 8 bit */
#define MUSB_HS_EOF1		USB_OFFSET(USB_HS_EOF1)	/* 8 bit */
#define MUSB_FS_EOF1		USB_OFFSET(USB_FS_EOF1)	/* 8 bit */
#define MUSB_LS_EOF1		USB_OFFSET(USB_LS_EOF1)	/* 8 bit */

/* Offsets to endpoint registers */
#define MUSB_TXMAXP		0x00
#define MUSB_TXCSR		0x04
#define MUSB_CSR0		MUSB_TXCSR	/* Re-used for EP0 */
#define MUSB_RXMAXP		0x08
#define MUSB_RXCSR		0x0C
#define MUSB_RXCOUNT		0x10
#define MUSB_COUNT0		MUSB_RXCOUNT	/* Re-used for EP0 */
#define MUSB_TXTYPE		0x14
#define MUSB_TYPE0		MUSB_TXTYPE	/* Re-used for EP0 */
#define MUSB_TXINTERVAL		0x18
#define MUSB_NAKLIMIT0		MUSB_TXINTERVAL	/* Re-used for EP0 */
#define MUSB_RXTYPE		0x1C
#define MUSB_RXINTERVAL		0x20
#define MUSB_TXCOUNT		0x28

/* Offsets to endpoint registers in indexed model (using INDEX register) */
#define MUSB_INDEXED_OFFSET(_epnum, _offset)	\
	(0x40 + (_offset))

/* Offsets to endpoint registers in flat models */
#define MUSB_FLAT_OFFSET(_epnum, _offset)	\
	(USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))

/* Not implemented - HW has seperate Tx/Rx FIFO */
#define MUSB_TXCSR_MODE			0x0000

static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
{
}

static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
{
}

static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
{
}

static inline void  musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
{
}

static inline u8 musb_read_configdata(void __iomem *mbase)
{
	return 0;
}

static inline u16 musb_read_hwvers(void __iomem *mbase)
{
	return 0;
}

static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase)
{
	return NULL;
}

static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
		u8 qh_addr_req)
{
}

static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
		u8 qh_h_addr_reg)
{
}

static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
		u8 qh_h_port_reg)
{
}

static inline void  musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
		u8 qh_addr_reg)
{
}

static inline void  musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
		u8 qh_addr_reg)
{
}

static inline void  musb_write_txhubport(void __iomem *mbase, u8 epnum,
		u8 qh_h_port_reg)
{
}

#endif /* CONFIG_BLACKFIN */

#endif	/* __MUSB_REGS_H__ */
Commit	Line	Data
550a7375 FB	1	/*
	2	* MUSB OTG driver register defines
	3	*
	4	* Copyright 2005 Mentor Graphics Corporation
	5	* Copyright (C) 2005-2006 by Texas Instruments
	6	* Copyright (C) 2006-2007 Nokia Corporation
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* version 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	20	* 02110-1301 USA
	21	*
	22	* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
	23	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	24	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	25	* NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
	26	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	27	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	28	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	29	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	30	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	31	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	32	*
	33	*/
	34
	35	#ifndef __MUSB_REGS_H__
	36	#define __MUSB_REGS_H__
	37
	38	#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
	39
550a7375 FB	40	/*
	41	* MUSB Register bits
	42	*/
	43
	44	/* POWER */
	45	#define MUSB_POWER_ISOUPDATE 0x80
	46	#define MUSB_POWER_SOFTCONN 0x40
	47	#define MUSB_POWER_HSENAB 0x20
	48	#define MUSB_POWER_HSMODE 0x10
	49	#define MUSB_POWER_RESET 0x08
	50	#define MUSB_POWER_RESUME 0x04
	51	#define MUSB_POWER_SUSPENDM 0x02
	52	#define MUSB_POWER_ENSUSPEND 0x01
	53
	54	/* INTRUSB */
	55	#define MUSB_INTR_SUSPEND 0x01
	56	#define MUSB_INTR_RESUME 0x02
	57	#define MUSB_INTR_RESET 0x04
	58	#define MUSB_INTR_BABBLE 0x04
	59	#define MUSB_INTR_SOF 0x08
	60	#define MUSB_INTR_CONNECT 0x10
	61	#define MUSB_INTR_DISCONNECT 0x20
	62	#define MUSB_INTR_SESSREQ 0x40
	63	#define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */
	64
	65	/* DEVCTL */
	66	#define MUSB_DEVCTL_BDEVICE 0x80
	67	#define MUSB_DEVCTL_FSDEV 0x40
	68	#define MUSB_DEVCTL_LSDEV 0x20
	69	#define MUSB_DEVCTL_VBUS 0x18
	70	#define MUSB_DEVCTL_VBUS_SHIFT 3
	71	#define MUSB_DEVCTL_HM 0x04
	72	#define MUSB_DEVCTL_HR 0x02
	73	#define MUSB_DEVCTL_SESSION 0x01
	74
	75	/* TESTMODE */
	76	#define MUSB_TEST_FORCE_HOST 0x80
	77	#define MUSB_TEST_FIFO_ACCESS 0x40
	78	#define MUSB_TEST_FORCE_FS 0x20
	79	#define MUSB_TEST_FORCE_HS 0x10
	80	#define MUSB_TEST_PACKET 0x08
	81	#define MUSB_TEST_K 0x04
	82	#define MUSB_TEST_J 0x02
	83	#define MUSB_TEST_SE0_NAK 0x01
	84
	85	/* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
	86	#define MUSB_FIFOSZ_DPB 0x10
	87	/* Allocation size (8, 16, 32, ... 4096) */
	88	#define MUSB_FIFOSZ_SIZE 0x0f
	89
	90	/* CSR0 */
	91	#define MUSB_CSR0_FLUSHFIFO 0x0100
	92	#define MUSB_CSR0_TXPKTRDY 0x0002
	93	#define MUSB_CSR0_RXPKTRDY 0x0001
	94
	95	/* CSR0 in Peripheral mode */
	96	#define MUSB_CSR0_P_SVDSETUPEND 0x0080
	97	#define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
	98	#define MUSB_CSR0_P_SENDSTALL 0x0020
	99	#define MUSB_CSR0_P_SETUPEND 0x0010
	100	#define MUSB_CSR0_P_DATAEND 0x0008
	101	#define MUSB_CSR0_P_SENTSTALL 0x0004
	102
	103	/* CSR0 in Host mode */
104	#define MUSB_CSR0_H_DIS_PING 0x0800
105	#define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */
106	#define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */
107	#define MUSB_CSR0_H_NAKTIMEOUT 0x0080
108	#define MUSB_CSR0_H_STATUSPKT 0x0040
109	#define MUSB_CSR0_H_REQPKT 0x0020
110	#define MUSB_CSR0_H_ERROR 0x0010
111	#define MUSB_CSR0_H_SETUPPKT 0x0008
112	#define MUSB_CSR0_H_RXSTALL 0x0004
113
114	/* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
115	#define MUSB_CSR0_P_WZC_BITS \
116	(MUSB_CSR0_P_SENTSTALL)
117	#define MUSB_CSR0_H_WZC_BITS \
118	(MUSB_CSR0_H_NAKTIMEOUT \| MUSB_CSR0_H_RXSTALL \
119	\| MUSB_CSR0_RXPKTRDY)
120
121	/* TxType/RxType */
122	#define MUSB_TYPE_SPEED 0xc0
123	#define MUSB_TYPE_SPEED_SHIFT 6
124	#define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */
125	#define MUSB_TYPE_PROTO_SHIFT 4
126	#define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */
127
128	/* CONFIGDATA */
129	#define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */
130	#define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */
131	#define MUSB_CONFIGDATA_BIGENDIAN 0x20
132	#define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
133	#define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
134	#define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */
135	#define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
136	#define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */
137
138	/* TXCSR in Peripheral and Host mode */
139	#define MUSB_TXCSR_AUTOSET 0x8000
550a7375 FB	140	#define MUSB_TXCSR_DMAENAB 0x1000
	141	#define MUSB_TXCSR_FRCDATATOG 0x0800
	142	#define MUSB_TXCSR_DMAMODE 0x0400
	143	#define MUSB_TXCSR_CLRDATATOG 0x0040
	144	#define MUSB_TXCSR_FLUSHFIFO 0x0008
	145	#define MUSB_TXCSR_FIFONOTEMPTY 0x0002
	146	#define MUSB_TXCSR_TXPKTRDY 0x0001
	147
	148	/* TXCSR in Peripheral mode */
	149	#define MUSB_TXCSR_P_ISO 0x4000
	150	#define MUSB_TXCSR_P_INCOMPTX 0x0080
	151	#define MUSB_TXCSR_P_SENTSTALL 0x0020
	152	#define MUSB_TXCSR_P_SENDSTALL 0x0010
	153	#define MUSB_TXCSR_P_UNDERRUN 0x0004
	154
	155	/* TXCSR in Host mode */
	156	#define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200
	157	#define MUSB_TXCSR_H_DATATOGGLE 0x0100
	158	#define MUSB_TXCSR_H_NAKTIMEOUT 0x0080
	159	#define MUSB_TXCSR_H_RXSTALL 0x0020
	160	#define MUSB_TXCSR_H_ERROR 0x0004
	161
	162	/* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
	163	#define MUSB_TXCSR_P_WZC_BITS \
	164	(MUSB_TXCSR_P_INCOMPTX \| MUSB_TXCSR_P_SENTSTALL \
	165	\| MUSB_TXCSR_P_UNDERRUN \| MUSB_TXCSR_FIFONOTEMPTY)
	166	#define MUSB_TXCSR_H_WZC_BITS \
	167	(MUSB_TXCSR_H_NAKTIMEOUT \| MUSB_TXCSR_H_RXSTALL \
	168	\| MUSB_TXCSR_H_ERROR \| MUSB_TXCSR_FIFONOTEMPTY)
	169
	170	/* RXCSR in Peripheral and Host mode */
	171	#define MUSB_RXCSR_AUTOCLEAR 0x8000
	172	#define MUSB_RXCSR_DMAENAB 0x2000
	173	#define MUSB_RXCSR_DISNYET 0x1000
	174	#define MUSB_RXCSR_PID_ERR 0x1000
	175	#define MUSB_RXCSR_DMAMODE 0x0800
	176	#define MUSB_RXCSR_INCOMPRX 0x0100
	177	#define MUSB_RXCSR_CLRDATATOG 0x0080
	178	#define MUSB_RXCSR_FLUSHFIFO 0x0010
	179	#define MUSB_RXCSR_DATAERROR 0x0008
	180	#define MUSB_RXCSR_FIFOFULL 0x0002
	181	#define MUSB_RXCSR_RXPKTRDY 0x0001
	182
	183	/* RXCSR in Peripheral mode */
	184	#define MUSB_RXCSR_P_ISO 0x4000
	185	#define MUSB_RXCSR_P_SENTSTALL 0x0040
	186	#define MUSB_RXCSR_P_SENDSTALL 0x0020
	187	#define MUSB_RXCSR_P_OVERRUN 0x0004
	188
	189	/* RXCSR in Host mode */
	190	#define MUSB_RXCSR_H_AUTOREQ 0x4000
	191	#define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400
	192	#define MUSB_RXCSR_H_DATATOGGLE 0x0200
	193	#define MUSB_RXCSR_H_RXSTALL 0x0040
	194	#define MUSB_RXCSR_H_REQPKT 0x0020
	195	#define MUSB_RXCSR_H_ERROR 0x0004
	196
	197	/* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
	198	#define MUSB_RXCSR_P_WZC_BITS \
	199	(MUSB_RXCSR_P_SENTSTALL \| MUSB_RXCSR_P_OVERRUN \
	200	\| MUSB_RXCSR_RXPKTRDY)
	201	#define MUSB_RXCSR_H_WZC_BITS \
	202	(MUSB_RXCSR_H_RXSTALL \| MUSB_RXCSR_H_ERROR \
	203	\| MUSB_RXCSR_DATAERROR \| MUSB_RXCSR_RXPKTRDY)
204
205	/* HUBADDR */
206	#define MUSB_HUBADDR_MULTI_TT 0x80
207
c6cf8b00 BW	208
	209	#ifndef CONFIG_BLACKFIN
	210
	211	/*
	212	* Common USB registers
	213	*/
	214
	215	#define MUSB_FADDR 0x00 /* 8-bit */
	216	#define MUSB_POWER 0x01 /* 8-bit */
	217
	218	#define MUSB_INTRTX 0x02 /* 16-bit */
	219	#define MUSB_INTRRX 0x04
	220	#define MUSB_INTRTXE 0x06
	221	#define MUSB_INTRRXE 0x08
	222	#define MUSB_INTRUSB 0x0A /* 8 bit */
	223	#define MUSB_INTRUSBE 0x0B /* 8 bit */
	224	#define MUSB_FRAME 0x0C
	225	#define MUSB_INDEX 0x0E /* 8 bit */
	226	#define MUSB_TESTMODE 0x0F /* 8 bit */
	227
	228	/* Get offset for a given FIFO from musb->mregs */
	229	#ifdef CONFIG_USB_TUSB6010
	230	#define MUSB_FIFO_OFFSET(epnum) (0x200 + ((epnum) * 0x20))
	231	#else
	232	#define MUSB_FIFO_OFFSET(epnum) (0x20 + ((epnum) * 4))
	233	#endif
	234
	235	/*
	236	* Additional Control Registers
	237	*/
	238
	239	#define MUSB_DEVCTL 0x60 /* 8 bit */
	240
	241	/* These are always controlled through the INDEX register */
	242	#define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */
	243	#define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */
	244	#define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */
	245	#define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */
	246
	247	/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
	248	#define MUSB_HWVERS 0x6C /* 8 bit */
	249
	250	#define MUSB_EPINFO 0x78 /* 8 bit */
	251	#define MUSB_RAMINFO 0x79 /* 8 bit */
	252	#define MUSB_LINKINFO 0x7a /* 8 bit */
	253	#define MUSB_VPLEN 0x7b /* 8 bit */
	254	#define MUSB_HS_EOF1 0x7c /* 8 bit */
	255	#define MUSB_FS_EOF1 0x7d /* 8 bit */
	256	#define MUSB_LS_EOF1 0x7e /* 8 bit */
	257
	258	/* Offsets to endpoint registers */
	259	#define MUSB_TXMAXP 0x00
	260	#define MUSB_TXCSR 0x02
	261	#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
	262	#define MUSB_RXMAXP 0x04
	263	#define MUSB_RXCSR 0x06
	264	#define MUSB_RXCOUNT 0x08
	265	#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
	266	#define MUSB_TXTYPE 0x0A
	267	#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
	268	#define MUSB_TXINTERVAL 0x0B
	269	#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
	270	#define MUSB_RXTYPE 0x0C
	271	#define MUSB_RXINTERVAL 0x0D
272	#define MUSB_FIFOSIZE 0x0F
273	#define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */
274
275	/* Offsets to endpoint registers in indexed model (using INDEX register) */
276	#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
277	(0x10 + (_offset))
278
279	/* Offsets to endpoint registers in flat models */
280	#define MUSB_FLAT_OFFSET(_epnum, _offset) \
281	(0x100 + (0x10*(_epnum)) + (_offset))
282
283	#ifdef CONFIG_USB_TUSB6010
284	/* TUSB6010 EP0 configuration register is special */
285	#define MUSB_TUSB_OFFSET(_epnum, _offset) \
286	(0x10 + _offset)
287	#include "tusb6010.h" /* Needed "only" for TUSB_EP0_CONF */
288	#endif
289
290	#define MUSB_TXCSR_MODE 0x2000
291
292	/* "bus control"/target registers, for host side multipoint (external hubs) */
293	#define MUSB_TXFUNCADDR 0x00
294	#define MUSB_TXHUBADDR 0x02
295	#define MUSB_TXHUBPORT 0x03
296
297	#define MUSB_RXFUNCADDR 0x04
298	#define MUSB_RXHUBADDR 0x06
299	#define MUSB_RXHUBPORT 0x07
300
301	#define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
302	(0x80 + (8*(_epnum)) + (_offset))
303
304	static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
305	{
306	musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
307	}
308
309	static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
310	{
311	musb_writew(mbase, MUSB_TXFIFOADD, c_off);
312	}
313
314	static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
315	{
316	musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
317	}
318
319	static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
320	{
321	musb_writew(mbase, MUSB_RXFIFOADD, c_off);
322	}
323
324	static inline u8 musb_read_configdata(void __iomem *mbase)
325	{
2bbff7b7	326	musb_writeb(mbase, MUSB_INDEX, 0);
c6cf8b00 BW	327	return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
	328	}
	329
	330	static inline u16 musb_read_hwvers(void __iomem *mbase)
	331	{
	332	return musb_readw(mbase, MUSB_HWVERS);
	333	}
	334
	335	static inline void __iomem musb_read_target_reg_base(u8 i, void __iomem mbase)
	336	{
	337	return (MUSB_BUSCTL_OFFSET(i, 0) + mbase);
	338	}
	339
	340	static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
	341	u8 qh_addr_reg)
	342	{
	343	musb_writeb(ep_target_regs, MUSB_RXFUNCADDR, qh_addr_reg);
	344	}
	345
	346	static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
	347	u8 qh_h_addr_reg)
	348	{
	349	musb_writeb(ep_target_regs, MUSB_RXHUBADDR, qh_h_addr_reg);
	350	}
	351
	352	static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
	353	u8 qh_h_port_reg)
	354	{
	355	musb_writeb(ep_target_regs, MUSB_RXHUBPORT, qh_h_port_reg);
	356	}
	357
	358	static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
	359	u8 qh_addr_reg)
	360	{
	361	musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR),
	362	qh_addr_reg);
	363	}
	364
	365	static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
	366	u8 qh_addr_reg)
	367	{
	368	musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR),
	369	qh_addr_reg);
	370	}
	371
	372	static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
	373	u8 qh_h_port_reg)
	374	{
	375	musb_writeb(mbase, MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT),
	376	qh_h_port_reg);
	377	}
	378
	379	#else /* CONFIG_BLACKFIN */
	380
	381	#define USB_BASE USB_FADDR
	382	#define USB_OFFSET(reg) (reg - USB_BASE)
	383
	384	/*
	385	* Common USB registers
	386	*/
	387	#define MUSB_FADDR USB_OFFSET(USB_FADDR) /* 8-bit */
	388	#define MUSB_POWER USB_OFFSET(USB_POWER) /* 8-bit */
	389	#define MUSB_INTRTX USB_OFFSET(USB_INTRTX) /* 16-bit */
	390	#define MUSB_INTRRX USB_OFFSET(USB_INTRRX)
391	#define MUSB_INTRTXE USB_OFFSET(USB_INTRTXE)
392	#define MUSB_INTRRXE USB_OFFSET(USB_INTRRXE)
393	#define MUSB_INTRUSB USB_OFFSET(USB_INTRUSB) /* 8 bit */
394	#define MUSB_INTRUSBE USB_OFFSET(USB_INTRUSBE)/* 8 bit */
395	#define MUSB_FRAME USB_OFFSET(USB_FRAME)
396	#define MUSB_INDEX USB_OFFSET(USB_INDEX) /* 8 bit */
397	#define MUSB_TESTMODE USB_OFFSET(USB_TESTMODE)/* 8 bit */
398
399	/* Get offset for a given FIFO from musb->mregs */
400	#define MUSB_FIFO_OFFSET(epnum) \
401	(USB_OFFSET(USB_EP0_FIFO) + ((epnum) * 8))
402
403	/*
404	* Additional Control Registers
405	*/
406
407	#define MUSB_DEVCTL USB_OFFSET(USB_OTG_DEV_CTL) /* 8 bit */
408
409	#define MUSB_LINKINFO USB_OFFSET(USB_LINKINFO)/* 8 bit */
410	#define MUSB_VPLEN USB_OFFSET(USB_VPLEN) /* 8 bit */
411	#define MUSB_HS_EOF1 USB_OFFSET(USB_HS_EOF1) /* 8 bit */
412	#define MUSB_FS_EOF1 USB_OFFSET(USB_FS_EOF1) /* 8 bit */
413	#define MUSB_LS_EOF1 USB_OFFSET(USB_LS_EOF1) /* 8 bit */
414
415	/* Offsets to endpoint registers */
416	#define MUSB_TXMAXP 0x00
417	#define MUSB_TXCSR 0x04
418	#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */
419	#define MUSB_RXMAXP 0x08
420	#define MUSB_RXCSR 0x0C
421	#define MUSB_RXCOUNT 0x10
422	#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */
423	#define MUSB_TXTYPE 0x14
424	#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */
425	#define MUSB_TXINTERVAL 0x18
426	#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */
427	#define MUSB_RXTYPE 0x1C
428	#define MUSB_RXINTERVAL 0x20
429	#define MUSB_TXCOUNT 0x28
430
431	/* Offsets to endpoint registers in indexed model (using INDEX register) */
432	#define MUSB_INDEXED_OFFSET(_epnum, _offset) \
433	(0x40 + (_offset))
434
435	/* Offsets to endpoint registers in flat models */
436	#define MUSB_FLAT_OFFSET(_epnum, _offset) \
437	(USB_OFFSET(USB_EP_NI0_TXMAXP) + (0x40 * (_epnum)) + (_offset))
438
439	/* Not implemented - HW has seperate Tx/Rx FIFO */
440	#define MUSB_TXCSR_MODE 0x0000
441
c6cf8b00 BW	442	static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
	443	{
	444	}
	445
	446	static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
	447	{
	448	}
	449
	450	static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
	451	{
	452	}
	453
	454	static inline void musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
	455	{
	456	}
	457
	458	static inline u8 musb_read_configdata(void __iomem *mbase)
	459	{
	460	return 0;
	461	}
	462
	463	static inline u16 musb_read_hwvers(void __iomem *mbase)
	464	{
	465	return 0;
	466	}
	467
92dea9f3	468	static inline void __iomem musb_read_target_reg_base(u8 i, void __iomem mbase)
c6cf8b00	469	{
92dea9f3	470	return NULL;
c6cf8b00 BW	471	}
	472
	473	static inline void musb_write_rxfunaddr(void __iomem *ep_target_regs,
	474	u8 qh_addr_req)
	475	{
	476	}
	477
	478	static inline void musb_write_rxhubaddr(void __iomem *ep_target_regs,
	479	u8 qh_h_addr_reg)
	480	{
	481	}
	482
	483	static inline void musb_write_rxhubport(void __iomem *ep_target_regs,
	484	u8 qh_h_port_reg)
	485	{
	486	}
	487
	488	static inline void musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
	489	u8 qh_addr_reg)
	490	{
	491	}
	492
	493	static inline void musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
	494	u8 qh_addr_reg)
	495	{
	496	}
	497
	498	static inline void musb_write_txhubport(void __iomem *mbase, u8 epnum,
	499	u8 qh_h_port_reg)
	500	{
	501	}
	502
	503	#endif /* CONFIG_BLACKFIN */
	504
550a7375	505	#endif /* __MUSB_REGS_H__ */