[deliverable/linux.git] / drivers / usb / musb / musbhsdma.c

/*
 * MUSB OTG driver - support for Mentor's DMA controller
 *
 * Copyright 2005 Mentor Graphics Corporation
 * Copyright (C) 2005-2007 by Texas Instruments
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "musb_core.h"
#include "musbhsdma.h"

static void dma_channel_release(struct dma_channel *channel);

static void dma_controller_stop(struct musb_dma_controller *controller)
{
	struct musb *musb = controller->private_data;
	struct dma_channel *channel;
	u8 bit;

	if (controller->used_channels != 0) {
		dev_err(musb->controller,
			"Stopping DMA controller while channel active\n");

		for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
			if (controller->used_channels & (1 << bit)) {
				channel = &controller->channel[bit].channel;
				dma_channel_release(channel);

				if (!controller->used_channels)
					break;
			}
		}
	}
}

static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
				struct musb_hw_ep *hw_ep, u8 transmit)
{
	struct musb_dma_controller *controller = container_of(c,
			struct musb_dma_controller, controller);
	struct musb_dma_channel *musb_channel = NULL;
	struct dma_channel *channel = NULL;
	u8 bit;

	for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
		if (!(controller->used_channels & (1 << bit))) {
			controller->used_channels |= (1 << bit);
			musb_channel = &(controller->channel[bit]);
			musb_channel->controller = controller;
			musb_channel->idx = bit;
			musb_channel->epnum = hw_ep->epnum;
			musb_channel->transmit = transmit;
			channel = &(musb_channel->channel);
			channel->private_data = musb_channel;
			channel->status = MUSB_DMA_STATUS_FREE;
			channel->max_len = 0x100000;
			/* Tx => mode 1; Rx => mode 0 */
			channel->desired_mode = transmit;
			channel->actual_len = 0;
			break;
		}
	}

	return channel;
}

static void dma_channel_release(struct dma_channel *channel)
{
	struct musb_dma_channel *musb_channel = channel->private_data;

	channel->actual_len = 0;
	musb_channel->start_addr = 0;
	musb_channel->len = 0;

	musb_channel->controller->used_channels &=
		~(1 << musb_channel->idx);

	channel->status = MUSB_DMA_STATUS_UNKNOWN;
}

static void configure_channel(struct dma_channel *channel,
				u16 packet_sz, u8 mode,
				dma_addr_t dma_addr, u32 len)
{
	struct musb_dma_channel *musb_channel = channel->private_data;
	struct musb_dma_controller *controller = musb_channel->controller;
	struct musb *musb = controller->private_data;
	void __iomem *mbase = controller->base;
	u8 bchannel = musb_channel->idx;
	u16 csr = 0;

	dev_dbg(musb->controller, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
			channel, packet_sz, dma_addr, len, mode);

	if (mode) {
		csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
		BUG_ON(len < packet_sz);
	}
	csr |= MUSB_HSDMA_BURSTMODE_INCR16
				<< MUSB_HSDMA_BURSTMODE_SHIFT;

	csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
		| (1 << MUSB_HSDMA_ENABLE_SHIFT)
		| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
		| (musb_channel->transmit
				? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
				: 0);

	/* address/count */
	musb_write_hsdma_addr(mbase, bchannel, dma_addr);
	musb_write_hsdma_count(mbase, bchannel, len);

	/* control (this should start things) */
	musb_writew(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
		csr);
}

static int dma_channel_program(struct dma_channel *channel,
				u16 packet_sz, u8 mode,
				dma_addr_t dma_addr, u32 len)
{
	struct musb_dma_channel *musb_channel = channel->private_data;
	struct musb_dma_controller *controller = musb_channel->controller;
	struct musb *musb = controller->private_data;

	dev_dbg(musb->controller, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
		musb_channel->epnum,
		musb_channel->transmit ? "Tx" : "Rx",
		packet_sz, dma_addr, len, mode);

	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
		channel->status == MUSB_DMA_STATUS_BUSY);

	/* Let targets check/tweak the arguments */
	if (musb->ops->adjust_channel_params) {
		int ret = musb->ops->adjust_channel_params(channel,
			packet_sz, &mode, &dma_addr, &len);
		if (ret)
			return ret;
	}

	/*
	 * The DMA engine in RTL1.8 and above cannot handle
	 * DMA addresses that are not aligned to a 4 byte boundary.
	 * It ends up masking the last two bits of the address
	 * programmed in DMA_ADDR.
	 *
	 * Fail such DMA transfers, so that the backup PIO mode
	 * can carry out the transfer
	 */
	if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
		return false;

	channel->actual_len = 0;
	musb_channel->start_addr = dma_addr;
	musb_channel->len = len;
	musb_channel->max_packet_sz = packet_sz;
	channel->status = MUSB_DMA_STATUS_BUSY;

	configure_channel(channel, packet_sz, mode, dma_addr, len);

	return true;
}

static int dma_channel_abort(struct dma_channel *channel)
{
	struct musb_dma_channel *musb_channel = channel->private_data;
	void __iomem *mbase = musb_channel->controller->base;

	u8 bchannel = musb_channel->idx;
	int offset;
	u16 csr;

	if (channel->status == MUSB_DMA_STATUS_BUSY) {
		if (musb_channel->transmit) {
			offset = MUSB_EP_OFFSET(musb_channel->epnum,
						MUSB_TXCSR);

			/*
			 * The programming guide says that we must clear
			 * the DMAENAB bit before the DMAMODE bit...
			 */
			csr = musb_readw(mbase, offset);
			csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
			musb_writew(mbase, offset, csr);
			csr &= ~MUSB_TXCSR_DMAMODE;
			musb_writew(mbase, offset, csr);
		} else {
			offset = MUSB_EP_OFFSET(musb_channel->epnum,
						MUSB_RXCSR);

			csr = musb_readw(mbase, offset);
			csr &= ~(MUSB_RXCSR_AUTOCLEAR |
				 MUSB_RXCSR_DMAENAB |
				 MUSB_RXCSR_DMAMODE);
			musb_writew(mbase, offset, csr);
		}

		musb_writew(mbase,
			MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
			0);
		musb_write_hsdma_addr(mbase, bchannel, 0);
		musb_write_hsdma_count(mbase, bchannel, 0);
		channel->status = MUSB_DMA_STATUS_FREE;
	}

	return 0;
}

static irqreturn_t dma_controller_irq(int irq, void *private_data)
{
	struct musb_dma_controller *controller = private_data;
	struct musb *musb = controller->private_data;
	struct musb_dma_channel *musb_channel;
	struct dma_channel *channel;

	void __iomem *mbase = controller->base;

	irqreturn_t retval = IRQ_NONE;

	unsigned long flags;

	u8 bchannel;
	u8 int_hsdma;

	u32 addr, count;
	u16 csr;

	spin_lock_irqsave(&musb->lock, flags);

	int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);

#ifdef CONFIG_BLACKFIN
	/* Clear DMA interrupt flags */
	musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
#endif

	if (!int_hsdma) {
		dev_dbg(musb->controller, "spurious DMA irq\n");

		for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
			musb_channel = (struct musb_dma_channel *)
					&(controller->channel[bchannel]);
			channel = &musb_channel->channel;
			if (channel->status == MUSB_DMA_STATUS_BUSY) {
				count = musb_read_hsdma_count(mbase, bchannel);

				if (count == 0)
					int_hsdma |= (1 << bchannel);
			}
		}

		dev_dbg(musb->controller, "int_hsdma = 0x%x\n", int_hsdma);

		if (!int_hsdma)
			goto done;
	}

	for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
		if (int_hsdma & (1 << bchannel)) {
			musb_channel = (struct musb_dma_channel *)
					&(controller->channel[bchannel]);
			channel = &musb_channel->channel;

			csr = musb_readw(mbase,
					MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
							MUSB_HSDMA_CONTROL));

			if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
				musb_channel->channel.status =
					MUSB_DMA_STATUS_BUS_ABORT;
			} else {
				u8 devctl;

				addr = musb_read_hsdma_addr(mbase,
						bchannel);
				channel->actual_len = addr
					- musb_channel->start_addr;

				dev_dbg(musb->controller, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
					channel, musb_channel->start_addr,
					addr, channel->actual_len,
					musb_channel->len,
					(channel->actual_len
						< musb_channel->len) ?
					"=> reconfig 0" : "=> complete");

				devctl = musb_readb(mbase, MUSB_DEVCTL);

				channel->status = MUSB_DMA_STATUS_FREE;

				/* completed */
				if ((devctl & MUSB_DEVCTL_HM)
					&& (musb_channel->transmit)
					&& ((channel->desired_mode == 0)
					    || (channel->actual_len &
					    (musb_channel->max_packet_sz - 1)))
				    ) {
					u8  epnum  = musb_channel->epnum;
					int offset = MUSB_EP_OFFSET(epnum,
								    MUSB_TXCSR);
					u16 txcsr;

					/*
					 * The programming guide says that we
					 * must clear DMAENAB before DMAMODE.
					 */
					musb_ep_select(mbase, epnum);
					txcsr = musb_readw(mbase, offset);
					txcsr &= ~(MUSB_TXCSR_DMAENAB
							| MUSB_TXCSR_AUTOSET);
					musb_writew(mbase, offset, txcsr);
					/* Send out the packet */
					txcsr &= ~MUSB_TXCSR_DMAMODE;
					txcsr |=  MUSB_TXCSR_TXPKTRDY;
					musb_writew(mbase, offset, txcsr);
				}
				musb_dma_completion(musb, musb_channel->epnum,
						    musb_channel->transmit);
			}
		}
	}

	retval = IRQ_HANDLED;
done:
	spin_unlock_irqrestore(&musb->lock, flags);
	return retval;
}

void dma_controller_destroy(struct dma_controller *c)
{
	struct musb_dma_controller *controller = container_of(c,
			struct musb_dma_controller, controller);

	dma_controller_stop(controller);

	if (controller->irq)
		free_irq(controller->irq, c);

	kfree(controller);
}

struct dma_controller *dma_controller_create(struct musb *musb, void __iomem *base)
{
	struct musb_dma_controller *controller;
	struct device *dev = musb->controller;
	struct platform_device *pdev = to_platform_device(dev);
	int irq = platform_get_irq_byname(pdev, "dma");

	if (irq <= 0) {
		dev_err(dev, "No DMA interrupt line!\n");
		return NULL;
	}

	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
	if (!controller)
		return NULL;

	controller->channel_count = MUSB_HSDMA_CHANNELS;
	controller->private_data = musb;
	controller->base = base;

	controller->controller.channel_alloc = dma_channel_allocate;
	controller->controller.channel_release = dma_channel_release;
	controller->controller.channel_program = dma_channel_program;
	controller->controller.channel_abort = dma_channel_abort;

	if (request_irq(irq, dma_controller_irq, 0,
			dev_name(musb->controller), &controller->controller)) {
		dev_err(dev, "request_irq %d failed!\n", irq);
		dma_controller_destroy(&controller->controller);

		return NULL;
	}

	controller->irq = irq;

	return &controller->controller;
}
Commit	Line	Data
550a7375 FB	1	/*
	2	* MUSB OTG driver - support for Mentor's DMA controller
	3	*
	4	* Copyright 2005 Mentor Graphics Corporation
	5	* Copyright (C) 2005-2007 by Texas Instruments
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* version 2 as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	19	* 02110-1301 USA
	20	*
	21	* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
	22	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	23	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	24	* NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
	25	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	26	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	27	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	28	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	30	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*
	32	*/
	33	#include <linux/device.h>
	34	#include <linux/interrupt.h>
	35	#include <linux/platform_device.h>
5a0e3ad6	36	#include <linux/slab.h>
550a7375	37	#include "musb_core.h"
6995eb68	38	#include "musbhsdma.h"
550a7375	39
458e6a51	40	static void dma_channel_release(struct dma_channel *channel);
550a7375	41
66c01883	42	static void dma_controller_stop(struct musb_dma_controller *controller)
550a7375	43	{
458e6a51 FB	44	struct musb *musb = controller->private_data;
	45	struct dma_channel *channel;
	46	u8 bit;
550a7375	47
458e6a51	48	if (controller->used_channels != 0) {
550a7375 FB	49	dev_err(musb->controller,
	50	"Stopping DMA controller while channel active\n");
	51
458e6a51 FB	52	for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
	53	if (controller->used_channels & (1 << bit)) {
	54	channel = &controller->channel[bit].channel;
	55	dma_channel_release(channel);
550a7375	56
458e6a51	57	if (!controller->used_channels)
550a7375 FB	58	break;
	59	}
	60	}
	61	}
550a7375 FB	62	}
	63
	64	static struct dma_channel dma_channel_allocate(struct dma_controller c,
	65	struct musb_hw_ep *hw_ep, u8 transmit)
	66	{
458e6a51 FB	67	struct musb_dma_controller *controller = container_of(c,
	68	struct musb_dma_controller, controller);
	69	struct musb_dma_channel *musb_channel = NULL;
	70	struct dma_channel *channel = NULL;
	71	u8 bit;
	72
	73	for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
	74	if (!(controller->used_channels & (1 << bit))) {
	75	controller->used_channels \|= (1 << bit);
	76	musb_channel = &(controller->channel[bit]);
	77	musb_channel->controller = controller;
	78	musb_channel->idx = bit;
	79	musb_channel->epnum = hw_ep->epnum;
	80	musb_channel->transmit = transmit;
	81	channel = &(musb_channel->channel);
	82	channel->private_data = musb_channel;
	83	channel->status = MUSB_DMA_STATUS_FREE;
6587cc0f	84	channel->max_len = 0x100000;
550a7375	85	/* Tx => mode 1; Rx => mode 0 */
458e6a51 FB	86	channel->desired_mode = transmit;
458e6a51 FB	87	channel->actual_len = 0;
550a7375 FB	88	break;
	89	}
	90	}
458e6a51 FB	91
458e6a51 FB	92	return channel;
550a7375 FB	93	}
550a7375 FB	94
458e6a51	95	static void dma_channel_release(struct dma_channel *channel)
550a7375	96	{
458e6a51	97	struct musb_dma_channel *musb_channel = channel->private_data;
550a7375	98
458e6a51 FB	99	channel->actual_len = 0;
	100	musb_channel->start_addr = 0;
	101	musb_channel->len = 0;
550a7375	102
458e6a51 FB	103	musb_channel->controller->used_channels &=
458e6a51 FB	104	~(1 << musb_channel->idx);
550a7375	105
458e6a51	106	channel->status = MUSB_DMA_STATUS_UNKNOWN;
550a7375 FB	107	}
550a7375 FB	108
458e6a51	109	static void configure_channel(struct dma_channel *channel,
550a7375 FB	110	u16 packet_sz, u8 mode,
	111	dma_addr_t dma_addr, u32 len)
	112	{
458e6a51 FB	113	struct musb_dma_channel *musb_channel = channel->private_data;
458e6a51 FB	114	struct musb_dma_controller *controller = musb_channel->controller;
5c8a86e1	115	struct musb *musb = controller->private_data;
458e6a51 FB	116	void __iomem *mbase = controller->base;
458e6a51 FB	117	u8 bchannel = musb_channel->idx;
550a7375 FB	118	u16 csr = 0;
550a7375 FB	119
5c8a86e1	120	dev_dbg(musb->controller, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
458e6a51	121	channel, packet_sz, dma_addr, len, mode);
550a7375 FB	122
	123	if (mode) {
	124	csr \|= 1 << MUSB_HSDMA_MODE1_SHIFT;
	125	BUG_ON(len < packet_sz);
550a7375	126	}
c0f1f8e3 HH	127	csr \|= MUSB_HSDMA_BURSTMODE_INCR16
c0f1f8e3 HH	128	<< MUSB_HSDMA_BURSTMODE_SHIFT;
550a7375	129
458e6a51	130	csr \|= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
550a7375 FB	131	\| (1 << MUSB_HSDMA_ENABLE_SHIFT)
550a7375 FB	132	\| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
458e6a51	133	\| (musb_channel->transmit
550a7375 FB	134	? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
	135	: 0);
	136
	137	/* address/count */
6995eb68 BW	138	musb_write_hsdma_addr(mbase, bchannel, dma_addr);
6995eb68 BW	139	musb_write_hsdma_count(mbase, bchannel, len);
550a7375 FB	140
	141	/* control (this should start things) */
	142	musb_writew(mbase,
458e6a51	143	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
550a7375 FB	144	csr);
	145	}
	146
458e6a51	147	static int dma_channel_program(struct dma_channel *channel,
550a7375 FB	148	u16 packet_sz, u8 mode,
	149	dma_addr_t dma_addr, u32 len)
	150	{
458e6a51	151	struct musb_dma_channel *musb_channel = channel->private_data;
6e16edfe AG	152	struct musb_dma_controller *controller = musb_channel->controller;
6e16edfe AG	153	struct musb *musb = controller->private_data;
550a7375	154
5c8a86e1	155	dev_dbg(musb->controller, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
458e6a51 FB	156	musb_channel->epnum,
458e6a51 FB	157	musb_channel->transmit ? "Tx" : "Rx",
550a7375 FB	158	packet_sz, dma_addr, len, mode);
550a7375 FB	159
458e6a51 FB	160	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN \|\|
458e6a51 FB	161	channel->status == MUSB_DMA_STATUS_BUSY);
550a7375	162
13254307 MF	163	/* Let targets check/tweak the arguments */
	164	if (musb->ops->adjust_channel_params) {
	165	int ret = musb->ops->adjust_channel_params(channel,
	166	packet_sz, &mode, &dma_addr, &len);
	167	if (ret)
	168	return ret;
	169	}
	170
6e16edfe AG	171	/*
	172	* The DMA engine in RTL1.8 and above cannot handle
	173	* DMA addresses that are not aligned to a 4 byte boundary.
	174	* It ends up masking the last two bits of the address
	175	* programmed in DMA_ADDR.
	176	*
	177	* Fail such DMA transfers, so that the backup PIO mode
	178	* can carry out the transfer
	179	*/
	180	if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
	181	return false;
	182
458e6a51 FB	183	channel->actual_len = 0;
	184	musb_channel->start_addr = dma_addr;
	185	musb_channel->len = len;
	186	musb_channel->max_packet_sz = packet_sz;
	187	channel->status = MUSB_DMA_STATUS_BUSY;
550a7375	188
8ca47c8a	189	configure_channel(channel, packet_sz, mode, dma_addr, len);
550a7375 FB	190
	191	return true;
	192	}
	193
458e6a51	194	static int dma_channel_abort(struct dma_channel *channel)
550a7375	195	{
458e6a51 FB	196	struct musb_dma_channel *musb_channel = channel->private_data;
	197	void __iomem *mbase = musb_channel->controller->base;
	198
	199	u8 bchannel = musb_channel->idx;
b6e434a5	200	int offset;
550a7375 FB	201	u16 csr;
550a7375 FB	202
458e6a51 FB	203	if (channel->status == MUSB_DMA_STATUS_BUSY) {
458e6a51 FB	204	if (musb_channel->transmit) {
b6e434a5 SS	205	offset = MUSB_EP_OFFSET(musb_channel->epnum,
	206	MUSB_TXCSR);
	207
	208	/*
	209	* The programming guide says that we must clear
	210	* the DMAENAB bit before the DMAMODE bit...
	211	*/
	212	csr = musb_readw(mbase, offset);
	213	csr &= ~(MUSB_TXCSR_AUTOSET \| MUSB_TXCSR_DMAENAB);
	214	musb_writew(mbase, offset, csr);
	215	csr &= ~MUSB_TXCSR_DMAMODE;
	216	musb_writew(mbase, offset, csr);
550a7375	217	} else {
b6e434a5 SS	218	offset = MUSB_EP_OFFSET(musb_channel->epnum,
	219	MUSB_RXCSR);
	220
	221	csr = musb_readw(mbase, offset);
550a7375 FB	222	csr &= ~(MUSB_RXCSR_AUTOCLEAR \|
	223	MUSB_RXCSR_DMAENAB \|
	224	MUSB_RXCSR_DMAMODE);
b6e434a5	225	musb_writew(mbase, offset, csr);
550a7375 FB	226	}
	227
	228	musb_writew(mbase,
458e6a51	229	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
550a7375	230	0);
6995eb68 BW	231	musb_write_hsdma_addr(mbase, bchannel, 0);
6995eb68 BW	232	musb_write_hsdma_count(mbase, bchannel, 0);
458e6a51	233	channel->status = MUSB_DMA_STATUS_FREE;
550a7375	234	}
458e6a51	235
550a7375 FB	236	return 0;
	237	}
	238
	239	static irqreturn_t dma_controller_irq(int irq, void *private_data)
	240	{
458e6a51 FB	241	struct musb_dma_controller *controller = private_data;
	242	struct musb *musb = controller->private_data;
	243	struct musb_dma_channel *musb_channel;
	244	struct dma_channel *channel;
	245
	246	void __iomem *mbase = controller->base;
	247
550a7375	248	irqreturn_t retval = IRQ_NONE;
458e6a51	249
550a7375 FB	250	unsigned long flags;
550a7375 FB	251
458e6a51 FB	252	u8 bchannel;
	253	u8 int_hsdma;
	254
f933a0c0	255	u32 addr, count;
458e6a51 FB	256	u16 csr;
458e6a51 FB	257
550a7375 FB	258	spin_lock_irqsave(&musb->lock, flags);
	259
	260	int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
550a7375	261
6bd03e7b CC	262	#ifdef CONFIG_BLACKFIN
	263	/* Clear DMA interrupt flags */
	264	musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
	265	#endif
	266
f933a0c0	267	if (!int_hsdma) {
5c8a86e1	268	dev_dbg(musb->controller, "spurious DMA irq\n");
f933a0c0 AG	269
	270	for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
	271	musb_channel = (struct musb_dma_channel *)
	272	&(controller->channel[bchannel]);
	273	channel = &musb_channel->channel;
	274	if (channel->status == MUSB_DMA_STATUS_BUSY) {
	275	count = musb_read_hsdma_count(mbase, bchannel);
	276
	277	if (count == 0)
	278	int_hsdma \|= (1 << bchannel);
	279	}
	280	}
	281
5c8a86e1	282	dev_dbg(musb->controller, "int_hsdma = 0x%x\n", int_hsdma);
f933a0c0 AG	283
	284	if (!int_hsdma)
	285	goto done;
	286	}
	287
458e6a51 FB	288	for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
	289	if (int_hsdma & (1 << bchannel)) {
	290	musb_channel = (struct musb_dma_channel *)
	291	&(controller->channel[bchannel]);
	292	channel = &musb_channel->channel;
550a7375 FB	293
550a7375 FB	294	csr = musb_readw(mbase,
458e6a51	295	MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
550a7375 FB	296	MUSB_HSDMA_CONTROL));
550a7375 FB	297
458e6a51 FB	298	if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
458e6a51 FB	299	musb_channel->channel.status =
550a7375	300	MUSB_DMA_STATUS_BUS_ABORT;
458e6a51	301	} else {
550a7375 FB	302	u8 devctl;
550a7375 FB	303
6995eb68 BW	304	addr = musb_read_hsdma_addr(mbase,
6995eb68 BW	305	bchannel);
458e6a51 FB	306	channel->actual_len = addr
458e6a51 FB	307	- musb_channel->start_addr;
550a7375	308
5c8a86e1	309	dev_dbg(musb->controller, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
458e6a51 FB	310	channel, musb_channel->start_addr,
	311	addr, channel->actual_len,
	312	musb_channel->len,
	313	(channel->actual_len
	314	< musb_channel->len) ?
550a7375 FB	315	"=> reconfig 0" : "=> complete");
	316
	317	devctl = musb_readb(mbase, MUSB_DEVCTL);
	318
458e6a51	319	channel->status = MUSB_DMA_STATUS_FREE;
550a7375 FB	320
	321	/* completed */
	322	if ((devctl & MUSB_DEVCTL_HM)
458e6a51 FB	323	&& (musb_channel->transmit)
	324	&& ((channel->desired_mode == 0)
	325	\|\| (channel->actual_len &
	326	(musb_channel->max_packet_sz - 1)))
b6e434a5 SS	327	) {
	328	u8 epnum = musb_channel->epnum;
	329	int offset = MUSB_EP_OFFSET(epnum,
	330	MUSB_TXCSR);
	331	u16 txcsr;
	332
	333	/*
	334	* The programming guide says that we
	335	* must clear DMAENAB before DMAMODE.
	336	*/
	337	musb_ep_select(mbase, epnum);
	338	txcsr = musb_readw(mbase, offset);
	339	txcsr &= ~(MUSB_TXCSR_DMAENAB
	340	\| MUSB_TXCSR_AUTOSET);
	341	musb_writew(mbase, offset, txcsr);
550a7375	342	/* Send out the packet */
b6e434a5 SS	343	txcsr &= ~MUSB_TXCSR_DMAMODE;
	344	txcsr \|= MUSB_TXCSR_TXPKTRDY;
	345	musb_writew(mbase, offset, txcsr);
458e6a51	346	}
c7bbc056 SS	347	musb_dma_completion(musb, musb_channel->epnum,
c7bbc056 SS	348	musb_channel->transmit);
550a7375 FB	349	}
	350	}
	351	}
6995eb68	352
550a7375 FB	353	retval = IRQ_HANDLED;
	354	done:
	355	spin_unlock_irqrestore(&musb->lock, flags);
	356	return retval;
	357	}
	358
	359	void dma_controller_destroy(struct dma_controller *c)
	360	{
458e6a51 FB	361	struct musb_dma_controller *controller = container_of(c,
458e6a51 FB	362	struct musb_dma_controller, controller);
550a7375	363
66c01883 SAS	364	dma_controller_stop(controller);
66c01883 SAS	365
550a7375 FB	366	if (controller->irq)
	367	free_irq(controller->irq, c);
	368
	369	kfree(controller);
	370	}
	371
41ac7b3a	372	struct dma_controller dma_controller_create(struct musb musb, void __iomem *base)
550a7375 FB	373	{
	374	struct musb_dma_controller *controller;
	375	struct device *dev = musb->controller;
	376	struct platform_device *pdev = to_platform_device(dev);
fcf173e4	377	int irq = platform_get_irq_byname(pdev, "dma");
550a7375	378
7effdbd6	379	if (irq <= 0) {
550a7375 FB	380	dev_err(dev, "No DMA interrupt line!\n");
	381	return NULL;
	382	}
	383
458e6a51	384	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
550a7375 FB	385	if (!controller)
	386	return NULL;
	387
458e6a51 FB	388	controller->channel_count = MUSB_HSDMA_CHANNELS;
	389	controller->private_data = musb;
	390	controller->base = base;
550a7375	391
458e6a51 FB	392	controller->controller.channel_alloc = dma_channel_allocate;
	393	controller->controller.channel_release = dma_channel_release;
	394	controller->controller.channel_program = dma_channel_program;
	395	controller->controller.channel_abort = dma_channel_abort;
550a7375	396
b5dd18d8	397	if (request_irq(irq, dma_controller_irq, 0,
427c4f33	398	dev_name(musb->controller), &controller->controller)) {
550a7375	399	dev_err(dev, "request_irq %d failed!\n", irq);
458e6a51 FB	400	dma_controller_destroy(&controller->controller);
458e6a51 FB	401
550a7375 FB	402	return NULL;
	403	}
	404
	405	controller->irq = irq;
	406
458e6a51	407	return &controller->controller;
550a7375	408	}