[deliverable/linux.git] / drivers / usb / musb / musbhsdma.h

/*
 * MUSB OTG driver - support for Mentor's DMA controller
 *
 * Copyright 2005 Mentor Graphics Corporation
 * Copyright (C) 2005-2007 by Texas Instruments
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
#include "omap2430.h"
#endif

#ifndef CONFIG_BLACKFIN

#define MUSB_HSDMA_BASE		0x200
#define MUSB_HSDMA_INTR		(MUSB_HSDMA_BASE + 0)
#define MUSB_HSDMA_CONTROL		0x4
#define MUSB_HSDMA_ADDRESS		0x8
#define MUSB_HSDMA_COUNT		0xc

#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset)		\
		(MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)

#define musb_read_hsdma_addr(mbase, bchannel)	\
	musb_readl(mbase,	\
		   MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))

#define musb_write_hsdma_addr(mbase, bchannel, addr) \
	musb_writel(mbase, \
		    MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
		    addr)

#define musb_read_hsdma_count(mbase, bchannel)	\
	musb_readl(mbase,	\
		   MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))

#define musb_write_hsdma_count(mbase, bchannel, len) \
	musb_writel(mbase, \
		    MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
		    len)
#else

#define MUSB_HSDMA_BASE		0x400
#define MUSB_HSDMA_INTR		(MUSB_HSDMA_BASE + 0)
#define MUSB_HSDMA_CONTROL		0x04
#define MUSB_HSDMA_ADDR_LOW		0x08
#define MUSB_HSDMA_ADDR_HIGH		0x0C
#define MUSB_HSDMA_COUNT_LOW		0x10
#define MUSB_HSDMA_COUNT_HIGH		0x14

#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset)		\
		(MUSB_HSDMA_BASE + (_bchannel * 0x20) + _offset)

static inline u32 musb_read_hsdma_addr(void __iomem *mbase, u8 bchannel)
{
	u32 addr = musb_readw(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH));

	addr = addr << 16;

	addr |= musb_readw(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW));

	return addr;
}

static inline void musb_write_hsdma_addr(void __iomem *mbase,
				u8 bchannel, dma_addr_t dma_addr)
{
	musb_writew(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW),
		((u16)((u32) dma_addr & 0xFFFF)));
	musb_writew(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH),
		((u16)(((u32) dma_addr >> 16) & 0xFFFF)));
}

static inline u32 musb_read_hsdma_count(void __iomem *mbase, u8 bchannel)
{
	return musb_readl(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH));
}

static inline void musb_write_hsdma_count(void __iomem *mbase,
				u8 bchannel, u32 len)
{
	musb_writel(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH),
		len);
}

#endif /* CONFIG_BLACKFIN */

/* control register (16-bit): */
#define MUSB_HSDMA_ENABLE_SHIFT		0
#define MUSB_HSDMA_TRANSMIT_SHIFT	1
#define MUSB_HSDMA_MODE1_SHIFT		2
#define MUSB_HSDMA_IRQENABLE_SHIFT	3
#define MUSB_HSDMA_ENDPOINT_SHIFT	4
#define MUSB_HSDMA_BUSERROR_SHIFT	8
#define MUSB_HSDMA_BURSTMODE_SHIFT	9
#define MUSB_HSDMA_BURSTMODE		(3 << MUSB_HSDMA_BURSTMODE_SHIFT)
#define MUSB_HSDMA_BURSTMODE_UNSPEC	0
#define MUSB_HSDMA_BURSTMODE_INCR4	1
#define MUSB_HSDMA_BURSTMODE_INCR8	2
#define MUSB_HSDMA_BURSTMODE_INCR16	3

#define MUSB_HSDMA_CHANNELS		8

struct musb_dma_controller;

struct musb_dma_channel {
	struct dma_channel		channel;
	struct musb_dma_controller	*controller;
	u32				start_addr;
	u32				len;
	u16				max_packet_sz;
	u8				idx;
	u8				epnum;
	u8				transmit;
};

struct musb_dma_controller {
	struct dma_controller		controller;
	struct musb_dma_channel		channel[MUSB_HSDMA_CHANNELS];
	void				*private_data;
	void __iomem			*base;
	u8				channel_count;
	u8				used_channels;
	u8				irq;
};
Commit	Line	Data
6995eb68 BW	1	/*
	2	* MUSB OTG driver - support for Mentor's DMA controller
	3	*
	4	* Copyright 2005 Mentor Graphics Corporation
	5	* Copyright (C) 2005-2007 by Texas Instruments
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* version 2 as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	19	* 02110-1301 USA
	20	*
	21	* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
	22	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	23	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	24	* NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
	25	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	26	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	27	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	28	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	30	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*
	32	*/
	33
	34	#if defined(CONFIG_ARCH_OMAP2430) \|\| defined(CONFIG_ARCH_OMAP3430)
	35	#include "omap2430.h"
	36	#endif
	37
	38	#ifndef CONFIG_BLACKFIN
	39
	40	#define MUSB_HSDMA_BASE 0x200
	41	#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
	42	#define MUSB_HSDMA_CONTROL 0x4
	43	#define MUSB_HSDMA_ADDRESS 0x8
	44	#define MUSB_HSDMA_COUNT 0xc
	45
	46	#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
	47	(MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
	48
	49	#define musb_read_hsdma_addr(mbase, bchannel) \
	50	musb_readl(mbase, \
	51	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
	52
	53	#define musb_write_hsdma_addr(mbase, bchannel, addr) \
	54	musb_writel(mbase, \
	55	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
	56	addr)
	57
452f0394 AG	58	#define musb_read_hsdma_count(mbase, bchannel) \
	59	musb_readl(mbase, \
	60	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
	61
6995eb68 BW	62	#define musb_write_hsdma_count(mbase, bchannel, len) \
	63	musb_writel(mbase, \
	64	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
	65	len)
	66	#else
	67
	68	#define MUSB_HSDMA_BASE 0x400
	69	#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
	70	#define MUSB_HSDMA_CONTROL 0x04
	71	#define MUSB_HSDMA_ADDR_LOW 0x08
	72	#define MUSB_HSDMA_ADDR_HIGH 0x0C
	73	#define MUSB_HSDMA_COUNT_LOW 0x10
	74	#define MUSB_HSDMA_COUNT_HIGH 0x14
	75
	76	#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
	77	(MUSB_HSDMA_BASE + (_bchannel * 0x20) + _offset)
	78
	79	static inline u32 musb_read_hsdma_addr(void __iomem *mbase, u8 bchannel)
	80	{
	81	u32 addr = musb_readw(mbase,
	82	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH));
	83
	84	addr = addr << 16;
	85
	86	addr \|= musb_readw(mbase,
	87	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW));
	88
	89	return addr;
	90	}
	91
	92	static inline void musb_write_hsdma_addr(void __iomem *mbase,
	93	u8 bchannel, dma_addr_t dma_addr)
	94	{
	95	musb_writew(mbase,
	96	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW),
	97	((u16)((u32) dma_addr & 0xFFFF)));
	98	musb_writew(mbase,
	99	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH),
	100	((u16)(((u32) dma_addr >> 16) & 0xFFFF)));
	101	}
	102
452f0394 AG	103	static inline u32 musb_read_hsdma_count(void __iomem *mbase, u8 bchannel)
452f0394 AG	104	{
ddb495d4	105	return musb_readl(mbase,
452f0394	106	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH));
452f0394 AG	107	}
452f0394 AG	108
6995eb68 BW	109	static inline void musb_write_hsdma_count(void __iomem *mbase,
	110	u8 bchannel, u32 len)
	111	{
ddb495d4	112	musb_writel(mbase,
6995eb68	113	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH),
ddb495d4	114	len);
6995eb68 BW	115	}
	116
	117	#endif /* CONFIG_BLACKFIN */
	118
	119	/* control register (16-bit): */
	120	#define MUSB_HSDMA_ENABLE_SHIFT 0
	121	#define MUSB_HSDMA_TRANSMIT_SHIFT 1
	122	#define MUSB_HSDMA_MODE1_SHIFT 2
	123	#define MUSB_HSDMA_IRQENABLE_SHIFT 3
	124	#define MUSB_HSDMA_ENDPOINT_SHIFT 4
	125	#define MUSB_HSDMA_BUSERROR_SHIFT 8
	126	#define MUSB_HSDMA_BURSTMODE_SHIFT 9
	127	#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
	128	#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
	129	#define MUSB_HSDMA_BURSTMODE_INCR4 1
	130	#define MUSB_HSDMA_BURSTMODE_INCR8 2
	131	#define MUSB_HSDMA_BURSTMODE_INCR16 3
	132
	133	#define MUSB_HSDMA_CHANNELS 8
	134
	135	struct musb_dma_controller;
	136
	137	struct musb_dma_channel {
	138	struct dma_channel channel;
	139	struct musb_dma_controller *controller;
	140	u32 start_addr;
	141	u32 len;
	142	u16 max_packet_sz;
	143	u8 idx;
	144	u8 epnum;
	145	u8 transmit;
	146	};
	147
	148	struct musb_dma_controller {
	149	struct dma_controller controller;
	150	struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
	151	void *private_data;
	152	void __iomem *base;
	153	u8 channel_count;
	154	u8 used_channels;
	155	u8 irq;
	156	};