[deliverable/linux.git] / drivers / usb / musb / omap2430.c

/*
 * Copyright (C) 2005-2007 by Texas Instruments
 * Some code has been taken from tusb6010.c
 * Copyrights for that are attributable to:
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * This file is part of the Inventra Controller Driver for Linux.
 *
 * The Inventra Controller Driver for Linux is free software; you
 * can redistribute it and/or modify it under the terms of the GNU
 * General Public License version 2 as published by the Free Software
 * Foundation.
 *
 * The Inventra Controller Driver for Linux is distributed in
 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
 * without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
 * License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with The Inventra Controller Driver for Linux ; if not,
 * write to the Free Software Foundation, Inc., 59 Temple Place,
 * Suite 330, Boston, MA  02111-1307  USA
 *
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/io.h>

#include "musb_core.h"
#include "omap2430.h"

static struct timer_list musb_idle_timer;

static void musb_do_idle(unsigned long _musb)
{
	struct musb	*musb = (void *)_musb;
	unsigned long	flags;
#ifdef CONFIG_USB_MUSB_HDRC_HCD
	u8	power;
#endif
	u8	devctl;

	spin_lock_irqsave(&musb->lock, flags);

	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);

	switch (musb->xceiv->state) {
	case OTG_STATE_A_WAIT_BCON:
		devctl &= ~MUSB_DEVCTL_SESSION;
		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);

		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
		if (devctl & MUSB_DEVCTL_BDEVICE) {
			musb->xceiv->state = OTG_STATE_B_IDLE;
			MUSB_DEV_MODE(musb);
		} else {
			musb->xceiv->state = OTG_STATE_A_IDLE;
			MUSB_HST_MODE(musb);
		}
		break;
#ifdef CONFIG_USB_MUSB_HDRC_HCD
	case OTG_STATE_A_SUSPEND:
		/* finish RESUME signaling? */
		if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
			power = musb_readb(musb->mregs, MUSB_POWER);
			power &= ~MUSB_POWER_RESUME;
			DBG(1, "root port resume stopped, power %02x\n", power);
			musb_writeb(musb->mregs, MUSB_POWER, power);
			musb->is_active = 1;
			musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
						| MUSB_PORT_STAT_RESUME);
			musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
			usb_hcd_poll_rh_status(musb_to_hcd(musb));
			/* NOTE: it might really be A_WAIT_BCON ... */
			musb->xceiv->state = OTG_STATE_A_HOST;
		}
		break;
#endif
#ifdef CONFIG_USB_MUSB_HDRC_HCD
	case OTG_STATE_A_HOST:
		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
		if (devctl &  MUSB_DEVCTL_BDEVICE)
			musb->xceiv->state = OTG_STATE_B_IDLE;
		else
			musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
#endif
	default:
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);
}


static void omap2430_musb_try_idle(struct musb *musb, unsigned long timeout)
{
	unsigned long		default_timeout = jiffies + msecs_to_jiffies(3);
	static unsigned long	last_timer;

	if (timeout == 0)
		timeout = default_timeout;

	/* Never idle if active, or when VBUS timeout is not set as host */
	if (musb->is_active || ((musb->a_wait_bcon == 0)
			&& (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
		DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
		del_timer(&musb_idle_timer);
		last_timer = jiffies;
		return;
	}

	if (time_after(last_timer, timeout)) {
		if (!timer_pending(&musb_idle_timer))
			last_timer = timeout;
		else {
			DBG(4, "Longer idle timer already pending, ignoring\n");
			return;
		}
	}
	last_timer = timeout;

	DBG(4, "%s inactive, for idle timer for %lu ms\n",
		otg_state_string(musb),
		(unsigned long)jiffies_to_msecs(timeout - jiffies));
	mod_timer(&musb_idle_timer, timeout);
}

static void omap2430_musb_enable(struct musb *musb)
{
}

static void omap2430_musb_disable(struct musb *musb)
{
}

static void omap2430_musb_set_vbus(struct musb *musb, int is_on)
{
	u8		devctl;
	/* HDRC controls CPEN, but beware current surges during device
	 * connect.  They can trigger transient overcurrent conditions
	 * that must be ignored.
	 */

	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);

	if (is_on) {
		musb->is_active = 1;
		musb->xceiv->default_a = 1;
		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
		devctl |= MUSB_DEVCTL_SESSION;

		MUSB_HST_MODE(musb);
	} else {
		musb->is_active = 0;

		/* NOTE:  we're skipping A_WAIT_VFALL -> A_IDLE and
		 * jumping right to B_IDLE...
		 */

		musb->xceiv->default_a = 0;
		musb->xceiv->state = OTG_STATE_B_IDLE;
		devctl &= ~MUSB_DEVCTL_SESSION;

		MUSB_DEV_MODE(musb);
	}
	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);

	DBG(1, "VBUS %s, devctl %02x "
		/* otg %3x conf %08x prcm %08x */ "\n",
		otg_state_string(musb),
		musb_readb(musb->mregs, MUSB_DEVCTL));
}

static int omap2430_musb_resume(struct musb *musb);

static int omap2430_musb_set_mode(struct musb *musb, u8 musb_mode)
{
	u8	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);

	devctl |= MUSB_DEVCTL_SESSION;
	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);

	return 0;
}

static int omap2430_musb_init(struct musb *musb)
{
	u32 l;
	struct device *dev = musb->controller;
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;

	/* We require some kind of external transceiver, hooked
	 * up through ULPI.  TWL4030-family PMICs include one,
	 * which needs a driver, drivers aren't always needed.
	 */
	musb->xceiv = otg_get_transceiver();
	if (!musb->xceiv) {
		pr_err("HS USB OTG: no transceiver configured\n");
		return -ENODEV;
	}

	omap2430_musb_resume(musb);

	l = musb_readl(musb->mregs, OTG_SYSCONFIG);
	l &= ~ENABLEWAKEUP;	/* disable wakeup */
	l &= ~NOSTDBY;		/* remove possible nostdby */
	l |= SMARTSTDBY;	/* enable smart standby */
	l &= ~AUTOIDLE;		/* disable auto idle */
	l &= ~NOIDLE;		/* remove possible noidle */
	l |= SMARTIDLE;		/* enable smart idle */
	/*
	 * MUSB AUTOIDLE don't work in 3430.
	 * Workaround by Richard Woodruff/TI
	 */
	if (!cpu_is_omap3430())
		l |= AUTOIDLE;		/* enable auto idle */
	musb_writel(musb->mregs, OTG_SYSCONFIG, l);

	l = musb_readl(musb->mregs, OTG_INTERFSEL);

	if (data->interface_type == MUSB_INTERFACE_UTMI) {
		/* OMAP4 uses Internal PHY GS70 which uses UTMI interface */
		l &= ~ULPI_12PIN;       /* Disable ULPI */
		l |= UTMI_8BIT;         /* Enable UTMI  */
	} else {
		l |= ULPI_12PIN;
	}

	musb_writel(musb->mregs, OTG_INTERFSEL, l);

	pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
			"sysstatus 0x%x, intrfsel 0x%x, simenable  0x%x\n",
			musb_readl(musb->mregs, OTG_REVISION),
			musb_readl(musb->mregs, OTG_SYSCONFIG),
			musb_readl(musb->mregs, OTG_SYSSTATUS),
			musb_readl(musb->mregs, OTG_INTERFSEL),
			musb_readl(musb->mregs, OTG_SIMENABLE));

	if (is_host_enabled(musb))
		musb->board_set_vbus = omap2430_musb_set_vbus;

	setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);

	return 0;
}

#ifdef CONFIG_PM
void musb_platform_save_context(struct musb *musb,
		struct musb_context_registers *musb_context)
{
	musb_context->otg_sysconfig = musb_readl(musb->mregs, OTG_SYSCONFIG);
	musb_context->otg_forcestandby = musb_readl(musb->mregs, OTG_FORCESTDBY);
}

void musb_platform_restore_context(struct musb *musb,
		struct musb_context_registers *musb_context)
{
	musb_writel(musb->mregs, OTG_SYSCONFIG, musb_context->otg_sysconfig);
	musb_writel(musb->mregs, OTG_FORCESTDBY, musb_context->otg_forcestandby);
}
#endif

static int omap2430_musb_suspend(struct musb *musb)
{
	u32 l;

	if (!musb->clock)
		return 0;

	/* in any role */
	l = musb_readl(musb->mregs, OTG_FORCESTDBY);
	l |= ENABLEFORCE;	/* enable MSTANDBY */
	musb_writel(musb->mregs, OTG_FORCESTDBY, l);

	l = musb_readl(musb->mregs, OTG_SYSCONFIG);
	l |= ENABLEWAKEUP;	/* enable wakeup */
	musb_writel(musb->mregs, OTG_SYSCONFIG, l);

	otg_set_suspend(musb->xceiv, 1);

	if (musb->set_clock)
		musb->set_clock(musb->clock, 0);
	else
		clk_disable(musb->clock);

	return 0;
}

static int omap2430_musb_resume(struct musb *musb)
{
	u32 l;

	if (!musb->clock)
		return 0;

	otg_set_suspend(musb->xceiv, 0);

	if (musb->set_clock)
		musb->set_clock(musb->clock, 1);
	else
		clk_enable(musb->clock);

	l = musb_readl(musb->mregs, OTG_SYSCONFIG);
	l &= ~ENABLEWAKEUP;	/* disable wakeup */
	musb_writel(musb->mregs, OTG_SYSCONFIG, l);

	l = musb_readl(musb->mregs, OTG_FORCESTDBY);
	l &= ~ENABLEFORCE;	/* disable MSTANDBY */
	musb_writel(musb->mregs, OTG_FORCESTDBY, l);

	return 0;
}

static int omap2430_musb_exit(struct musb *musb)
{

	omap2430_musb_suspend(musb);

	otg_put_transceiver(musb->xceiv);
	return 0;
}

const struct musb_platform_ops musb_ops = {
	.init		= omap2430_musb_init,
	.exit		= omap2430_musb_exit,

	.suspend	= omap2430_musb_suspend,
	.resume		= omap2430_musb_resume,

	.enable		= omap2430_musb_enable,
	.disable	= omap2430_musb_disable,

	.set_mode	= omap2430_musb_set_mode,
	.try_idle	= omap2430_musb_try_idle,

	.set_vbus	= omap2430_musb_set_vbus,
};
Commit	Line	Data
550a7375 FB	1	/*
	2	* Copyright (C) 2005-2007 by Texas Instruments
	3	* Some code has been taken from tusb6010.c
	4	* Copyrights for that are attributable to:
	5	* Copyright (C) 2006 Nokia Corporation
550a7375 FB	6	* Tony Lindgren <tony@atomide.com>
	7	*
	8	* This file is part of the Inventra Controller Driver for Linux.
	9	*
	10	* The Inventra Controller Driver for Linux is free software; you
	11	* can redistribute it and/or modify it under the terms of the GNU
	12	* General Public License version 2 as published by the Free Software
	13	* Foundation.
	14	*
	15	* The Inventra Controller Driver for Linux is distributed in
	16	* the hope that it will be useful, but WITHOUT ANY WARRANTY;
	17	* without even the implied warranty of MERCHANTABILITY or
	18	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	19	* License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with The Inventra Controller Driver for Linux ; if not,
	23	* write to the Free Software Foundation, Inc., 59 Temple Place,
	24	* Suite 330, Boston, MA 02111-1307 USA
	25	*
	26	*/
	27	#include <linux/module.h>
	28	#include <linux/kernel.h>
	29	#include <linux/sched.h>
550a7375 FB	30	#include <linux/init.h>
	31	#include <linux/list.h>
	32	#include <linux/clk.h>
	33	#include <linux/io.h>
	34
550a7375 FB	35	#include "musb_core.h"
	36	#include "omap2430.h"
	37
550a7375 FB	38	static struct timer_list musb_idle_timer;
	39
	40	static void musb_do_idle(unsigned long _musb)
	41	{
	42	struct musb musb = (void )_musb;
	43	unsigned long flags;
eef767b7	44	#ifdef CONFIG_USB_MUSB_HDRC_HCD
550a7375	45	u8 power;
eef767b7	46	#endif
550a7375 FB	47	u8 devctl;
550a7375 FB	48
550a7375 FB	49	spin_lock_irqsave(&musb->lock, flags);
550a7375 FB	50
71783e0d DB	51	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
71783e0d DB	52
84e250ff	53	switch (musb->xceiv->state) {
550a7375 FB	54	case OTG_STATE_A_WAIT_BCON:
	55	devctl &= ~MUSB_DEVCTL_SESSION;
	56	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
	57
	58	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
	59	if (devctl & MUSB_DEVCTL_BDEVICE) {
84e250ff	60	musb->xceiv->state = OTG_STATE_B_IDLE;
550a7375 FB	61	MUSB_DEV_MODE(musb);
550a7375 FB	62	} else {
84e250ff	63	musb->xceiv->state = OTG_STATE_A_IDLE;
550a7375 FB	64	MUSB_HST_MODE(musb);
	65	}
	66	break;
	67	#ifdef CONFIG_USB_MUSB_HDRC_HCD
	68	case OTG_STATE_A_SUSPEND:
	69	/* finish RESUME signaling? */
	70	if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
	71	power = musb_readb(musb->mregs, MUSB_POWER);
	72	power &= ~MUSB_POWER_RESUME;
	73	DBG(1, "root port resume stopped, power %02x\n", power);
	74	musb_writeb(musb->mregs, MUSB_POWER, power);
	75	musb->is_active = 1;
	76	musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
	77	\| MUSB_PORT_STAT_RESUME);
	78	musb->port1_status \|= USB_PORT_STAT_C_SUSPEND << 16;
	79	usb_hcd_poll_rh_status(musb_to_hcd(musb));
	80	/* NOTE: it might really be A_WAIT_BCON ... */
84e250ff	81	musb->xceiv->state = OTG_STATE_A_HOST;
550a7375 FB	82	}
	83	break;
	84	#endif
	85	#ifdef CONFIG_USB_MUSB_HDRC_HCD
	86	case OTG_STATE_A_HOST:
	87	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
	88	if (devctl & MUSB_DEVCTL_BDEVICE)
84e250ff	89	musb->xceiv->state = OTG_STATE_B_IDLE;
550a7375	90	else
84e250ff	91	musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
550a7375 FB	92	#endif
	93	default:
	94	break;
	95	}
	96	spin_unlock_irqrestore(&musb->lock, flags);
	97	}
	98
	99
743411b3	100	static void omap2430_musb_try_idle(struct musb *musb, unsigned long timeout)
550a7375 FB	101	{
	102	unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
	103	static unsigned long last_timer;
	104
	105	if (timeout == 0)
	106	timeout = default_timeout;
	107
	108	/* Never idle if active, or when VBUS timeout is not set as host */
	109	if (musb->is_active \|\| ((musb->a_wait_bcon == 0)
84e250ff	110	&& (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
550a7375 FB	111	DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
	112	del_timer(&musb_idle_timer);
	113	last_timer = jiffies;
	114	return;
	115	}
	116
	117	if (time_after(last_timer, timeout)) {
	118	if (!timer_pending(&musb_idle_timer))
	119	last_timer = timeout;
	120	else {
	121	DBG(4, "Longer idle timer already pending, ignoring\n");
	122	return;
	123	}
	124	}
	125	last_timer = timeout;
	126
	127	DBG(4, "%s inactive, for idle timer for %lu ms\n",
	128	otg_state_string(musb),
	129	(unsigned long)jiffies_to_msecs(timeout - jiffies));
	130	mod_timer(&musb_idle_timer, timeout);
	131	}
	132
743411b3	133	static void omap2430_musb_enable(struct musb *musb)
550a7375 FB	134	{
550a7375 FB	135	}
743411b3 FB	136
743411b3 FB	137	static void omap2430_musb_disable(struct musb *musb)
550a7375 FB	138	{
550a7375 FB	139	}
743411b3 FB	140
743411b3 FB	141	static void omap2430_musb_set_vbus(struct musb *musb, int is_on)
550a7375 FB	142	{
	143	u8 devctl;
	144	/* HDRC controls CPEN, but beware current surges during device
	145	* connect. They can trigger transient overcurrent conditions
	146	* that must be ignored.
	147	*/
	148
	149	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
	150
	151	if (is_on) {
	152	musb->is_active = 1;
84e250ff DB	153	musb->xceiv->default_a = 1;
84e250ff DB	154	musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
550a7375 FB	155	devctl \|= MUSB_DEVCTL_SESSION;
	156
	157	MUSB_HST_MODE(musb);
	158	} else {
	159	musb->is_active = 0;
	160
	161	/* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and
	162	* jumping right to B_IDLE...
	163	*/
	164
84e250ff DB	165	musb->xceiv->default_a = 0;
84e250ff DB	166	musb->xceiv->state = OTG_STATE_B_IDLE;
550a7375 FB	167	devctl &= ~MUSB_DEVCTL_SESSION;
	168
	169	MUSB_DEV_MODE(musb);
	170	}
	171	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
	172
	173	DBG(1, "VBUS %s, devctl %02x "
	174	/* otg %3x conf %08x prcm %08x */ "\n",
	175	otg_state_string(musb),
	176	musb_readb(musb->mregs, MUSB_DEVCTL));
	177	}
550a7375	178
743411b3	179	static int omap2430_musb_resume(struct musb *musb);
550a7375	180
743411b3	181	static int omap2430_musb_set_mode(struct musb *musb, u8 musb_mode)
550a7375 FB	182	{
	183	u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
	184
	185	devctl \|= MUSB_DEVCTL_SESSION;
	186	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
	187
96a274d1	188	return 0;
550a7375 FB	189	}
550a7375 FB	190
743411b3	191	static int omap2430_musb_init(struct musb *musb)
550a7375 FB	192	{
550a7375 FB	193	u32 l;
ea65df57 HK	194	struct device *dev = musb->controller;
	195	struct musb_hdrc_platform_data *plat = dev->platform_data;
	196	struct omap_musb_board_data *data = plat->board_data;
550a7375	197
84e250ff DB	198	/* We require some kind of external transceiver, hooked
	199	* up through ULPI. TWL4030-family PMICs include one,
	200	* which needs a driver, drivers aren't always needed.
	201	*/
	202	musb->xceiv = otg_get_transceiver();
	203	if (!musb->xceiv) {
	204	pr_err("HS USB OTG: no transceiver configured\n");
	205	return -ENODEV;
	206	}
	207
743411b3	208	omap2430_musb_resume(musb);
550a7375	209
8573e6a6	210	l = musb_readl(musb->mregs, OTG_SYSCONFIG);
550a7375 FB	211	l &= ~ENABLEWAKEUP; /* disable wakeup */
	212	l &= ~NOSTDBY; /* remove possible nostdby */
	213	l \|= SMARTSTDBY; /* enable smart standby */
	214	l &= ~AUTOIDLE; /* disable auto idle */
	215	l &= ~NOIDLE; /* remove possible noidle */
	216	l \|= SMARTIDLE; /* enable smart idle */
9a4b5e36 NM	217	/*
	218	* MUSB AUTOIDLE don't work in 3430.
	219	* Workaround by Richard Woodruff/TI
	220	*/
	221	if (!cpu_is_omap3430())
	222	l \|= AUTOIDLE; /* enable auto idle */
8573e6a6	223	musb_writel(musb->mregs, OTG_SYSCONFIG, l);
550a7375	224
8573e6a6	225	l = musb_readl(musb->mregs, OTG_INTERFSEL);
de2e1b0c MM	226
	227	if (data->interface_type == MUSB_INTERFACE_UTMI) {
	228	/* OMAP4 uses Internal PHY GS70 which uses UTMI interface */
	229	l &= ~ULPI_12PIN; /* Disable ULPI */
	230	l \|= UTMI_8BIT; /* Enable UTMI */
	231	} else {
	232	l \|= ULPI_12PIN;
	233	}
	234
8573e6a6	235	musb_writel(musb->mregs, OTG_INTERFSEL, l);
550a7375 FB	236
	237	pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
	238	"sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n",
8573e6a6 FB	239	musb_readl(musb->mregs, OTG_REVISION),
	240	musb_readl(musb->mregs, OTG_SYSCONFIG),
	241	musb_readl(musb->mregs, OTG_SYSSTATUS),
	242	musb_readl(musb->mregs, OTG_INTERFSEL),
	243	musb_readl(musb->mregs, OTG_SIMENABLE));
550a7375	244
550a7375	245	if (is_host_enabled(musb))
743411b3	246	musb->board_set_vbus = omap2430_musb_set_vbus;
550a7375 FB	247
	248	setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
	249
	250	return 0;
	251	}
	252
4f712e01	253	#ifdef CONFIG_PM
8573e6a6 FB	254	void musb_platform_save_context(struct musb *musb,
8573e6a6 FB	255	struct musb_context_registers *musb_context)
4f712e01	256	{
8573e6a6 FB	257	musb_context->otg_sysconfig = musb_readl(musb->mregs, OTG_SYSCONFIG);
8573e6a6 FB	258	musb_context->otg_forcestandby = musb_readl(musb->mregs, OTG_FORCESTDBY);
4f712e01 AKG	259	}
4f712e01 AKG	260
8573e6a6 FB	261	void musb_platform_restore_context(struct musb *musb,
8573e6a6 FB	262	struct musb_context_registers *musb_context)
4f712e01	263	{
8573e6a6 FB	264	musb_writel(musb->mregs, OTG_SYSCONFIG, musb_context->otg_sysconfig);
8573e6a6 FB	265	musb_writel(musb->mregs, OTG_FORCESTDBY, musb_context->otg_forcestandby);
4f712e01 AKG	266	}
	267	#endif
	268
743411b3	269	static int omap2430_musb_suspend(struct musb *musb)
550a7375 FB	270	{
	271	u32 l;
	272
	273	if (!musb->clock)
	274	return 0;
	275
	276	/* in any role */
8573e6a6	277	l = musb_readl(musb->mregs, OTG_FORCESTDBY);
550a7375	278	l \|= ENABLEFORCE; /* enable MSTANDBY */
8573e6a6	279	musb_writel(musb->mregs, OTG_FORCESTDBY, l);
550a7375	280
8573e6a6	281	l = musb_readl(musb->mregs, OTG_SYSCONFIG);
550a7375	282	l \|= ENABLEWAKEUP; /* enable wakeup */
8573e6a6	283	musb_writel(musb->mregs, OTG_SYSCONFIG, l);
550a7375	284
84e250ff	285	otg_set_suspend(musb->xceiv, 1);
550a7375 FB	286
	287	if (musb->set_clock)
	288	musb->set_clock(musb->clock, 0);
	289	else
	290	clk_disable(musb->clock);
	291
	292	return 0;
	293	}
	294
743411b3	295	static int omap2430_musb_resume(struct musb *musb)
550a7375 FB	296	{
	297	u32 l;
	298
	299	if (!musb->clock)
	300	return 0;
	301
84e250ff	302	otg_set_suspend(musb->xceiv, 0);
550a7375 FB	303
	304	if (musb->set_clock)
	305	musb->set_clock(musb->clock, 1);
	306	else
	307	clk_enable(musb->clock);
	308
8573e6a6	309	l = musb_readl(musb->mregs, OTG_SYSCONFIG);
550a7375	310	l &= ~ENABLEWAKEUP; /* disable wakeup */
8573e6a6	311	musb_writel(musb->mregs, OTG_SYSCONFIG, l);
550a7375	312
8573e6a6	313	l = musb_readl(musb->mregs, OTG_FORCESTDBY);
550a7375	314	l &= ~ENABLEFORCE; /* disable MSTANDBY */
8573e6a6	315	musb_writel(musb->mregs, OTG_FORCESTDBY, l);
550a7375 FB	316
	317	return 0;
	318	}
	319
743411b3	320	static int omap2430_musb_exit(struct musb *musb)
550a7375 FB	321	{
550a7375 FB	322
743411b3	323	omap2430_musb_suspend(musb);
550a7375	324
f4053874	325	otg_put_transceiver(musb->xceiv);
550a7375 FB	326	return 0;
550a7375 FB	327	}
743411b3 FB	328
	329	const struct musb_platform_ops musb_ops = {
	330	.init = omap2430_musb_init,
	331	.exit = omap2430_musb_exit,
	332
	333	.suspend = omap2430_musb_suspend,
	334	.resume = omap2430_musb_resume,
	335
	336	.enable = omap2430_musb_enable,
	337	.disable = omap2430_musb_disable,
	338
	339	.set_mode = omap2430_musb_set_mode,
	340	.try_idle = omap2430_musb_try_idle,
	341
	342	.set_vbus = omap2430_musb_set_vbus,
	343	};