[deliverable/linux.git] / drivers / usb / musb / ux500_dma.c

/*
 * drivers/usb/musb/ux500_dma.c
 *
 * U8500 DMA support code
 *
 * Copyright (C) 2009 STMicroelectronics
 * Copyright (C) 2011 ST-Ericsson SA
 * Authors:
 *	Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
 *	Praveena Nadahally <praveen.nadahally@stericsson.com>
 *	Rajaram Regupathy <ragupathy.rajaram@stericsson.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/pfn.h>
#include <linux/sizes.h>
#include <linux/platform_data/usb-musb-ux500.h>
#include "musb_core.h"

static const char *iep_chan_names[] = { "iep_1_9", "iep_2_10", "iep_3_11", "iep_4_12",
					"iep_5_13", "iep_6_14", "iep_7_15", "iep_8" };
static const char *oep_chan_names[] = { "oep_1_9", "oep_2_10", "oep_3_11", "oep_4_12",
					"oep_5_13", "oep_6_14", "oep_7_15", "oep_8" };

struct ux500_dma_channel {
	struct dma_channel channel;
	struct ux500_dma_controller *controller;
	struct musb_hw_ep *hw_ep;
	struct dma_chan *dma_chan;
	unsigned int cur_len;
	dma_cookie_t cookie;
	u8 ch_num;
	u8 is_tx;
	u8 is_allocated;
};

struct ux500_dma_controller {
	struct dma_controller controller;
	struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
	struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
	void *private_data;
	dma_addr_t phy_base;
};

/* Work function invoked from DMA callback to handle rx transfers. */
static void ux500_dma_callback(void *private_data)
{
	struct dma_channel *channel = private_data;
	struct ux500_dma_channel *ux500_channel = channel->private_data;
	struct musb_hw_ep       *hw_ep = ux500_channel->hw_ep;
	struct musb *musb = hw_ep->musb;
	unsigned long flags;

	dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n",
		hw_ep->epnum);

	spin_lock_irqsave(&musb->lock, flags);
	ux500_channel->channel.actual_len = ux500_channel->cur_len;
	ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
	musb_dma_completion(musb, hw_ep->epnum, ux500_channel->is_tx);
	spin_unlock_irqrestore(&musb->lock, flags);

}

static bool ux500_configure_channel(struct dma_channel *channel,
				u16 packet_sz, u8 mode,
				dma_addr_t dma_addr, u32 len)
{
	struct ux500_dma_channel *ux500_channel = channel->private_data;
	struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
	struct dma_chan *dma_chan = ux500_channel->dma_chan;
	struct dma_async_tx_descriptor *dma_desc;
	enum dma_transfer_direction direction;
	struct scatterlist sg;
	struct dma_slave_config slave_conf;
	enum dma_slave_buswidth addr_width;
	struct musb *musb = ux500_channel->controller->private_data;
	dma_addr_t usb_fifo_addr = (musb->io.fifo_offset(hw_ep->epnum) +
					ux500_channel->controller->phy_base);

	dev_dbg(musb->controller,
		"packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
		packet_sz, mode, (unsigned long long) dma_addr,
		len, ux500_channel->is_tx);

	ux500_channel->cur_len = len;

	sg_init_table(&sg, 1);
	sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_addr)), len,
					    offset_in_page(dma_addr));
	sg_dma_address(&sg) = dma_addr;
	sg_dma_len(&sg) = len;

	direction = ux500_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
	addr_width = (len & 0x3) ? DMA_SLAVE_BUSWIDTH_1_BYTE :
					DMA_SLAVE_BUSWIDTH_4_BYTES;

	slave_conf.direction = direction;
	slave_conf.src_addr = usb_fifo_addr;
	slave_conf.src_addr_width = addr_width;
	slave_conf.src_maxburst = 16;
	slave_conf.dst_addr = usb_fifo_addr;
	slave_conf.dst_addr_width = addr_width;
	slave_conf.dst_maxburst = 16;
	slave_conf.device_fc = false;

	dmaengine_slave_config(dma_chan, &slave_conf);

	dma_desc = dmaengine_prep_slave_sg(dma_chan, &sg, 1, direction,
					     DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	if (!dma_desc)
		return false;

	dma_desc->callback = ux500_dma_callback;
	dma_desc->callback_param = channel;
	ux500_channel->cookie = dma_desc->tx_submit(dma_desc);

	dma_async_issue_pending(dma_chan);

	return true;
}

static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c,
				struct musb_hw_ep *hw_ep, u8 is_tx)
{
	struct ux500_dma_controller *controller = container_of(c,
			struct ux500_dma_controller, controller);
	struct ux500_dma_channel *ux500_channel = NULL;
	struct musb *musb = controller->private_data;
	u8 ch_num = hw_ep->epnum - 1;

	/* 8 DMA channels (0 - 7). Each DMA channel can only be allocated
	 * to specified hw_ep. For example DMA channel 0 can only be allocated
	 * to hw_ep 1 and 9.
	 */
	if (ch_num > 7)
		ch_num -= 8;

	if (ch_num >= UX500_MUSB_DMA_NUM_RX_TX_CHANNELS)
		return NULL;

	ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) :
				&(controller->rx_channel[ch_num]) ;

	/* Check if channel is already used. */
	if (ux500_channel->is_allocated)
		return NULL;

	ux500_channel->hw_ep = hw_ep;
	ux500_channel->is_allocated = 1;

	dev_dbg(musb->controller, "hw_ep=%d, is_tx=0x%x, channel=%d\n",
		hw_ep->epnum, is_tx, ch_num);

	return &(ux500_channel->channel);
}

static void ux500_dma_channel_release(struct dma_channel *channel)
{
	struct ux500_dma_channel *ux500_channel = channel->private_data;
	struct musb *musb = ux500_channel->controller->private_data;

	dev_dbg(musb->controller, "channel=%d\n", ux500_channel->ch_num);

	if (ux500_channel->is_allocated) {
		ux500_channel->is_allocated = 0;
		channel->status = MUSB_DMA_STATUS_FREE;
		channel->actual_len = 0;
	}
}

static int ux500_dma_is_compatible(struct dma_channel *channel,
		u16 maxpacket, void *buf, u32 length)
{
	if ((maxpacket & 0x3)		||
		((unsigned long int) buf & 0x3)	||
		(length < 512)		||
		(length & 0x3))
		return false;
	else
		return true;
}

static int ux500_dma_channel_program(struct dma_channel *channel,
				u16 packet_sz, u8 mode,
				dma_addr_t dma_addr, u32 len)
{
	int ret;

	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
		channel->status == MUSB_DMA_STATUS_BUSY);

	channel->status = MUSB_DMA_STATUS_BUSY;
	channel->actual_len = 0;
	ret = ux500_configure_channel(channel, packet_sz, mode, dma_addr, len);
	if (!ret)
		channel->status = MUSB_DMA_STATUS_FREE;

	return ret;
}

static int ux500_dma_channel_abort(struct dma_channel *channel)
{
	struct ux500_dma_channel *ux500_channel = channel->private_data;
	struct ux500_dma_controller *controller = ux500_channel->controller;
	struct musb *musb = controller->private_data;
	void __iomem *epio = musb->endpoints[ux500_channel->hw_ep->epnum].regs;
	u16 csr;

	dev_dbg(musb->controller, "channel=%d, is_tx=%d\n",
		ux500_channel->ch_num, ux500_channel->is_tx);

	if (channel->status == MUSB_DMA_STATUS_BUSY) {
		if (ux500_channel->is_tx) {
			csr = musb_readw(epio, MUSB_TXCSR);
			csr &= ~(MUSB_TXCSR_AUTOSET |
				 MUSB_TXCSR_DMAENAB |
				 MUSB_TXCSR_DMAMODE);
			musb_writew(epio, MUSB_TXCSR, csr);
		} else {
			csr = musb_readw(epio, MUSB_RXCSR);
			csr &= ~(MUSB_RXCSR_AUTOCLEAR |
				 MUSB_RXCSR_DMAENAB |
				 MUSB_RXCSR_DMAMODE);
			musb_writew(epio, MUSB_RXCSR, csr);
		}

		dmaengine_terminate_all(ux500_channel->dma_chan);
		channel->status = MUSB_DMA_STATUS_FREE;
	}
	return 0;
}

static void ux500_dma_controller_stop(struct ux500_dma_controller *controller)
{
	struct ux500_dma_channel *ux500_channel;
	struct dma_channel *channel;
	u8 ch_num;

	for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
		channel = &controller->rx_channel[ch_num].channel;
		ux500_channel = channel->private_data;

		ux500_dma_channel_release(channel);

		if (ux500_channel->dma_chan)
			dma_release_channel(ux500_channel->dma_chan);
	}

	for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
		channel = &controller->tx_channel[ch_num].channel;
		ux500_channel = channel->private_data;

		ux500_dma_channel_release(channel);

		if (ux500_channel->dma_chan)
			dma_release_channel(ux500_channel->dma_chan);
	}
}

static int ux500_dma_controller_start(struct ux500_dma_controller *controller)
{
	struct ux500_dma_channel *ux500_channel = NULL;
	struct musb *musb = controller->private_data;
	struct device *dev = musb->controller;
	struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
	struct ux500_musb_board_data *data;
	struct dma_channel *dma_channel = NULL;
	char **chan_names;
	u32 ch_num;
	u8 dir;
	u8 is_tx = 0;

	void **param_array;
	struct ux500_dma_channel *channel_array;
	dma_cap_mask_t mask;

	if (!plat) {
		dev_err(musb->controller, "No platform data\n");
		return -EINVAL;
	}

	data = plat->board_data;

	dma_cap_zero(mask);
	dma_cap_set(DMA_SLAVE, mask);

	/* Prepare the loop for RX channels */
	channel_array = controller->rx_channel;
	param_array = data ? data->dma_rx_param_array : NULL;
	chan_names = (char **)iep_chan_names;

	for (dir = 0; dir < 2; dir++) {
		for (ch_num = 0;
		     ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS;
		     ch_num++) {
			ux500_channel = &channel_array[ch_num];
			ux500_channel->controller = controller;
			ux500_channel->ch_num = ch_num;
			ux500_channel->is_tx = is_tx;

			dma_channel = &(ux500_channel->channel);
			dma_channel->private_data = ux500_channel;
			dma_channel->status = MUSB_DMA_STATUS_FREE;
			dma_channel->max_len = SZ_16M;

			ux500_channel->dma_chan =
				dma_request_slave_channel(dev, chan_names[ch_num]);

			if (!ux500_channel->dma_chan)
				ux500_channel->dma_chan =
					dma_request_channel(mask,
							    data ?
							    data->dma_filter :
							    NULL,
							    param_array ?
							    param_array[ch_num] :
							    NULL);

			if (!ux500_channel->dma_chan) {
				ERR("Dma pipe allocation error dir=%d ch=%d\n",
					dir, ch_num);

				/* Release already allocated channels */
				ux500_dma_controller_stop(controller);

				return -EBUSY;
			}

		}

		/* Prepare the loop for TX channels */
		channel_array = controller->tx_channel;
		param_array = data ? data->dma_tx_param_array : NULL;
		chan_names = (char **)oep_chan_names;
		is_tx = 1;
	}

	return 0;
}

void ux500_dma_controller_destroy(struct dma_controller *c)
{
	struct ux500_dma_controller *controller = container_of(c,
			struct ux500_dma_controller, controller);

	ux500_dma_controller_stop(controller);
	kfree(controller);
}
EXPORT_SYMBOL_GPL(ux500_dma_controller_destroy);

struct dma_controller *
ux500_dma_controller_create(struct musb *musb, void __iomem *base)
{
	struct ux500_dma_controller *controller;
	struct platform_device *pdev = to_platform_device(musb->controller);
	struct resource	*iomem;
	int ret;

	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
	if (!controller)
		goto kzalloc_fail;

	controller->private_data = musb;

	/* Save physical address for DMA controller. */
	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!iomem) {
		dev_err(musb->controller, "no memory resource defined\n");
		goto plat_get_fail;
	}

	controller->phy_base = (dma_addr_t) iomem->start;

	controller->controller.channel_alloc = ux500_dma_channel_allocate;
	controller->controller.channel_release = ux500_dma_channel_release;
	controller->controller.channel_program = ux500_dma_channel_program;
	controller->controller.channel_abort = ux500_dma_channel_abort;
	controller->controller.is_compatible = ux500_dma_is_compatible;

	ret = ux500_dma_controller_start(controller);
	if (ret)
		goto plat_get_fail;
	return &controller->controller;

plat_get_fail:
	kfree(controller);
kzalloc_fail:
	return NULL;
}
EXPORT_SYMBOL_GPL(ux500_dma_controller_create);
Commit	Line	Data
8dcc8f72 MYK	1	/*
	2	* drivers/usb/musb/ux500_dma.c
	3	*
3ee1f2e6	4	* U8500 DMA support code
8dcc8f72 MYK	5	*
	6	* Copyright (C) 2009 STMicroelectronics
	7	* Copyright (C) 2011 ST-Ericsson SA
	8	* Authors:
	9	* Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
	10	* Praveena Nadahally <praveen.nadahally@stericsson.com>
	11	* Rajaram Regupathy <ragupathy.rajaram@stericsson.com>
	12	*
	13	* This program is free software: you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License as published by
	15	* the Free Software Foundation, either version 2 of the License, or
	16	* (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	25	*/
	26
	27	#include <linux/device.h>
	28	#include <linux/interrupt.h>
	29	#include <linux/platform_device.h>
	30	#include <linux/dma-mapping.h>
	31	#include <linux/dmaengine.h>
	32	#include <linux/pfn.h>
0f53e481	33	#include <linux/sizes.h>
db298da2	34	#include <linux/platform_data/usb-musb-ux500.h>
8dcc8f72 MYK	35	#include "musb_core.h"
8dcc8f72 MYK	36
2968da0b LJ	37	static const char *iep_chan_names[] = { "iep_1_9", "iep_2_10", "iep_3_11", "iep_4_12",
	38	"iep_5_13", "iep_6_14", "iep_7_15", "iep_8" };
	39	static const char *oep_chan_names[] = { "oep_1_9", "oep_2_10", "oep_3_11", "oep_4_12",
	40	"oep_5_13", "oep_6_14", "oep_7_15", "oep_8" };
	41
8dcc8f72 MYK	42	struct ux500_dma_channel {
	43	struct dma_channel channel;
	44	struct ux500_dma_controller *controller;
	45	struct musb_hw_ep *hw_ep;
8dcc8f72 MYK	46	struct dma_chan *dma_chan;
	47	unsigned int cur_len;
	48	dma_cookie_t cookie;
	49	u8 ch_num;
	50	u8 is_tx;
	51	u8 is_allocated;
	52	};
	53
	54	struct ux500_dma_controller {
	55	struct dma_controller controller;
be2dbb09 LJ	56	struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
be2dbb09 LJ	57	struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
8dcc8f72 MYK	58	void *private_data;
	59	dma_addr_t phy_base;
	60	};
	61
8dcc8f72	62	/* Work function invoked from DMA callback to handle rx transfers. */
6b0cfc65	63	static void ux500_dma_callback(void *private_data)
8dcc8f72	64	{
be18a251 PF	65	struct dma_channel *channel = private_data;
be18a251 PF	66	struct ux500_dma_channel *ux500_channel = channel->private_data;
8dcc8f72 MYK	67	struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
	68	struct musb *musb = hw_ep->musb;
	69	unsigned long flags;
	70
afbd0749 PF	71	dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n",
afbd0749 PF	72	hw_ep->epnum);
8dcc8f72 MYK	73
	74	spin_lock_irqsave(&musb->lock, flags);
	75	ux500_channel->channel.actual_len = ux500_channel->cur_len;
	76	ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
3147dad6	77	musb_dma_completion(musb, hw_ep->epnum, ux500_channel->is_tx);
8dcc8f72	78	spin_unlock_irqrestore(&musb->lock, flags);
8dcc8f72	79
8dcc8f72 MYK	80	}
	81
	82	static bool ux500_configure_channel(struct dma_channel *channel,
	83	u16 packet_sz, u8 mode,
	84	dma_addr_t dma_addr, u32 len)
	85	{
	86	struct ux500_dma_channel *ux500_channel = channel->private_data;
	87	struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
	88	struct dma_chan *dma_chan = ux500_channel->dma_chan;
	89	struct dma_async_tx_descriptor *dma_desc;
8341544c	90	enum dma_transfer_direction direction;
8dcc8f72 MYK	91	struct scatterlist sg;
	92	struct dma_slave_config slave_conf;
	93	enum dma_slave_buswidth addr_width;
afbd0749	94	struct musb *musb = ux500_channel->controller->private_data;
1b40fc57 TL	95	dma_addr_t usb_fifo_addr = (musb->io.fifo_offset(hw_ep->epnum) +
1b40fc57 TL	96	ux500_channel->controller->phy_base);
8dcc8f72	97
afbd0749	98	dev_dbg(musb->controller,
50f9f798	99	"packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
6a3b0036 FB	100	packet_sz, mode, (unsigned long long) dma_addr,
6a3b0036 FB	101	len, ux500_channel->is_tx);
8dcc8f72 MYK	102
	103	ux500_channel->cur_len = len;
	104
	105	sg_init_table(&sg, 1);
	106	sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_addr)), len,
	107	offset_in_page(dma_addr));
	108	sg_dma_address(&sg) = dma_addr;
	109	sg_dma_len(&sg) = len;
	110
8341544c	111	direction = ux500_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
8dcc8f72 MYK	112	addr_width = (len & 0x3) ? DMA_SLAVE_BUSWIDTH_1_BYTE :
	113	DMA_SLAVE_BUSWIDTH_4_BYTES;
	114
	115	slave_conf.direction = direction;
d366d39b PF	116	slave_conf.src_addr = usb_fifo_addr;
	117	slave_conf.src_addr_width = addr_width;
	118	slave_conf.src_maxburst = 16;
	119	slave_conf.dst_addr = usb_fifo_addr;
	120	slave_conf.dst_addr_width = addr_width;
	121	slave_conf.dst_maxburst = 16;
258aea76	122	slave_conf.device_fc = false;
d366d39b	123
3da6702f	124	dmaengine_slave_config(dma_chan, &slave_conf);
8dcc8f72	125
16052827	126	dma_desc = dmaengine_prep_slave_sg(dma_chan, &sg, 1, direction,
8dcc8f72 MYK	127	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	128	if (!dma_desc)
	129	return false;
	130
	131	dma_desc->callback = ux500_dma_callback;
	132	dma_desc->callback_param = channel;
	133	ux500_channel->cookie = dma_desc->tx_submit(dma_desc);
	134
	135	dma_async_issue_pending(dma_chan);
	136
	137	return true;
	138	}
	139
	140	static struct dma_channel ux500_dma_channel_allocate(struct dma_controller c,
	141	struct musb_hw_ep *hw_ep, u8 is_tx)
	142	{
	143	struct ux500_dma_controller *controller = container_of(c,
	144	struct ux500_dma_controller, controller);
	145	struct ux500_dma_channel *ux500_channel = NULL;
afbd0749	146	struct musb *musb = controller->private_data;
8dcc8f72	147	u8 ch_num = hw_ep->epnum - 1;
8dcc8f72	148
be2dbb09	149	/* 8 DMA channels (0 - 7). Each DMA channel can only be allocated
8dcc8f72 MYK	150	* to specified hw_ep. For example DMA channel 0 can only be allocated
	151	* to hw_ep 1 and 9.
	152	*/
	153	if (ch_num > 7)
	154	ch_num -= 8;
	155
be2dbb09	156	if (ch_num >= UX500_MUSB_DMA_NUM_RX_TX_CHANNELS)
8dcc8f72 MYK	157	return NULL;
	158
	159	ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) :
	160	&(controller->rx_channel[ch_num]) ;
	161
	162	/* Check if channel is already used. */
	163	if (ux500_channel->is_allocated)
	164	return NULL;
	165
	166	ux500_channel->hw_ep = hw_ep;
	167	ux500_channel->is_allocated = 1;
	168
afbd0749	169	dev_dbg(musb->controller, "hw_ep=%d, is_tx=0x%x, channel=%d\n",
8dcc8f72 MYK	170	hw_ep->epnum, is_tx, ch_num);
	171
	172	return &(ux500_channel->channel);
	173	}
	174
	175	static void ux500_dma_channel_release(struct dma_channel *channel)
	176	{
	177	struct ux500_dma_channel *ux500_channel = channel->private_data;
afbd0749	178	struct musb *musb = ux500_channel->controller->private_data;
8dcc8f72	179
afbd0749	180	dev_dbg(musb->controller, "channel=%d\n", ux500_channel->ch_num);
8dcc8f72 MYK	181
	182	if (ux500_channel->is_allocated) {
	183	ux500_channel->is_allocated = 0;
	184	channel->status = MUSB_DMA_STATUS_FREE;
	185	channel->actual_len = 0;
	186	}
	187	}
	188
	189	static int ux500_dma_is_compatible(struct dma_channel *channel,
	190	u16 maxpacket, void *buf, u32 length)
	191	{
	192	if ((maxpacket & 0x3) \|\|
6a3b0036	193	((unsigned long int) buf & 0x3) \|\|
8dcc8f72 MYK	194	(length < 512) \|\|
	195	(length & 0x3))
	196	return false;
	197	else
	198	return true;
	199	}
	200
	201	static int ux500_dma_channel_program(struct dma_channel *channel,
	202	u16 packet_sz, u8 mode,
	203	dma_addr_t dma_addr, u32 len)
	204	{
	205	int ret;
	206
	207	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN \|\|
	208	channel->status == MUSB_DMA_STATUS_BUSY);
	209
8dcc8f72 MYK	210	channel->status = MUSB_DMA_STATUS_BUSY;
	211	channel->actual_len = 0;
	212	ret = ux500_configure_channel(channel, packet_sz, mode, dma_addr, len);
	213	if (!ret)
	214	channel->status = MUSB_DMA_STATUS_FREE;
	215
	216	return ret;
	217	}
	218
	219	static int ux500_dma_channel_abort(struct dma_channel *channel)
	220	{
	221	struct ux500_dma_channel *ux500_channel = channel->private_data;
	222	struct ux500_dma_controller *controller = ux500_channel->controller;
	223	struct musb *musb = controller->private_data;
	224	void __iomem *epio = musb->endpoints[ux500_channel->hw_ep->epnum].regs;
	225	u16 csr;
	226
afbd0749 PF	227	dev_dbg(musb->controller, "channel=%d, is_tx=%d\n",
afbd0749 PF	228	ux500_channel->ch_num, ux500_channel->is_tx);
8dcc8f72 MYK	229
	230	if (channel->status == MUSB_DMA_STATUS_BUSY) {
	231	if (ux500_channel->is_tx) {
	232	csr = musb_readw(epio, MUSB_TXCSR);
	233	csr &= ~(MUSB_TXCSR_AUTOSET \|
	234	MUSB_TXCSR_DMAENAB \|
	235	MUSB_TXCSR_DMAMODE);
	236	musb_writew(epio, MUSB_TXCSR, csr);
	237	} else {
	238	csr = musb_readw(epio, MUSB_RXCSR);
	239	csr &= ~(MUSB_RXCSR_AUTOCLEAR \|
	240	MUSB_RXCSR_DMAENAB \|
	241	MUSB_RXCSR_DMAMODE);
	242	musb_writew(epio, MUSB_RXCSR, csr);
	243	}
	244
3da6702f	245	dmaengine_terminate_all(ux500_channel->dma_chan);
8dcc8f72 MYK	246	channel->status = MUSB_DMA_STATUS_FREE;
	247	}
	248	return 0;
	249	}
	250
66c01883	251	static void ux500_dma_controller_stop(struct ux500_dma_controller *controller)
8dcc8f72	252	{
8dcc8f72 MYK	253	struct ux500_dma_channel *ux500_channel;
	254	struct dma_channel *channel;
	255	u8 ch_num;
	256
be2dbb09	257	for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
8dcc8f72 MYK	258	channel = &controller->rx_channel[ch_num].channel;
	259	ux500_channel = channel->private_data;
	260
	261	ux500_dma_channel_release(channel);
	262
	263	if (ux500_channel->dma_chan)
	264	dma_release_channel(ux500_channel->dma_chan);
	265	}
	266
be2dbb09	267	for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
8dcc8f72 MYK	268	channel = &controller->tx_channel[ch_num].channel;
	269	ux500_channel = channel->private_data;
	270
	271	ux500_dma_channel_release(channel);
	272
	273	if (ux500_channel->dma_chan)
	274	dma_release_channel(ux500_channel->dma_chan);
	275	}
8dcc8f72 MYK	276	}
8dcc8f72 MYK	277
66c01883	278	static int ux500_dma_controller_start(struct ux500_dma_controller *controller)
8dcc8f72	279	{
8dcc8f72 MYK	280	struct ux500_dma_channel *ux500_channel = NULL;
	281	struct musb *musb = controller->private_data;
	282	struct device *dev = musb->controller;
c1a7d67c	283	struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
5f6091a0	284	struct ux500_musb_board_data *data;
8dcc8f72	285	struct dma_channel *dma_channel = NULL;
2968da0b	286	char **chan_names;
8dcc8f72 MYK	287	u32 ch_num;
	288	u8 dir;
	289	u8 is_tx = 0;
	290
	291	void **param_array;
	292	struct ux500_dma_channel *channel_array;
8dcc8f72 MYK	293	dma_cap_mask_t mask;
8dcc8f72 MYK	294
5f6091a0 LJ	295	if (!plat) {
5f6091a0 LJ	296	dev_err(musb->controller, "No platform data\n");
8dcc8f72	297	return -EINVAL;
5f6091a0	298	}
8dcc8f72	299
5f6091a0	300	data = plat->board_data;
8dcc8f72 MYK	301
	302	dma_cap_zero(mask);
	303	dma_cap_set(DMA_SLAVE, mask);
	304
	305	/* Prepare the loop for RX channels */
	306	channel_array = controller->rx_channel;
5f6091a0	307	param_array = data ? data->dma_rx_param_array : NULL;
2968da0b	308	chan_names = (char **)iep_chan_names;
8dcc8f72 MYK	309
8dcc8f72 MYK	310	for (dir = 0; dir < 2; dir++) {
be2dbb09 LJ	311	for (ch_num = 0;
	312	ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS;
	313	ch_num++) {
8dcc8f72 MYK	314	ux500_channel = &channel_array[ch_num];
	315	ux500_channel->controller = controller;
	316	ux500_channel->ch_num = ch_num;
	317	ux500_channel->is_tx = is_tx;
	318
	319	dma_channel = &(ux500_channel->channel);
	320	dma_channel->private_data = ux500_channel;
	321	dma_channel->status = MUSB_DMA_STATUS_FREE;
	322	dma_channel->max_len = SZ_16M;
	323
2968da0b LJ	324	ux500_channel->dma_chan =
	325	dma_request_slave_channel(dev, chan_names[ch_num]);
	326
	327	if (!ux500_channel->dma_chan)
	328	ux500_channel->dma_chan =
	329	dma_request_channel(mask,
0f2aa8ca LJ	330	data ?
	331	data->dma_filter :
	332	NULL,
086ed9a0 LJ	333	param_array ?
	334	param_array[ch_num] :
	335	NULL);
2968da0b	336
8dcc8f72 MYK	337	if (!ux500_channel->dma_chan) {
	338	ERR("Dma pipe allocation error dir=%d ch=%d\n",
	339	dir, ch_num);
	340
	341	/* Release already allocated channels */
66c01883	342	ux500_dma_controller_stop(controller);
8dcc8f72 MYK	343
	344	return -EBUSY;
	345	}
	346
8dcc8f72 MYK	347	}
	348
	349	/* Prepare the loop for TX channels */
	350	channel_array = controller->tx_channel;
5f6091a0	351	param_array = data ? data->dma_tx_param_array : NULL;
2968da0b	352	chan_names = (char **)oep_chan_names;
8dcc8f72 MYK	353	is_tx = 1;
	354	}
	355
	356	return 0;
	357	}
	358
7f6283ed	359	void ux500_dma_controller_destroy(struct dma_controller *c)
8dcc8f72 MYK	360	{
	361	struct ux500_dma_controller *controller = container_of(c,
	362	struct ux500_dma_controller, controller);
	363
66c01883	364	ux500_dma_controller_stop(controller);
8dcc8f72 MYK	365	kfree(controller);
8dcc8f72 MYK	366	}
7f6283ed	367	EXPORT_SYMBOL_GPL(ux500_dma_controller_destroy);
8dcc8f72	368
7f6283ed TL	369	struct dma_controller *
7f6283ed TL	370	ux500_dma_controller_create(struct musb musb, void __iomem base)
8dcc8f72 MYK	371	{
	372	struct ux500_dma_controller *controller;
	373	struct platform_device *pdev = to_platform_device(musb->controller);
	374	struct resource *iomem;
66c01883	375	int ret;
8dcc8f72 MYK	376
	377	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
	378	if (!controller)
399e0f4f	379	goto kzalloc_fail;
8dcc8f72 MYK	380
	381	controller->private_data = musb;
	382
	383	/* Save physical address for DMA controller. */
	384	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
399e0f4f VS	385	if (!iomem) {
	386	dev_err(musb->controller, "no memory resource defined\n");
	387	goto plat_get_fail;
	388	}
	389
8dcc8f72 MYK	390	controller->phy_base = (dma_addr_t) iomem->start;
8dcc8f72 MYK	391
8dcc8f72 MYK	392	controller->controller.channel_alloc = ux500_dma_channel_allocate;
	393	controller->controller.channel_release = ux500_dma_channel_release;
	394	controller->controller.channel_program = ux500_dma_channel_program;
	395	controller->controller.channel_abort = ux500_dma_channel_abort;
	396	controller->controller.is_compatible = ux500_dma_is_compatible;
	397
66c01883 SAS	398	ret = ux500_dma_controller_start(controller);
	399	if (ret)
	400	goto plat_get_fail;
8dcc8f72	401	return &controller->controller;
399e0f4f VS	402
	403	plat_get_fail:
	404	kfree(controller);
	405	kzalloc_fail:
	406	return NULL;
8dcc8f72	407	}
7f6283ed	408	EXPORT_SYMBOL_GPL(ux500_dma_controller_create);