[deliverable/linux.git] / drivers / usb / phy / omap-usb3.c

/*
 * omap-usb3 - USB PHY, talking to dwc3 controller in OMAP.
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * Author: Kishon Vijay Abraham I <kishon@ti.com>
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/usb/omap_usb.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/pm_runtime.h>
#include <linux/delay.h>
#include <linux/usb/omap_control_usb.h>

#define	NUM_SYS_CLKS		5
#define	PLL_STATUS		0x00000004
#define	PLL_GO			0x00000008
#define	PLL_CONFIGURATION1	0x0000000C
#define	PLL_CONFIGURATION2	0x00000010
#define	PLL_CONFIGURATION3	0x00000014
#define	PLL_CONFIGURATION4	0x00000020

#define	PLL_REGM_MASK		0x001FFE00
#define	PLL_REGM_SHIFT		0x9
#define	PLL_REGM_F_MASK		0x0003FFFF
#define	PLL_REGM_F_SHIFT	0x0
#define	PLL_REGN_MASK		0x000001FE
#define	PLL_REGN_SHIFT		0x1
#define	PLL_SELFREQDCO_MASK	0x0000000E
#define	PLL_SELFREQDCO_SHIFT	0x1
#define	PLL_SD_MASK		0x0003FC00
#define	PLL_SD_SHIFT		0x9
#define	SET_PLL_GO		0x1
#define	PLL_TICOPWDN		0x10000
#define	PLL_LOCK		0x2
#define	PLL_IDLE		0x1

/*
 * This is an Empirical value that works, need to confirm the actual
 * value required for the USB3PHY_PLL_CONFIGURATION2.PLL_IDLE status
 * to be correctly reflected in the USB3PHY_PLL_STATUS register.
 */
# define PLL_IDLE_TIME  100;

enum sys_clk_rate {
	CLK_RATE_UNDEFINED = -1,
	CLK_RATE_12MHZ,
	CLK_RATE_16MHZ,
	CLK_RATE_19MHZ,
	CLK_RATE_26MHZ,
	CLK_RATE_38MHZ
};

static struct usb_dpll_params omap_usb3_dpll_params[NUM_SYS_CLKS] = {
	{1250, 5, 4, 20, 0},		/* 12 MHz */
	{3125, 20, 4, 20, 0},		/* 16.8 MHz */
	{1172, 8, 4, 20, 65537},	/* 19.2 MHz */
	{1250, 12, 4, 20, 0},		/* 26 MHz */
	{3125, 47, 4, 20, 92843},	/* 38.4 MHz */
};

static int omap_usb3_suspend(struct usb_phy *x, int suspend)
{
	struct omap_usb *phy = phy_to_omapusb(x);
	int	val;
	int timeout = PLL_IDLE_TIME;

	if (suspend && !phy->is_suspended) {
		val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
		val |= PLL_IDLE;
		omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);

		do {
			val = omap_usb_readl(phy->pll_ctrl_base, PLL_STATUS);
			if (val & PLL_TICOPWDN)
				break;
			udelay(1);
		} while (--timeout);

		omap_control_usb3_phy_power(phy->control_dev, 0);

		phy->is_suspended	= 1;
	} else if (!suspend && phy->is_suspended) {
		phy->is_suspended	= 0;

		val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
		val &= ~PLL_IDLE;
		omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);

		do {
			val = omap_usb_readl(phy->pll_ctrl_base, PLL_STATUS);
			if (!(val & PLL_TICOPWDN))
				break;
			udelay(1);
		} while (--timeout);
	}

	return 0;
}

static inline enum sys_clk_rate __get_sys_clk_index(unsigned long rate)
{
	switch (rate) {
	case 12000000:
		return CLK_RATE_12MHZ;
	case 16800000:
		return CLK_RATE_16MHZ;
	case 19200000:
		return CLK_RATE_19MHZ;
	case 26000000:
		return CLK_RATE_26MHZ;
	case 38400000:
		return CLK_RATE_38MHZ;
	default:
		return CLK_RATE_UNDEFINED;
	}
}

static void omap_usb_dpll_relock(struct omap_usb *phy)
{
	u32		val;
	unsigned long	timeout;

	omap_usb_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);

	timeout = jiffies + msecs_to_jiffies(20);
	do {
		val = omap_usb_readl(phy->pll_ctrl_base, PLL_STATUS);
		if (val & PLL_LOCK)
			break;
	} while (!WARN_ON(time_after(jiffies, timeout)));
}

static int omap_usb_dpll_lock(struct omap_usb *phy)
{
	u32			val;
	unsigned long		rate;
	enum sys_clk_rate	clk_index;

	rate		= clk_get_rate(phy->sys_clk);
	clk_index	= __get_sys_clk_index(rate);

	if (clk_index == CLK_RATE_UNDEFINED) {
		pr_err("dpll cannot be locked for sys clk freq:%luHz\n", rate);
		return -EINVAL;
	}

	val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
	val &= ~PLL_REGN_MASK;
	val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
	omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);

	val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	val &= ~PLL_SELFREQDCO_MASK;
	val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
	omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);

	val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
	val &= ~PLL_REGM_MASK;
	val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
	omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);

	val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
	val &= ~PLL_REGM_F_MASK;
	val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
	omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);

	val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
	val &= ~PLL_SD_MASK;
	val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
	omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);

	omap_usb_dpll_relock(phy);

	return 0;
}

static int omap_usb3_init(struct usb_phy *x)
{
	struct omap_usb	*phy = phy_to_omapusb(x);

	omap_usb_dpll_lock(phy);
	omap_control_usb3_phy_power(phy->control_dev, 1);

	return 0;
}

static int omap_usb3_probe(struct platform_device *pdev)
{
	struct omap_usb			*phy;
	struct resource			*res;

	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
	if (!phy) {
		dev_err(&pdev->dev, "unable to alloc mem for OMAP USB3 PHY\n");
		return -ENOMEM;
	}

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll_ctrl");
	phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(phy->pll_ctrl_base))
		return PTR_ERR(phy->pll_ctrl_base);

	phy->dev		= &pdev->dev;

	phy->phy.dev		= phy->dev;
	phy->phy.label		= "omap-usb3";
	phy->phy.init		= omap_usb3_init;
	phy->phy.set_suspend	= omap_usb3_suspend;
	phy->phy.type		= USB_PHY_TYPE_USB3;

	phy->is_suspended	= 1;
	phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
	if (IS_ERR(phy->wkupclk)) {
		dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
		return PTR_ERR(phy->wkupclk);
	}
	clk_prepare(phy->wkupclk);

	phy->optclk = devm_clk_get(phy->dev, "usb_otg_ss_refclk960m");
	if (IS_ERR(phy->optclk)) {
		dev_err(&pdev->dev, "unable to get usb_otg_ss_refclk960m\n");
		return PTR_ERR(phy->optclk);
	}
	clk_prepare(phy->optclk);

	phy->sys_clk = devm_clk_get(phy->dev, "sys_clkin");
	if (IS_ERR(phy->sys_clk)) {
		pr_err("%s: unable to get sys_clkin\n", __func__);
		return -EINVAL;
	}

	phy->control_dev = omap_get_control_dev();
	if (IS_ERR(phy->control_dev)) {
		dev_dbg(&pdev->dev, "Failed to get control device\n");
		return -ENODEV;
	}

	omap_control_usb3_phy_power(phy->control_dev, 0);
	usb_add_phy_dev(&phy->phy);

	platform_set_drvdata(pdev, phy);

	pm_runtime_enable(phy->dev);
	pm_runtime_get(&pdev->dev);

	return 0;
}

static int omap_usb3_remove(struct platform_device *pdev)
{
	struct omap_usb *phy = platform_get_drvdata(pdev);

	clk_unprepare(phy->wkupclk);
	clk_unprepare(phy->optclk);
	usb_remove_phy(&phy->phy);
	if (!pm_runtime_suspended(&pdev->dev))
		pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

#ifdef CONFIG_PM_RUNTIME

static int omap_usb3_runtime_suspend(struct device *dev)
{
	struct platform_device	*pdev = to_platform_device(dev);
	struct omap_usb	*phy = platform_get_drvdata(pdev);

	clk_disable(phy->wkupclk);
	clk_disable(phy->optclk);

	return 0;
}

static int omap_usb3_runtime_resume(struct device *dev)
{
	u32 ret = 0;
	struct platform_device	*pdev = to_platform_device(dev);
	struct omap_usb	*phy = platform_get_drvdata(pdev);

	ret = clk_enable(phy->optclk);
	if (ret) {
		dev_err(phy->dev, "Failed to enable optclk %d\n", ret);
		goto err1;
	}

	ret = clk_enable(phy->wkupclk);
	if (ret) {
		dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
		goto err2;
	}

	return 0;

err2:
	clk_disable(phy->optclk);

err1:
	return ret;
}

static const struct dev_pm_ops omap_usb3_pm_ops = {
	SET_RUNTIME_PM_OPS(omap_usb3_runtime_suspend, omap_usb3_runtime_resume,
		NULL)
};

#define DEV_PM_OPS     (&omap_usb3_pm_ops)
#else
#define DEV_PM_OPS     NULL
#endif

#ifdef CONFIG_OF
static const struct of_device_id omap_usb3_id_table[] = {
	{ .compatible = "ti,omap-usb3" },
	{}
};
MODULE_DEVICE_TABLE(of, omap_usb3_id_table);
#endif

static struct platform_driver omap_usb3_driver = {
	.probe		= omap_usb3_probe,
	.remove		= omap_usb3_remove,
	.driver		= {
		.name	= "omap-usb3",
		.owner	= THIS_MODULE,
		.pm	= DEV_PM_OPS,
		.of_match_table = of_match_ptr(omap_usb3_id_table),
	},
};

module_platform_driver(omap_usb3_driver);

MODULE_ALIAS("platform: omap_usb3");
MODULE_AUTHOR("Texas Instruments Inc.");
MODULE_DESCRIPTION("OMAP USB3 phy driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
57f6ce07 KVA	1	/*
	2	* omap-usb3 - USB PHY, talking to dwc3 controller in OMAP.
	3	*
	4	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* Author: Kishon Vijay Abraham I <kishon@ti.com>
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	*/
	18
	19	#include <linux/module.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/slab.h>
	22	#include <linux/usb/omap_usb.h>
	23	#include <linux/of.h>
	24	#include <linux/clk.h>
	25	#include <linux/err.h>
	26	#include <linux/pm_runtime.h>
	27	#include <linux/delay.h>
	28	#include <linux/usb/omap_control_usb.h>
	29
	30	#define NUM_SYS_CLKS 5
	31	#define PLL_STATUS 0x00000004
	32	#define PLL_GO 0x00000008
	33	#define PLL_CONFIGURATION1 0x0000000C
	34	#define PLL_CONFIGURATION2 0x00000010
	35	#define PLL_CONFIGURATION3 0x00000014
	36	#define PLL_CONFIGURATION4 0x00000020
	37
	38	#define PLL_REGM_MASK 0x001FFE00
	39	#define PLL_REGM_SHIFT 0x9
	40	#define PLL_REGM_F_MASK 0x0003FFFF
	41	#define PLL_REGM_F_SHIFT 0x0
	42	#define PLL_REGN_MASK 0x000001FE
	43	#define PLL_REGN_SHIFT 0x1
	44	#define PLL_SELFREQDCO_MASK 0x0000000E
	45	#define PLL_SELFREQDCO_SHIFT 0x1
	46	#define PLL_SD_MASK 0x0003FC00
	47	#define PLL_SD_SHIFT 0x9
	48	#define SET_PLL_GO 0x1
	49	#define PLL_TICOPWDN 0x10000
	50	#define PLL_LOCK 0x2
	51	#define PLL_IDLE 0x1
	52
	53	/*
	54	* This is an Empirical value that works, need to confirm the actual
	55	* value required for the USB3PHY_PLL_CONFIGURATION2.PLL_IDLE status
	56	* to be correctly reflected in the USB3PHY_PLL_STATUS register.
	57	*/
	58	# define PLL_IDLE_TIME 100;
	59
	60	enum sys_clk_rate {
	61	CLK_RATE_UNDEFINED = -1,
	62	CLK_RATE_12MHZ,
	63	CLK_RATE_16MHZ,
	64	CLK_RATE_19MHZ,
65	CLK_RATE_26MHZ,
66	CLK_RATE_38MHZ
67	};
68
69	static struct usb_dpll_params omap_usb3_dpll_params[NUM_SYS_CLKS] = {
70	{1250, 5, 4, 20, 0}, /* 12 MHz */
71	{3125, 20, 4, 20, 0}, /* 16.8 MHz */
72	{1172, 8, 4, 20, 65537}, /* 19.2 MHz */
73	{1250, 12, 4, 20, 0}, /* 26 MHz */
74	{3125, 47, 4, 20, 92843}, /* 38.4 MHz */
75	};
76
77	static int omap_usb3_suspend(struct usb_phy *x, int suspend)
78	{
79	struct omap_usb *phy = phy_to_omapusb(x);
80	int val;
81	int timeout = PLL_IDLE_TIME;
82
83	if (suspend && !phy->is_suspended) {
84	val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
85	val \|= PLL_IDLE;
86	omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
87
88	do {
89	val = omap_usb_readl(phy->pll_ctrl_base, PLL_STATUS);
90	if (val & PLL_TICOPWDN)
91	break;
92	udelay(1);
93	} while (--timeout);
94
95	omap_control_usb3_phy_power(phy->control_dev, 0);
96
97	phy->is_suspended = 1;
98	} else if (!suspend && phy->is_suspended) {
99	phy->is_suspended = 0;
100
101	val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
102	val &= ~PLL_IDLE;
103	omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
104
105	do {
106	val = omap_usb_readl(phy->pll_ctrl_base, PLL_STATUS);
107	if (!(val & PLL_TICOPWDN))
108	break;
109	udelay(1);
110	} while (--timeout);
111	}
112
113	return 0;
114	}
115
116	static inline enum sys_clk_rate __get_sys_clk_index(unsigned long rate)
117	{
118	switch (rate) {
119	case 12000000:
120	return CLK_RATE_12MHZ;
121	case 16800000:
122	return CLK_RATE_16MHZ;
123	case 19200000:
124	return CLK_RATE_19MHZ;
125	case 26000000:
126	return CLK_RATE_26MHZ;
127	case 38400000:
128	return CLK_RATE_38MHZ;
129	default:
130	return CLK_RATE_UNDEFINED;
131	}
132	}
133
134	static void omap_usb_dpll_relock(struct omap_usb *phy)
135	{
136	u32 val;
137	unsigned long timeout;
138
139	omap_usb_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
140
141	timeout = jiffies + msecs_to_jiffies(20);
142	do {
143	val = omap_usb_readl(phy->pll_ctrl_base, PLL_STATUS);
144	if (val & PLL_LOCK)
145	break;
146	} while (!WARN_ON(time_after(jiffies, timeout)));
147	}
148
149	static int omap_usb_dpll_lock(struct omap_usb *phy)
150	{
151	u32 val;
152	unsigned long rate;
153	enum sys_clk_rate clk_index;
154
155	rate = clk_get_rate(phy->sys_clk);
156	clk_index = __get_sys_clk_index(rate);
157
158	if (clk_index == CLK_RATE_UNDEFINED) {
159	pr_err("dpll cannot be locked for sys clk freq:%luHz\n", rate);
160	return -EINVAL;
161	}
162
163	val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
164	val &= ~PLL_REGN_MASK;
165	val \|= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
166	omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
167
168	val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
169	val &= ~PLL_SELFREQDCO_MASK;
170	val \|= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
171	omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
172
173	val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
174	val &= ~PLL_REGM_MASK;
175	val \|= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
176	omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
177
178	val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
179	val &= ~PLL_REGM_F_MASK;
180	val \|= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
181	omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
182
183	val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
184	val &= ~PLL_SD_MASK;
185	val \|= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
186	omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
187
188	omap_usb_dpll_relock(phy);
189
190	return 0;
191	}
192
193	static int omap_usb3_init(struct usb_phy *x)
194	{
195	struct omap_usb *phy = phy_to_omapusb(x);
196
197	omap_usb_dpll_lock(phy);
198	omap_control_usb3_phy_power(phy->control_dev, 1);
199
200	return 0;
201	}
202
203	static int omap_usb3_probe(struct platform_device *pdev)
204	{
205	struct omap_usb *phy;
206	struct resource *res;
207
208	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
209	if (!phy) {
210	dev_err(&pdev->dev, "unable to alloc mem for OMAP USB3 PHY\n");
211	return -ENOMEM;
212	}
213
214	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll_ctrl");
862421da SK	215	phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
	216	if (IS_ERR(phy->pll_ctrl_base))
	217	return PTR_ERR(phy->pll_ctrl_base);
57f6ce07 KVA	218
	219	phy->dev = &pdev->dev;
	220
	221	phy->phy.dev = phy->dev;
	222	phy->phy.label = "omap-usb3";
	223	phy->phy.init = omap_usb3_init;
	224	phy->phy.set_suspend = omap_usb3_suspend;
	225	phy->phy.type = USB_PHY_TYPE_USB3;
	226
	227	phy->is_suspended = 1;
	228	phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
	229	if (IS_ERR(phy->wkupclk)) {
	230	dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
	231	return PTR_ERR(phy->wkupclk);
	232	}
	233	clk_prepare(phy->wkupclk);
	234
	235	phy->optclk = devm_clk_get(phy->dev, "usb_otg_ss_refclk960m");
	236	if (IS_ERR(phy->optclk)) {
	237	dev_err(&pdev->dev, "unable to get usb_otg_ss_refclk960m\n");
	238	return PTR_ERR(phy->optclk);
	239	}
	240	clk_prepare(phy->optclk);
	241
	242	phy->sys_clk = devm_clk_get(phy->dev, "sys_clkin");
	243	if (IS_ERR(phy->sys_clk)) {
	244	pr_err("%s: unable to get sys_clkin\n", __func__);
	245	return -EINVAL;
	246	}
	247
	248	phy->control_dev = omap_get_control_dev();
	249	if (IS_ERR(phy->control_dev)) {
	250	dev_dbg(&pdev->dev, "Failed to get control device\n");
	251	return -ENODEV;
	252	}
	253
	254	omap_control_usb3_phy_power(phy->control_dev, 0);
	255	usb_add_phy_dev(&phy->phy);
	256
	257	platform_set_drvdata(pdev, phy);
	258
	259	pm_runtime_enable(phy->dev);
	260	pm_runtime_get(&pdev->dev);
	261
	262	return 0;
	263	}
	264
	265	static int omap_usb3_remove(struct platform_device *pdev)
	266	{
	267	struct omap_usb *phy = platform_get_drvdata(pdev);
	268
	269	clk_unprepare(phy->wkupclk);
	270	clk_unprepare(phy->optclk);
	271	usb_remove_phy(&phy->phy);
	272	if (!pm_runtime_suspended(&pdev->dev))
	273	pm_runtime_put(&pdev->dev);
	274	pm_runtime_disable(&pdev->dev);
	275
	276	return 0;
	277	}
	278
	279	#ifdef CONFIG_PM_RUNTIME
	280
	281	static int omap_usb3_runtime_suspend(struct device *dev)
282	{
283	struct platform_device *pdev = to_platform_device(dev);
284	struct omap_usb *phy = platform_get_drvdata(pdev);
285
286	clk_disable(phy->wkupclk);
287	clk_disable(phy->optclk);
288
289	return 0;
290	}
291
292	static int omap_usb3_runtime_resume(struct device *dev)
293	{
294	u32 ret = 0;
295	struct platform_device *pdev = to_platform_device(dev);
296	struct omap_usb *phy = platform_get_drvdata(pdev);
297
298	ret = clk_enable(phy->optclk);
299	if (ret) {
300	dev_err(phy->dev, "Failed to enable optclk %d\n", ret);
301	goto err1;
302	}
303
304	ret = clk_enable(phy->wkupclk);
305	if (ret) {
306	dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
307	goto err2;
308	}
309
310	return 0;
311
312	err2:
313	clk_disable(phy->optclk);
314
315	err1:
316	return ret;
317	}
318
319	static const struct dev_pm_ops omap_usb3_pm_ops = {
320	SET_RUNTIME_PM_OPS(omap_usb3_runtime_suspend, omap_usb3_runtime_resume,
321	NULL)
322	};
323
324	#define DEV_PM_OPS (&omap_usb3_pm_ops)
325	#else
326	#define DEV_PM_OPS NULL
327	#endif
328
329	#ifdef CONFIG_OF
330	static const struct of_device_id omap_usb3_id_table[] = {
331	{ .compatible = "ti,omap-usb3" },
332	{}
333	};
334	MODULE_DEVICE_TABLE(of, omap_usb3_id_table);
335	#endif
336
337	static struct platform_driver omap_usb3_driver = {
338	.probe = omap_usb3_probe,
339	.remove = omap_usb3_remove,
340	.driver = {
341	.name = "omap-usb3",
342	.owner = THIS_MODULE,
343	.pm = DEV_PM_OPS,
344	.of_match_table = of_match_ptr(omap_usb3_id_table),
345	},
346	};
347
348	module_platform_driver(omap_usb3_driver);
349
350	MODULE_ALIAS("platform: omap_usb3");
351	MODULE_AUTHOR("Texas Instruments Inc.");
352	MODULE_DESCRIPTION("OMAP USB3 phy driver");
353	MODULE_LICENSE("GPL v2");